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Integrated Device Technology, Inc.
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| Part No. |
9DBV0631
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| OCR Text |
...ures ? 6 - 1-200 mhz low-power (lp) hcsl dif pairs key specifications ? dif additive cycle-to-cycle jitter <5ps ? dif output-to-output skew <60ps ? dif additive phase jitter is <100fs rms for pcie gen3 ? dif additive phase jitter <300... |
| Description |
6-output 1.8 V PCIe Gen1-2-3 Zero Delay/Fanout Buffer
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| File Size |
161.89K /
17 Page |
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Integrated Device Techn...
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| Part No. |
9ZXL0651
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| OCR Text |
...ures ? 6 - 0.7v low-power hcsl (lp-hcsl) output pairs w/integrated terminations features/benefits ? low-power-hcsl outputs w/zo = 85 ? ; save power and board space - no termination resistors required. ideal for blade servers. ? space-sav... |
| Description |
PLL or bypass mode
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| File Size |
219.18K /
17 Page |
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Integrated Device Techn...
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| Part No. |
9ZXL1251
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| OCR Text |
...res ? 12 - low-power push-pull (lp) hcsl output pairs w/integrated terminations features/benefits ? 85 ? low-power push-pull hcsl outputs; eliminate 24 resistors, save 41mm 2 of area ? pin compatible to 9zx21201 and 9zxl1231; easy path ... |
| Description |
Space-saving 64-pin VFQFPN package
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| File Size |
374.00K /
20 Page |
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Integrated Device Techn...
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| Part No. |
9ZXL1530
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| OCR Text |
...uffer utilizing low-power hcsl (lp-hcsl) outputs to reduce power consumption more than 50% from the original idt9zx21501. it is suitable for pci-express gen3 or qpi applications, and uses a fixed external feedback to maintain lo w drift... |
| Description |
Fixed feedback path
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| File Size |
213.44K /
19 Page |
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Integrated Circuit Syst...
Integrated Device Techn...
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| Part No. |
9DBU0531
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| OCR Text |
...tures ? 5 - 1-167mhz low-power (lp) hcsl dif pairs key specifications ? dif additive cycle-to-cycle jitter <5ps ? dif output-to-output skew <60ps ? dif additive phase jitter is <300fs rms for pcie gen3 ? dif additive phase jitter <35... |
| Description |
slew rate for each output
HCSL-compatible differential input
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| File Size |
179.36K /
16 Page |
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Integrated Circuit Syst...
Integrated Device Techn...
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| Part No. |
9DBU0541
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| OCR Text |
...tures ? 5 - 1-167mhz low-power (lp) hcsl dif pairs w/zo=100 ? key specifications ? dif additive cycle-to-cycle jitter <5ps ? dif output-to-output skew <60ps ? dif additive phase jitter is <300fs rms for pcie gen3 ? dif additive phase... |
| Description |
slew rate for each output
HCSL-compatible differential input
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| File Size |
186.14K /
16 Page |
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it Online |
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Integrated Device Techn...
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| Part No. |
5P49V5907
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| OCR Text |
...? four copies of low power hcsl(lp-hcsl) outputs. ? programmable frequency: ? see output features and descriptions for details ? one reference lvcmos output clock ? high performance, low phase noise pll, <0.7 ps rms typical phase jitter on... |
| Description |
Programmable frequency
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| File Size |
429.63K /
30 Page |
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Integrated Device Techn...
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| Part No. |
5P49V5908
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| OCR Text |
... eight copies of low power hcsl(lp-hcsl) outputs. programmable frequency ? see output features and descriptions for details ? one reference lvcmos output clock ? high performance, low phase noise pll, <0.7 ps rms typical phase jitter on o... |
| Description |
One reference LVCMOS output clock
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| File Size |
515.09K /
30 Page |
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it Online |
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Integrated Circuit Syst...
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| Part No. |
9DBV0441
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| OCR Text |
...atures ? 4 ? 1-200hz low-power (lp) hcsl dif pairs w/z o =100 ? key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif additive phase jitter is <100fs rms for pcie gen3 ? dif additive phase jitter <... |
| Description |
53mW typical power consumption in PLL mode
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| File Size |
207.64K /
17 Page |
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it Online |
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