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Cypress Semiconductor Corp. CYPRESS[Cypress Semiconductor]
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| Part No. |
W199
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| OCR Text |
... Tables 2 and 6. This output is affected by the PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and PCI outputs. Fixed PCI Clock Output: As an output, frequency is set by the FS0:3 inputs or through serial in... |
| Description |
Spread Spectrum FTG for VIA Apollo Pro-133 From old datasheet system
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| File Size |
153.16K /
14 Page |
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INTEL[Intel Corporation]
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| Part No. |
M82C288-8 M82C288 82C288 D82C288 M82C288-10 M82C288-6
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| OCR Text |
...r the halt bus cycle and is not affected by any of the control inputs MASTER CASCADE ENABLE signals that a cascade address from a master M8259A interrupt controller may be placed onto the CPU address bus for latching by the address latches ... |
| Description |
BUS CONTROLLER FOR M80286 PROCESSORS
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| File Size |
317.24K /
20 Page |
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it Online |
Download Datasheet
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IDT Integrated Device Technology, Inc.
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| Part No. |
IDTCV115C IDTCV115CPV IDTCV115CPVG CV115C CV115CPV CV115CPV8
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| OCR Text |
...
Bit 7 6 5 4 3 2 1 0 Output(s) affected CPUT2, CPUC2/ SRCT7, SRCC7 SRCT6, SRCC6 SRCT5, SRCC5 SRCT4, SRCC4 (SATA) SRCT3, SRCC3 SRCT2, SRCC2 SRCT1, SRCC1 REF0 2x drive Description/Function Output enable Output enable Output enable Output ena... |
| Description |
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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| File Size |
83.04K /
19 Page |
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it Online |
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Price and Availability
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