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Integrated Device Techn...
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| Part No. |
6V49205B
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| OCR Text |
...6m. the 6v49205b also provides lp-hcsl pcie outputs for low power and reduced board space. output features ? 1 - sys_ccb 3.3v lvcmos output @ 100m/83.33m/ 80m/66.66m ? 1 - ddrclk 3.3v lvcmos output @ 100m or 66.66m 1 ? 1 - 125m 3.3v lvcm... |
| Description |
Industrial temperature range operation
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| File Size |
333.15K /
16 Page |
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Integrated Device Techn...
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| Part No. |
9ZXL1950BKLF 9ZXL1950BKLFT
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| OCR Text |
...ffer utilizing low-power hcsl (lp-hcsl) outp uts to increase edge rates on long traces, reduce board space, and reduce power consumption more than 50% from the original 9zx21901.it is pin-compatible to the 9zxl19 30 and fully integrates... |
| Description |
19-output DB1900Z Low-Power Derivative w/85ohm Terminations
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| File Size |
292.32K /
18 Page |
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it Online |
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Integrated Device Techn...
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| Part No. |
9DBV0731-17
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| OCR Text |
...atures ? 7 1?200mhz low-power (lp) hcsl dif pairs ? easy ac-coupling to other logic families, see idt application note an-891 key specifications ? additive cycle-to-cycle jitter < 5ps ? output-to-output skew < 60ps ? additive phase jit... |
| Description |
7-Output 1.8V HCSL Fanout Buffer
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| File Size |
261.00K /
17 Page |
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Integrated Device Techn...
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| Part No. |
9FGV0231AKLFT
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| OCR Text |
...0.7v low-power hcsl-compatible (lp-hcsl) dif pairs ? 1 - 1.8v lvcmos ref output w/wake-on-lan (wol) support key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1-2-3 complia... |
| Description |
2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
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| File Size |
217.11K /
15 Page |
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it Online |
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Integrated Device Techn...
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| Part No. |
9FGV0241-16 9FGV0241AKILFT
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| OCR Text |
...0.7v low-power hcsl-compatible (lp-hcsl) dif pairs w/zo=100 ? ? 1 - 1.8v lvcmos ref output w/wake-on-lan (wol) support key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1-... |
| Description |
2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR
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| File Size |
223.71K /
15 Page |
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it Online |
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Integrated Device Techn...
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| Part No. |
9FGV0241
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| OCR Text |
...0.7v low-power hcsl-compatible (lp-hcsl) dif pairs w/zo=100 ? ? 1 - 1.8v lvcmos ref output w/wake-on-lan (wol) support key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1-... |
| Description |
Programmable Slew rate for each output
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| File Size |
223.46K /
15 Page |
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Integrated Device Techn...
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| Part No. |
9FGV0431AKLF 9FGV0431AKILFT
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...0.7v low-power hcsl-compatible (lp-hcsl) dif pairs ? 1 - 1.8v lvcmos ref output w/wake-on-lan key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1-2-3 compliant ? ref phase ... |
| Description |
4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
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| File Size |
217.72K /
15 Page |
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it Online |
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Integrated Device Techn...
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| Part No. |
9FGV0431AKILF
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| OCR Text |
...0.7v low-power hcsl-compatible (lp-hcsl) dif pairs ? 1 ? 1.8v lvcmos ref output w/wake-on-lan key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1-2-3-4 compliant ? ref phas... |
| Description |
4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
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| File Size |
280.65K /
16 Page |
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it Online |
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Integrated Device Techn...
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| Part No. |
9FGV0241AKLF
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| OCR Text |
...0.7v low-power hcsl-compatible (lp-hcsl) dif pairs w/zo=100 ? ? 1 ? 1.8v lvcmos ref output w/wake-on-lan (wol) support key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1-... |
| Description |
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
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| File Size |
281.36K /
16 Page |
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it Online |
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