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august 2010 doc id 14335 rev 5 1/29 29 l6226q dmos dual full bridge driver features operating supply voltage from 8 to 52 v 2.8 a output peak current (1.4 a dc) r ds(on) 0.73 typ. value @ t j = 25 c operating frequency up to 100 khz programmable high side overcurrent detection and protection diagnostic output paralleled operation cross conduction protection thermal shutdown under voltage lockout integrated fast free wheeling diodes applications bipolar stepper motor dual or quad dc motor description the l6226q is a dmos dual full bridge designed for motor control applic ations, realized in bcdmultipower technology, which combines isolated dmos power transistors with cmos and bipolar circuits on the same chip. available in qfn32 5x5 package, the l6226q features thermal shutdown and a non-dissipative overcurrent detection on the high side power mosfets plus a diagnostic output that can be easily used to implement the overcurrent protection. figure 1. block diagram d99in1088a gate logic over current detection over current detection gate logic vcp vboot en a in1 a in2 a en b in1 b in2 b v boot 5v 10v vs a v s b out1 a out2 a out1 b out2 b sense a charge pump voltage regulator thermal protection v boot v boot 10v 10v bridge a bridge b sense b progcl b ocd b ocd a progcl a ocd a ocd b www.st.com
contents l6226q 2/29 doc id 14335 rev 5 contents 1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 non-dissipative overcurrent detection and pr otection . . . . . . . . . . . . . . . 12 4.5 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 paralleled operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 output current capability and ic power dissipation . . . . . . . . . . . . . . 23 8 thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
l6226q electrical data doc id 14335 rev 5 3/29 1 electrical data 1.1 absolute maximum ratings 1.2 recommended operating conditions table 1. absolute maximum ratings symbol parameter parameter value unit v s supply voltage v sa = v sb = v s 60 v v od differential voltage between vs a , out1 a , out2 a , sense a and vs b , out1 b , out2 b , sense b v sa = v sb = v s = 60 v, v sensea = v senseb = gnd 60 v ocd a ,ocd b ocd pins voltage range -0.3 to + 10 v progcl a , progcl b progcl pins voltage range -0.3 to + 7 v v boot bootstrap peak voltage v sa = v sb = v s v s + 10 v v in ,v en input and enable voltage range -0.3 to + 7 v v sensea, v senseb voltage range at pins sense a and sense b -1 to + 4 v i s(peak) pulsed supply current (for each v s pin), internally limited by the overcurrent protection v sa = v sb = v s , t pulse < 1 ms 3.55 a i s rms supply current (for each v s pin) v sa = v sb = v s 1.4 a t stg , t op storage and operating temperature range -40 to 150 c table 2. recommended operating conditions symbol parameter parameter min max unit v s supply voltage v sa = v sb = v s 852v v od differential voltage between vs a , out1 a , out2 a , sense a and vs b , out1 b , out2 b , sense b v sa = v sb = v s , v sensea = v senseb 52 v v sensea, v senseb voltage range at pins sense a and sense b (pulsed t w < t rr ) (dc) -6 -1 6 1 v v i out rms output current 1.4 a t j operating junction temperature -25 +125 c f sw switching frequency 100 khz
electrical data l6226q 4/29 doc id 14335 rev 5 1.3 thermal data table 3. thermal data symbol parameter value unit r th(ja) thermal resistance j unction-ambient max. (1) 1. mounted on a double-layer fr4 pcb with a dissipating copper surface of 0.5 cm 2 on the top side plus 6 cm 2 ground layer connected through 18 via holes (9 below the ic). 42 c/w
l6226q pin connection doc id 14335 rev 5 5/29 2 pin connection figure 2. pin connection (top view) note: 1 the pins 2 to 8 are connected to die pad. 2 the die pad must be connected to gnd pin.
pin connection l6226q 6/29 doc id 14335 rev 5 table 4. pin description n pin type function 1, 21 gnd gnd signal ground terminals. 9 out1b power output bridge b output 1. 11 ocdb open drain output bridge b overcurrent detection and thermal protection pin. an internal open drain transistor pulls to gnd when overcurrent on bridge b is detected or in case of thermal protection. 12 senseb power supply bridge b source pin. this pin must be connected to power ground directly or through a sensing power resistor. 13 in1b logic input bridge b input 1 14 in2b logic input bridge b input 2 15 progclb r pin bridge b overcurrent level programming. a resistor connected between this pin and ground sets the programmable current limiting value for the bridge b. by connecting this pin to ground the maximum current is set. this pin cannot be left non-connected. 16 enb logic input bridge b enable. low logic level switches off all power mosfets of bridge b. if not used, it has to be connected to +5 v. 17 vboot supply voltage bootstrap voltage needed for driving the upper power mosfets of both bridge a and bridge b. 19 out2b power output bridge b output 2. 20 vsb power supply bridge b power supply voltage. it must be connected to the supply voltage together with pin vsa. 22 vsa power supply bridge a power supply voltage. it must be connected to the supply voltage together with pin vsb. 23 out2a power output bridge a output 2. 24 vcp output charge pump oscillator output. 25 ena logic input bridge a enable. low logic level switches off all power mosfets of bridge a. if not used, it has to be connected to +5 v. 26 progcla r pin bridge a overcurrent level programming. a resistor connected between this pin and ground sets the programmable cu rrent limiting value for the bridge a. by connecting this pin to ground the maximum current is set. this pin cannot be left non-connected. 27 in1a logic input bridge a logic input 1. 28 in2a logic input bridge a logic input 2. 29 sensea power supply bridge a source pin. this pin must be connected to power ground directly or through a sensing power resistor. 30 ocda open drain output bridge a overcurrent detection and thermal protection pin. an internal open drain transistor pulls to gnd when overcurrent on bridge a is detected or in case of thermal protection. 31 out1a power output bridge a output 1.
l6226q electrical characteristics doc id 14335 rev 5 7/29 3 electrical characteristics t a = 25 c, vs = 48 v, unless otherwise specified table 5. electrical characteristics symbol parameter test condition min typ max unit v sth(on) turn-on threshold 5.8 6.3 6.8 v v sth(off) turn-off threshold 5 5.5 6 v i s quiescent supply current all bridges off; t j = -25 c to 125 c (1) 510ma t j(off) thermal shutdown temperature 165 c output dmos transistors r ds(on) high-side + low-side switch on resistance t j = 25 c 1.47 1.69 t j = 125 c (1) 2.35 2.70 i dss leakage current en = low; out = v s 2ma en = low; out = gnd -0.3 ma source drain diodes v sd forward on voltage i sd = 2.8 a, en = low 1.15 1.3 v t rr reverse recovery time i f = 1.4 a 300 ns t fr forward recovery time 200 ns logic input v il low level logic input voltage -0.3 0.8 v v ih high level logic input voltage 2 7 v i il low level logic input current gnd logic input voltage -10 a i ih high level logic input current 7 v logic input voltage 10 a v th(on) turn-on input threshold 1.8 2.0 v v th(off) turn-off input threshold 0.8 1.3 v v th(hys) input threshold h ysteresis 0.25 0.5 v switching characteristics t d(on)en enable to out turn on delay time (2) i load =1.4 a, resistive load 500 800 ns t d(on)in input to out turn on delay time i load =1.4 a, resistive load (dead time included) 1.9 s t rise output rise time (2) i load =1.4 a, resistive load 40 250 ns t d(off)en enable to out turn off delay time (2) i load =1.4 a, resistive load 500 800 1000 ns t d(off)in input to out turn off delay time i load =1.4 a, resistive load 500 800 1000 ns t fall output fall time (2) i load =1.4 a, resistive load 40 250 ns
electrical characteristics l6226q 8/29 doc id 14335 rev 5 figure 3. switching char acteristic definition t dt dead time protection 0.5 1 s f cp charge pump frequency -25 c < t j < 125 c 0.6 1 mhz over current detection i s over input supply over current detection threshold -25 c l6226q electrical characteristics doc id 14335 rev 5 9/29 figure 4. overcurrent de tection timing definition 2&' 7kuhvkrog , 287 9 2&' w w w 2&'2)) w 2&'21 ',1
circuit description l6226q 10/29 doc id 14335 rev 5 4 circuit description 4.1 power stages and charge pump the l6226q integrates two independent power mos full bridges. each power mos has an r ds(on) = 0.73 (typical value @ 25 c), with intrinsic fast freewheeling diode. cross conduction protection is achieved using a dead time (td = 1 s typical) between the switch off and switch on of two power mos in one leg of a bridge. using n-channel power mos for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. the bootstrapped (vboot) supply is obtained through an internal oscillator and few external components to realize a charge pump circuit as shown in figure 5 . the oscillator output (vcp) is a squa re wave at 600 khz (typical) with 10 v amplitude. recommended values/part numbers for the charge pump circuit are shown in ta b l e 6 . figure 5. charge pump circuit table 6. charge pump external components values component value c boot 220 nf c p 10 nf d1 1n4148 d2 1n4148 9 6 ' & %227 ' & 3 96 $ 9&3 9%227 96 % ',1
l6226q circuit description doc id 14335 rev 5 11/29 4.2 logic inputs pins in1 a , in2 a , in1 b , in2 b , en a and en b are ttl/cmos and microcontroller compatible logic inputs. the internal structure is shown in figure 6 . typical value for turn-on and turn-off thresholds are respectively vthon = 1.8 v and vthoff = 1.3 v. pins en a and en b are commonly used to implement overcurrent and thermal protection by connecting them respectively to the outputs ocd a and ocd b , which are open-drain outputs. if that type of connection is chosen , some care needs to be taken in driving these pins. two configurations are shown in figure 7 and figure 8 . if driven by an open drain (collector) structure, a pull-up resistor r en and a capacitor c en are connected as shown in figure 7 . if the driver is a standard push-pull structure the resistor r en and the capacitor c en are connected as shown in figure 8 . the resistor r en should be chosen in the range from 2.2 k to 180 k . recommended values for r en and c en are respectively 100 k and 5.6 nf. more information on selecting the values is found in the overcurrent protection section. figure 6. logic inputs internal structure figure 7. en a and en b pins open collector driving figure 8. en a and en b pins push-pull driving 9 ',1 (6' 3527(&7,21
circuit description l6226q 12/29 doc id 14335 rev 5 4.3 truth table 4.4 non-dissipative overcurrent detection and protection an overcurrent detection circuit (ocd) is integr ated. this circuit can be used to provides protection against a short circuit to ground or between two phases of the bridge as well as a roughly regulation of the load current. with this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. figure 9 shows a simplified schematic of the overcurrent detection circuit for the bridge a. bridge b is provided of an analogous circuit. to implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power mos. since this current is a small fraction of the output current there is very little additional power dissipation. this current is compared with an internal reference current i ref . when the output current reaches the detection threshold isover the ocd comparator signals a fault condition. when a fault condition is detected, an internal open drain mos with a pull down capability of 4 ma connected to ocd pin is turned on. figure 10 shows the ocd operation. this signal can be used to regulate the output current simply by connecting the ocd pin to en pin and adding an external r-c as shown in figure 9 . the off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. i ref and, therefore, the output current detection threshold are selectable by r cl value, following the equations: isover = 2.8 a 30 % at -25 c < t j < 125 c if r cl = 0 (progcl connected to gnd) isover = 10 % at -25 c < t j < 125 c if 5 k < r cl < 40 k figure 11 shows the output current protection threshold versus r cl value in the range 5 k to 40 k . the disable time t disable before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. it is affected whether by c en and r en table 7. truth table inputs outputs en in1 in2 out1 out2 lx (1) 1. x = don't care x high z (2) 2. high z = high impedance output high z hllgndgnd hhlvsgnd hlhgndvs hhhvsvs 11050 r cl ----------------
l6226q circuit description doc id 14335 rev 5 13/29 values and its magnitude is reported in figure 12 . the delay time t delay before turning off the bridge when an overcurrent has been detected depends only by c en value. its magnitude is reported in figure 13 . c en is also used for providing immunity to pin en against fast transient noises. therefore the value of c en should be chosen as big as possible according to the maximum tolerable delay time and the r en value should be chosen according to the desired disable time. the resistor r en should be chosen in the range from 2.2 k to 180 k . recommended values for r en and c en are respectively 100 k and 5.6 nf that allow obtaining 200 s disable time. figure 9. overcurrent protection simplified schematic
circuit description l6226q 14/29 doc id 14335 rev 5 figure 10. overcurrent protection waveforms figure 11. output current protection threshold versus r cl value i sover i out v th(on) v th(off) v en(low) v dd t ocd(on) t d(on)en t en(fall) t en(rise) t disable t delay t ocd(off) t d(off)en v en bridge on off ocd on off d02in1400 5k 10k 15k 20k 25k 30k 35k 40k 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2.5 r cl [ ] 2 2.25 i sover [a]
l6226q circuit description doc id 14335 rev 5 15/29 figure 12. t disable versus c en and r en (v dd = 5 v) figure 13. t delay versus c en (v dd = 5 v) 1 10 100 1 10 100 1 . 10 3 c en [nf] t disable [s] r en = 220 k r en = 100 k r en = 47 k r en = 33 k r en = 10 k 1 10 100 1 10 100 1 . 10 3 c en [nf] t disable [s] r en = 220 k r en = 100 k r en = 47 k r en = 33 k r en = 10 k 1 10 100 0.1 1 10 cen [nf] tdelay [ s]
circuit description l6226q 16/29 doc id 14335 rev 5 4.5 thermal protection in addition to the overcurrent detection, the l6226q integrates a thermal protection for preventing the device destruction in case of junction over temperature. it works sensing the die temperature by means of a sensible element integrated in the die. the device switch-off when the junction temperature reaches 165 c (typ. value) with 15 c hysteresis (typ. value).
l6226q application information doc id 14335 rev 5 17/29 5 application information a typical application using l6226q is shown in figure 14 . typical component values for the application are shown in ta b l e 8 . a high quality ceramic capacitor in the range of 100 to 200 nf should be placed between the power pins (vs a and vs b ) and ground near the l6226q to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. the capacitors connected from the en a /ocd a and en b /ocd b nodes to ground set the shut down time for the bridge a and bridge b respectively when an over current is detected (see overcurrent protection). the two current sources (sense a and sense b ) should be connected to power ground with a trace length as short as possible in the layout. to increa se noise immunity, unused logic pins are best connected to 5 v (high logic level) or gnd (low logic level) (see pin description). it is recommended to keep power ground and signal ground separated on pcb. table 8. component values for typical application component value c 1 100 nf c 2 100 f c boot 220 nf c p 10 nf c ena 5.6 nf c enb 5.6 nf c ref 68 nf d 1 1n4148 d 2 1n4148 r cla 5 k r clb 5 k r ena 100 k r enb 100 k
application information l6226q 18/29 doc id 14335 rev 5 figure 14. typical application note: to reduce the ic thermal resistance, therefore improve the dissipation path, the nc pins can be connected to gnd.
l6226q paralleled operation doc id 14335 rev 5 19/29 6 paralleled operation the outputs of the l6226q can be paralleled to increase the output current capability or reduce the power dissipation in the device at a given current level. it must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half bridges. when the two halves of one full bridge (for example out1 a and out2 a ) are connected in parallel, the peak current rating is not increased since the total current must st ill flow through one bond wire on the power supply or sense pin. in addition the over current detection senses the sum of the current in the upper devices of each bridge (a or b) so connecting the two halves of one bridge in parallel does not increase the over current detection threshold. for most applications the recommended configuration is half bridge 1 of bridge a paralleled with the half bridge 1 of the bridge b, and the same for the half bridges 2 as shown in figure 15 . the current in the two devices connected in parallel will share very well since the r ds(on) of the devices on the same die is well matched. when connected in this configuration the over current detection circuit, which senses the current in each bridge (a and b), will sense the current in upper devices connected in parallel independently and the sense circuit with the lowest threshold will trip first. with the enables connected in parallel, the first detection of an over current in either upper dmos device will turn of both bridges. assuming that the two dmos devi ces share the current equally, the resulting over current detection threshold will be twice the minimum threshold set by the resistors r cla or r clb in figure 15 . it is recommended to use r cla = r clb . in this configuration the resulting bridge has the following characteristics. equivalent device: full bridge r ds(on) 0.37 typ. value @ t j = 25 c 2.8 a max rms load current 5.6 a max ocd threshold
paralleled operation l6226q 20/29 doc id 14335 rev 5 figure 15. parallel connection for higher current to operate the device in parallel and maintain a lower over current threshold, half bridge 1 and the half bridge 2 of the bridge a can be connected in parallel and the same done for the bridge b as shown in figure 16 . in this configuration, the peak current for each half bridge is still limited by the bond wires fo r the supply and sense pins so the dissipation in the device will be reduced, but the peak curr ent rating is not increased. when connected in this configuration the over current detection circuit, senses the sum of the current in upper devices connected in parallel. with the enables connected in parallel, an over current will turn of both bridges. since the circui t senses the tota l current in the upper devices, the over current threshold is equal to the threshold set the resistor r cla or r clb in figure 16 . r cla sets the threshold when outputs out1 a and out2 a are high and resistor r clb sets the threshold when outputs out1 b and out2 b are high. it is recommended to use r cla = r clb . in this configuration, the resulting br idge has the following characteristics. equivalent device: full bridge r ds(on) 0.37 typ. value @ t j = 25 c 1.4 a max rms load current 2.8 a max ocd threshold
l6226q paralleled operation doc id 14335 rev 5 21/29 figure 16. parallel connection with lower overcurrent threshold it is also possible to parallel th e four half bridges to obtain a simple half bridge as shown in figure 17 . in this configuration the, the over current threshold is equal to twice the minimum threshold set by the resistors r cla or r clb in figure 17 . it is recommended to use r cla = r clb . the resulting half bridge has the following characteristics. equivalent device: half bridge r ds(on) 0.18 typ. value @ t j = 25 c 2.8 a max rms load current 5.6 a max ocd threshold
paralleled operation l6226q 22/29 doc id 14335 rev 5 figure 17. paralleling the four half bridges
l6226q output current capability and ic power dissipation doc id 14335 rev 5 23/29 7 output current capability and ic power dissipation in figure 18 and figure 19 are shown the approximate relation between the output current and the ic power dissipation using pwm current control driving two loads, for two different driving types: one full bridge on at a time ( figure 18 ) in which only one load at a time is energized. two full bridges on at the same time ( figure 19 ) in which two loads at the same time are energized. for a given output current and driving type the power dissipated by the ic can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125 c maximum). figure 18. ic power dissipation vs output current with one full bridge on at a time figure 19. ic power dissipation vs output current with two full bridges on at the same time no pwm f sw = 3 0 khz (slow decay) test conditions: supply voltage = 24v i a i b i out i out one full bridge on at a time p d [w] i out [a] 0 0.25 0.5 0.75 1 1.25 1.5 0 2 4 6 8 10 no pwm f sw = 30 khz (slow decay) test conditions: supply volt age = 24 v i a i b i out i out p d [w ] i out [a ] two full bridges on at the same time 0 0.25 0.5 0.75 1 1.25 1.5 0 2 4 6 8 10
thermal management l6226q 24/29 doc id 14335 rev 5 8 thermal management in most applications the power dissipation in the ic is the main factor that sets the maximum current that can be deliver by the device in a safe operating condition. therefore, it has to be taken into account very carefully. besides the available space on the pcb, the right package should be chosen considering the power dissipation. heat sinking can be achieved using copper on the pcb with proper area and thickness. for instance, using a vfqfpn32l 5x5 package the typical r th(ja) is about 42 c/w when mounted on a double-layer fr4 pcb with a dissipating copper surface of 0.5 cm 2 on the top side plus 6 cm 2 ground layer connected through 18 via holes (9 below the ic).
l6226q package mechanical data doc id 14335 rev 5 25/29 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com . ecopack? is an st trademark. note: 1 vfqfpn stands for thermally enhanced very thin profile fine pitch quad flat package no lead. very thin profile: 0.80 < a = 1.00 mm. 2 details of terminal 1 are optional but must be located on the top surface of the package by using either a mold or marked features. table 9. vfqfpn32 5x5x1.0 pitch 0.50 dim. databook (mm) min typ max a 0.80 0.85 0.95 b 0.18 0.25 0.30 b1 0.165 0.175 0.185 d 4.85 5.00 5.15 d2 3.00 3.10 3.20 d3 1.10 1.20 1.30 e 4.85 5.00 5.15 e2 4.20 4.30 4.40 e3 0.60 0.70 0.80 e0.50 l 0.30 0.40 0.50 ddd 0.08
package mechanical data l6226q 26/29 doc id 14335 rev 5 figure 20. package dimensions
l6226q order codes doc id 14335 rev 5 27/29 10 order codes table 10. order code order code package packaging l6226q vfqfpn32 5x5x1.0 tu b e L6226QTR tape and reel
revision history l6226q 28/29 doc id 14335 rev 5 11 revision history table 11. document revision history date revision changes 18-jan-2008 1 first release 10-jun-2008 2 updated: figure 14 on page 18 , figure 15 on page 20 , figure 16 on page 21 and figure 17 on page 22 added: note 1 on page 4 28-jan-2009 3 updated value in table 3: thermal data on page 4 23-sep-2009 4 updated value in table 1: absolute maximum ratings on page 3 30-aug-2010 5 updated ta bl e 1 0
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