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tps65131-q1 slvsbb2d ? may 2012 ? revised october 2014 tps65131-q1 positive- and negative-output dc-dc converter 1 features 3 description 1 ? qualified for automotive applications the tps65131-q1 device is dual-output dc-dc converter generating a positive output voltage up to ? aec-q100 qualified with the following results: 15 v and a negative output voltage down to ? 15 v ? device temperature grade 2: ? 40 c to 105 c with output currents of typically 200 ma, depending ambient operating temperature range on input-voltage to output-voltage ratio. with a total ? electrical characteristics tested over ? 40 c efficiency up to 85%, the device is ideal for portable battery-powered equipment. the input-voltage range to 125 c junction temperature range of 2.7 v to 5.5 v allows, for example, 3.3-v and 5-v ? device hbm esd classification level h2 rails to power the tps65131-q1 device. the ? device cdm esd classification level c4b tps65131-q1 device comes in a qfn-24 package ? dual adjustable output voltages up to 15 v and with thermal pad. requiring few and small external components, the overall solution size can be small. down to ? 15 v ? 2 ? a typical switch-current limit for boost and the converter operates with a fixed-frequency pwm inverter main switches control topology and, with power-save mode enabled, uses a pulse-skipping mode at light load currents. in ? high conversion efficiency operation, the typical overall device quiescent current ? up to 91% at positive output rail is only 500 a. in shutdown, the device draws ? up to 85% at negative output rail typically 0.2 a. independent enable pins allow power-up and power-down sequencing for both ? power-save mode at low load outputs. the device has an internal current limit, ? independent enable inputs for power-up and overvoltage protection, and a thermal shutdown for power-down sequencing highest reliability under fault conditions. ? control output for external pfet to support the tps65131-q1 device is qualified for automotive complete supply disconnect when shut down applications, according to aec-q100 temperature ? 2.7-v to 5.5-v input-voltage range grade 2. the electrical characteristics are tested over ? minimum 1.25-mhz fixed-frequency pwm ? 40 c to 125 c device junction temperature. this, operation combined with lowest shutdown currents, small solution size, package with thermal pad, plus good ? thermal shutdown efficiency and protection features, targets automotive ? overvoltage protection on both outputs and industrial applications. ? 0.2- a typical shutdown current device information (1) ? small 4-mm 4-mm qfn-24 package (rge) part number package body size (nom) 2 applications tps65131-q1 vqfn (24) 4 mm 4 mm ? small- to medium-size oled displays (1) for all available packages, see the orderable addendum. ? (tft) lcd, ccd bias supply application schematic 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. inp vneg cp bsw fbp agnd enn psn inn c1 4.7 f outn tps65131-q1 vpos l2 4.7 h c5 22 f r1 c4 22 f r2 fbn vref r3 r4 cn pgnd psp enp vin d1 d2 q1 c9 c8 220 nf v pos v i v neg l1 4.7 h r7 100 c6 10nf c7 4.7nf c3 100 nf c2 4.7 f c10
tps65131-q1 slvsbb2d ? may 2012 ? revised october 2014 www.ti.com table of contents 8.2 functional block diagram ......................................... 9 1 features .................................................................. 1 8.3 feature description ................................................. 10 2 applications ........................................................... 1 8.4 device functional modes ........................................ 11 3 description ............................................................. 1 9 applications and implementation ...................... 12 4 revision history ..................................................... 2 9.1 application information ............................................ 12 5 pin configuration and functions ......................... 4 9.2 typical applications ................................................ 12 6 specifications ......................................................... 5 10 power supply recommendations ..................... 24 6.1 absolute maximum ratings ...................................... 5 11 layout ................................................................... 24 6.2 handling ratings ....................................................... 5 11.1 layout guidelines ................................................. 24 6.3 recommended operating conditions ....................... 5 11.2 layout example .................................................... 24 6.4 thermal information .................................................. 6 12 device and documentation support ................. 25 6.5 electrical characteristics ........................................... 6 12.1 device support ...................................................... 25 6.6 switching characteristics .......................................... 7 12.2 trademarks ........................................................... 25 6.7 typical characteristics .............................................. 7 12.3 electrostatic discharge caution ............................ 25 7 parameter measurement information .................. 8 12.4 glossary ................................................................ 25 8 detailed description .............................................. 9 13 mechanical, packaging, and orderable 8.1 overview ................................................................... 9 information ........................................................... 25 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision c (march 2014) to revision d page ? global editorial changes bringing the datasheet into the new format .................................................................................... 1 ? changed max. efficiency from 89% to 91% and from 81% to 85% ...................................................................................... 1 ? deleted " minimum 1.25 mhz " ................................................................................................................................................. 1 ? changed 1- a shutdown current to typ. 0.2 a ..................................................................................................................... 1 ? relocated and renamed the pin functions table ................................................................................................................... 4 ? added thermal pad to pin functions table. ............................................................................................................................ 4 ? added thermal pad to absolute maximum ratings. added min./max. values where missing .............................................. 5 ? added v (vin) , v (inn) , v neg , v pos , v (enn) , v (enp) , v (psn) to recommended operating conditions table .................................... 5 ? changed symbol names to jedec compliance ..................................................................................................................... 6 ? added frequency and duty cycles to switching characteristics table. removed from electrical characteristics table ......... 7 ? added rectifier diode selection guide ................................................................................................................................ 15 ? added p-mosfet selection guide ..................................................................................................................................... 15 changes from revision b (february 2013) to revision c page ? added " electrical characteristics tested over ? 40 c to 125 c junction temperature range " ............................................. 1 ? deleted t a table row ............................................................................................................................................................... 5 ? changed i nn to v inn , added pin names vin and inn ............................................................................................................. 5 ? added pin name vpos .......................................................................................................................................................... 5 ? added pin name vneg .......................................................................................................................................................... 5 ? changed i np to v inp , added pin name inp ............................................................................................................................. 5 ? changed " between pins outn to v inn " to " between pins outn to inn " .............................................................................. 5 ? added operating junction temperature ................................................................................................................................... 5 ? added " in applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may reqiuire derating. see thermal information for details. " .............................................. 5 ? deleted " virtual " from " operating virtual junction temperature range " .................................................................................... 5 2 submit documentation feedback copyright ? 2012 ? 2014, texas instruments incorporated product folder links: tps65131-q1
tps65131-q1 www.ti.com slvsbb2d ? may 2012 ? revised october 2014 ? changed electrical characteristics condition statement to " this specification applies over the full recommended input voltage range v i = 2.7 v to 5.5 v and over the temperature range t j = t a = ? 40 c to 125 c unless otherwise noted. typical values apply for v i = 3.6 v and t j = t a = 25 c. " ............................................................................................ 6 ? changed i lim,min = 1800 ma to 1700 ma ................................................................................................................................ 6 ? deleted v pos = 5 v (105 c) row ............................................................................................................................................. 6 ? changed r ds(on)p,max (v pos = 5 v) = 300 m ? to 390 m ? ......................................................................................................... 6 ? changed r ds(on)p,max (v pos = 10 v) = 200 m ? to 230 m ? ....................................................................................................... 6 ? changed i limp,min = 1800 ma to 1700 ma ............................................................................................................................... 6 ? changed i limp,max = 2200 ma to 2250 ma .............................................................................................................................. 6 ? added t a = ? 40 c to 85 c ..................................................................................................................................................... 6 ? changed minimum f = 1250 khz to 1150 khz........................................................................................................................ 7 ? editorially updated block diagram .......................................................................................................................................... 9 ? changed " the maximum recommended junction temperature (t j ) of the tps65131-q1 is 125 c. " to " the recommended device junction temperature range, t j , is -40 c to 125 c. " ......................................................................... 16 ? changed r ja = 37.8 c/w to r ja = 34.1 c/w .................................................................................................................... 16 ? changed " specified regulator operation is ensured to a maximum ambient temperature t a of 105 c. " to " the recommended operating ambient temperature range for the device is t a = ? 40 c to 105 c. " ........................................... 16 ? changed " therefore, the maximum power dissipation is about 1058 mw " to " use equation 13 to calculate the maximum power dissipation, p d max, as a function of t a . in this equation, use t j = 125 c to operate the device within the recommended temperature range, use t j = t (ts) to determine the absolute maximum threshold when the device might go into thermal shutdown. " .............................................................................................................................. 16 ? changed equation 13 ........................................................................................................................................................... 16 changes from revision a (november 2012) to revision b page ? changed cdm esd rating from c3b to c4b. ........................................................................................................................ 1 changes from original (may 2012) to revision a page ? device is going from preview to production ........................................................................................................................... 1 ? added thermal information table values. ................................................................................................................................ 6 ? added v pos = 5 v (105 c) row and values to electrical characteristics table. ...................................................................... 6 copyright ? 2012 ? 2014, texas instruments incorporated submit documentation feedback 3 product folder links: tps65131-q1
tps65131-q1 slvsbb2d ? may 2012 ? revised october 2014 www.ti.com 5 pin configuration and functions 24-pin vqfn with powerpad ? package place rge package place (bottom view) (top view) table 1. pin functions pin i/o description name no. agnd 19 ? analog ground pin bsw 7 o gate-control pin for external battery switch. this pin goes low when enp is set high. cn 18 i/o compensation pin for inverting converter control cp 21 i/o compensation pin for boost converter control enn 10 i enable pin for the negative-output voltage (0 v: disabled, vin: enabled) enp 8 i enable pin for the positive-output voltage (0 v: disabled, vin: enabled) fbn 16 i feedback pin for the negative-output voltage divider fbp 22 i feedback pin for the positive-output voltage divider inn 5, 6 o inverting converter switch pin inp 1, 24 o boost converter switch pin nc (1) 12, 20 ? not connected outn 13, 14 i/o inverting converter switch output pgnd 2, 3 ? power ground pin psn 11 i power-save mode enable for inverter stage (0 v: disabled, vin: enabled) psp 9 i power-save mode enable for boost converter stage (0 v: disabled, vin: enabled) vin 4 i control supply input vneg 15 i negative-output voltage-sense input vpos 23 i positive-output voltage-sense input reference output voltage. bypass this pin with a 220-nf capacitor to ground. connect the lower resistor of the vref 17 o negative-output voltage divider to this pin. thermal pad thermal pad for thermal performance, connect to pgnd (1) (1) nc - no internal connection 4 submit documentation feedback copyright ? 2012 ? 2014, texas instruments incorporated product folder links: tps65131-q1 thermal pad 19 20 21 22 23 24 12 11 10 9 8 7 12 3 4 5 6 1817 16 15 14 13 cn vref fbn vneg outnoutn inppgnd pgnd vin inn inn inp vpos fbp cp nc agnd bsw enp psp enn psn nc nc C no internal connection thermal pad 24 23 22 21 20 19 7 8 9 10 11 12 12 3 4 5 6 1817 16 15 14 13 cnvref fbn vneg outn outn inp pgnd pgnd vin inninn inp vpos fbp cp nc agnd bsw enp psp enn psn nc
tps65131-q1 www.ti.com slvsbb2d ? may 2012 ? revised october 2014 6 specifications 6.1 absolute maximum ratings over operating free-air temperature, unless otherwise noted (1) value unit min max input voltage range at pins vin, inn (2) ? 0.3 6 v voltage at pin vpos (2) ? 0.3 17 v voltage at pin vneg (2) ? 17 v (vin) + 0.3 v voltage at pins enn, enp, fbp, fbn, cn, cp, psp, psn, bsw (2) ? 0.3 v (vin) + 0.3 v input voltage at pin inp (2) ? 0.3 17 v differential voltage between pins outn to inn (2) ? 0.3 24 v thermal pad (2) ? 0.3 0.3 v t j operating junction temperature ? 40 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to the network ground pin, unless otherwise noted. 6.2 handling ratings min max unit t stg storage temperature range ? 65 150 c human body model (hbm), per aec q100-002 (1) ? 2 2 kv v (esd) electrostatic discharge charged device model (cdm), per aec q100-011 ? 750 750 v (1) aec q100-002 indicates hbm stressing is done in accordance with the ansi/esda/jedec js-001 specification. 6.3 recommended operating conditions over operating free-air temperature, unless otherwise noted min max unit v i , v (vin) , application input voltage range, input voltage range at vin and inn pins 2.7 5.5 v v (inn) v pos adjustable output voltage range for the boost converter v i + 0.5 15 v v neg adjustable output voltage range for the inverting converter ? 15 ? 2 v v (enn) , enable signals voltage 0 5.5 v v (enp) v (psn) , power-save mode enable signals voltage 0 5.5 v v (psp) t a operating free-air temperature range (1) ? 40 105 c t j operating junction temperature range ? 40 125 c (1) in applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may require derating. see thermal information for details. copyright ? 2012 ? 2014, texas instruments incorporated submit documentation feedback 5 product folder links: tps65131-q1
tps65131-q1 slvsbb2d ? may 2012 ? revised october 2014 www.ti.com 6.4 thermal information tps65131-q1 thermal metric (1) rge package unit 24 pins r ja junction-to-ambient thermal resistance 34.1 c/w r jctop junction-to-case (top) thermal resistance 36.8 c/w r jb junction-to-board thermal resistance 12.2 c/w jt junction-to-top characterization parameter 0.4 c/w jb junction-to-board characterization parameter 12.3 c/w r jcbot junction-to-case (bottom) thermal resistance 2.8 c/w (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . 6.5 electrical characteristics this specification applies over the full recommended input voltage range v i = 2.7 v to 5.5 v and over the temperature range t j = t a = ? 40 c to 125 c unless otherwise noted. typical values apply for v i = 3.6 v and t j = t a = 25 c. parameter test conditions min typ max unit dc-dc stage (v (vpos) , v (vneg) ) v ref reference voltage i ref = 10 a 1.2 1.213 1.225 v i (fbp) positive feedback input bias current v (fbp) = v ref 50 na i (fbn) negative feedback input bias current v (fbn) = 0.1 v ref 50 na v (fbp) positive feedback regulation voltage 1.189 1.213 1.237 v v (fbn) negative feedback regulation voltage ? 0.024 0 0.024 v total output dc accuracy 3% v (vin) = 3.6 v 440 620 r ds(on)(n) inverter switch on-resistance m ? v (vin) = 5 v 330 530 i (lim-n) inverter switch current limit v (vin) = 3.6 v 1700 1950 2200 ma v (pos) = 5 v 230 390 r ds(on)(p) boost switch on-resistance m ? v (pos) = 10 v 170 230 i (lim-p) boost switch current limit v (vin) = 3.6 v, v (pos) = 8 v 1700 1950 2250 ma control stage high-level input voltage, enp, enn, v ih 1.4 v psp, psn low-level input voltage, enp, enn, v il 0.4 v psp, psn enp, enn, psp, psn connected input current, enp, enn, psp, psn 0.01 0.1 a to gnd or vin r (bsw) output resistance 27 k vin v (vin) = 3.6 v, i (pos) = i (neg) = 0, 300 500 enp = enn = psp = psn = vpos 100 120 i q quiescent current a v (vin) , vneg 100 120 v (pos) = 8 v, v (neg) = ? 5 v enn = enp = low, t a = ? 40 c to i sd shutdown supply current 0.2 1.5 a 85 c v (uvlo) undervoltage lockout threshold 2.1 2.35 2.7 v t (ts) thermal shutdown 150 c t (ts-hys) thermal shutdown hysteresis junction temperature decreasing 5 c 6 submit documentation feedback copyright ? 2012 ? 2014, texas instruments incorporated product folder links: tps65131-q1
tps65131-q1 www.ti.com slvsbb2d ? may 2012 ? revised october 2014 6.6 switching characteristics the specification applies over the full recommended input voltage range v i = 2.7 v to 5.5 v and over the temperature range t j = t a = ? 40 c to 125 c unless otherwise noted. typical values apply for v i = 3.6 v and t j = t a = 25 c. parameter test conditions min typ max unit frequency f oscillator frequency 1150 1380 1500 khz duty cycle d (max-p) maximum-duty-cycle, boost converter 87.5% maximum-duty-cycle, inverting d (max-n) 87.5% converter d (min-p) minimum-duty-cycle, boost converter 12.5% minimum-duty-cycle, inverting d (min-n) 12.5% converter 6.7 typical characteristics at 25 c, unless otherwise noted. figure 1. boost converter (v pos ) maximum output current figure 2. inverting converter (v pos ) output current vs input vs input voltage voltage v i = 3.6 v figure 4. quiescent current (into vin and inn) over input figure 3. shutdown current (into vin and inn) over input voltage voltage copyright ? 2012 ? 2014, texas instruments incorporated submit documentation feedback 7 product folder links: tps65131-q1 temperature ( q c) shutdown current ( p a) -40 -20 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 1.2 d003 v i = 5.5 v v i = 3.3 v temperature ( q c) q u ie sce n t c u rre n t ( p a ) -40 -20 0 20 40 60 80 100 120 240 250 260 270 280 290 300 310 320 330 340 d004 input voltage (v) m a x o u tp u t c u rre n t (a ) 2.5 3 3.5 4 4.5 5 5.5 0 0.1 0.2 0.3 0.4 0.5 0.6 d002 v neg = -10 v v neg = -15 v input voltage (v) m a x o u tp u t c u rre n t (a ) 2.5 3 3.5 4 4.5 5 5.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 d001 v pos = 10.5 v v pos = 15 v
tps65131-q1 slvsbb2d ? may 2012 ? revised october 2014 www.ti.com 7 parameter measurement information table 2. list of components reference setup value, description c1, c2 4.7 f, ceramic, 6.3 v, x5r c3 0.1 f, ceramic, 10 v, x5r c4, c5 4 x 4.7 f, ceramic, 25 v, x7r ? c6 10 nf, ceramic, 16 v, x7r c7 4.7 nf, 50 v, c0g c8 220 nf, ceramic, 6.3 v, x5r v pos = 10.5 v 1 m r1 v pos = 15 v 975 k v pos = 10.5 v 130 k r2 v pos = 15 v 85.8 k v neg = ? 10 v 1 m r3 v neg = ? 15 v 1.3 m v neg = ? 10 v 121.2 k r4 v neg = ? 15 v 104.8 k r7 100 schottky, 1 a, 20 v, onsemi d1, d2 mbrm120 ? l1, l2 4.7 h, epcos b82462-g4472 mosfet, p-channel, 12 v, 4 a, q1 vishay si2323ds figure 5. parameter measurement setup 8 submit documentation feedback copyright ? 2012 ? 2014, texas instruments incorporated product folder links: tps65131-q1 l1 inp vneg cn bsw fbp agnd enn psn inn c1 outn tps65131-q1 vpos l2 c5 r1 c4 r2 fbn vref r3 r4 cp pgnd c6 c7 psp enp vin c3 r7 c2 d1 d2 q1 v i v pos v neg c8
tps65131-q1 www.ti.com slvsbb2d ? may 2012 ? revised october 2014 8 detailed description 8.1 overview the tps65131-q1 is a dual-output dc-dc converter that generates two adjustable output voltages. one output voltage is positive (boost converter), the other is negative (inverting converter). the positive output is adjustable up to 15 v, the negative output is adjustable down to ? 15 v. the device operates with an input voltage range of 2.7 v to 5.5 v. both converters (positive and negative output) work independently of each other. they share a common clock and a common voltage reference. a fixed-frequency, pulse-width-modulated (pwm) regulator controls both outputs separately. in general, each converter operates in continuous-conduction mode (ccm). to improve efficiency at light loads, the converters can operate in discontinuous-conduction mode (dcm). when the power-save mode is enabled, the converters automatically transition between ccm and dcm operation: as the load current decreases, the converter enters dcm mode. power-save mode is individually configurable for both outputs. the transition as a function of the load current works independently for each converter. 8.2 functional block diagram copyright ? 2012 ? 2014, texas instruments incorporated submit documentation feedback 9 product folder links: tps65131-q1 boost converter control inverting converter control oscillator temperature control gate control + - v ref - + gate control vpos inn vin vin vin vin inp enp vin vin psp cp bsw enn psn cn inn agnd vpos fbp vref fbn outn pgnd vneg + -
tps65131-q1 slvsbb2d ? may 2012 ? revised october 2014 www.ti.com 8.3 feature description 8.3.1 power conversion both converters operate in a fixed-frequency, pwm control scheme. the on-time of the internal switches varies depending on the input-to-output voltage ratio and the load. during the on-time, the inductors connected to the converters charge with current. in the remaining time, the off-time with a time period set by the fixed operating frequency, the inductors discharge into the output capacitors through the rectifier diodes. usually at higher loads, the inductor currents are continuous. at lighter loads, the boost converter uses an additional internal switch to allow current to flow back to the input. this avoids inductor current becoming discontinuous in the boost converter. at the inverting converter, during light loads, the inductor current can become discontinuous. in this case, the control circuit of the inverting controller output automatically takes care of these changing conditions to operate always with an optimum control setup. 8.3.2 control the controller circuits of both converters employ a fixed-frequency, multiple-feedforward controller topology. these circuits monitor input voltage, output voltage, and voltage drop across the switches. changes in the operating conditions of the converters directly affect the duty cycle and must not take the indirect and slow way through the output voltage-control loops. a self-learning control corrects measurement errors in this feedforward system. an external capacitor damps the output to avoid output-voltage steps due to output changes of this self- learning control system. the voltage loops, determined by the error amplifiers, must only handle small signal errors. the error amplifiers feature internal compensation. their inputs are the feedback voltages on the fbp and fbn pins. the device uses a comparison of these voltages with the internal reference voltage to generate an accurate and stable output voltage. 8.3.3 output rails enable or disable both converters can be enabled or disabled individually. applying a logic high signal at the enable pins (enp for the boost converter, enn for the inverting converter) enables the corresponding output. after enabling, internal circuitry, necessary to operate the specific converter, then turns on, followed by the soft start . applying a low signal at the enable enp or enn pin shuts down the corresponding converter. when both enable pins are low, the device enters shutdown mode, where all internal circuitry turns off. the device now consumes shutdown current flowing into the vin pin. the output loads of the converters can be disconnected from the input, see load disconnect . 8.3.4 load disconnect the device supports completely disconnecting the load when the converters are disabled. for the inverting converter, the device turns off the internal pmos switch. if the inverting converter is turned off, no dc current path remains which could discharge the battery or supply. this is different for the boost converter. the external rectifying diode, together with the boost inductor, form a dc current path which could discharge the battery or supply if any load connects to the output. the device has no internal switch to prevent current from flowing. for this reason, the device offers a pmos gate control output (bsw) to enable and disable a pmos switch in this dc current path, ideally directly between the boost inductor and battery. to be able to fully disconnect the battery, the forward direction of the parasitic backgate diode of this switch must point to the battery or supply. the external pmos switch, which connects to bsw, turns on when the boost converter is enabled and turns off when the boost converter is disabled. 8.3.5 soft start both converters have implemented soft-start functions. when each converter is enabled, the implemented switch current limit ramps up slowly to its nominal programmed value in typically 1 ms. the device includes this function to limit the input current during start-up to avoid high peak input currents, which could interfere with other systems connected to the same battery or supply. if the application includes the load disconnect pmos switch, a current flows from the input to the output of the boost converter at the moment the pmos switch becomes conducting. 10 submit documentation feedback copyright ? 2012 ? 2014, texas instruments incorporated product folder links: tps65131-q1
tps65131-q1 www.ti.com slvsbb2d ? may 2012 ? revised october 2014 feature description (continued) 8.3.6 overvoltage protection both built-in converters (boost and inverter) have implemented individual overvoltage protection. if the feedback voltage under normal operation exceeds the nominal value by typically 5%, the corresponding converter shuts down immediately to protect any connected circuitry from possible damage. 8.3.7 undervoltage lockout an undervoltage lockout prevents the device from starting up and operating if the supply voltage at the vin pin is lower than the undervoltage lockout threshold. for this case, the device automatically shuts down both converters when the supply voltage at vin falls below this threshold. nevertheless, parts of the control circuits remain active, which is different than device shutdown using en inputs. the device includes the undervoltage lockout function to prevent device malfunction. 8.3.8 overtemperature shutdown the device automatically shuts down both converters if the implemented internal temperature sensor detects a chip temperature above the thermal shutdown temperature. it automatically starts operating again when the chip temperature falls below this threshold plus hysteresis threshold. the built-in hysteresis avoids undefined operation caused by ringing from shutdown and prevents operating at a temperature close to the overtemperature shutdown threshold. 8.4 device functional modes 8.4.1 power-save mode the power-save mode can improve efficiency at light loads. in power-save mode, the converter only operates when the output voltage falls below an device internally set threshold voltage. the converter ramps up the output voltage with one or several operating pulses and goes again into power-save mode once the inductor current becomes discontinuous. the psn and psp logic level selects between power-save mode and continuous-conduction mode. if the specific pins (psp for the boost converter, psn for the inverting converter) are high, the power-save mode for the corresponding converter operates at light loads. similary, a low on the psp pin or psn pin disables the power- save mode for the corresponding converter. copyright ? 2012 ? 2014, texas instruments incorporated submit documentation feedback 11 product folder links: tps65131-q1
tps65131-q1 slvsbb2d ? may 2012 ? revised october 2014 www.ti.com 9 applications and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the tps656131-q1 boost converter output voltage, v pos , and the inverting converter output voltage, v neg , require external components to set the required output voltages. the valid output voltage ranges are as shown in recommended operating conditions ). the passages below show typical application examples with different output voltage settings and guidance for external component choices. 9.2 typical applications 9.2.1 tps65131-q1 with v pos = 10.5 v, v neg = ? 10 v figure 6. typical application schematic with v pos = 10.5 v, v neg = ? 10 v 9.2.1.1 design requirements this design example uses the following parameters: table 3. design parameters design parameter example value input voltage range 2.7 v to 5.5 v r1 = 1 m boost converter output r2 = 130 k 10.5 v voltage, v pos c9 = 6.8 pf r3 = 1 m inverting converter output r4 = 121.2 k ? 10 v voltage, v neg c10 = 7.5 pf 12 submit documentation feedback copyright ? 2012 ? 2014, texas instruments incorporated product folder links: tps65131-q1 inp vneg cp bsw fbp agnd enn psn inn c1 4.7 f outn tps65131-q1 vpos l2 4.7 h c5 22 f r1 c4 22 f r2 fbn vref r3 r4 cn pgnd psp enp vin d1 d2 q1 c9 c8 220 nf v pos v i v neg l1 4.7 h r7 100 c6 10nf c7 4.7nf c3 100 nf c2 4.7 f c10
tps65131-q1 www.ti.com slvsbb2d ? may 2012 ? revised october 2014 in this example, the converters operate with power-save mode both enabled and disabled (see power-save mode ). 9.2.1.2 detailed design procedure 9.2.1.2.1 programming the output voltage 9.2.1.2.1.1 boost converter an external resistor divider adjusts the output voltage of the tps65131-q1 boost converter stage. connect this divider to the fbp pin. the typical value of the voltage at the fbp pin is the reference voltage, which is 1.213 v. the maximum recommended output voltage at the boost converter is 15 v. to achieve appropriate accuracy, the current through the feedback divider should be about 100 times higher than the current into the fbp pin. typical current into the fbp pin is 0.05 a, and the voltage across r2 is 1.213 v. based on those values, the recommended value for r2 should be lower than 200 k in order to set the divider current at 5 a or higher. calculate the value of resistor r1, as a function of the needed output voltage (v pos ), with equation 1 : (1) in this example, with r2 = 130 k , choose r1 = 1 m to set v pos = 10.5 v. 9.2.1.2.1.2 inverting converter an external resistor divider adjusts the output voltage of the tps65131-q1 inverting converter stage. connect this divider to the fbn pin. unlike the feedback divider at the boost converter, the reference point of the feedback divider is not gnd, but v ref . so the typical value of the voltage at the fbn pin is 0 v. the minimum recommended output voltage at the inverting converter is ? 15 v. feedback divider current considerations are similar to the considerations for the boost converter. for the same reasons, the feedback divider current should be in the range of 5 a or higher. the voltage across r4 is 1.213 v. based on those values, the recommended value for r4 should be lower than 200 k in order to set the divider current at the required value. calculate the value of resistor r3, as a function of the needed output voltage (v neg ), with equation 2 : (2) in this example, with r4 = 121.2 k k , choose r3 = 1 m to set v neg = ? 10 v. 9.2.1.2.2 inductor selection an inductive converter normally requires two main passive components to store energy during the conversion. therefore, each converter requires an inductor and a storage capacitor. to select the right inductor, it is recommended to keep the possible peak inductor current below the current-limit threshold of the power switch in the chosen configuration. for example, the current-limit threshold of the switch for the boost converter and for the inverting converters is nominally 1950 ma. the highest peak current through the switches and the inductor depends on the output load (i pos , i neg ), the input voltage (v i ), and the output voltages (v pos , v neg ). use equation 3 to estimate the peak inductor current in the boost converter, i (l-p) . equation 4 shows the corresponding formula for the inverting converter, i (l-n) . (3) (4) the second parameter for choosing the inductor is the desired current ripple in the inductor. normally, it is advisable to work with a ripple of less than 20% of the average inductor current. a smaller ripple reduces the losses in the inductor, as well as output voltage ripple and emi. but in the same way, output voltage regulation gets slower, causing higher voltage changes during fast load changes. in addition, a larger inductor usually increases the total system cost. keep those parameters in mind and calculate the possible inductor value with equation 5 for the boost converter (l1) and equation 6 for the inverting converter (l2). copyright ? 2012 ? 2014, texas instruments incorporated submit documentation feedback 13 product folder links: tps65131-q1 pos (l p) pos i v i i v 0.64 u u neg ref v r3 r4 v u ? ? 1 pos ref v r1 r2 1 v u ? ? 1 i neg (l n) neg i v v i i v 0.64 u u
tps65131-q1 slvsbb2d ? may 2012 ? revised october 2014 www.ti.com (5) (6) the parameter f is the switching frequency. for the boost converter, i (l-p) is the ripple current in the inductor, that is, 20% of i (l-p) . accordingly, for the inverting converter, i (l-n) is the ripple current in the inductor, that is, 20% of i (l-n) . v i is the input voltage, which is 3.3 v in this example. so, the calculated inductance value for the boost inductor is 5.1 h and for the inverting converter inductor is 5.1 h. with these calculated values and the calculated currents, it is possible to choose a suitable inductor. in typical applications, the recommendation is to choose a 4.7- h inductor. the device is optimized to work with inductance values between 3.3 h and 6.8 h. nevertheless, operation with higher inductance values may be possible in some applications. perform detailed stability analysis in this case. be aware of the possibility that load transients and losses in the circuit can lead to higher currents than estimated in equation 3 and equation 4 . also, the losses caused by magnetic hysteresis and conductor resistance are a major parameter for total circuit efficiency. the following table shows inductors from different suppliers used with the tps65131-q1 converter: table 4. list of inductors vendor inductor series epcos b8246284-g4 7447789xxx wurth elektronik 744031xxx vlf3010 tdk vlf4012 cooper electronics technologies sd12 9.2.1.2.3 capacitor selection 9.2.1.2.3.1 input capacitor as a recommendation, choose an input capacitors of at least 4.7 f for the input of the boost converter (inp) and accordingly for the input of the inverting converter (inn). this improves transient behavior of the regulators and emi behavior of the total power-supply circuit. choose a ceramic capacitor or a tantalum capacitor. for the use of a tantalum capcitor, an additonal, smaller ceramic capacitor (100 nf) in parallel is required. place the input capacitor(s) close to the input pins. 9.2.1.2.3.2 output capacitors one of the major parameters necessary to define the capacitance value of the output capacitor is the maximum allowed output voltage ripple of the converter. two parameters, which are the capacitance and the equivalent series resitance (esr), affect this ripple. it is possible to calculate the minimum capacitance needed for the defined ripple, supposing that the esr is zero. use equation 7 for the boost-converter output capacitor (c4min) and equation 8 for the inverting-converter output capacitor (c5min). (7) (8) the parameter f is the switching frequency. v pos and v neg are the maximum allowed ripple voltages for each converter. choosing a ripple voltage in the range of 10 mv requires a minimum capacitance of 12 f. the total ripple is larger due to the esr of the output capacitor. use equation 9 for the boost converter and equation 10 for the inverting converter to calculate this additional ripple component. 14 submit documentation feedback copyright ? 2012 ? 2014, texas instruments incorporated product folder links: tps65131-q1 neg neg neg neg i i v c5min f v v v u u ' u pos pos i pos pos i v v c4min f v v u u ' u i neg (l n) neg i v v l2 i f v v u ' u u i pos i (l p) pos v v v l1 i f v u ' u u
tps65131-q1 www.ti.com slvsbb2d ? may 2012 ? revised october 2014 (9) (10) in this example, an additional ripple of 2 mv is the result of using a typical ceramic capacitor with an esr in the 10-m range. the total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the esr of the capacitor. in this example, the total ripple is 10 mv. load transients can create additional ripple. when the load current increases rapidly, the output capacitor must provide the additional current until the inductor current increases by the control loop which sets a higher on-time (duty cycle) of the main switch. the higher duty cycle results in longer inductor charging periods. the inductance itself also limits the rate of increase of the inductor current. when the load current decreases rapidly, the output capacitor must store the excess energy (stored in the inductor) until the regulator has decreased the inductor current by reducing the duty cycle. the recommendation is to use higher capacitance values, as the foregoing calculations show. 9.2.1.2.4 rectifier diode selection both converters (the boost and inverting converter) require rectifier diodes, d1 and d2. as a recommendation, to reduce losses, use schottky diodes. the forward current rating needed is equal to the maximum output current. consider that the maximum currents, i pos max and i neg max, might differ for v pos and v neg when choosing the diodes. 9.2.1.2.5 external p-mosfet selection during shutdown, when connected to a power supply, a path from the power supply to the positive output conducts through the inductor and an external diode. optionally, in oder to fully disconnect the positive output v pos during shutdown, add an external p-mosfet (q1). the bsw pin controls the gate of the p-mosfet. when choosing a proper p-mosfet, the v gs and v gd voltage ratings must cover the input voltage range, the drain current rating must not be lower than the maximum input current flowing into the application, and conditions of the p-mosfet operating area must fit. if there is no intention to use an external p-mosfet, leave the bsw pin floating. 9.2.1.2.6 stabilizing the control loop 9.2.1.2.6.1 feedforward capacitors as a recommendation, to speed up the control loop, place feedforward capacitors in the feedback divider, parallel to r1 (boost converter) and r3 (inverting converter). equation 11 shows how to calculate the appropriate value for the boost converter, and equation 12 for the inverting converter. (11) (12) in this application example, c9 = 6.8 pf and c10 = 7.5 pf match the choices of r1 and r3. to avoid coupling noise into the control loop from the feedforward capacitors, it is possible to place a series resistor to limit the bandwidth of the feedforward effect. any value between 10 k ? and 100 k ? is suitable. the higher the resistance, the lower the noise coupled into the control loop system. 9.2.1.2.6.2 compensation capacitors the device features completely internally compensated control loops for both converters. the internal feedforward system has built-in error correction which requires external capacitors. as a recommendation, use a 10-nf capacitor at the cp pin of the boost converter and a 4.7-nf capacitor at the cn pin of the inverting converter. copyright ? 2012 ? 2014, texas instruments incorporated submit documentation feedback 15 product folder links: tps65131-q1 7.5 v c10 r3 6.8 v c9 r1 (esr n) neg (esr c5) v i r ' u (esr p) pos (esr c4) v i r ' u
tps65131-q1 slvsbb2d ? may 2012 ? revised october 2014 www.ti.com 9.2.1.3 thermal information implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. many system-dependent issues, such as thermal coupling, airflow, added heatsinks and convection surfaces, and the presence of heat-generating components affect the power- dissipation limits of a given component. three basic approaches for enhancing thermal performance follow. ? improving the power dissipation capability of the pcb design ? improving the thermal coupling of the component to the pcb ? introducing airflow to the system the recommended device junction temperature range, t j , is ? 40 c to 125 c. the thermal resistance of the 24- pin qfn, 4 ? mm 4 ? mm package (rge) is r ja = 34.1 c/w . the recommended operating ambient temperature range for the device is t a = ? 40 c to 105 c. use equation 13 to calculate the maximum power dissipation, p d max, as a function of t a . in this equation, use t j = 125 c to operate the device within the recommended temperature range, use t j = t (ts) to determine the absolute maximum threshold when the device might go into thermal shutdown. if the maximum ambient temperature of the application is lower, more heat dissipation is possible. (13) 9.2.1.4 application curves v i = 3.3 v v pos = 10.5 v power-save mode v i = 5 v v pos = 10.5 v power-save mode on and off on and off figure 7. boost converter (v pos ) efficiency vs output figure 8. boost converter (v pos ) efficiency vs output current current 16 submit documentation feedback copyright ? 2012 ? 2014, texas instruments incorporated product folder links: tps65131-q1 output current (a) efficiency (%) 0.001 0.01 0.1 1 0 10 20 30 40 50 60 70 80 90 100 d005 v pos = 10.5 v psm off v pos = 10.5 v psm on output current (a) efficiency (%) 0.001 0.01 0.1 1 0 10 20 30 40 50 60 70 80 90 100 d006 v pos = 10.5 v psm off v pos = 10.5 v psm on j a d ja t t p max r t
tps65131-q1 www.ti.com slvsbb2d ? may 2012 ? revised october 2014 v i = 3.3 v v neg = ? 10 v power-save mode v i = 5 v v neg = ? 10 v power-save mode on and off on and off figure 9. inverting converter (v neg ) efficiency vs output figure 10. inverting converter (v neg ) efficiency vs output current current v i = 3.3 v v pos = 10.5 v power-save mode v i = 5 v v pos = 10.5 v power-save mode on and off on and off figure 11. boost converter (v pos ) output voltage vs figure 12. boost converter (v pos ) output voltage vs output current output current v i = 3.3 v v neg = ? 10 v power-save mode v i = 5 v v neg = ? 10 v power-save mode on and off on and off figure 13. inverting converter (v neg ) output voltage vs figure 14. inverting converter (v neg ) output voltage vs output current output current copyright ? 2012 ? 2014, texas instruments incorporated submit documentation feedback 17 product folder links: tps65131-q1 output current (a) output voltage (v) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 -10.5 -10.4 -10.3 -10.2 -10.1 -10 -9.9 -9.8 -9.7 -9.6 -9.5 d011 v neg = -10 v psm off v neg = -10 v psm on output current (a) output voltage (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 -10.5 -10.4 -10.3 -10.2 -10.1 -10 -9.9 -9.8 -9.7 -9.6 -9.5 d012 v neg = -10 v psm off v neg = -10 v psm on output current (a) output voltage (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11 d009 v pos = 10.5 v psm off v pos = 10.5 v psm on output current (a) output voltage (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11 d010 v pos = 10.5 v psm off v pos = 10.5 v psm on output current (a) efficiency (%) 0.001 0.01 0.1 1 0 10 20 30 40 50 60 70 80 90 100 d007 v neg = -10 v psm off v neg = -10 v psm on output current (a) efficiency (%) 0.001 0.01 0.1 1 0 10 20 30 40 50 60 70 80 90 100 d008 v neg = -10 v psm off v neg = -10 v psm on
tps65131-q1 slvsbb2d ? may 2012 ? revised october 2014 www.ti.com v i = 3.3 v v pos = 10.5 v power-save mode v i = 3.3 v v pos = 10.5 v power-save mode off on i pos = 200 ma i pos = 20 ma figure 15. boost converter (v pos ) output ripple figure 16. boost converter (v pos ) output ripple v i = 3.3 v v neg = ? 10 v power-save mode v i = 3.3 v v neg = ? 10 v power-save mode off on i neg = 200 ma i neg = 20 ma figure 17. inverting converter (v neg ) output ripple figure 18. inverting converter (v neg ) output ripple v i = 3.3 v v pos = 10.5 v v i = 3.3 v v neg = ? 10 v i pos = 200 ma to 250 ma i neg = 150 ma to 200 ma figure 19. boost converter (v pos ) load transient figure 20. inverting converter (v neg ) load transient response response 18 submit documentation feedback copyright ? 2012 ? 2014, texas instruments incorporated product folder links: tps65131-q1 time = 1 s/div output voltage 10 mv/div inductor current 100 ma/div time = 40 s/div output voltage 10 mv/div inductor current 100 ma/div time = 400 ns/div output voltage 10 mv/div inductor current 200 ma/div time = 20 s/div output voltage 50 mv/div inductor current 200 ma/div time = 1 ms/div output voltage 50 mv/div output current 20 ma/div offset = 200 ma time = 1 ms/div output voltage 100 mv/div output current 20 ma/div offset = 150 ma
tps65131-q1 www.ti.com slvsbb2d ? may 2012 ? revised october 2014 v i = 3 v to 3.6 v v pos = 10.5 v i pos = 150 ma v i = 3 v to 3.6 v v neg = ? 10 v i neg = 100 ma figure 21. boost converter (v pos ) line transient figure 22. inverting (v neg ) converter line transient response response v i = 3.3 v v pos = 10.5 v i pos = 46 ma v i = 3.3 v v neg = ? 10 v i neg = 150 ma figure 23. boost converter (v pos ) start-up into load figure 24. inverting converter (v neg ) start-up into load v i = 3.3 v v pos = 10.5 v v neg = ? 10 v i pos = i neg = 160 ma figure 25. boost and inverting converter start-up into load copyright ? 2012 ? 2014, texas instruments incorporated submit documentation feedback 19 product folder links: tps65131-q1 time = 1 ms/div output voltage, boost converter 5 v/div enabling inverter converter 2 v/div output voltage, inverting converter 10 v/div enabling boost converter 2 v/div time = 200 s/div output voltage 5 v/div input voltage 2 v/div inductor current 500 ma/div voltage at switching pin 10 v/div time = 400 s/div output voltage 5 v/div input voltage 2 v/div inductor current 1 a/div voltage at switching pin 10 v/div time = 2 ms/div output voltage 200 mv/div input voltage 500 mv/div offset = 3 v time = 2 ms/div output voltage 500 mv/div input voltage 500 mv/div offset = 3 v
tps65131-q1 slvsbb2d ? may 2012 ? revised october 2014 www.ti.com 9.2.2 tps65131-q1 with v pos = 5.5 v, v neg = ? 5 v 9.2.2.1 design requirements the design procedure for this setup is similar to the first example, see detailed design procedure . change the feedback dividers to set the output voltage, see programming the output voltage . further, choose the feed- forward capacitors according to feedforward capacitors . table 5 shows the components being changed. see figure 6 . table 5. design parameters design parameter example value input voltage range 2.7 v to 5.5 v r1 = 390 k boost converter output r2 = 110 k 5.5 v voltage, v pos c9 = 18 pf r3 = 620 k inverting converter output r4 = 150 k ? 5 v voltage, v neg c10 = 12 pf in this example, the converters are operated with power-save mode both enabled and disabled (see power-save mode ). 9.2.2.2 application curves v i = 3.3 v v pos = 5.5 v power-save mode v i = 5 v v pos = 5.5 v power-save mode on and off on and off figure 26. boost converter (v pos ) efficiency vs output figure 27. boost converter (v pos ) efficiency vs output current current 20 submit documentation feedback copyright ? 2012 ? 2014, texas instruments incorporated product folder links: tps65131-q1 output current (a) efficiency (%) 0.001 0.01 0.1 1 0 10 20 30 40 50 60 70 80 90 100 d013 v pos = 5.5 v psm off v pos = 5.5 v psm on output current (a) efficiency (%) 0.001 0.01 0.1 1 0 10 20 30 40 50 60 70 80 90 100 d014 v pos = 5.5 v psm off v pos = 5.5 v psm on
tps65131-q1 www.ti.com slvsbb2d ? may 2012 ? revised october 2014 v i = 3.3 v v neg = ? 5 v power-save mode v i = 5 v v neg = ? 5 v power-save mode on and off on and off figure 28. inverting converter (v neg ) efficiency vs output figure 29. inverting converter (v neg ) efficiency vs output current current v i = 3.3 v v pos = 5.5 v power-save mode v i = 5 v v pos = 5.5 v power-save mode on and off on and off figure 30. boost converter (v pos ) output voltage vs figure 31. boost converter (v pos ) output voltage vs output current output current v i = 3.3 v v neg = ? 5 v power-save mode v i = 3.3 v v neg = ? 5 v power-save mode on and off on and off figure 32. inverting converter (v neg ) output voltage vs figure 33. inverting converter (v neg ) output voltage vs output current output current copyright ? 2012 ? 2014, texas instruments incorporated submit documentation feedback 21 product folder links: tps65131-q1 output current (a) output voltage (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 -5.5 -5.4 -5.3 -5.2 -5.1 -5 -4.9 -4.8 -4.7 -4.6 -4.5 d019 v neg = -5 v psm off v neg = -5 v psm on output current (a) output voltage (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -5.5 -5.4 -5.3 -5.2 -5.1 -5 -4.9 -4.8 -4.7 -4.6 -4.5 d020 v neg = -5 v psm off v neg = -5 v psm on output current (a) output voltage (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6 d017 v pos = 5.5 v psm off v pos = 5.5 v psm on output current (a) output voltage (v) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6 d018 v pos = 5.5 v psm off v pos = 5.5 v psm on output current (a) efficiency (%) 0.001 0.01 0.1 1 0 10 20 30 40 50 60 70 80 90 100 d015 v neg = -5 v psm off v neg = -5 v psm on output current (a) efficiency (%) 0.001 0.01 0.1 1 0 10 20 30 40 50 60 70 80 90 100 d016 v neg = -5 v psm off v neg = -5 v psm on
tps65131-q1 slvsbb2d ? may 2012 ? revised october 2014 www.ti.com 9.2.3 tps65131-q1 with v pos = 15 v, v neg = ? 15 v 9.2.3.1 design requirements the design procedure for this setup is similar to the first example, see detailed design procedure . change the feedback dividers to set the output voltage, see programming the output voltage . further, choose the feedforward capacitors according to feedforward capacitors . table 6 shows the components being changed. see figure 6 . table 6. design parameters design parameter example value input voltage range 2.7 v to 5.5 v r1 = 975 k boost converter output r2 = 85.8 k 15 v voltage, v pos c9 = 6.8 pf r3 = 1.3 m inverting converter output r4 = 104.8 k ? 15 v voltage, v neg c10 = 5.6 pf in this example, the converters operate with power-save mode both enabled and disabled (see power-save mode ). 9.2.3.2 application curves v i = 3.3 v v pos = 15 v power-save mode v i = 5 v v pos = 15 v power-save mode on and off on and off figure 34. boost converter (v pos ) efficiency vs output figure 35. boost converter (v pos ) efficiency vs output current current 22 submit documentation feedback copyright ? 2012 ? 2014, texas instruments incorporated product folder links: tps65131-q1 output current (a) efficiency (%) 0.001 0.01 0.1 1 0 10 20 30 40 50 60 70 80 90 100 d021 v pos = 15 v psm off v pos = 15 v psm on output current (a) efficiency (%) 0.001 0.01 0.1 1 0 10 20 30 40 50 60 70 80 90 100 d022 v pos = 15 v psm off v pos = 15 v psm on
tps65131-q1 www.ti.com slvsbb2d ? may 2012 ? revised october 2014 v i = 3.3 v v neg = ? 15 v power-save mode v i = 5 v v neg = ? 15 v power-save mode on and off on and off figure 36. inverting converter (v neg ) efficiency vs output figure 37. inverting converter (v neg ) efficiency vs output current current v i = 3.3 v v pos = 15 v power-save mode v i = 5 v v pos = 15 v power-save mode on and off on and off figure 38. boost converter (v pos ) output voltage vs figure 39. boost converter (v pos ) output voltage vs output current output current v i = 3.3 v v neg = ? 15 v power-save mode v i = 5 v v neg = ? 15 v power-save mode on and off on and off figure 40. inverting converter (v neg ) output voltage vs figure 41. inverting converter (v neg ) output voltage vs output current output current copyright ? 2012 ? 2014, texas instruments incorporated submit documentation feedback 23 product folder links: tps65131-q1 output current (a) output voltage (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 14.5 14.6 14.7 14.8 14.9 15 15.1 15.2 15.3 15.4 15.5 d026 v pos = 15 v psm off v pos = 15 v psm on output current (a) efficiency (%) 0.001 0.01 0.1 1 0 10 20 30 40 50 60 70 80 90 100 d023 v neg = -15 v psm off v neg = -15 v psm on output current (a) efficiency (%) 0.001 0.01 0.1 1 0 10 20 30 40 50 60 70 80 90 100 d024 v neg = -15 v psm off v neg = -15 v psm on output current (a) output voltage (v) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 -15.5 -15.4 -15.3 -15.2 -15.1 -15 -14.9 -14.8 -14.7 -14.6 -14.5 d027 v neg = -15 v psm off v neg = -15 v psm on output current (a) output voltage (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 -15.5 -15.4 -15.3 -15.2 -15.1 -15 -14.9 -14.8 -14.7 -14.6 -14.5 d028 v neg = -15 v psm off v neg = -15 v psm on output current (a) output voltage (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 14.5 14.6 14.7 14.8 14.9 15 15.1 15.2 15.3 15.4 15.5 d025 v pos = 15 v psm off v pos = 15 v psm on
tps65131-q1 slvsbb2d ? may 2012 ? revised october 2014 www.ti.com 10 power supply recommendations the tps65131-q1 input voltage ranges from 2.7 v to 5.5 v. consequently, the supply can come, for example, from a 3.3-v or 5-v rail. if the device starts into load during the soft start phase, the drawn input current can be higher than during post-start operation. consider the application requirements when selecting the power supply. to avoid unintended toggling of the undervoltage lockout , connect the tps65131-q1 via a low-impedance path to the power supply. 11 layout 11.1 layout guidelines as for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. improper layout might show the symptoms of poor line or load regulation, ground and output voltage shifts, stability issues, unsatisfying emi behavior or worsened efficiency. therefore, use wide and short traces for the main current paths and for the power ground tracks. the input capacitors (c1, c2, c3), output capacitors (c4, c5), the inductors (l1, l2), and the rectifying diodes (d1, d2) should be placed as close as possible to the ic to keep parasitic inductances low. use a wide pgnd plane. connect the analog ground pin (agnd) to the pgnd plane. further, connect the pgnd plane with the exposed thermal pad. place the feedback dividers as close as possible to the control pin (boost converter) or the vref pin (inverting converter) of the ic. figure 42 provides an layout example which is recommended to be followed. 11.2 layout example figure 42. tps65131-q1 layout recommendation 24 submit documentation feedback copyright ? 2012 ? 2014, texas instruments incorporated product folder links: tps65131-q1 c7 19 20 21 22 23 24 12 11 10 9 8 7 18 17 16 15 14 13 1 2 3 4 5 6 v neg v pos pgnd v i c6 r3 r4 c8 d2 l2 u1 r2 r1 c9 d1 l1 c4 r7 c3 c2 c1 q1 pgnd pgnd inp pgnd psn nc enn psp enp bsw pgnd vin inn inn outn outn vneg fbn vref cn agnd nc cp fbp vpos inp c5 c10
tps65131-q1 www.ti.com slvsbb2d ? may 2012 ? revised october 2014 12 device and documentation support 12.1 device support 12.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 12.2 trademarks powerpad is a trademark of texas instruments. 12.3 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.4 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical packaging and orderable information. this information is the most- current data available for the designated device. this data is subject to change without notice and without revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. copyright ? 2012 ? 2014, texas instruments incorporated submit documentation feedback 25 product folder links: tps65131-q1
package option addendum www.ti.com 9-aug-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TPS65131TRGERQ1 active vqfn rge 24 3000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 2u65131 q1 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 9-aug-2016 addendum-page 2 other qualified versions of tps65131-q1 : ? catalog: tps65131 note: qualified version definitions: ? catalog - ti's standard catalog product
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS65131TRGERQ1 vqfn rge 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 q2 package materials information www.ti.com 24-feb-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS65131TRGERQ1 vqfn rge 24 3000 367.0 367.0 35.0 package materials information www.ti.com 24-feb-2015 pack materials-page 2

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