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32-bit arm ? cortex?-m3 microcontroller, up to 64kb flash and 16kb sram with 1 msps adc, usart, uart, spi, i 2 c, i 2 s, mctm, gptm, bftm, pdma, sci, crc, ebi and usb2.0 fs HT32F1653/ht32f1654 series datasheet revision: v1.00 date: ? an ? a ?? ??? ? 01 ? ? an ? a ?? ??? ? 01 ?
rev. 1.00 ? of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 table of contents table of contents 1 general description ........... ..................................................................................... 6 2 features ................................................................................................................... 7 co ? e ....................................................................................................................................... 7 on-chip memo ?? .................................................................................................................... 7 flash memo ?? cont ? olle ? C fmc ............ ................................................................................ 7 reset cont ? ol unit C rstcu ................................................................................................. ? clock cont ? ol unit C ckcu ............ ........................................................................................ ? powe ? management C pwrcu ............................................................................................. ? exte ? nal inte ??? pt/event cont ? olle ? C exti ............................................................................ 9 analog to digital conve ? te ? C adc ........................................................................................ 9 analog compa ? ato ? C cmp ............ ........................................................................................ 9 i/o po ? ts ............ ................................................................................................................... 10 pwm gene ? ation and capt ?? e time ? s C gptm .................................................................. 10 moto ? cont ? ol time ? C mctm .............................................................................................. 11 basic f ? nction time ? C bftm ............................................................................................. 11 watchdog time ? C wdt ....................................................................................................... 1 ? real time clock C rtc ....................................................................................................... 1 ? inte ? -integ ? ated ci ? c ? it C i ? c ................................................................................................ 13 se ? ial pe ? iphe ? al inte ? face C spi ......................................................................................... 13 unive ? sal s ? nch ? ono ? s as ? nch ? ono ? s receive ? t ? ansmitte ? C usart .............................. 14 unive ? sal as ? nch ? ono ? s receive ? t ? ansmitte ? C uart ...................................................... 1 ? sma ? t ca ? d inte ? face C sci ................................................................................................. 1 ? inte ? -ic so ? nd C i ? s ............................................................................................................. 16 c ? clic red ? ndanc ? check C crc ....................................................................................... 16 pe ? iphe ? al di ? ect memo ?? access C pdma ......................................................................... 17 exte ? nal b ? s inte ? face C ebi ............ .................................................................................... 17 unive ? sal se ? ial b ? s device cont ? olle ? C usb .................................................................... 1 ? deb ? g s ? ppo ? t ..................................................................................................................... 1 ? package and ope ? ation tempe ? at ?? e .................................................................................. 1 ? 3 overview ................................................................................................................ 19 device info ? mation ............................................................................................................... 19 block diag ? am ..................................................................................................................... ? 0 memo ?? map ........................................................................................................................ ? 1 clock st ?? ct ?? e ........... ......................................................................................................... ??
rev. 1.00 3 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 table of contents table of contents 4 pin assignment ..................................................................................................... 23 5 electrical characteristics ..................................................................................... 29 absol ? te maxim ? m ratings ................................................................................................. ? 9 recommended dc ope ? ating conditions ........................................................................... ? 9 on-chip ldo voltage reg ? lato ? cha ? acte ? istics ................................................................. ? 9 powe ? cons ? mption ............................................................................................................ 30 reset and s ? ppl ? monito ? cha ? acte ? istics ........................................................................... 31 exte ? nal clock cha ? acte ? istics ............................................................................................. 31 inte ? nal clock cha ? acte ? istics .............................................................................................. 3 ? pll cha ? acte ? istics .............................................................................................................. 33 memo ?? cha ? acte ? istics ....................................................................................................... 33 i/o po ? t cha ? acte ? istics ........................................................................................................ 34 adc cha ? acte ? istics ........... ................................................................................................. 3 ? compa ? ato ? cha ? acte ? istics ................................................................................................. 37 gptm/mctm cha ? acte ? istics .............................................................................................. 37 i ? c cha ? acte ? istics ............................................................................................................... 3 ? spi cha ? acte ? istics ........... ................................................................................................... 39 i ? s cha ? acte ? istics ............................................................................................................... 40 usb cha ? acte ? istics ............................................................................................................. 4 ? 6 package information ............................................................................................ 43 4 ? -pin lqfp (7mm7mm) o ? tline dimensions ................................................................... 44 64-pin lqfp (7mm7mm) o ? tline dimensions ................................................................... 4 ?
rev. 1.00 4 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 list of tables list of tables table 1 ht3 ? f16 ? 4/16 ? 3 se ? ies feat ?? es and pe ? iphe ? al list ....... ........................................................ 19 table ? ht3 ? f16 ? 4/16 ? 3 se ? ies pin assignment fo ? lqfp 64 / 4 ? package ......................................... ?? table 3 ht3 ? f16 ? 4/16 ? 3 pin desc ? iption ...... ......................................................................................... ? 7 table 4 absol ? te maxim ? m ratings ......................................................................................................... ? 9 table ? recommended dc ope ? ating conditions ................................................................................... ? 9 table 6 ldo cha ? acte ? istics ...... .............................................................................................................. ? 9 table 7 powe ? cons ? mption cha ? acte ? istics ........................................................................................... 30 table ? lvd/bod cha ? acte ? istics ....... ..................................................................................................... 31 table 9 high speed exte ? nal clock (hse) cha ? acte ? istics ...................................................................... 31 table 10 low speed exte ? nal clock (lse) cha ? acte ? istics ..................................................................... 3 ? table 11 high speed inte ? nal clock (hsi) cha ? acte ? istics ....................................................................... 3 ? table 1 ? low speed inte ? nal clock (lsi) cha ? acte ? istics ........................................................................ 33 table 13 pll cha ? acte ? istics ................................................................................................................... 33 table 14 flash memo ?? cha ? acte ? istics ................................................................................................... 33 table 1 ? i/o po ? t cha ? acte ? istics ............................................................................................................. 34 table 16 adc cha ? acte ? istics .................................................................................................................. 3 ? table 17 compa ? ato ? cha ? acte ? istics ...................................................................................................... 37 table 1 ? gptm/mctm cha ? acte ? istics ................................................................................................... 37 table 19 i ? c cha ? acte ? istics ..................................................................................................................... 3 ? table ? 0 spi cha ? acte ? istics .................................................................................................................... 39 table ? 1 i ? s cha ? acte ? istics ..................................................................................................................... 40 table ?? usb dc elect ? ical cha ? acte ? istics ............................................................................................ 4 ? table ? 3 usb ac elect ? ical cha ? acte ? istics ............................................................................................. 4 ?
rev. 1.00 ? of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 list of tables list of figures list of figures fig ?? e 1 ht3 ? f16 ? 4/16 ? 3 block diag ? am .............................................................................................. ? 0 fig ?? e ? ht3 ? f16 ? 4/16 ? 3 memo ?? map ................................................................................................. ? 1 fig ?? e 3 ht3 ? f16 ? 4/16 ? 3 clock st ?? ct ?? e ............................................................................................. ?? fig ?? e 4 ht3 ? f16 ? 4/16 ? 3 lqfp-4 ? pin assignment ............................................................................. ? 3 fig ?? e ? ht3 ? f16 ? 4/16 ? 3 lqfp-64 pin assignment ............................................................................. ? 4 fig ?? e 6 adc sampling netwo ? k model .................................................................................................. 36 fig ?? e 7 i ? c timing diag ? ams ....... ........................................................................................................... 3 ? fig ?? e ? spi timing diag ? ams - spi maste ? mode .................................................................................. 39 fig ?? e 9 spi timing diag ? ams - spi slave mode with cpha=1 ............................................................. 40 fig ?? e 10 timing of i ? s maste ? mode ...................................................................................................... 41 fig ?? e 11 timing of i ? s slave mode ....... .................................................................................................. 41 figure 12 usb signal rise time and fall time and cross-point voltage (vcrs) defnition ...... ........... 4 ?
rev. 1.00 6 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 general description 1 general description the holtek ht32f1654/1653 devices are high performance, low power consumption 32-bit microcontrollers based around an arm ? cortex?-m3 processor core. the cortex?-m3 is a next- generation processor core which is tightly coupled with a nested vectored interrupt controller (nvic), systick timer and which includes advanced debug support. the devices operate at a frequency of up to 72mhz with a flash accelerator to obtain maximum effciency. they provide up to 64kb of embedded flash memory for code/data storage and 16kb of embedded sram memory for system operation and application program usage. a variety of peripherals, such as adc, i 2 c, usart, uart, spi, i 2 s, pdma, gptm, mctm, sci, ebi, crc- 16/32, usb2.0 fs, sw-dp (serial wire debug port), etc., are also implemented in the devices. several power saving modes provide the fexibility for maximum optimisation between wakeup latency and power consumption, an especially important consideration in low power applications. the above features ensure that the devices are suitable for use in a wide range of applications, especially in areas such as white goods application control, power monitors, alarm systems, consumer products, handheld equipment, data logging applications, motor control, fingerprint recognition and so on.
rev. 1.00 7 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 general description features 2 features core 32-bit arm ? cortex?-m3 processor core up to 72 mhz operati ng frequency 1.25 dmips/mhz - dhrystone 2.1 single-cycle multiplication and hardware division integrated nested vectored interrupt controller - nvic 24-bit systick timer the cortex?-m3 processor is a general-purpose 32-bit processor core especially suitable for products requiring high performance and low power consumption microcontrollers. it offers many special features such as a thumb-2 instruction set, hardware divider, low latency interrupt respon se time, atomic bit-banding access and multiple buses for simultaneous accesses. the cortex?-m3 processor is based on the armv7 architecture and supports both thumb and thumb-2 instruction sets. on-chip memory supports multiple boot modes the arm ? cortex?-m3 processor is structured using harvard architecture which implements a separate bus structure to fetch instructions and load/store data. the instruction code and data are both located in the same memory address space but in different address ranges. the maximum dgguhvvudqhrih&ruhlv% due to its 32-bit bus address width. additionally, a pre- ghqhgphprupdslvsurlghgeh&ruhsurfhvvruruhgxfhhvriduhfrpsohl of repeated implementation for different device vendors. however, some regions are used by the arm ? cortex?-m3 system peripherals. refer to the arm ? cortex?-m3 technical reference manual for more information. figure 2 shows the memory map of the ht32f1654/53 series of ghlfhvlqfoxglq&rgh65shulshudodqgrhusuhghqhguhlrqv flash memory controller C fmc 32-bit word programming with in system programming interface (isp) and in application programming (iap) flash protection capability to prevent illegal access the flash memory controller, fmc, provides all the necessary functions and pre-fetch buffer for the embedded on-chip flash memory. since the access speed of the flash memory is slower than the cpu, a wide access interface with a pre-fetch buffer and cache are provided for the flash memory in order to reduce the cpu waiting time which will cause cpu instruction execution delays. flash memory word program/page erase functions are also provided.
rev. 1.00 ? of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 features reset control unit C rstcu supply supervisor: power-on reset - por %urqrxhhfru - %2 programmable low voltage detector - lvd the reset control unit , rstcu , has three kinds of reset, a power on reset, a system reset and an 3%xqluhvh7hsrhurquhvhnqrqdvdfroguhvhuhvhvhixoovvhpgxulqsrhuxs a system reset resets the processor core and peripheral ip components with the exception of the 6:3frquroohu7huhvhvfdqehulhuhgedqhhuqdovlqdolqhuqdohhqvdqghuhvh generators. clock control unit C ckcu external 4 to 16 mhz crystal oscillator external 32,768 hz crystal oscillator internal 8mhz rc oscillator trimmed to 2 % accuracy at 3.3v operating voltage and 25c operating temperature internal 32 khz rc oscillator integrated system clock pll independent clock divider and gating bits for peripheral clock sources 7h&orfn&rquroxql&.&8surlghvdudqhrirvfloodrudqgforfnixqflrqv7hvhlqfoxgh a high speed internal rc oscillator (hsi), a high speed external crystal oscillator (hse), a low speed internal rc oscillator (lsi), a low speed external crystal oscillator (lse), a phase lock /rrs3//d+6(forfnprqlruforfnsuhvfdohuvforfnpxolsohhuv3%forfngllghudqg dlqflufxlu7hforfnvrih+%3%dqg&ruh tm -m3 are derived from the system clock &.6<6lffdqfrphiurph+6,+6(ru3//7h:dfgr7lphudqg5hdo7lph&orfn (rtc) use either the lsi or lse as their clock source. the maximum operating frequency of the vvhpfruhforfn&.+%fdqehxsr+ power management C pwrcu single 3.3 v power supply: 2.7 v to 3.6 v integrated 1.8 v ldo regulator for core and peripheral power supply v % 7 battery power supply for rtc and backup registers four power saving modes: sleep, deep-sleep1, deep-sleep2, power-down power consumption can be regarded as one of the most important issues for many embedded vvhpdssolfdlrqvffruglqoh3rhu&rquro8ql3:5&8lqhvhghlfhvsurlghvpdq types of power saving modes such as sleep, deep-sleep1, deep-sleep2 and power-down mode. these operating modes reduce the power consumption and allow the application to achieve the best udghriiehhhqhfrqlflqghpdqgvri&38rshudlqlphvshhgdqgsrhufrqvxpslrq
rev. 1.00 9 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 features features external interrupt/event controller C exti all gpio pins can be selected as exti trigger source source trigger type includes high level, low level, negative edge, positive edge, or both edge individual interrupt enable, wakeup enable and status bits for each exti line software interrupt trigger mode for each exti line the external interrupt/event controller, exti, comprises 16 edge detectors which can generate a wake-up event or interrupt requests independently. each exti line can also be masked independently. analog to digital converter C adc 12-bit sar adc engine up to 12 external analog input channels supply voltage range: 2.7 v ~ 3.6 v conversion range: v ref+ ~ v ref- a 12-bit multi-channel adc is integrated in the device. there are up to 12 multiplexed channels, which include external channels on which the external analog signals can be measured, and 2 lqhuqdofdqqhov,ihlqsxrodhlvuhtxluhgruhpdlqllqdvshflfuhvroglqgr an qdor:dfgrixqflrqlooprqlrudqgghhfh se signal s . an interrupt will then be generated to inform the device that the input voltage is not within the pre set threshold level s. there are three conversion modes to convert an analog signal to digital data. the adc can be operated in one shot, continuous and discontinuous conversion modes. analog comparator C cmp dual rail-to-rail comparator s dedicated i/o pin or internal voltage reference provided by an internal 6-bit scaler programmable hysteresis programming speed and consumption comparator output s can be routed to i/o pins, to timers or to adc trigger inputs ed to dedicated i/o pins for a voltage reference comparator s have interrupt generation capability with wakeup function from within the sleep or deep sleep modes through the exti controller supply voltage range: 2.7 v ~ 3.6 v two general purpose comparators C cmp - are implemented within the device s . the se can be configured either as standalone comparators or combined with the different kinds of peripheral functions . each comparator is capable of generating an interrupt to the nvic and waking up the mcu from the deep sleep mode through exti wakeup event management unit.
rev. 1.00 10 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 features i/o ports up to 51 gpios almost all i/o pins are 5 v-tolerant except for pins shared with analog inputs there are up to 51 general purpose i/o pins, gpio, named from 3a3r3a3iruh implementation of logic input/output functions. each of the gpio ports has a series of related frqurodqgfrqxudlrquhlvhuvrpdlplh hleloldqgrphh the requirements of a wide range of applications. the gpio ports are pin-shared with other alternative functions to obtain maximum functional flexibility on the package pins. the gpio pins can be used as alternative functional pins by frqxulqhfruuhvsrqglquhlvhuvuhdugohvvrihlqsxrurxsxslqv the external interrupts on the gpio pins of the device have related control and configuration registers in the external interrupt control unit , exti. pwm generation and capture timers C gptm two 16-bit up, down, up/down auto-reload counters 16-bit programmable prescaler allowing counter clock frequency division ratio between 1 and 65536 input capture function compare match output single pulse mode output encoder interface controller with two inputs using a quadrature decoder the general purpose timer s consists of one 16-bit up/down-counter, four 16-bit capture/compare registers (ccrs), one 16-bit counter reload register (crr) and several control/status registers. they can be used for a variety of purposes including general time measurement , input signal pulse width measurement and output waveform generation such as that for single pulse generation or for 3:rxsx generation . the gptm includes an encoder interface using a decoder with two inputs.
rev. 1.00 11 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 features features motor control timer C mctm two 16-bit up, down, up/down auto-reload counters 16-bit programmable prescaler allowing counter clock frequency division ratio between 1 and 65536 input capture function compare match output single pulse mode output complementary outputs with programmable dead-time insertion encoder interface controller with two inputs using a quadrature decoder includes a 3-phase motor control and hall sensor interface the motor control timer consists of a single 16-bit up/down counter; four 16-bit ccrs (capture/ compare register s ), single one 16-bit counter-reload register (crr), single 8-bit repetition counter and several control/status registers. it can be used for a variety of purposes including measuring the pulse width s of input signal s or generating output waveforms such as compare match output s , 3:rxsx s rufrpsohphqdu3:rxsx s with dead-time insertion. the mctm supports an encoder interface controller to an incremental encoder with two inputs. th e mctm is capable of offering full functional support for motor control, hall sensor interfac ing and brake input. basic function timer C bftm two 32-bit compare/match count-up counters - no i/o control features one shot mode - counting stops after a match condition repetitive mode - restart counter after a match condition 7h%dvlf)xqflrq7lphulvdvlpsoh count- up 32-bit counter designed to measure time interval s and generate a one shot or repetitive interrupt s 7h%)7rshudhvlqrixqflrqdoprghv repetitive or one shot mode. in the uhshllhprghh%)7uhvduvhfrxqhuhq a compare pdfhhqrffxuv7h%)7dovrvxssruv a o ne shot mode which forces the counter to stop counting when a compare match event occurs.
rev. 1.00 1 ? of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 features watchdog timer C wdt 12-bit down counter with 3-bit prescaler interrupt or reset event for the system programmable watchdog timer window function register write protection function 7h:dfgr7lphulvddugduhlplqflufxldfdqehxvhgrghhfvvhpidloxuhvgxhr software malfunctions. it includes a 12-bit count- grqfrxqhudsuhvfdohud:7frxqhudoxh uhlvhud:7ghoddoxhuhlvhulqhuuxsuhodhgflufxlv:7rshudlrqfrquroflufxlu and a :7surhflrqphfdqlvp7h:dfgr7lphufdqehrshudhglqdqlqhuuxsprghru duhvhprgh7h:dfgr7lphuloohqhudhdqlqhuuxsruduhvhhqhfrxqhufrxqv down and reaches a zero value. if the software does not reload the counter value before a :dfgr 7lphuxqghurrffxuvdqlqhuuxsruduhvhlooehhqhudhghqhfrxqhuxqghurv,q addition, an interrupt or reset is also generated if the software reloads the counter when the counter doxhlvuhdhudqruhtxdorh:7ghoddoxh this means the counter must be reloaded llqdolplhglplqlqgrxvlqdvshflilfphrg7h:dfgr7lphufrxqhufdqeh stopped while the processor is in the debug mode. there is a register write protect function which can be enabled to suhhqliurpfdqlqh:dfgr7lphu frqxudlrq unexpectedly. real time clock C rtc 32-bit up-counter with a programmable prescaler alarm function the real time clock, rtc for short , includes an 3%lqhuidfhdel count- up counter, a control register, a prescaler, a compare register and a status register. most of the rtc circuits are orfdhglqh%dfnxsrpdlqhfhsiruh3%lqhuidfh7h3%lqhuidfhlvorfdhglqh v dd18 power domain. therefore, it is necessary to be isolated from the iso signal that comes from the power control unit when the v dd18 power domain is powered off, that is when the device enters the power-down mode. the rtc counter is used as a wakeup timer to generate a system resume signal from the power-down mode.
rev. 1.00 13 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 features features inter-integrated circuit C i 2 c supports both master and slave modes with a frequency of up to 1 mhz provide an arbitration function and clock synchronization s and general call addressing supports slave multi-addressing mode with maskable address the i 2 c module is an internal circuit allowing communication with an external i 2 c interface which is an industry standard two line serial interface used for connection to external hardware. these two serial lines are known as a serial data line, sda, and a serial clock line, scl. the i 2 c module provides three data transfer rates: 1 . n+lqh6dqgdugprgh . n+lqh)dvprgh and 3 . 1 mhz in the fast mode plus mode . the scl period generation register is used to setup different kinds of duty cycle implementation s for the scl pulse. the sda line which is connected directly to the i 2 c bus is a bi-directional data line between the master and slave devices and is used for data transmission and reception. the i 2 c module also has an arbitration detect function and clock synchronization to prevent situation s where more than one master attempts to transmit data to the i 2 c bus at the same time. serial peripheral interface C spi supports both master and slave mode frequency of up to f 3&/. /2 mhz for master mode and f 3&/. /3 mhz for slave mode fifo depth: 8 levels multi-master and multi-slave operation the serial peripheral interface, spi, provides an spi protocol data transmit and receive function in both master and slave mode. the spi interface uses 4 pins, which are the serial data input and rxsxolqhv,62dqg26,hforfnolqh6&.dqghvodhvhohfolqh6(/2qh63,ghlfh acts as a master device lffrqurovhgddrxvlqh6(/dqg6&.vlqdovrlqglfdhh start of data communication and the data sampling rate. to receive a data byte, the streamed data elvduhodfhgrqdvshflfforfnhghdqgvruhglqhgdduhlvhurulqh5;),)2dd transmission is carried out in a similar way but in a reverse sequence. the mode fault detection provides a capability for multi-master applications.
rev. 1.00 14 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 features universal synchronous asynchronous receiver transmitter C usart supports both asynchronous and clocked synchronous serial communication modes asynchronous operating baud rate up to f 3&/. /16 mhz and synchronous operating rate up to f p- &/. /8 mhz full duplex communication fully programmable serial communication characteristics including: :rugohqruelfdudfhu parity: even, odd, or no-parity bit generation and detection stop bit: 1 or 2 stop bit generation %lrughu/6%uvru6%uvudqvihu error detection: parity, overrun, and frame error - rts, cts irda sir encoder and decoder rs485 mode with output enable control the universal synchronous asynchronous receiver transceiver, usart, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. the usart is used to translate data between parallel and serial interfaces, and is commonly used for rs232 standard communication. the usart peripheral function supports four types of interrupt including line status interrupt, transmitter fifo empty interrupt, receiver threshold level reaching interrupt dqg7lph2x,qhuuxs7h8657prgxohlqfoxghvdehudqvplhu),)27;),)2dqg dehuhfhlhu),)25;),)2 the s oftware can detect a usart error status by reading the line status register, lsr. the status includes the type and the condition of transfer operations as hoodvvhhudohuurufrqgllrqvuhvxolqiurp3dul2huuxq)udplqdqg%uhdnhhqv
rev. 1.00 1 ? of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 features features universal asynchronous receiver transmitter C uart asynchronous serial communication operating baud-rate up to f 3&/. /16 mhz full duplex communication fully programmable serial communication characteristics including: :rugohqruelfdudfhu parity: even, odd, or no-parity bit generation and detection stop bit: 1 or 2 stop bit generation %lrughu/6%uvru6%uvudqvihu error detection: parity, overrun, and frame error the universal asynchronous receiver transceiver, uart, provides a flexible full duplex data exchange using asynchronous transfer. the uart is used to translate data between parallel and serial interfaces, and is commonly used for rs232 standard communication. the uart peripheral function supports four types of interrupt including line status interrupt, transmitter fifo empty interrupt, receiver threshold level reaching interrupt and time out interrupt. the uart prgxohlqfoxghvdehudqvplhu),)27;),)2dqgdehuhfhlhu),)25; fifo). the s oftware can detect a uart error status by reading the line status register, lsr. the status includes the type and the condition of transfer operations as well as several error conditions uhvxolqiurp3dul2huuxq)udplqdqg%uhdnhhqv smart card interface C sci supports iso 7816-3 standard character mode single transmit buffer and single receive buffer 11-bit etu (elementary time unit) counter 24-bit general purpose waiting time counter parity generation and checking automatic character retry on parity error detection in transmission and reception modes the smart card interface is compatible with the iso 7816-3 standard. this interface includes card insertion/removal detection, sci data transfer control logic and data buffers, internal timer counters and corresponding control logic circuits to perform all the necessary smart card operations. the smart card interface acts as a smart card reader to facilitate communication with the external smart card. the overall functions of the smart card interface are controlled by a series of registers including control and status registers together with several corresponding interrupts which are generated to get the attention of the microcontroller for sci transfer status.
rev. 1.00 16 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 features inter-ic sound C i 2 s master or slave mode mono and stereo i 2 6mxvlhg/himxvlhgdqg5lmxvlhgprgh 8/16/24/32-bit sample size with 32-bit channel extended 8 x 32-bit tx & rx fifo with pdma supported 8-bit fractional clock divider with rate control the i 2 s is a synchronous communication interface that can be used as a master or slave to exchange data with other audio peripherals, such as adcs or dacs. the i 2 s supports a variety of data formats. in addition to the stereo i 2 6mxvlhg/himxvlhgdqg5lmxvlhgprghvhuh duhprqr3&prghvlelvdpsohvlh:hqh, 2 s operates in the master mode, then when using the fractional divider, it can provide an accurate sampling frequency output and vxssruhudhfrquroixqflrqdqgqhxqlqrihrxsxiuhtxhqfrdrlgvvhpsureohpv caused by the cumulative frequency error between different devices. cyclic redundancy check C crc x 16 +x 15 +x 2 +1 x 16 +x 12 +x 5 +1 x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x +x 8 +x 7 +x 5 +x 4 +x 2 +x+1 supports vfrpsohphqehuhhuvheluhhuvhrshudlrqrqgdddqgfhfnvxp supports byte, half-word & word data size programmable crc initial seed value crc computation executed lq+%forfnffohiruelgdddqg+%forfnffohviru bit data supports pdma to complete a crc computation of a block of memory the crc calculation unit is an error detection technique test algorithm which is used to verify data transmission or storage data correctness. a crc calculation takes a data stream or a block of data dvlqsxdqghqhudhvdruelrxsxuhpdlqghu2uglqdulodgddvuhdplvvxihged crc code and used as a checksum when being sent or stored. therefore, the received or restored data stream is calculated by the same generator polynomial as described above. if the new crc code result does not match the one calculated earlier, that means data stream contains a data error.
rev. 1.00 17 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 features features peripheral direct memory access C pdma 8 channels with trigger source grouping 8-/16-/32-bit width data transfer 4-level programmable channel priority auto reload mode supports trigger source: adc, spi, usart, uart, i 2 c, i 2 6(%,37&76&,dqg software request the peripheral d irect m emory a ccess controller , pdma , moves data between the peripherals and the system memory on the +%exv(df3fdqqhodvdvrxufhdgguhvvghvlqdlrq address, block length and transfer count. the pdma can exclude the cpu intervention and avoid interrupt service routine execution. it improves system performance as the software does not need to join each data movement operation. external bus interface C ebi programmable interface for various memory types memory bank regions and independent chip select control for each memory bank programmable timings to support a wide range of devices includes page read mode automatic translation when the +%udqvdflrqlgdqghhuqdophprulqhuidfhlglv different up to 21 address lines up to 16-bit data bus width the external bus interface is able to access external parallel interface devices such as sram, flash and lcd modules. t he interface is memory mapped into the internal address map of the cpu. the data and address lines are multiplexed in order to reduce the number of pins required to connect to the external devices. the read/write timing of the bus can be adjusted to meet the timing vshflfdlrqrihhhuqdoghlfhv1rhhlqhuidfhrqovxssruv asynchronous 8 or 16-bit bus interface.
rev. 1.00 1 ? of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 features universal serial bus device controller C usb 3 single-buffered endpoints for bulk and interrupt transfer 4 double-buffered endpoints for bulk, interrupt and isochronous transfer the 86%ixoovshhgvshflfdlrq7huh is one frqurohqgsrlqnqrqdv(qgsrlqdqgvhhqfrqilxudeohhqgsrlqveh65 is used as the endpoint buffer. each endpoint buffer size is programmable using corresponding uhlvhuvlfsurlghvpdlpxphlelolirudulrxvdssolfdlrqv7hlqhudhg86%ixoo vshhgudqvfhlhuhosvrplqlplhhrhudoovvhpfrpsohldqgfrv7h86% functional block also contains the resume and suspend feature to meet the requirements of low-power consumption. debug support - 6:3 6 instruction comparators and 2 literal comparators for hardware breakpoint or code / literal patch es 4 comparators for hardware watchpoint s package and operation temperature 48/64-pin lqfp package
rev. 1.00 19 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 features overview 3 overview device information table 1 ht32f1654/1653 series features and peripheral list peripherals ht32f1654 HT32F1653 main flash (kb) 63 3 ? option b ? tes flash 1 1 sram (kb) 16 ? time ? s mctm ? gptm ? bftm ? rtc 1 wdt 1 comm ? nication usb 1 spi ? usart ? uart ? i ? c ? i ? s 1 sci 1 ebi 1 crc-16/3 ? 1 exti 16 1 ? -bit adc n ? mbe ? of channels 1 1 ? channels compa ? ato ? ? gpio up to ? 1 cpu f ? eq ? enc ? up to 7 ? mhz ope ? ating voltage ? .7 v ~ 3.6 v ope ? ating tempe ? at ?? e -40 ~ + ?? packages 4 ? /64-pin lqfp
rev. 1.00 ? 0 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 overview block diagram tpiu sw-dp aapb0 ahb peripherals flash memory icode dcode cortex tm -m3 processor f max : 72 mhz ssystem nvic sram controller fmc control registers ckcu/rstcu control registers pdma control registers pdma 8 channels dma request interrupt request usart0 uart0 afio exti spi1 mosi, miso sck, sel powered by v dd33 v ss33 v dd33 pll f max : 144 mhz por 1.8 v ch3 ~ ch0 eti boot0 boot1 clock and reset control bod lvd xtalin xtalout cldo hsi 8 mhz hse 4 ~ 16 mhz power control bus matrix af af af af af af af af ldo 1.8 v powered by v dd18 usb control/data registers swclk swdio sda scl af usart1 power supply: bus: control signal: alternate function: af powered by v dd18 mosi, miso sck, sel af flash memory interface tx, rx rts/txe cts/sck tx, rx rts/txe cts/sck ch0 ~ch2 ch0n ~ ch2n ch3, eti, brk af xtal32kin xtal32kout af porb v bak 3.3 v lsi 32 khz lse 32,768 hz breg backup domain v dd33 v bat v ss33 v bak pwrsw rtc pwrcu nrst rtcout wakeup af af gptm 0 ~ 1 analog cmp powered by v dda v dda v ssa cn0, cp0 cout0 cn1, cp1 cout1 opa/cmp adc_in0 ... adc_in11 af af i2c 0 ~ 1 adc 12-bit sar adc traceswo mctm0 bftm 0 ~ 1 sci af clk, dio, det ahb to apb bridge external bus interafce usb device af dp dm wdt af ad0~ad15 a0~a24 cs0~cs3 oe, wr ale, rdy bl0~bl1 sram gpio a~d pa ~ pd15:0] spi0 af tx, rx af uart1 tx, rx i2s mclk, bclk ws, sdo, sdi crc -16/32 ch0 ~ch2 ch0n ~ ch2n ch3, eti, brk af mctm1 cap. aapb1 figure 1 ht32f1654/1653 block diagram
rev. 1.00 ? 1 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 overview overview memory map usb gpioa ~ d ebi up to 64 kb on-chip flash 0x0000_0000 reserved 0x0001_0000 boot loader 0x1f00_0000 reserved 0x1f00_2000 option byte alias 0x1ff0_0000 up to 64 kbytes 8 kbytes 1 kbytes reserved 0x1ff0_0400 code sram peripheral up to 16 kb on-chip sram 0x2000_0000 reserved 0x2000_4000 sram bit band alias 0x2200_0000 reserved 0x2220_0000 up to 16 kbytes 2 mbytes apb peripherals 0x4000_0000 ahb peripherals 0x4008_0000 reserved 0x4010_0000 apb/ahb bit band alias 0x4200_0000 reserved 0x4400_0000 private peripheral bus 0xe000_0000 reserved 0xe010_0000 0xffff_ffff 512 kbytes 512 kbytes 32 mbytes usart0 0x4000_0000 uart0 0x4000_1000 spi0 0x4000_4000 reserved 0x4000_5000 adc 0x4001_0000 0x4001_1000 reserved opa/cmp 0x4001_8000 reserved 0x4001_9000 0x4001_a000 0x4001_b000 0x4001_c000 0x4001_d000 0x4001_e000 0x4001_f000 afio 0x4002_2000 reserved 0x4002_3000 exti 0x4002_4000 i2s 0x4002_6000 mctm0 0x4002_c000 0x4002_d000 mctm1 usart1 0x4004_0000 uart1 0x4004_1000 sci 0x4004_3000 reserved 0x4004_5000 spi1 0x4004_4000 i2c0 0x4004_8000 reserved 0x4004_a000 i2c1 0x4004_9000 reserved 0x4004_f000 usb 0x4004_e000 reserved 0x4006_9000 wdt 0x4006_8000 reserved 0x4006_b000 rtc/pwrcu 0x4006_a000 gptm0 0x4006_e000 reserved 0x4007_0000 gptm1 0x4006_f000 bftm0 0x4007_6000 reserved 0x4007_8000 bftm1 0x4007_7000 apb0 apb1 fmc 0x4008_0000 reserved 0x4008_2000 ckcu/rstcu 0x4008_8000 crc-16/32 0x4008_a000 pdma 0x4009_0000 0x4009_8000 0x400a_8000 reserved 0x400b_0000 0x400f_ffff ahb ebi selection bank reserved 0x6000_0000 0x7000_0000 64 mbytes x 4 figure 2 ht32f1654/1653 memory map
rev. 1.00 ?? of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 overview clock structure 4-16 mhz hse xtal 8 mhz hsi rc 32 khz lsi rc legend: hse = high speed external clock hsi = high speed internal clock lse = low speed external clock lsi = low speed internal clock 32.768 khz lse osc wdtsrc pllsrc ahb prescaler 1,2,4,8 fclk ( free running clock) hclkd ( to pdma) stclk (to systick) ck_adc ip ck_wdt wdten ck_ref ck_hsi/16 ck_hse/16 ck_sys/16 ckout ckoutsrc[2:0] hseen hsien lseen (note1) lsien (note1) f ck_sys,max = 144mhz ck_lsi ck_lse ck_ahb/16 ck_hsi ck_hse pclk ( opax, afio, adc, spix, usartx, uartx, i2cx, i2s, gptmx, mctmx, bftmx, exti, rtc, sci, wdt) pll clock monitor pllen ck_lse ck_pll dmaen adcen f ck_pll,max = 144mhz ck_lsi hclks ( to sram) hclkf ( to flash) cm3en fmcen cm3en sramen 1 0 rtcsrc (note1) ck_rtc rtcen (note1) 1 0 1 0 note 1: those control bits are located at rtc control register (rtc_ctrl) ck_ahb 000 001 010 011 100 101 110 ck_sys sw[1:0] 0x 11 10 8 ck_usb f ck_usb,max = 48mhz usben hclkc ( to cortex tm -m3) cm3en (control by hw) prescaler 1 ~ 32 ck_ref ck_ebi ( to ebi) ebien divider 2 ckrefpre hclkbm ( to bus matrix) cm3en bmen hclkapb0 ( to apb0 bridge) cm3en apb0en hclkapb1 ( to apb1 bridge) cm3en apb1en ck_crc ( to crc) crcen peripherals clock prescaler 1,2,4,8 prescaler 1, 2, 3 adc prescaler 2,4,6,8 ... 00 01 10 11 pclk pclk/2 pclk/4 pclk/8 spien scien ck_gpio ( to gpio port) gpioeen gpioaen ckrefen hsi auto trimming controller ck_lse usb frame pulse ,16 figure 3 ht32f1654/1653 clock structure
rev. 1.00 ? 3 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 overview pin assignment 4 pin assignment vssa pb9 vdda pb11 pb10 pb? pb7 pb6 pb? pb4 pb? pb3 4? 47 46 4? 44 43 4? 41 40 39 3? 1 ? 3 4 ? 6 7 ? 9 10 11 13 14 1? 16 17 1? 19 ?0 ?1 ?? ?3 3? 34 33 3? 31 30 ?9 ?? ?7 ?6 ?? pa0 pa1 pa? pa3 pa4 pa? pa6 pa7 vdd33_1 usbdm /pb1? usbdp /pb13 vss33_3 vdd33_3 pb1 pb0 pa1? pa14 pa10 pa9_ boot1 pa?_ boot0 xtalin af0 (defa?lt) af0 (defa?lt) af0 (defa?lt) vdd33_? vss33_? nrst vbat xtal3?ki n xtal3?k out rtcout pd? xtalout pd1 p33 bak ?vt bak p33 bak 33v bak 33v bak ?vt ?vt ?vt ?vt p1? usb usb 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v ap ap p33 ap p1? 33v ?vt ?vt 3.3 v digital powe? pad 3.3 v analog powe? pad 1.? v powe? pad 3.3 v i/o pad ? v tole?ance i/o pad high c???ent o?tp?t ? v tole?ance i/o pad holtek ht32f1654/1653 48 lqfp-a 37 1? ?4 36 cldo af0 (defa?lt) 33v vss33_1 p33 33v 33v p33 p33 ?vt 33v 33v p33 p33 ?vt ?vt ?vt ?vt ?vt ?vt ?vt ?vt ?vt ?vt usb usb phy pad swclk traceswo swdio bak back?p domain pad pa11 pa1? pa13 pc13 pc14 pc1? pb14 pb1? af1 af1 ?vt ?vt figure 4 ht32f1654/1653 lqfp-48 pin assignment
rev. 1.00 ? 4 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 pin assignment 64 63 6? 61 60 ?9 ?? ?7 ?6 ?? ?4 1 ? 3 4 ? 6 7 ? 9 10 1? 17 1? 19 ?0 ?1 ?? ?3 ?4 ?? ?6 ?7 47 46 4? 44 43 4? 41 40 39 3? 37 pa0 pa1 pa? pa3 pa4 pa? pa6 pa7 vdd33_1 usbdm /pb1? usbdp /pb13 vss33_3 vdd33_3 pb1 pb0 pa1? pa14 pa10 xtalin af0 (defa?lt) af1 af0 (defa?lt) af0 (defa?lt) af1 vdd33_? vss33_? nrst vbat xtal3?kin xtal3?kout pc13 pc14 rtcout pc1? pb14 pb1? pd? xtalout pd1 vssa pb9 vdda pb11 pb10 pb? pb7 pb6 pc7 p33 bak ?vt bak p33 bak 33v bak 33v bak ?vt ?vt ?vt ?vt p1? usb usb 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v ap ap p33 ap p1? 33v ?vt ?vt 3.3 v digital powe? pad 3.3 v analog powe? pad 1.? v powe? pad 3.3 v i/o pad ? v tole?ance i/o pad high c???ent o?tp?t ? v tole?ance i/o pad holtek HT32F1653/1654 64 lqfp-a ?3 16 ?? 4? cldo pc? af0 (defa?lt) 33v vss33_1 p33 33v pa13 pa1? pa11 p33 p33 ?vt ?vt 33v 33v ?vt ?vt p33 p33 11 1? 13 pc9 pc11 pc1? 14 pc10 ?9 30 31 pc0 pd0 pc1 pc? 3? 33v ?? ?1 ?0 pb? pb4 pb? 49 pb3 36 3? 34 33 pa9_ boot1 pa?_ boot0 pc3 ?vt ?vt 33v 33v 33v 33v ?vt pc? pc4 pc6 p33 p33 vdd33_4 vss33_4 ?vt ?vt ?vt ?vt ?vt ?vt ?vt ?vt ?vt ?vt ?vt ?vt ?vt usb usb phy pad ?vt swclk traceswo swdio bak back?p domain pad ?vt ?vt figure 5 ht32f1654/1653 lqfp-64 pin assignment
rev. 1.00 ?? of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 pin assignment pin assignment table 2 ht32f1654/1653 series pin assignment for lqfp 64 / 48 package package alternate function number af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 lqfp -64 lqfp -4 ? s ? stem defa ? lt gpio adc cmp mctm /gptm spi usart /uart i ? c sci ebi i ? s n/a n/a n/a n/a s ? stem othe ? 1 1 pa0 adc_ in0 gt1_ ch0 usr0_ rts i ? c1_ scl sci_ clk i ? s _ws ? ? pa1 adc_ in1 gt1_ ch1 usr0_ cts i ? c1_ sda sci_ dio i ? s _bclk 3 3 pa ? adc_ in ? gt1_ ch ? usr0_ tx i ? s _sdo 4 4 pa3 adc_ in3 gt1_ ch3 usr0_ rx i ? s _sdi ? ? pa4 adc_ in4 gt0_ ch0 spi0_ sck usr1_ tx i ? c0_ scl 6 6 pa ? adc_ in ? gt0_ ch1 spi0_ mosi usr1_ rx i ? c0_ sda 7 7 pa6 adc_ in6 gt0_ ch ? spi0_ miso usr1_ rts ? ? pa7 adc_ in7 gt0_ ch3 spi0_ sel usr1_ cts i ? s _mclk 9 9 vdd33_1 10 10 vss33_1 11 pc9 adc_ in ? gt0_ ch0 spi1_ sel ur0_ tx i ? c1_ scl ebi _a19 1 ? pc10 adc_ in9 gt0_ ch1 spi1_ sck ur0_ rx i ? c1_ sda ebi _a ? 0 13 pc11 adc_ in10 gt0_ ch ? spi1_ mosi ebi _a0 14 pc1 ? adc_ in11 gt0_ ch3 spi1_ miso ebi _a1 1 ? 11 pb1 ? mt1_ ch ? i ? c0_ scl 1 ? 11 usbdm 16 1 ? usbdp 16 1 ? pb13 mt1_ ch ? n i ? c0_ sda 17 13 cldo 1 ? 14 vdd33_ ? 19 1 ? vss33_ ? ? 0 16 nrst ? 1 17 vbat ?? 1 ? xtal3 ? kin pc13 ? 3 19 xtal3 ? kout pc14 ? 4 ? 0 rtcout pc1 ? _wake - up ?? pd0 mt1_ eti i ? c0_ sda ebi_ a1 ? i ? s_ sdi ? 6 ? 1 xtalin pb14 ? 7 ?? xtalout pb1 ? ?? ? 3 pd1 mt1_ ch0 spi0_ sel i ? c1_ scl ebi_ a16 i ? s_ mclk ? 9 ? 4 pd ? mt1_ ch0n spi0_ sck i ? c1_ sda ebi_ a17 30 pc0 gt1_ ch0 spi1_ sel ebi_ ad13 i ? s_ ws 31 pc1 gt1_ ch1 spi1_ sck ebi_ ad14 i ? s_ bclk 3 ? pc ? gt1_ ch ? spi1_ mosi ur1_ tx i ? c0_ scl ebi_ ad1 ? i ? s_ sdo 33 pc3 gt1_ ch3 spi1_ miso ur1_ rx i ? c0_ sda ebi_ cs3 i ? s_ sdi
rev. 1.00 ? 6 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 pin assignment package alternate function number af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 34 ?? pa ? _boot0 gt0_ eti usr0_ tx i ? s_ mclk ckout 3 ? ? 6 pa9_boot1 spi0_ mosi ebi_ a1 i ? s_ ws 36 ? 7 pa10 mt1_ ch1 usr0_ rx sci_ det 37 ?? traceswo pa11 mt1_ ch1n spi0_ miso ebi_ a0 i ? s_ mclk traceswo 3 ? ? 9 swclk pa1 ? 39 30 swdio pa13 40 31 pa14 mt0_ ch0 spi1_ sel usr1_ tx sci_ clk ebi_ ad0 41 3 ? pa1 ? mt0_ ch0n spi1_ sck usr1_ rx sci_ dio ebi_ ad1 4 ? vdd33_3 43 vss33_3 44 33 pb0 mt0_ ch1 spi1_ mosi usr0_ tx i ? c0_ scl ebi_ ad ? 4 ? 34 pb1 mt0_ ch1n spi1_ miso usr0_ rx i ? c0_ sda ebi_ ad3 46 pc4 mt1_ ch ? usr1_ rts sci_ clk ebi_ ad10 47 pc ? mt1_ ch ? n usr1_ cts sci_ dio ebi_ ad11 4 ? pc6 mt1_ ch3 sci_ det ebi_ ad1 ? 3 ? vdd33_3 36 vss33_3 49 37 pb ? mt0_ ch ? spi0_ sel ur0_ tx ebi_ ad4 ? 0 3 ? pb3 mt0_ ch ? n spi0_ sck ur0_ rx ebi_ ad ? ? 1 39 pb4 mt0_ brk spi0_ mosi ur1_ tx ebi_ ad6 ?? 40 pb ? mt1_ brk spi0_ miso ur1_ rx ebi_ ad7 ? 3 pc7 mt0_ ch3 i ? c0_ scl ebi_ ad ? ? 4 pc ? mt0_ eti i ? c0_ sda ebi_ ad9 ?? vdd33_4 ? 6 vss33_4 ? 7 41 pb6 cn0 mt1_ ch0 spi1_ sel ur1_ tx ebi_ oe i ? s_ mclk ?? 4 ? pb7 cp0 mt1_ ch0n spi1_ sck ebi_ cs0 ? 9 43 pb ? cout0 gt1_ eti spi1_ mosi ur1_ rx ebi_ we 60 44 pb9 cn1 mt1_ ch ? spi1_ miso ur0_ tx ebi_ ale i ? s_ bclk 61 4 ? pb10 cp1 mt1_ ch ? n i ? c1_ scl ebi_ cs1 i ? s_ sdo 6 ? 46 pb11 cout1 mt1_ ch3 ur0_ rx i ? c1_ sda ebi_ cs ? i ? s_ sdi 63 47 vdda 64 4 ? vssa
rev. 1.00 ? 7 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 pin assignment pin assignment table 3 ht32f1654/1653 pin description pin number pin name type (note1) io structure (note2) output driving description lqfp 64 lqfp 48 default function (af0) 1 1 pa0 ai/o 33v 4/ ? ma pa0 ? ? pa1 ai/o 33v 4/ ? ma pa1 3 3 pa ? ai/o 33v 4/ ? ma pa ? 4 4 pa3 ai/o 33v 4/ ? ma pa3 ? ? pa4 ai/o 33v 4/ ? ma pa4 6 6 pa ? ai/o 33v 4/ ? ma pa ? 7 7 pa6 ai/o 33v 4/ ? ma pa6 ? ? pa7 ai/o 33v 4/ ? ma pa7 9 9 vdd33_1 p 3.3 v voltage fo ? digital i/o 10 10 vss33_1 p g ? o ? nd ? efe ? ence fo ? digital i/o 11 pc9 ai/o 33v 4/ ? ma pc9 1 ? pc10 ai/o 33v 4/ ? ma pc10 13 pc11 ai/o 33v 4/ ? ma pc11 14 pc1 ? ai/o 33v 4/ ? ma pc1 ? 1 ? 11 pb1 ? i/o ? vt ? ma pb1 ? 1 ? 11 usbdm ai/o usb diffe ? ential data b ? s confo ? ming to the unive ? sal se ? ial b ? s standa ? d. 16 1 ? usbdp ai/o usb diffe ? ential data b ? s confo ? ming to the unive ? sal se ? ial b ? s standa ? d. 16 1 ? pb13 i/o ? vt ? ma pb13 17 13 cldo p co ? e powe ? ldo 1. ? v o ? tp ? t it is ? ecommended to connect a 4.7 ? f capacito ? as close as possible between this pin and vss33_ ? . 1 ? 14 vdd33_ ? p 3.3 v voltage fo ? digital i/o 19 1 ? vss33_ ? p g ? o ? nd ? efe ? ence fo ? digital i/o ? 0 16 nrst i (bk) ? vt_pu exte ? nal ? eset pin and exte ? nal wake ? p pin in the powe ? -down mode ? 1 17 vbat p batte ?? powe ? inp ? t fo ? the back ? p domain ?? 1 ? pc13 note 4 ai/o (bk) 33v 1ma xtal3 ? kin ? 3 19 pc14 note 4 ai/o (bk) 33v 1ma xtal3 ? kout ? 4 ? 0 pc1 ? note 4 i/o (bk) ? vt 1ma rtcout ?? pd0 i/o ? vt ? ma pd0 ? 6 ? 1 pb14 ai/o 33v 4/ ? ma xtalin ? 7 ?? pb1 ? ai/o 33v 4/ ? ma xtalout ?? ? 3 pd1 i/o ? vt ? ma pd1 ? 9 ? 4 pd ? i/o ? vt ? ma pd ? 30 pc0 i/o ? vt 1 ? ma pc0 31 pc1 i/o ? vt 1 ? ma pc1 3 ? pc ? i/o ? vt 1 ? ma pc ? 33 pc3 i/o ? vt 1 ? ma pc3
rev. 1.00 ?? of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 pin assignment pin number pin name type (note1) io structure (note2) output driving description lqfp 64 lqfp 48 default function (af0) 34 ?? pa ? i/o ? vt_pu 1 ? ma pa ? _boot0 3 ? ? 6 pa9 i/o ? vt_pu 1 ? ma pa9_boot1 36 ? 7 pa10 i/o ? vt ? ma pa10 37 ?? pa11 i/o ? vt ? ma traceswo 3 ? ? 9 pa1 ? i/o ? vt_pu ? ma swclk 39 30 pa13 i/o ? vt_pu ? ma swdio 40 31 pa14 i/o ? vt 1 ? ma pa14 41 3 ? pa1 ? i/o ? vt 1 ? ma pa1 ? 4 ? vdd33_3 p 3.3 v voltage fo ? digital i/o 43 vss33_3 p g ? o ? nd ? efe ? ence fo ? digital i/o 44 33 pb0 i/o ? vt 1 ? ma pb0 4 ? 34 pb1 i/o ? vt 1 ? ma pb1 46 pc4 i/o ? vt ? ma pc4 47 pc ? i/o ? vt ? ma pc ? 4 ? pc6 i/o ? vt ? ma pc6 3 ? vdd33_3 p 3.3 v voltage fo ? digital i/o 36 vss33_3 p g ? o ? nd ? efe ? ence fo ? digital i/o 49 37 pb ? i/o ? vt 1 ? ma pb ? ? 0 3 ? pb3 i/o ? vt 1 ? ma pb3 ? 1 39 pb4 i/o ? vt 1 ? ma pb4 ?? 40 pb ? i/o ? vt 1 ? ma pb ? ? 3 pc7 i/o ? vt ? ma pc7 ? 4 pc ? i/o ? vt ? ma pc ? ?? vdd33_4 p 3.3 v voltage fo ? digital i/o ? 6 vss33_4 p g ? o ? nd ? efe ? ence fo ? digital i/o ? 7 41 pb6 ai/o 33v 4/ ? ma pb6 ?? 4 ? pb7 ai/o 33v 4/ ? ma pb7 ? 9 43 pb ? ai/o 33v 4/ ? ma pb ? 60 44 pb9 ai/o 33v 4/ ? ma pb9 61 4 ? pb10 ai/o 33v 4/ ? ma pb10 6 ? 46 pb11 ai/o 33v 4/ ? ma pb11 63 47 vdda p 3.3 v analog voltage fo ? adc and compa ? ato ? 64 4 ? vssa p g ? o ? nd ? efe ? ence fo ? the adc and compa ? ato ? note: 1. i = inp ? t ? o = o ? tp ? t ? a = analog po ? t ? p = powe ? s ? ppl ?? pu = p ? ll- ? p ? bk = back- ? p domain ? . ? vt = ? v tole ? ant; 33v = 3.3 v tole ? ant. 3. the gpios a ? e in an af0 state afte ? a v dd1 ? powe ? on ? eset (por) except fo ? the rtcout pin in the back ? p domain i/o. the rtcout pin is ? eset b ? the back ? p domain powe ? -on- ? eset (porb) o ? b ? the back ? p domain softwa ? e ? eset (bak_rst bit in bak_cr ? egiste ? ). 4. the back ? p domain of the i/o pins ha ve a so ?? ce c ??? ent capabilit ? limitation of < 1 ma @ v bat = 3.3v and sink c ??? ent t ? pical is 4 ma @ v bat = 3.3v.
rev. 1.00 ? 9 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 pin assignment electrical characteristics 5 electrical characteristics absolute maximum ratings the following table shows the absolute maximum ratings of the device. these are stress ratings only. s tresses beyond absolute maximum ratings may cause permanent damage to the device. note that the device is not guaranteed to operate properly at the maximum ratings. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. table 4 absolute maximum ratings symbol parameter min max unit v dd33 exte ? nal main s ? ppl ? voltage v ss - 0.3 v ss + 3.6 v v dda exte ? nal analog s ? ppl ? voltage v ssa - 0.3 v ssa + 3.6 v v bat exte ? nal batte ?? s ? ppl ? voltage v ss - 0.3 v ss + 3.6 v v ldoin exte ? nal ldo s ? ppl ? voltage v ss - 0.3 v ss + 3.6 v v in inp ? t voltage on ? v-tole ? ant i/o v ss - 0.3 v ss + ? . ? v inp ? t voltage on othe ? i/o v ss - 0.3 v dd33 + 0.3 v t a ambient ope ? ating tempe ? at ?? e ? ange -40 + ?? c t stg sto ? age tempe ? at ?? e ? ange - ?? +1 ? 0 c t ? maxim ? m j ? nction tempe ? at ?? e 1 ?? c p d total powe ? dissipation ? 00 mw v esd elect ? ostatic discha ? ge voltage - h ? man bod ? mode -4000 +4000 v recommended dc operating conditions table 5 recommended dc operating conditions t a = 25c, unless otherwise specifed. symbol parameter conditions min typ max unit v dd33 i/o o pe ? ating voltage ? .7 3.3 3.6 v v dda analog ope ? ating voltage ? .7 3.3 3.6 v v bat ba tte ?? s ? ppl ? o pe ? ating voltage ? .7 3.3 3.6 v v ldoin ldo o pe ? ating voltage ? .7 3.3 3.6 v on-chip ldo voltage regulator characteristics table 6 ldo characteristics t a = ?? c , unless otherwise specifed. symbol parameter conditions min typ max unit v ldoout inte ? nal ? eg ? lato ? o ? tp ? t voltage v dd33 = 3.3 v reg ? lato ? inp ? t 1.71 1. ? 1. ? 9 v i ldoout o ? tp ? t c ??? ent v dd33 = ? .7 v reg ? lato ? inp ? t ? 00 ma c ldo external flter capacitor value fo ? inte ? nal co ? e powe ? s ? ppl ? the capacito ? val ? e is depen - dent on the co ? e powe ? c ?? - ? ent cons ? mption ? . ? 10 f
rev. 1.00 30 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 electrical characteristics power consumption table 7 power consumption characteristics t a = ?? c , unless otherwise specifed. symbol parameter conditions min typ max unit i dd s ? ppl ? c ??? ent (r ? n mode) v dd33 = v bat = 3.3 v ? hse = ? mhz ? pll = 144 mhz ? f hclk = 7 ? mhz ? f pclk = 7 ? mhz ? all pe ? iphe ? als enabled 76 ma v dd33 = v bat = 3.3 v ? hse = ? mhz ? pll = 144 mhz ? f hclk = 7 ? mhz ? f pclk = 7 ? mhz ? all pe ? iphe ? als disabled 33 ma s ? ppl ? c ??? ent (sleep mode) v dd = v bat = 3.3 v ? hse = ? mhz ? pll = 144 mhz ? f hclk = 0 mhz ? f pclk = 7 ? mhz ? all pe ? iphe ? als enabled ?? ma v dd33 = v bat = 3.3 v ? hse = ? mhz ? pll = 144 mhz ? f hclk = 0 mhz ? f pclk = 7 ? mhz ? all pe ? iphe ? als disabled 10 ma s ? ppl ? c ??? ent (deep-sleep1 mode) v dd33 = v bat = 3.3 v ? all clock off (hse/pll/f hclk ) ? ldo in low powe ? mode ? lsi on ? rtc on 63 a s ? ppl ? c ??? ent (deep-sleep ? mode) v dd33 = v bat = 3.3 v ? all clock off (hse/pll/f hclk ) ? ldo off (dmos on) ? lsi on ? rtc on ?? a s ? ppl ? c ??? ent (powe ? -down mode) v dd33 = v bat = 3.3 v ? ldo off ? lse on ? lsi off ? rtc on - a v dd33 = v bat = 3.3 v ? ldo off ? lse on ? lsi off ? rtc off - a v dd33 = v bat = 3.3 v ? ldo off ? lse off ? lsi on ? rtc on - a v dd33 = v bat = 3.3 v ? ldo off ? lse off ? lsi on ? rtc off ? a i bat batte ?? s ? ppl ? c ??? ent (powe ? -down mode) v dd33 not p ? esent ? v bat = 3.3 v ? ldo off ? lse off ? lsi on ? rtc on 4 a v dd33 not p ? esent ? v bat = 3.3 v ? ldo off ? lse off ? lsi on ? rtc off 3.9 a note: 1. hse means high speed exte ? nal oscillato ? . hsi means ? mhz high speed inte ? nal oscillato ? . ? . lse means low speed exte ? nal oscillato ? . lsi means 3 ? .76 ? khz low speed inte ? nal oscillato ? . 3. rtc means ? eal time clock. 4. code = while (1) { ? 0 ? nop } exec ? ted in flash.
rev. 1.00 31 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 electrical characteristics electrical characteristics reset and supply monitor characteristics table 8 lvd/bod characteristics t a = ?? c , unless otherwise specifed. symbol parameter conditions min typ max unit v bod b ? own o ? t detecto ? voltage ? .6 v v lvd voltage of low voltage detecto ? lvds (note1) = 000 ? .7 v lvds (note1) = 001 ? . ? v lvds (note1) = 010 ? .9 v lvds (note1) = 011 3.0 v lvds (note1) = 100 3.1 v lvds (note1) = 101 3. ? v lvds (note1) = 110 3.4 v lvds (note1) = 111 3. ? v v por powe ? on reset voltage 1.36 v note: lvds feld is in pwrcu lvdcsr register external clock characteristics table 9 high speed external clock (hse) characteristics t a = ?? c , unless otherwise specifed. symbol parameter conditions min typ max unit f hse high speed exte ? nal oscillato ? f ? eq ? enc ? (hse) v dd33 = 3.3 v 4 16 mhz c hse recommended load capacitance on xtalin and xtalout pins tbd pf r fhse recommended exte ? nal feedback ? esisto ? between xtalin and xtalout pins 1.0 m d hse hse oscillato ? d ? t ? c ? cle 40 60 % i ddhse hse oscillato ? c ??? ent cons ? mption v dd33 = 3.3 v ? t a = ?? c 0.96 ma i stbhse hse oscillato ? s tandb ? c ??? ent v dd33 = 3.3 v ? t a = ?? c 0.1 a t suhse hse oscillato ? s ta ? t ? p time v dd33 = 3.3 v ? t a = ?? c 4 ms
rev. 1.00 3 ? of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 electrical characteristics table 10 low speed external clock (lse) characteristics t a = ?? c , unless otherwise specifed. symbol parameter conditions min typ max unit f lse low speed exte ? nal oscillato ? f ? eq ? enc ? (lse) v dd33 = v bat = 3.3 v 3 ? .76 ? khz c lse recommended load capacitance on xtal3 ? kin and xtal3 ? kout pins tbd pf r flse recommended exte ? nal feedback ? esisto ? between xtal3 ? kin and xtal3 ? kout pins 10 m d lse lse oscillato ? d ? t ? c ? cle 40 60 % i ddlse lse oscillato ? ope ? ating c ??? ent v dd33 = v bat = 3.3 v ? lsesm = 0 (no ? mal sta ? t ? p mode) 1.7 a i stblse lse oscillato ? standb ? c ??? ent v dd33 = v bat = 3.3 v ? lsesm = 1 (fast sta ? t ? p mode) 3 ? a t sulse lse oscillato ? sta ? t ? p time v dd33 = v bat = 3.3 v ? lsesm = 1 (fast sta ? t ? p mode) ? 00 ms note: the following pcb la ? o ? t g ? idelines a ? e ? ecommended to inc ? ease the stabilit ? of the c ?? stal ci ? - c ? it fo ? the hse/lse clock: the crystal oscillator should be located as close as possible to the mcu to minimise trace length thus reducing parasitic capacitance. use a ground plane as a shield under the crystal circuit to reduce the effects of noise interference.. route high frequency signals away from crystal oscillator area to prevent crosstalk. internal clock characteristics table 11 high speed internal clock (hsi) characteristics t a = ?? c , unless otherwise specifed. symbol parameter conditions min typ max unit f hsi high speed inte ? nal oscillato ? f ? eq ? enc ? (hsi) v dd33 = 3.3 v ? t a = -40c ~ + ?? c ? mhz acc hsi hsi oscillato ? f ? eq ? enc ? acc ?? ac ? facto ?? -t ? immed ? v dd33 = 3.3 v ? t a = -40c ~ + ?? c - ? + ? % d hsi hsi oscillato ? d ? t ? c ? cle v dd33 = 3.3 v ? f hsi = ? mhz 3 ? 6 ? % i ddhsi hsi oscillato ? c ??? ent v dd33 = 3.3 v ? f hsi = ? mhz 0.9 ? ma t suhsi hsi oscillato ? sta ? t ? p time v dd33 = 3.3 v ? f hsi = ? mhz ? hsircbl = 0 (hsi read ? co ? nte ? bits length 7 bits ) 17 s note: hsircbl feld is in pwrcu hsircr register
rev. 1.00 33 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 electrical characteristics electrical characteristics table 12 low speed internal clock (lsi) characteristics t a = ?? c , unless otherwise specifed. symbol parameter conditions min typ max unit f lsi low speed inte ? nal oscillato ? f ? eq ? enc ? (lsi) v dd33 = v bat = 3.3 v ? t a = -40 c ~ + ?? c ?? 3 ? 43 khz i ddlsi lsi oscillato ? ope ? ating c ??? ent v dd33 = v bat = 3.3 v ? t a = ?? c 1.0 ? a t sulsi lsi oscillato ? s ta ? t ? p time v dd33 = v bat = 3.3 v ? t a = ?? c 3 ? ms pll characteristics table 13 pll characteristics t a = ?? c, unless otherwise specifed. symbol parameter conditions min typ max unit f pllin pll inp ? t clock 4 16 mhz f ck_pll pll o ? tp ? t clock ? 144 mhz t lock pll lock time tbd ms memory characteristics table 14 flash memory characteristics t a = ?? c, unless otherwise specifed. symbol parameter conditions min typ max unit n endu n ? mbe ? of g ? a ? anteed p ? og ? am/ e ? ase c ? cles befo ? e fail ?? e. (end ?? ance) t a = -40c ~ + ?? c ? 0 k c ? cles t ret data ? etention time t a = ?? c 100 yea ? s t prog wo ? d p ? og ? amming time t a = -40c ~ + ?? c ? 0 40 s t erase page e ? ase time t a = -40c ~ + ?? c ? 0 40 ms t merase mass e ? ase time t a = -40c ~ + ?? c ? 0 40 ms
rev. 1.00 34 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 electrical characteristics i/o port characteristics table 15 i/o port characteristics t a = ?? c, unless otherwise specifed. symbol parameter conditions min typ max unit i il low level inp ? t c ??? ent 3.3 v io v i = 0 v ? on-chip p ? ll- ? p ? esiste ? disabled. 3 a ? v-tole ? ant io 3 a reset pin 3 a i ih high level inp ? t c ??? ent 3.3 v io v i = v dd33 ? on-chip p ? ll-down ? esiste ? disabled. 3 a ? v-tole ? ant io 3 a reset pin 3 a v il low level inp ? t voltage 3.3 v io -0.3 0. ? v ? v-tole ? ant io -0.3 0. ? v reset pin -0.3 0. ? v v ih high level inp ? t voltage 3.3 v io ? 3.6 v ? v-tole ? ant io ? ? . ? v reset pin ? ? . ? v v hys schmitt t ? igge ? inp ? t voltage h ? ste ? esis 3.3 v io 400 mv ? v-tole ? ant io 400 mv reset pin 400 mv i ol low level o ? tp ? t c ??? ent (gpio sink c ??? ent) 3.3 v io 4 ma d ? ive ? v ol = 0.4 v 4 ma 3.3 v io ? ma d ? ive ? v ol = 0.4 v ? ma ? v-tole ? ant io ? ma d ? ive ? v ol = 0.4 v ? ma ? v-tole ? ant io 1 ? ma d ? ive ? v ol = 0.4 v 1 ? ma back ? p domain io d ? ive @ v bat = 3.3 v ? v ol = 0.4 v ? pc13 ? pc14 ? pc1 ? . 4 ma i oh high level o ? tp ? t c ??? ent (gpio so ?? ce c ??? ent) 3.3 v i/o 4 ma d ? ive ? v oh = v dd33 - 0.4 v 4 ma 3.3 v i/o ? ma d ? ive ? v oh = v dd33 - 0.4 v ? ma ? v-tole ? ant i/o ? ma d ? ive ? v oh = v dd33 - 0.4 v ? ma ? v-tole ? ant i/o 1 ? ma d ? ive ? v oh = v dd33 - 0.4 v 1 ? ma back ? p domain io d ? ive @ v bat = 3.3 v ? v ol = v dd33 - 0.4v ? pc13 ? pc14 ? pc1 ? . 1 ma v ol low level o ? tp ? t voltage 3.3 v 4 ma d ? ive io ? i ol = 4 ma 0.4 v 3.3 v ? ma d ? ive io ? i ol = ? ma 0.4 v ? v-tole ? ant ? ma d ? ive io ? i ol = ? ma 0.4 v ? v-tole ? ant 1 ? ma d ? ive io ? i ol = 1 ? ma 0.4 v
rev. 1.00 3 ? of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 electrical characteristics electrical characteristics symbol parameter conditions min typ max unit v oh high level o ? tp ? t voltage 3.3 v 4 ma d ? ive io ? i oh = 4 ma v dd33 - 0.4 v v 3.3 v ? ma d ? ive io ? i oh = ? ma v dd33 - 0.4 v v ? v-tole ? ant ? ma d ? ive io ? i oh = ? ma v dd33 - 0.4 v v ? v-tole ? ant 1 ? ma d ? ive io ? i oh = 1 ? ma v dd33 - 0.4 v v r pu inte ? nal p ? ll- ? p ? esisto ? 3.3 v i/o 34 74 k ? v-tole ? ant i/o 3 ? ? 9 k r pd inte ? nal p ? ll-down ? esisto ? 3.3 v i/o ? 9 ? 6 k ? v-tole ? ant i/o 3 ? 107 k adc characteristics table 16 adc characteristics t a = ?? c, unless otherwise specifed. symbol parameter conditions min typ max unit v dda ope ? ating voltage ? .7 3.3 3.6 v v adcin a/d conve ? te ? inp ? t voltage ? ange 0 v ref+ v v ref+ a/d conve ? te ? refe ? ence voltage v dda v dda v i adc c ??? ent cons ? mption v dda = 3.3 v 1 tbd ma i adc_dn powe ? down c ??? ent cons ? mption v dda = 3.3 v 1 10 a f adc a/d conve ? te ? clock 0.7 14 mhz f s sampling ? ate 0.0 ? 1 mhz f adcconv a/d conve ? te ? conve ? sion time 14 1/f adc c ? cles r i inp ? t sampling switch ? esistance 1 k c i inp ? t sampling capacitance no pin/pad capacitance incl ? ded ? pf t su sta ? t ? p ? p time 1 s n resol ? tion 1 ? bits inl integ ? al non-linea ? it ? e ?? o ? f s = 1 mhz ? v dda = 3.3 v ? ? lsb dnl diffe ? ential non-linea ? it ? e ?? o ? f s = 1 mhz ? v dda = 3.3 v 1 lsb e o offset e ?? o ? 10 lsb e g gain e ?? o ? 10 lsb note: 1. g ? a ? anteed b ? design ? not tested in p ? od ? ction. 2. the fgure below shows the equivalent circuit of the a/d converter sample-and-hold input stage whe ? e ci is the sto ? age capacito ?? ri is the ? esistance of the sampling switch and rs is the o ? tp ? t impedance of the signal so ?? ce vs. no ? mall ? the sampling phase d ?? ation is app ? ox imatel ?? 1. ? /fadc. the capacitance ? ci ? m ? st be cha ? ged wit hin this time f ? am e and it must be ensured that the voltage at its terminals becomes suffciently close to vs for acc ?? ac ? . to g ? a ? antee this ? rs ma ? not have an a ? bit ? a ? il ? la ? ge val ? e.
rev. 1.00 36 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 electrical characteristics sar adc c i sample r i r s v s figure 6 adc sampling network model the worst case occurs when the extremities of the input range (0v and vref) are sampled consecutively. in this situation a sampling error below ? lsb is ensured by using the following equation: i n iadc s r cf r ? < + )2ln( 5.1 2 where f adc is the adc clock frequency and n is the adc resolution (n = 12 in this case). a safe margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for in this simple model. if, in a system where the a/d converter is used, there are no rail-to-rail input voltage variations between consecutive sampling phases, rs may be larger than the value indicated by the equation above.
rev. 1.00 37 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 electrical characteristics electrical characteristics comparator characteristics table 17 comparator characteristics t a = -40c ~ ?? c, unless otherwise specifed. symbol parameter conditions min typ max unit v dda ope ? ating voltage compa ? ato ? mode ? .7 3.3 3.6 v v in inp ? t common mode voltage range cp o ? cn v ssa v dda v v ios inp ? t offset voltage (note) t a = ?? c - ? ? mv v h ? s inp ? t h ? ste ? esis no h ? ste ? esis (cmpnhm [1:0] = 00) 0 mv low h ? ste ? esis (cmpnhm [1:0] = 01) 30 mv middle h ? ste ? esis (cmpnhm [1:0] = 10) 70 mv high h ? ste ? esis (cmpnhm [1:0] = 11) 100 mv t rt response time inp ? t ove ? d ? ive = 100mv high speed mode ? 0 100 ns low speed mode ? ? ? s i cmp c ??? ent cons ? mption v dda = 3.3 v high speed mode 100 ? a low speed mode 10 ? a t cmpst compa ? ato ? sta ? t ? p time compa ? ato ? enabled to o ? tp ? t valid. ? 0 ? s i cmp_dn powe ? down s ? ppl ? c ??? ent cmpen = 0 cvrefen = 0 cvrefoe=0 0.1 ? a comparator voltage reference (cvr) v cvr o ? tp ? t range v ssa v dda v n bits cvr scale ? resol ? tion 6 bits t cvrst setting time cvr scale ? setting time f ? om cvref = 000000 to 111111 100 ? s i cvr c ??? ent cons ? mption v dda = 3.3 v cvrefen=1 ? cmprefoe=0 10 ? a cvrefen=1 ? cvrefoe=1 ? 0 40 ? a note: g ? a ? anteed b ? design ? not tested in p ? od ? ction. gptm/mctm characteristics table 18 gptm/mctm characteristics symbol parameter conditions min typ max unit f tm time ? clock so ?? ce fo ? gptm and mctm 7 ? mhz t res time ? ? esol ? tion time 1 f tm f ext exte ? nal single f ? eq ? enc ? on channel 1 ~ 4 1/ ? f tm res time ? ? esol ? tion 16 bits
rev. 1.00 3 ? of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 electrical characteristics i 2 c characteristics table 19 i 2 c characteristics symbol parameter standard mode fast mode fast mode plus unit min max min max min max f scl scl clock f ? eq ? enc ? 100 400 1000 khz t scl(h) scl clock high time 4. ? 1.1 ?? 0.4 ? s t scl(l) scl clock low time 4. ? 1.1 ?? 0.4 ? s t fall scl and sda fall time 1.3 0.34 0.13 ? s t rise scl and sda ? ise time 1.3 0.34 0.13 ? s t su(sda) sda data set ? p time ? 00 1 ?? ? 0 ns t h(sda) sda data hold time 0 0 0 ns t su(sta) start condition set ? p time ? 00 1 ?? ? 0 ns t h(sta) start condition hold time 0 0 0 ns t su(sto) stop condition set ? p time ? 00 1 ?? ? 0 ns note: 1. g ? a ? anteed b ? design ? not tested in p ? od ? ction. ? . to achieve 100khz standa ? d mode ? the pe ? iphe ? al clock f ? eq ? enc ? m ? st be highe ? than ? mhz. 3. to achieve 400khz fast mode ? the pe ? iphe ? al clock f ? eq ? enc ? m ? st be highe ? than ? mhz. 4. to achieve 1mhz fast mode pl ? s ? the pe ? iphe ? al clock f ? eq ? enc ? m ? st be highe ? than ? 0mhz. ? . the above cha ? acte ? istic pa ? amete ? s of the i ? c b ? s timing a ? e based on : seq_filter = 01 and comb_filter_en is disabled. t su(sta) t h(sta) t fall t scl(l) t rise t scl(h) t h(sda) t su(sda) t su(sto) scl sda figure 7 i 2 c timing diagrams
rev. 1.00 39 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 electrical characteristics electrical characteristics spi characteristics table 20 spi characteristics symbol parameter conditions min typ max unit f sck sck clock f ? eq ? enc ? f pclk / ? mhz t sck(h) sck clock high time f pclk / ? ns t sck(l) sck clock low time f pclk / ? ns spi master mode t v(mo) data o ? tp ? t valid time ? ns t h(mo) data o ? tp ? t hold time ? ns t su(mi) data inp ? t set ? p time ? ns t h(mi) data inp ? t hold time ? ns spi slave mode t su(sel) sel enable set ? p time 4 t pclk ns t h(sel) sel enable hold time ? t pclk ns t a(so) data o ? tp ? t access time 3 t pclk ns t dis(so) data o ? tp ? t disable time 10 ns t v(so) data o ? tp ? t valid time ?? ns t h(so) data o ? tp ? t hold time 1 ? ns t su(si) data inp ? t set ? p time ? ns t h(si) data inp ? t hold time 4 ns sck (cpol = 0) sck (cpol = 1) mosi miso mosi miso t sck(h) t sck(l) t sck data valid data valid data valid data valid data valid data valid data valid data valid t v(mo) cpha = 0 cpha = 1 t h(mo) t h(mi) t su(mi) t v(mo) t h(mo) t su(mi) t h(mi) data valid data valid data valid data valid figure 8 spi timing diagrams - spi master mode
rev. 1.00 40 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 electrical characteristics sck (cpol=0) sck (cpol=1) mosi miso t sck(h) t sck(l) t sck msb/lsb out msb/lsb in t v(so) t h(so) t su(si) t h(si) sel lsb/msb out lsb/msb in t a(so) t su(sel) t dis(so) t h(sel) figure 9 spi timing diagrams - spi slave mode with cpha=1 i 2 s characteristics table 21 i 2 s characteristics symbol parameter conditions min typ max unit i ? s maste ? mode t wsd(mo) ws o ? tp ? t to bclk dela ? tbd ns t dod(mo) data o ? tp ? t to bclk dela ? tbd ns t dis(mi) data inp ? t set ? p time tbd ns t dih(mi) data inp ? t hold time tbd ns i ? s slave mode t bch(si) bclk high p ? lse width tbd ns t bcl(si) bclk low p ? lse width tbd ns t wss(si) ws inp ? t set ? p time tbd ns t dod(so) data o ? tp ? t to bclk dela ? tbd ns t dis(si) data inp ? t set ? p time tbd ns t dih(si) data inp ? t hold time tbd ns
rev. 1.00 41 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 electrical characteristics electrical characteristics bclk ws sdo sdi t dis(mi) t dih(mi) t dod(mo) t wsd(mo) figure 1 timing of i 2 s master mode bclk ws sdo sdi t dis(si) t dih(si) t dod(so) t wss(si) t bch(si) t bcl(si) figure 11 timing of i 2 s slave mode
rev. 1.00 4 ? of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 electrical characteristics usb characteristics the usb interface is usb-if certifed - full speed. table 22 usb dc electrical characteristics symbol parameter conditions min typ max unit v dd33 usb ope ? ating voltage 3.0 3.6 v v di diffe ? ential inp ? t sensitivit ? usbdp-usbdm 0. ? v v cm common mode voltage ? ange 0. ? ? . ? v v se single-ended ? eceive ? th ? eshold 0. ? ? .0 v v ol pad o ? tp ? t low voltage r l of 1.5 k to v dd33 0 0.3 v v oh pad o ? tp ? t high voltage ? . ? 3.6 v v crs diffe ? ential o ? tp ? t signal c ? oss- point voltage 1.3 ? .0 v z drv d ? ive ? o ? tp ? t ? esistance 10 c in t ? ansceive ? pad capacitance ? 0 pf note: 1. g ? a ? anteed b ? design ? not tested in p ? od ? ction. 2. to be compliant with the usb 2.0 full-speed electrical specifcation, the usbdp pin should be pulled up with a 1.5 k external resistor to a 3.0-to-3.6 v voltage s ? ppl ? . 3. the usb f ? nctionalit ? is ens ?? ed down to ? .7 v b ? t not the f ? ll usb elect ? ical cha ? acte ? istics which will expe ? ience deg ? adation in the ? .7-to-3.0 v vdd33 voltage ? ange. 4. rl is the load connected to the usb d ? ive ? usbdp. t r t f 90% 90% 10% 10% fall time rise time v crs figure 12 usb signal rise time and fall time and cross-point voltage (vcrs) defnition table 23 usb ac electrical characteristics symbol parameter conditions min typ max unit t ? rise time c l = ? 0 pf 4 - ? 0 ns t f fall time c l = ? 0 pf 4 - ? 0 ns t ? /f rise time / fall time matching t ? /f = t ? / t f 90 - 110 %
rev. 1.00 43 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 electrical characteristics package information 6 package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to p ackaging is listed below. click o n the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product tape and reel specifcations) ? packing meterials information ? carton information
rev. 1.00 44 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 package information 48-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.3 ? 4 bsc b 0. ? 76 bsc c 0.3 ? 4 bsc d 0. ? 76 bsc e 0.0197 bsc f 0.007 0.009 0.011 g 0.0 ? 3 0.0 ?? 0.0 ? 7 h 0.063 i 0.00 ? 0.006 ? 0.01 ? 0.0 ? 4 0.030 k 0.004 0.00 ? 0 D 7 symbol dimensions in mm min. nom. max. a 9.0 bsc b 7.0 bsc c 9.0 bsc d 7.0 bsc e 0. ? bsc f 0.17 0. ?? 0. ? 7 g 1.3 ? 1.4 1.4 ? h 1.60 i 0.0 ? 0.1 ? ? 0.4 ? 0.60 0.7 ? k 0.09 0. ? 0 0 D 7
rev. 1.00 4 ? of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 package information package information 64-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.3 ? 4 bsc b 0. ? 76 bsc c 0.3 ? 4 bsc d 0. ? 76 bsc e 0.016 bsc f 0.00 ? 0.007 0.009 g 0.0 ? 3 0.0 ?? 0.0 ? 7 h 0.063 i 0.00 ? 0.006 ? 0.01 ? 0.0 ? 4 0.030 k 0.004 0.00 ? 0 D 7 symbol dimensions in mm min. nom. max. a 9.0 bsc b 7.0 bsc c 9.0 bsc d 7.0 bsc e 0.4 bsc f 0.13 0.1 ? 0. ? 3 g 1.3 ? 1.4 1.4 ? h 1.60 i 0.0 ? 0.1 ? ? 0.4 ? 0.60 0.7 ? k 0.09 0. ? 0 0 D 7
rev. 1.00 46 of 46 ? an ? a ?? ??? ? 01 ? 3 ? -bit arm ? co ? tex?-m3 mcu ht3 ? f16 ? 3/ht3 ? f16 ? 4 cop ?? ight ? ? 01 ? b ? holtek semiconductor inc. the info ? mation appea ? ing in this data sheet is believed to be acc ?? ate at the time of p ? blication. howeve ?? holtek ass ? mes no ? esponsibilit ? a ? ising f ? om the ? se of the specifcations described. the applications mentioned herein are used solely fo ? the p ?? pose of ill ? st ? ation and holtek makes no wa ?? ant ? o ? ? ep ? esentation that s ? ch applications will be s ? itable witho ? t f ?? the ? modification ? no ? ? ecommends the ? se of its p ? od ? cts fo ? application that ma ? p ? esent a ? isk to h ? man life d ? e to malf ? nction o ? othe ? wise. holtek's p ? od ? cts a ? e not a ? tho ? ized fo ? ? se as c ? itical components in life s ? ppo ? t devices o ? s ? stems. holtek ? ese ? ves the ? ight to alte ? its products without prior notifcation. for the most up-to-date information, please visit o ?? web site at http://www.holtek.com.tw.

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