1 errata sheet v1.0 this errata sheet refers to: ? the following datasheets: at91m42800a summary, rev. 1779as?06/01 at91m42800a, rev. 1779a?06/01 at91m42800a, electrical characteristics, rev. 1776a?08/01 144-lead tqfp and 144s-ball bga devices with the following markings: 9. warning: additional nwait constraints when the nwait signal is asserted during an external memory access, the fol- lowing ebi behavior is correct: ? nwait is asserted before the first rising edge of the master clock and respects the nwait to mcki rising setup timing as defined in the electrical characteristics datasheet. ? nwait is sampled inactive and at least one standard wait state remains to be executed, even if nwait does not meet the nwait to first mcki rising setup timing (i.e., nwait is asserted only on the second rising edge of mcki). in these cases, the access is delayed as required by nwait and the access oper- ations are correctly performed. in other cases, the following erroneous behavior occurs: ? 32-bit read accesses are not managed correctly and the first 16-bit data sampling takes into account only the standard wait states. 16- and 8-bit accesses are not affected. ? during write accesses of any type, the nwe rises on the rising edge of the last cycle as defined by the programmed number of wait states. however, nwait assertion does affect the length of the total access. only the nwe pulse length is inaccurate. at maximum speed, asserting the nwait in the first access cycle is not possible, as the sum of the timings ?mcki falling to chip select? and ?nwait setup to mcki rising? are generally higher than one half of a clock period. this leads to using at least one standard wait state. however, this is not sufficient except to per- form byte or half-word read accesses. word and write accesses require at least two standard wait states. at91 arm ? thumb ? microcontrollers at91m42800a errata sheet v1.0 rev. 1782b?01/02 at91m42800a-33ai at91m42800a-33ci internal product reference 56544c
2 at91m42800a errata sheet 1782b?01/02 the following waveforms further explain the issue: if the nwait setup time is satisfied on the first rising edge of mcki, the behavior is accurate. the ebi operations are not affected when the nwait rises. figure 1. nwait rising if the nwait setup time is satisfied on the following edges of mcki and if at least one standard wait state remains to be executed, the behavior is accurate. in the following example, the number of standard wait states is two. the nwait setup time on the second rising edge of mcki must be met. figure 2. number of standard wait states is two note: 1. these numbers refer to the standard access cycles. nwait setup before mcki rising (eb16) mcki nwait standard access length with two wait states eb16 1 (1) 2 (1) 3 (1) mcki nwait ncs
3 at91m42800a errata sheet 1782b ? 01/02 if the first two conditions are not met during a 32-bit read access, the first 16-bit data is read at the end of the standard 16-bit read access. in the following example, the number of standard waits is one. nwait assertions do affect both nrd pulse lengths, but first data sampling is not delayed. the second data sampling is correct. figure 3. number of standard wait states is one note: 1. these numbers refer to the standard access cycles. if the first two conditions are not met during write accesses, the nwe signal is not affected by the nwait assertion. the following example illustrates the number of standard wait states. nwait is not asserted during the first cycle, but is asserted at the second and last cycle of the standard access. the access is correctly delayed as the ncs line rises accordingly to the nwait assertion. however, the nwe signal waveform is unchanged, and rises too early. figure 4. description of the number of standard wait states 32-bit access = two 16-bit accesses each access length = one wait state + assertion for one more cycle eb16 1 (1) 2 (1) mcki nwait nrd 2 (1) first data sampling (erroneous) 1 (1) 2 (1) 2 (1) second data sampling (correct) access length = one wait state + assertion of the nwait for one more cycle eb16 mcki nwait nwe ncs erroneous nwe rising
4 at91m42800a errata sheet 1782b ? 01/02 8. possible glitches on mcko while commuting clock unpredictable transitional pulses may occur on the mcko pin when modifying the mckoss field in the pmc clock generator mode register. the length of these glitches can be lower than the lowest period of the selected or current clock. when switching from the slow clock (i.e., after reset) to any of the pll outputs (inverted or divided by 2), a pulse of less than 10 ns is output on the pin mcko. problem fix/workaround the glitch description above is merely a user warning/possibility. if the glitches do occur, there is no problem fix/workaround to propose. 7. initializing spi in master mode may cause problems initializing the spi in master mode may cause a mode fault detection. problem fix/workaround in order to prevent this error, the user should pull up the pa14/npcsa0/nssa pin for spia or the pa21/npcsa0/nssb pin for spib to the v ddio power supply. 6. break is sent before last written character when the start break command is activated in the usart control register and while a character is in the usart transmit holding register, the break is transmitted before the character. problem fix/workaround the user must wait for the txempty flag in the usart status register before sending a break command. 5. end of break is not guaranteed when performing a stop break command, the usart transmitter normally inserts a ? 12-bit at level 1 ? sequence after the break. this feature is not guaranteed. problem fix/workaround the user must use the time guard programmed at the value 12. 4. sck is ignored at 32 khz if the origin of the master clock is the slow clock, the usart channels cannot be synchronized with a clock that comes from the sck pin. problem fix/workaround no problem fix/workaround to propose. 3. sck maximum frequency relative to mck in synchronous mode in usart synchronous mode, the external clock frequency (sck) must be at least 10 times lower than the master clock. problem fix/workaround no problem fix/workaround to propose. 2. pio input filters are not bit-to-bit selectable the pio input filters are enabled and disabled only for all of the pio input pins and not individually. to activate them, the user must write 0x0001 in the pio ifer and 0x0001 in the pio ifdr to deactivate them. problem fix/workaround no problem fix/workaround to propose.
5 at91m42800a errata sheet 1782b ? 01/02 1. pio multi-drive capability not usable the pio multi-drive capability does not work in pio mode or in peripheral mode. problem fix/workaround no practical workaround proposed.
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