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1 features applications description ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 16-bit, 80/105/135-msps analog-to-digital converters wireless infrastructure (multi-carrier gsm, 23 80/105/135-msps sample rates wcdma, lte) 16-bit resolution test and measurement instrumentation sfdr: 95 dbc at 70 mhz and 135 msps software-defined radio snr: 78.6 dbfs at 70 mhz and 135 msps data acquisition efficient ddr lvds-compatible outputs power amplifier linearization internal dither available communication instrumentation total power dissipation: 2.2 w radar power-down mode: 70 mw medical imaging on-chip high impedance analog buffer qfn-64 powerpad? package (9 mm 9 mm footprint) industrial temperature range: ? 40 c to +85 c the ads5481/ads5482/ads5483 (ads548x) is a 16-bit family of analog-to-digital converters (adcs) that operate from both a 5-v supply and 3.3-v supply while providing lvds-compatible digital outputs. the ads548x integrated analog input buffer isolates the internal switching of the onboard track and hold (t & h) from disturbing the signal source while providing a high-impedance input. an internal reference generator is also provided to simplify the system design. designed for highest total enob, the ads548x family has outstanding low noise performance and spurious-free dynamic range. the ads548x is available in an qfn-64 powerpad package. the device is built on texas instruments complementary bipolar process (bicom3) and is specified over the full industrial temperature range ( ? 40 c to +85 c). sfdr snr vs vs input frequency input frequency 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 powerpad is a trademark of texas instruments. 3 all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2008, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. f i ? input frequency ? mhz 80 85 90 95 100 0 20 40 60 80 100 120 140 sfdr ? dbc g068 ads5482 ads5483 ads5481 f i ? input frequency ? mhz 75 76 77 78 79 80 81 82 0 20 40 60 80 100 120 140 snr ? dbfs g069 ads5483 ads5481 ads5482
ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package/ordering information (1) specified package package ordering transport product package-lead temperature designator marking number media, quantity range ads5481irgct tape and reel, 250 ads5481 qfn-64 rgc ? 40 c to +85 c az5481 ads5481irgcr tape and reel, 2000 ads5482irgct tape and reel, 250 ads5482 qfn-64 rgc ? 40 c to +85 c az5482 ADS5482IRGCR tape and reel, 2000 ads5483irgct tape and reel, 250 ads5483 qfn-64 rgc ? 40 c to +85 c az5483 ads5483irgcr tape and reel, 2000 (1) for the most current product and ordering information see the package option addendum located at the end of this document, or see the ti website at www.ti.com.. 2 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483
absolute maximum ratings (1) thermal characteristics (1) ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 over operating free-air temperature range, unless otherwise noted. ads5481, ads5482, ads5483 unit avdd5 to gnd 6 v supply voltage avdd3 to gnd 5 v dvdd3 to gnd 5 v valid when avdd5 is within normal operating range. when avdd5 is off, analog inputs should be < 0.5v. if not, the protection diode between analog input to the inputs and avdd5 will become forward-biased and could be ? 0.3 to (avdd5 + 0.3) v gnd damaged or shorten device lifetime (see figure 60 ). short transient conditions during power on/off are not a concern. valid when avdd3 is within normal operating range. when avdd3 is off, clock inputs should be < 0.5v. if not, the protection diode between the clock input to gnd inputs and avdd3 will become forward-biased and could be damaged or ? 0.3 to (avdd3 + 0.3) v shorten device lifetime (see figure 67 ). short transient conditions during power on/off are not a concern. clkp to clkm 2.5 v digital data output to gnd ? 0.3 to (dvdd3 + 0.3) v digital data output plus-to-minus 1 v operating temperature range ? 40 to +85 c maximum junction temperature +150 c storage temperature range ? 65 to +150 c esd, human-body model (hbm) 2 kv (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. kirkendall voidings and current density information for calculation of expected lifetime are available upon request. parameter test conditions typ unit soldered thermal pad, no airflow 20 r q ja soldered thermal pad, 150-lfm airflow 16 c/w r q jc thermal resistance from the junction to the package case (top) 7 r q jp thermal resistance from the junction to the thermal pad (bottom) 0.2 (1) using 49 thermal vias ( 7 7 array). see powerpad package in the application information section. copyright ? 2008, texas instruments incorporated submit documentation feedback 3 product folder link(s): ads5481 ads5482 ads5483
recommended operating conditions electrical characteristics (ads5481, ads5482, ads5483) ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com ads5481, ads5482, ads5483 unit min typ max supplies avdd5 analog supply voltage 4.75 5 5.25 v avdd3 analog supply voltage 3.1 3.3 3.6 v dvdd3 output driver supply voltage 3 3.3 3.6 v analog input differential input range 3 v pp vcm input common mode 3.1 v digital output (dry, data) maximum differential output load (parasitic or intentional) 5 pf differential output resistance 100 ? clock input (clk) max clk input sample rate (sine wave) 10 rated msps clock clock amplitude, differential sine wave (see figure 69 ) 1.5 5 v pp clock duty cycle (see figure 74 ) 45 50 55 % t a operating free-air temperature ? 40 +85 c typical values at t a = +25 c: minimum and maximum values over full temperature range t min = ? 40 c to t max = +85 c, sampling rate = max rated, 50% clock duty cycle, avdd5 = 5 v, avdd3 = 3.3 v, dvdd3 = 3.3 v, ? 1 dbfs differential input, and 3-v pp differential clock, unless otherwise noted. ads5481 ads5482 ads5483 parameter test conditions unit min typ max min typ max min typ max clock rate 80 105 135 msps resolution 16 16 16 bits analog inputs differential input range 3 3 3 v pp analog input common-mode self-biased; see vcm 3.1 3.1 3.1 v voltage specification below input resistance (dc) each input to vcm 1000 1000 1000 ? each input to gnd input capacitance 3.5 3.5 3.5 pf (including package) analog input bandwidth 125 125 485 mhz ( ? 3db) common-mode signal cmrr common-mode rejection ratio 65 65 65 db 70 mhz (see figure 56 ) internal reference voltage vref reference voltage 1.2 1.2 1.2 v analog input common-mode with internal voltage vcm 3 3.15 3.35 3 3.15 3.35 3 3.15 3.35 v voltage reference output reference vcm temperature coefficient -1 -1 -1 mv/ c 4 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483
ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 electrical characteristics (ads5481, ads5482, ads5483) (continued) typical values at t a = +25 c: minimum and maximum values over full temperature range t min = ? 40 c to t max = +85 c, sampling rate = max rated, 50% clock duty cycle, avdd5 = 5 v, avdd3 = 3.3 v, dvdd3 = 3.3 v, ? 1 dbfs differential input, and 3-v pp differential clock, unless otherwise noted. ads5481 ads5482 ads5483 parameter test conditions unit min typ max min typ max min typ max dynamic accuracy no missing codes, dnl differential linearity error -0.99 0.5 1.0 -0.99 0.5 1.0 -0.99 0.5 1.0 lsb f in = 30 mhz inl integral linearity error f in = 30 mhz -10 3 +10 -10 3 +10 -10 3 +10 lsb offset error -15 15 -15 15 -15 15 mv offset temperature coefficient -0.02 -0.02 -0.02 mv/ c gain error -6 2 6 -6 2 6 -6 2 6 %fs gain temperature coefficient -0.01 -0.01 -0.01 mv/ c power supply i avdd5 5-v analog 316 330 316 330 317 330 ma v in = full-scale, i avdd3 3.3-v analog 131 150 131 150 133 150 ma f in = 30 mhz, f s = max rated, normal i dvdd3 3.3-v digital/lvds 60 65 60 65 60 65 ma operation total power dissipation 2.15 2.35 2.15 2.35 2.2 2.35 w i avdd5 5-v analog 98 98 98 ma i avdd3 3.3-v analog 35 35 35 ma light sleep mode (pdwnf=h, pdwns=l) i dvdd3 3.3-v digital/lvds 0.07 0.07 0.07 ma total power dissipation 605 680 680 680 605 680 mw i avdd5 5-v analog 13 13 13 ma i avdd3 3.3-v analog 2 2 2 ma deep sleep mode (pdwnf=l, pdwns=h) i dvdd3 3.3-v digital/lvds 0.07 0.07 0.07 ma total power dissipation 70 100 70 100 70 100 mw fast wakeup time (light sleep) from pdwnf disabled 600 600 600 m s slow wakeup time (deep from pdwns disabled 6 6 6 ms sleep) avdd5 supply power-supply rejection ratio, 60 60 60 db without 0.1- m f board supply avdd3 supply 80 80 80 db psrr capacitors, with 1-mhz supply noise (see dvdd3 supply 95 95 95 db figure 76 ) dynamic ac characteristics f in = 10 mhz 79.5 81 79.5 80.8 77 79 f in = 30 mhz 79.4 80.6 79.4 80.7 77 79 snr signal-to-noise ratio f in = 70 mhz 80.1 80.1 78.6 dbfs f in = 100 mhz 79.6 80 78.2 f in = 130 mhz 77.8 f in = 10 mhz 88 98 88 98 87 97 f in = 30 mhz 88 97 88 98 87 97 sfdr spurious-free dynamic range f in = 70 mhz 93 91 95 dbc f in = 100 mhz 92 90 88 f in = 130 mhz 85 f in = 10 mhz 88 108 88 107 87 102 f in = 30 mhz 88 101 88 105 87 99 hd2 second-harmonic f in = 70 mhz 100 101 95 dbc f in = 100 mhz 99 100 92 f in = 130 mhz 85 copyright ? 2008, texas instruments incorporated submit documentation feedback 5 product folder link(s): ads5481 ads5482 ads5483
ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com electrical characteristics (ads5481, ads5482, ads5483) (continued) typical values at t a = +25 c: minimum and maximum values over full temperature range t min = ? 40 c to t max = +85 c, sampling rate = max rated, 50% clock duty cycle, avdd5 = 5 v, avdd3 = 3.3 v, dvdd3 = 3.3 v, ? 1 dbfs differential input, and 3-v pp differential clock, unless otherwise noted. ads5481 ads5482 ads5483 parameter test conditions unit min typ max min typ max min typ max f in = 10 mhz 88 103 88 96 87 110 f in = 30 mhz 88 100 88 98 87 100 hd3 third-harmonic f in = 70 mhz 93 91 96 dbc f in = 100 mhz 92 90 88 f in = 130 mhz 88 f in = 10 mhz 88 98 88 98 87 97 f in = 30 mhz 88 97 88 98 87 97 worst harmonic/spur f in = 70 mhz 96 97 98 dbc (other than hd2 and hd3) f in = 100 mhz 96 94 97 f in = 130 mhz 96 f in = 10 mhz 85 96 85 95 84 97 f in = 30 mhz 85 94 85 95 84 94 thd total harmonic distortion f in = 70 mhz 93 88 91 dbc f in = 100 mhz 88 92 86 f in = 130 mhz 83 f in = 10 mhz 77.8 80 77.8 79.5 75 77.9 f in = 30 mhz 77.7 79.5 77.7 79.3 75 77.8 sinad signal-to-noise and distortion f in = 70 mhz 78.9 78.2 77.4 dbc f in = 100 mhz 77.8 78 76.6 f in = 130 mhz 76 f in1 = 29.5 mhz, f in2 = 30.5 mhz, each at ? 7 dbfs, 103 101 100 worst spur imd two-tone sfdr dbfs f in1 = 102 mhz, f in2 = 103 mhz, each at ? 7 dbfs, 90 worst spur f in = 10 mhz (from sinad 12.63 13 12.63 12.9 12.16 12.64 in dbc) enob effective number of bits bits f in = 30 mhz (from sinad 12.61 12.9 12.61 12.88 12.16 12.63 in dbc) analog inputs shorted rms idle-channel noise 1.8 1.8 2.2 lsbrms together lvds digital outputs assumes a 100 ? differential v od differential output voltage ( ) load on each lvds pair and 247 350 454 247 350 454 247 350 454 mv lvds bias = 3.5 ma common-mode output v oc 1.125 1.375 1.125 1.375 1.125 1.375 v voltage digital inputs v ih high level input voltage 2.0 2.0 2.0 v v il low level input voltage 0.8 0.8 0.8 v i ih high level input current pdwnf, pdwns, dither 1 1 1 m a i il low level input current -1 -1 -1 m a input capacitance 2 2 2 pf 6 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483
timing information timing characteristics (1) ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 figure 1. timing diagram typical values at t a = +25 c: minimum and maximum values over full temperature range t min = ? 40 c to t max = +85 c, sampling rate = max rated, 50% clock duty cycle, avdd5 = 5 v, avdd3 = 3.3 v, dvdd3 = 3.3 v, and 3-v pp differential clock, unless otherwise noted. parameter test conditions min typ max unit t a aperture delay 200 ps aperture jitter, rms internal jitter of the adc 80 fs latency 4.5 cycles t clk clock period 1e9/clk 100 ns t clkh clock pulse duration, high clk = max rated clock for that part number 0.5e9/clk 50 ns t clkl clock pulse duration, low 0.5e9/clk 50 ns t dry clk to dry delay (2) 800 1250 1700 ps zero crossing, 5-pf parasitic to gnd t data clk to data delay (2) 700 1250 1800 ps t skew data to dry skew t data ? t dry , 5-pf parasitic to gnd ? 600 0 600 ps t rise dry/data rise time 500 ps 5-pf parasitic to gnd t fall dry/data fall time 500 ps (1) timing parameters are assured by design or characterization, but not production tested. (2) dry and data are updated on the rising edge of clk input. the latency must be added to t data to determine the overall propagation delay. copyright ? 2008, texas instruments incorporated submit documentation feedback 7 product folder link(s): ads5481 ads5482 ads5483 n+1 dx_y_p n+2 n+6 t clkl t dry t data t clkh t a dx_y_m clkp clkm n+3 n+4 n+5 dry_m dry_p sample n t0158-02 latency = 4.5 clock cycles clk input clk output output data o o o o o o o o e e e e e e e n+1 n nC1 nC2 nC3 nC4 nC5 e = even bits = b0, b2, b4, b6, b8, b10, b12, b14 o = odd bits = b1, b3, b5, b7, b9, b11, b13, b15
pin configuration ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com 8 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483 agnd 4847 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ads548x rgc package (top view) 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 avdd5 avdd5 agnd ref ncnc agnd avdd5 avdd3 agnd inp inm agnd avdd5 avdd3 vcm agnd avdd5 avdd3 agnd clkm clkp agnd a vdd5 avdd3 agnd avdd5 avdd3 agnd avdd5 avdd3 agnd 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 50 32 49 d4_5_pd4_5_m d2_3_p d2_3_m d0_1_p d0_1_m dvdd3 dgnd nc nc nc nc dither pdwnf pdwns lvdsb dgnd dvdd3 d14_15_p d14_15_m d12_13_p d12_13_m d10_11_p d10_11_m d8_9_p d8_9_m dry_p dry_m dvdd3 dgnd d6_7_p d6_7_m p0056-08
ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 table 1. terminal functions terminal description name no. 1, 2, 8, 14, 18, avdd5 5v analog supply 24, 27, 30 9, 15, 19, 25, avdd3 3.3v analog supply 28, 31 3, 7, 10, 13, 17, agnd 20, 23, 26, 29, analog ground 32 dvdd3 42, 52, 63 3.3v digital supply dgnd 41, 51, 64 digital ground nc 5, 6, 37-40 no connects - leave floating inp, inm 11, 12 differential analog inputs (p = plus = true, m = minus = complement) clkm, clkp 21, 22 differential clock inputs (p = plus = true, m = minus = complement) reference voltage input/output (1.2v nominal). to use an external reference and to turn the internal ref 4 reference off, pull both pdwnf and pdwns to logic high (dvdd3). analog input common mode, output (3.1v), for use in applications that require use of the internally vcm 16 generated common-mode. see the applications section for more information on using vcm. external bias resistor for lvds bias current, normally 10k ? to gnd to provide nominal 3.5ma lvds lvdsb 33 current light sleep power down, fast wakeup, logic high (dvdd3) = light sleep enabled (bandgap reference pdwnf 35 remains on) deep sleep power down, slow wakeup, logic high (dvdd3) = deep sleep enabled (bandgap reference is pdwns 34 off) dither 36 dither enable, logic high (dvdd3) = dither enabled dry_p, 54, 53 dataready signal (lvds clockout) (p = plus = true, m = minus = complement) dry_m d14_15_p, 62, 61 ddr lvds output bits 14 then 15 (15 is msb) (p = plus = true, m = minus = complement) d14_15_m de_o_p, 43-50, 55-62 ddr lvds output bits e (even) then o (odd) (p = plus = true, m = minus = complement) de_o_m d0_1_p, 44, 43 ddr lvds output bits 0 then 1 (0 is lsb) (p = plus = true, m = minus = complement) d0_1_m powerpad 65 analog ground (exposed pad on bottom of package) copyright ? 2008, texas instruments incorporated submit documentation feedback 9 product folder link(s): ads5481 ads5482 ads5483
typical characteristics ads5481 - 80 msps typical data ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. plots in this section are with a clock of 80msps unless otherwise specified. ads5481 spectral performance ads5481 spectral performance vs vs fft for 10 mhz input signal fft for 30 mhz input signal figure 2. figure 3. ads5481 spectral performance ads5481 spectral performance vs vs fft for 60 mhz input signal fft for 100 mhz input signal figure 4. figure 5. 10 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483 f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 10 20 30 40 amplitude ? db g001 sfdr = 99 dbc sinad = 81 dbfssnr = 81.1 dbfs thd = 96.5 dbc f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 10 20 30 40 amplitude ? db g002 sfdr = 99 dbc sinad = 80.8 dbfssnr = 80.9 dbfs thd = 94.2 dbc f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 10 20 30 40 amplitude ? db g003 sfdr = 102 dbc sinad = 80.3 dbfssnr = 80.4 dbfs thd = 97.7 dbc f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 10 20 30 40 amplitude ? db g004 sfdr = 94 dbc sinad = 79.6 dbfssnr = 79.8 dbfs thd = 92.6 dbc
ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. ads5481 ac performance ads5481 sfdr vs vs input amplitude (70 mhz input signal) input amplitude (70 mhz input signal) figure 6. figure 7. ads5481 two-tone intermodulation distortion ads5481 two-tone intermodulation distortion (fft for 29.5 mhz and 30.5 mhz at ? 7 dbfs) (fft for 69.5 mhz and 70.5 mhz at ? 7 dbfs) figure 8. figure 9. copyright ? 2008, texas instruments incorporated submit documentation feedback 11 product folder link(s): ads5481 ads5482 ads5483 input amplitude ? dbfs 0 10 20 30 40 50 60 70 80 90 100 110 120 130 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ac performance ? db g009 f s = 80 msps f in = 70 mhz a in = 0 to ?100 dbfs 256k point fft sfdr (dbfs,dither on) snr (dbc,dither on) snr (dbfs,dither on) sfdr (dbc,dither off) sfdr (dbfs,dither off) sfdr (dbc,dither on) input amplitude ? dbfs 60 65 70 75 80 85 90 95 100 ?40 ?36 ?32 ?28 ?24 ?20 ?16 ?12 ?8 ?4 0 sfdr ? dbc g010 f s = 80 msps f in = 70 mhz a in = 0 to ?40 dbfs 256k point fft sfdr (dbc,dither off) sfdr (dbc,dither on) f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 10 20 30 40 amplitude ? db g011 f in 1 = 29.5 mhz, 7 dbfs f in 2 = 30.5 mhz, 7 dbfs imd3 = 101 dbfssfdr = 101 dbfs snr = 80.9 dbfs dither enabled, clk = 80 msps f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 10 20 30 40 amplitude ? db g012 f in 1 = 69.5 mhz, 7 dbfs f in 2 = 70.5 mhz, 7 dbfs imd3 = 95 dbfssfdr = 95 dbfs snr = 80.5 dbfs dither enabled, clk = 80 msps
ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. ads5481 two-tone performance vs input amplitude (f 1 = 29.5 mhz and f 2 = 30.5 mhz) ads5481 differential nonlinearity figure 10. figure 11. ads5481 sfdr vs ads5481 integral nonlinearity avdd5 over temperature figure 12. figure 13. 12 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483 input amplitude ? dbfs ?140 ?130 ?120 ?110 ?100 ?90 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 performance ? dbfs g013 dither, dominant spur (dbfs) dither , 2f1?f2 (dbfs) no dither , dominant spur (dbfs) dither , 2f2?f1 (dbfs) code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 16384 32768 49152 65536 dnl ? lsb g014 f s = 80 msps f in = 10 mhz, 1 dbfs code ?4 ?3 ?2 ?1 0 1 2 3 4 0 16384 32768 49152 65536 inl ? lsb g015 f s = 80 msps f in = 10 mhz, 1 dbfs a vdd5 ? supply v oltage ? v 80 85 90 95 100 4.7 4.8 4.9 5.0 5.1 5.2 5.3 sfdr ? dbc g016 f s = 80 msps f in = 30 mhz t a = 25 c t a = 55 c t a = 10 c t a = 100 c t a = 85 c t a = ?20 c t a = 0 c t a = ?40 c
ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. ads5481 snr ads5481 sfdr vs vs avdd5 over temperature avdd3 over temperature figure 14. figure 15. ads5481 snr ads5481 sfdr vs vs avdd3 over temperature dvdd3 over temperature figure 16. figure 17. copyright ? 2008, texas instruments incorporated submit documentation feedback 13 product folder link(s): ads5481 ads5482 ads5483 a vdd5 ? supply v oltage ? v 75 76 77 78 79 80 81 82 4.7 4.8 4.9 5.0 5.1 5.2 5.3 snr ? dbfs g017 t a = 55 c t a = 85 c t a = 25 c t a = 100 c f s = 80 msps f in = 30 mhz t a = 10 c t a = ?20 c t a = 0 c t a = ?40 c a vdd3 ? supply v oltage ? v 80 85 90 95 100 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 sfdr ? dbc g018 t a = 100 c t a = 85 c t a = 25 c f s = 80 msps f in = 30 mhz t a = 10 c t a = 55 c t a = 0 c t a = ?20 c t a = ?40 c a vdd3 ? supply v oltage ? v 75 76 77 78 79 80 81 82 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 snr ? dbfs g019 f s = 80 msps f in = 30 mhz t a = 55 c t a = 85 c t a = 25 c t a = 100 c t a = 10 c t a = ?20 c t a = 0 c t a = ?40 c dvdd3 ? supply v oltage ? v 80 85 90 95 100 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 sfdr ? dbc g020 t a = 100 c t a = 85 c t a = 25 c f s = 80 msps f in = 30 mhz t a = 10 c t a = 55 c t a = 0 c t a = ?20 c t a = ?40 c
ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. ads5481 snr vs dvdd3 over temperature figure 18. 14 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483 dvdd3 ? supply v oltage ? v 75 76 77 78 79 80 81 82 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 snr ? dbfs g021 t a = 55 c t a = 85 c t a = 25 c t a = 100 c t a = 10 c t a = ?20 c t a = ?40 c t a = 0 c f s = 80 msps f in = 30 mhz
ads5482 - 105 msps typical data ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. plots in this section are with a clock of 105msps unless otherwise specified. ads5482 spectral performance ads5482 spectral performance vs vs fft for 10 mhz input signal fft for 30 mhz input signal figure 19. figure 20. ads5482 spectral performance ads5482 spectral performance vs vs fft for 70 mhz input signal fft for 90 mhz input signal figure 21. figure 22. copyright ? 2008, texas instruments incorporated submit documentation feedback 15 product folder link(s): ads5481 ads5482 ads5483 f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 10 20 30 40 50 amplitude ? db g005 sfdr = 101 dbc sinad = 80.8 dbfssnr = 80.8 dbfs thd = 100.4 dbc f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 10 20 30 40 50 amplitude ? db g006 sfdr = 100 dbc sinad = 80.2 dbfssnr = 80.3 dbfs thd = 96.6 dbc f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 10 20 30 40 50 amplitude ? db g007 sfdr = 97 dbc sinad = 79.4 dbfssnr = 79.5 dbfs thd = 93.8 dbc f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 10 20 30 40 50 amplitude ? db g008 sfdr = 90 dbc sinad = 78.8 dbfssnr = 79.3 dbfs thd = 88.1 dbc
ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. ads5482 ac performance ads5482 sfdr vs vs input amplitude (70 mhz input signal) input amplitude (70 mhz input signal) figure 23. figure 24. ads5482 two-tone intermodulation distortion ads5482 two-tone intermodulation distortion (fft for 29.5 mhz and 30.5 mhz at ? 7 dbfs) (fft for 69.5 mhz and 70.5 mhz at ? 7 dbfs) figure 25. figure 26. 16 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483 input amplitude ? dbfs 0 10 20 30 40 50 60 70 80 90 100 110 120 130 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ac performance ? db g022 f s = 105 msps f in = 70 mhz a in = 0 to ?100 dbfs 256k point fft sfdr (dbfs,dither on) snr (dbc,dither on) snr (dbfs,dither on) sfdr (dbc,dither off) sfdr (dbfs,dither off) sfdr (dbc,dither on) input amplitude ? dbfs 60 65 70 75 80 85 90 95 100 ?40 ?36 ?32 ?28 ?24 ?20 ?16 ?12 ?8 ?4 0 sfdr ? dbc g023 f s = 105 msps f in = 70 mhz a in = 0 to ?40 dbfs 256k point fft sfdr (dbc,dither off) sfdr (dbc,dither on) f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 10 20 30 40 50 amplitude ? db g024 f in 1 = 29.5 mhz, 7 dbfs f in 2 = 30.5 mhz, 7 dbfs imd3 = 101 dbfssfdr = 101 dbfs snr = 80.6 dbfs dither enabled, clk = 105 msps f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 10 20 30 40 50 amplitude ? db g025 f in 1 = 69.5 mhz, 7 dbfs f in 2 = 70.5 mhz, 7 dbfs imd3 = 102 dbfssfdr = 100 dbfs snr = 80.1 dbfs dither enabled, clk = 105 msps
ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. ads5482 two-tone performance vs input amplitude (f 1 = 69.5 mhz and f 2 =70.5 mhz) ads5482 differential nonlinearity figure 27. figure 28. ads5482 sfdr vs ads5482 integral nonlinearity avdd5 over temperature figure 29. figure 30. copyright ? 2008, texas instruments incorporated submit documentation feedback 17 product folder link(s): ads5481 ads5482 ads5483 input amplitude ? dbfs ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 performance ? dbfs g026 dither, 2f1?f2 (dbfs) no dither , dominant spur (dbfs) dither , 2f2?f1 (dbfs) dither , dominant spur (dbfs) code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 16384 32768 49152 65536 dnl ? lsb g027 f s = 105 msps f in = 10 mhz, 1 dbfs code ?4 ?3 ?2 ?1 0 1 2 3 4 0 16384 32768 49152 65536 inl ? lsb g028 f s = 105 msps f in = 10 mhz, 1 dbfs a vdd5 ? supply v oltage ? v 80 85 90 95 100 4.7 4.8 4.9 5.0 5.1 5.2 5.3 sfdr ? dbc g029 f s = 105 msps f in = 30 mhz t a = 55 c t a = 100 c t a = 85 c t a = ?20 c t a = ?40 c t a = 0 c t a = 10 c t a = 25 c
ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. ads5482 snr ads5482 sfdr vs vs avdd5 over temperature avdd3 over temperature figure 31. figure 32. ads5482 snr ads5482 sfdr vs vs avdd3 over temperature dvdd3 over temperature figure 33. figure 34. 18 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483 a vdd5 ? supply v oltage ? v 75 76 77 78 79 80 81 82 4.7 4.8 4.9 5.0 5.1 5.2 5.3 snr ? dbfs g030 t a = 85 c t a = 100 c t a = ?20 c t a = 0 c t a = ?40 c f s = 105 msps f in = 30 mhz t a = 55 c t a = 10 c t a = 25 c a vdd3 ? supply v oltage ? v 80 85 90 95 100 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 sfdr ? dbc g031 f s = 105 msps f in = 30 mhz t a = ?20 c t a = 0 c t a = 85 c t a = ?40 c t a = 10 c t a = 25 c t a = 100 c t a = 55 c a vdd3 ? supply v oltage ? v 75 76 77 78 79 80 81 82 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 snr ? dbfs g032 t a = 55 c t a = 85 c t a = 25 c t a = 100 c t a = 10 c t a = ?20 c t a = 0 c t a = ?40 c f s = 105 msps f in = 30 mhz dvdd3 ? supply v oltage ? v 80 85 90 95 100 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 sfdr ? dbc g033 f s = 105 msps f in = 30 mhz t a = ?20 c t a = 0 c t a = 85 c t a = ?40 c t a = 10 c t a = 25 c t a = 100 c t a = 55 c
ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. ads5482 snr vs dvdd3 over temperature figure 35. ads5482/5481 snr vs input frequency and sampling frequency figure 36. copyright ? 2008, texas instruments incorporated submit documentation feedback 19 product folder link(s): ads5481 ads5482 ads5483 dvdd3 ? supply v oltage ? v 75 76 77 78 79 80 81 82 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 snr ? dbfs g034 t a = 55 c t a = 85 c t a = 25 c t a = 100 c t a = ?20 c t a = ?40 c t a = 0 c f s = 105 msps f in = 30 mhz t a = 10 c 10 20 60 80 f - input frequency - mhz in f - sampling frequency - msps s snr - dbfs 100 140 170 10 20 30 8040 50 60 70 90 100 105 64 70 68 72 74 m0048-06 78 78 78 78 75 79 79 79 80 80 80 79 78 66 80 75 75 73 73 70 70 68 76 78 40 120 160
ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. ads5482/5481 sfdr vs input frequency and sampling frequency figure 37. 20 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483 10 20 60 80 f - input frequency - mhz in f - sampling frequency - msps s sfdr - dbc 100 140 170 10 20 30 8040 50 60 70 90 100 105 60 70 75 80 m0049-06 80 80 85 85 85 85 85 80 90 90 90 90 95 95 95 95 65 95 75 75 75 73 70 70 65 85 90 40 120 160
ads5483 - 135 msps typical data ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. plots in this section are with a clock of 135msps unless otherwise specified. ads5483 spectral performance ads5483 spectral performance fft for 10 mhz input signal fft for 30 mhz input signal figure 38. figure 39. ads5483 spectral performance ads5483 spectral performance fft for 70 mhz input signal fft for 100 mhz input signal figure 40. figure 41. copyright ? 2008, texas instruments incorporated submit documentation feedback 21 product folder link(s): ads5481 ads5482 ads5483 f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.0 13.5 27.0 40.5 54.0 67.5 amplitude ? db g037 sfdr = 97 dbc sinad = 78.9 dbfssnr = 78.9 dbfs thd = 94.6 dbc f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.0 13.5 27.0 40.5 54.0 67.5 amplitude ? db g038 sfdr = 97 dbc sinad = 78.8 dbfssnr = 78.9 dbfs thd = 94.6 dbc f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.0 13.5 27.0 40.5 54.0 67.5 amplitude ? db g039 sfdr = 95 dbc sinad = 78.3 dbfssnr = 78.5 dbfs thd = 91 dbc f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.0 13.5 27.0 40.5 54.0 67.5 amplitude ? db g040 sfdr = 88 dbc sinad = 77.7 dbfssnr = 78.1 dbfs thd = 86.6 dbc
ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. normalized gain response ads5483 two-tone intermodulation distortion vs (fft for 39.5 mhz and 40.5 mhz at ? 10 dbfs) input frequency figure 42. figure 43. ads5483 differential nonlinearity ads5483 integral nonlinearity figure 44. figure 45. 22 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483 f ? frequency ? mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.0 13.5 27.0 40.5 54.0 67.5 amplitude ? db g041 f in 1 = 39.5 mhz, 10 dbfs f in 2 = 40.5 mhz, 10 dbfs imd3 = 103 dbfssfdr = 100 dbfs snr = 79 dbfs f ? frequency ? hz ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 normalized gain ? db 10m 100m 1g g042 ads5483 ads5481 ads5482 code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 16384 32768 49152 65536 dnl ? lsb g043 f s = 135 msps f in = 10 mhz, 1 dbfs code ?4 ?3 ?2 ?1 0 1 2 3 4 0 16384 32768 49152 65536 inl ? lsb g044 f s = 135 msps f in = 10 mhz, 1 dbfs
ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. ads5483 ac performance vs noise histogram with inputs shorted input amplitude (30 mhz input signal) figure 46. figure 47. ads5483 ac performance ads5483 two-tone performance vs vs input amplitude (100 mhz input signal) input amplitude (f 1 = 39.5 mhz and f 2 = 40.5 mhz) figure 48. figure 49. copyright ? 2008, texas instruments incorporated submit documentation feedback 23 product folder link(s): ads5481 ads5482 ads5483 input amplitude ? dbfs ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 140 160 180 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ac performance ? db g046 f s = 135 msps f in = 30 mhz a in = ?0.8 to ?100 dbfs 512k point fft sfdr (dbc,dither off) sfdr (dbfs,dither off) snr (dbfs,dither off) sfdr (dbc,dither on) snr (dbc,dither off) sfdr (dbfs,dither on) snr (dbc,dither on) snr (dbfs,dither on) output code 0 5 10 15 20 25 30 35 percentage ? % g045 f s = 80 msps for ads5481 f s = 105 msps for ads5482 f s = 135 msps for ads5483 analog inputs shorted tovcm ads5481/5482 ads5483 32687 32688 32689 32690 32691 32692 32693 32694 32695 32696 32697 32698 32699 32700 32701 32702 input amplitude ? dbfs ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 140 160 180 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ac performance ? db g065 f s = 135 msps f in = 100 mhz a in = ?0.6 to ?100 dbfs 512k point fft sfdr (dbc,dither off) sfdr (dbfs,dither off) snr (dbfs,dither off) sfdr (dbc,dither on) snr (dbc,dither off) sfdr (dbfs,dither on) snr (dbc,dither on) snr (dbfs,dither on) input amplitude ? dbfs ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 performance ? dbfs g047 dither , dominant spur (dbfs) dither , 2f1?f2 (dbfs) no dither , dominant spur (dbfs) dither , 2f2?f1 (dbfs)
ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. ads5483 sfdr ads5483 snr vs vs avdd5 over temperature avdd5 over temperature figure 50. figure 51. ads5483 sfdr ads5483 snr vs vs avdd3 over temperature avdd3 over temperature figure 52. figure 53. 24 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483 a vdd5 ? supply v oltage ? v 80 85 90 95 100 4.7 4.8 4.9 5.0 5.1 5.2 5.3 sfdr ? dbc g048 f s = 135 msps f in = 70 mhz t a = ?20 c t a = 25 c t a = 100 c t a = ?40 c t a = 0 c t a = 55 c t a = 85 c a vdd5 ? supply v oltage ? v 75 76 77 78 79 80 4.7 4.8 4.9 5.0 5.1 5.2 5.3 snr ? dbfs g049 f s = 135 msps f in = 70 mhz t a = ?20 c t a = ?40 c t a = 0 c t a = 55 c t a = 85 c t a = 25 c t a = 100 c a vdd3 ? supply v oltage ? v 80 85 90 95 100 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 sfdr ? dbc g050 f s = 135 msps f in = 70 mhz t a = 100 c t a = ?40 c t a = 0 c t a = 55 c t a = 85 c t a = ?20 c t a = 25 c a vdd3 ? supply v oltage ? v 75 76 77 78 79 80 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 snr ? dbfs g051 t a = ?20 c t a = ?40 c t a = 0 c t a = 55 c t a = 85 c t a = 25 c t a = 100 c f s = 135 msps f in = 70 mhz
ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. ads5483 sfdr ads5483 snr vs vs dvdd3 over temperature dvdd3 over temperature figure 54. figure 55. cmrr vs common-mode input frequency adc wakeup time figure 56. figure 57. copyright ? 2008, texas instruments incorporated submit documentation feedback 25 product folder link(s): ads5481 ads5482 ads5483 dvdd3 ? supply v oltage ? v 80 85 90 95 100 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 sfdr ? dbc g052 f s = 135 msps f in = 70 mhz t a = 100 c t a = ?40 c t a = 0 c t a = 55 c t a = 85 c t a = ?20 c t a = 25 c dvdd3 ? supply v oltage ? v 75 76 77 78 79 80 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 snr ? dbfs g053 t a = ?20 c t a = ?40 c t a = 0 c t a = 85 c t a = 25 c t a = 100 c f s = 135 msps f in = 70 mhz t a = 55 c t ? time ? ms 0 10 20 30 40 50 60 70 80 90 0 1 2 3 4 5 6 7 8 9 10 snr ? dbfs g066 pdwnf pdwns f s = 135 msps f in = 10 mhz pdwnf and pdwns t ested independently pdwnx disabled at 0 mspdwnx enabled at 8 ms f in ? input frequency ? hz ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 cmrr ? db 0.1 10 1k g054 1 100
ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com typical characteristics (continued) at t a = +25 c, sampling rate = max rated, 50% clock duty cycle, 3-v pp differential sinusoidal clock, analog input amplitude = ? 1 dbfs, avdd5 = 5 v, avdd3 = 3.3 v, and dvdd3 = 3.3 v, unless otherwise noted. ads5483 snr vs input frequency and sampling frequency figure 58. ads5483 sfdr vs input frequency and sampling frequency figure 59. 26 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483 10 50 100 150 f - input frequency - mhz in f - sampling frequency - msps s snr - dbfs 200 250 300 40 50 60 110 70 80 90 100 120 130 135 70 72 74 73 75 76 m0048-02 78 78 78 77 77 77 79 79 78.5 78.5 78.5 71 80 76 76 76 75 75 75 74 74 73 72 74 77 78 79 10 50 100 150 f - input frequency - mhz in f - sampling frequency - msps s sfdr - dbc 200 250 300 40 50 60 110 70 80 90 100 120 130 135 60 70 80 75 85 90 m0049-02 90 90 90 85 85 80 85 95 95 95 65 95 80 75 80 75 70 75 70 70 65 65 65
applications information theory of operation input configuration ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 the ads5481/ads5482/ads5483 (ads548x) is a 16-bit, 80-135msps family of monolithic pipeline adcs. the bipolar analog core operates from 5-v and 3.3-v supplies, while the output uses a 3.3-v supply to provide lvds-compatible outputs. prior to the track-and-hold, the analog input signal passes through a high-performance bipolar buffer. the buffer presents a high and consistent impedance to the analog inputs. the buffer isolates the board circuitry external to the adc from the sampling glitches caused by the track-and-hold in the adc. the conversion process is initiated by the falling edge of the external input clock. at that instant, the differential input signal is captured by the input track-and-hold, and the input sample is converted sequentially by a series of lower resolution stages, with the outputs combined in a digital correction logic block. both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. this process results in a data latency of 4.5 clock cycles, after which the output data are available as a 16-bit parallel word, coded in offset binary format. the analog input for the ads548x consists of an analog pseudo-differential buffer followed by a bipolar transistor t & h. the analog buffer isolates the source driving the input of the adc from any internal switching and presents a high impedance that is easy to drive at high input frequencies, compared to an adc without a buffered input. the input common-mode is set internally through a 1000- ? resistor connected from 3.1 v to each of the inputs. this configuration results in a differential input impedance of 2 k ? at 0 hz. figure 60. analog input circuit for a full-scale differential input, each of the differential lines of the input signal (pins 11 and 12) swings symmetrically between (3.1 v + 0.75 v) and (3.1 v ? 0.75 v). this range means that each input has a maximum signal swing of 1.5 v pp for a total differential input signal swing of 3 v pp . operation below 3 v pp is allowable, with the characteristics of performance versus input amplitude demonstrated in figure 6 through figure 10 . for instance, for performance at 2 v pp rather than 3 v pp , refer to the snr and sfdr at ? 3.5 dbfs (0 dbfs = 3 v pp ). the maximum swing is determined by the internal reference voltage generator, eliminating the need for any external circuitry for this purpose. the primary degradation visible if the max amplitude is kept to 2 v pp is ~3 dbc of snr compared to using 3 v pp , while sfdr will be the same or even improved. the smaller input signal will also likely help any components in the signal chain prior to the adc to be more linear and provide better distortion. copyright ? 2008, texas instruments incorporated submit documentation feedback 27 product folder link(s): ads5481 ads5482 ads5483 1000 w 1000 w 10 w 10 w vcm 3 pf 3 pf agnd s0293-02 inp inm avdd5 avdd5 ads548x agnd agnd ~ 2 nh bond wire ~ 2 nh bond wire ~ 200 ff package ~ 200 ff package ~ 200 ff bond pad ~ 200 ff bond pad analog inputs bipolar transistor buffer bipolar transistor buffer track and hold, 1 stage st pipeline
dither external voltage reference ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com the ads548x performs optimally when the analog inputs are driven differentially. the circuit in figure 61 shows one possible configuration using an rf transformer with termination either on the primary or on the secondary of the transformer. if voltage gain is required, a step-up transformer can be used. figure 61. converting a single-ended input to a differential signal using an rf transformer the ads548x family of devices contain a dither option that is enabled via the ditheren pin. dither is a technique applied to convert small static errors in the converter to dynamic errors, which will look similar to white noise in the output. in virtually all cases tested, the harmonic performance is equal or better when dither is enabled versus disabled. it improves the harmonics that are a function of the static errors. the dither is very low level and will only be indicated in the output waveform as wideband noise that may slightly degrade the snr ( < 0.5db). it is recommended that it be enabled, but users should allow the capability to disable it in the event they suspect it may be degrading their specific application, or to compare the results during their evaluation. figure 6 through figure 10 show the minor differences of dither on/off when carefully studied. for systems that require the analog signal gain to be adjusted or calibrated, this can be performed by using an external reference. the dependency on the signal amplitude to the value of the external reference voltage is characterized typically by figure 62 (vref = 1.2 v is normalized to 0 db as this is the internal reference voltage). as can be seen in the linear fit, this equates to approximately ~1 db of signal adjustment per 100 mv of reference adjustment. the range of allowable variation depends on the analog input amplitude that is applied to the inputs and the desired spectral performance, as can be seen in the performance versus external reference graphs in figure 63 and figure 64 . for dc-coupled applications that use the vcm pin of the ads548x as the common mode of the signal in the analog signal gain path prior to the adc inputs, figure 66 indicates very little change in vcm output as vref is externally adjusted. the vcm output is buffered with a 2k ? series output resistor. the method for disabling the internal reference for use with an external reference is described in table 4 . 28 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483 r 50 0 w z 50 0 w ads548x inpinm s0176-04 r200 w ac signalsource n = 2:1
ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 figure 62. signal gain adjustment versus external figure 63. sfdr versus external vref and a in reference (vref) figure 64. snr versus external vref and a in figure 65. total power consumption versus external vref figure 66. vcm pin output versus external vref copyright ? 2008, texas instruments incorporated submit documentation feedback 29 product folder link(s): ads5481 ads5482 ads5483 applied external vref ? v ?4 ?2 0 2 4 6 8 10 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 normalized gain adjustment ? db g057 f s = 135 msps f in = 30 mhz a in = < ?1 dbfs normalized to 1.2 vref linear fit: y = ?9.8x + 1 1.8 applied external vref ? v 70 75 80 85 90 95 100 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 sfdr ? dbc g058 f s = 135 msps f in = 30 mhz dither enabledsignal amplitude relative to adjusted fullscale a in = ?3 dbfs a in = ?7 dbfs a in = ?6 dbfs a in = ?4 dbfs a in = ?10 dbfs a in = ?2 dbfs a in = ?1 dbfs applied external vref ? v 60 62 64 66 68 70 72 74 76 78 80 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 snr ? dbc g059 f s = 135 msps f in = 30 mhz dither enabledsignal amplitude relative to adjusted fullscale a in = ?6 dbfs a in = ?10 dbfs a in = ?7 dbfs a in = ?4 dbfs a in = ?3 dbfs a in = ?1 dbfs a in = ?2 dbfs applied external vref ? v 1.7 1.8 1.9 2.0 2.1 2.2 2.3 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 p ? power ? w g060 f s = 135 msps f in = 30 mhz signal adjusted to ?1 dbfs applied external vref ? v 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 vcm pin output v oltage ? v g061
clock inputs ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com the ads548x equivalent clock input circuit is shown in figure 67 . the clock inputs can be driven with either a differential clock signal or a single-ended clock input, but differential is highly recommended. the characterization of the ads548x is typically performed with a 3-v pp differential clock, but the adc performs well with a differential clock amplitude down to ~1 v pp , as shown in figure 69 and figure 70 . the clock amplitude becomes more of a factor in performance as the analog input frequency increases. when single-ended clocking is a necessity, it is best to connect clkm to ground with a 0.01- m f capacitor, while clkp is ac-coupled with a 0.01- m f capacitor to the clock source, as shown in figure 68 . figure 67. clock input circuit figure 68. single-ended clock 30 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483 clkpclkm ads548x square wave or sine wave 0.01 f m 0.01 f m s0168-08
ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 sfdr snr vs vs clock amplitude clock amplitude figure 69. figure 70. for jitter-sensitive applications, the use of a differential clock has some advantages at the system level. the differential clock allows for common-mode noise rejection at the printed circuit board (pcb) level. with a differential clock, the signal-to-noise ratio of the adc is better for jitter-sensitive, high-frequency applications because the board level clock jitter is superior. the sampling process will be more sensitive to jitter using high analog input frequencies or slow clock frequencies. large clock amplitude levels are recommended when possible to reduce the indecision (jitter) in the adc clock input buffer. whenever possible, the ideal combination is a differential clock with large signal swing (~1-3vpp). figure 71 demonstrates a recommended method for converting a single-ended clock source into a differential clock; it is similar to the configuration found on the evaluation board and was used for much of the characterization. see also clocking high speed data converters (slyt075 ) for more details. figure 71. differential clock the common-mode voltage of the clock inputs is set internally to ~2 v using internal 0.5-k ? resistors. it is recommended to use ac coupling, but if this scheme is not possible, the ads548x features good tolerance to clock common-mode variation (as shown in figure 72 and figure 73 ). the internal adc core uses both edges of the clock for the conversion process. ideally, a 50% duty-cycle clock signal should be provided. performance degradation as a result of duty cycle can be seen in figure 74 . copyright ? 2008, texas instruments incorporated submit documentation feedback 31 product folder link(s): ads5481 ads5482 ads5483 clock amplitude ? v pp 70 75 80 85 90 95 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 sfdr ? dbc g055 f s = 135 msps f in = 100.33 mhz f in = 9.97 mhz f in = 30.13 mhz f in = 69.59 mhz clock amplitude ? v pp 60 62 64 66 68 70 72 74 76 78 80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 snr ? dbfs g056 f s = 135 msps f in = 9.97 mhz f in = 30.13 mhz f in = 69.59 mhz f in = 100.33 mhz clkpclkm ads548x 0.1 f m clock source s0194-03
ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com figure 72. sfdr versus clock common mode figure 73. snr versus clock common mode figure 74. sfdr vs clock duty cycle the ads5483 is capable of achieving 78.2 dbfs snr at 100 mhz of analog input frequency. in order to achieve the snr at 100 mhz the clock source rms jitter (at the adc clock input pins) must be at most 205 fsec in order for the total rms jitter to be 220 fsec due to internal adc aperture jitter of ~80 fsec. a summary of maximum recommended rms clock jitter as a function of analog input frequency for the ads5483 is provided in table 2 . the equations used to create the table are presented and can be used to estimate required clock jitter for virtually any pipeline adc. table 2. recommended approximate rms clock jitter for ads5483 analog input frequency measured snr total jitter maximum clock jitter (mhz) (dbc) (fsec rms) (fsec rms) 1 78.2 19581 19581 10 78 2004 2002 70 77.8 300 289 100 77.2 220 205 130 76 177 158 170 75.8 152 129 230 75.1 122 92 300 73.2 116 84 32 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483 clock common mode v oltage ? v 50 60 70 80 90 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 sfdr ? dbc g062 10 mhz 30 mhz 70 mhz 231 mhz 100 mhz clock common mode v oltage ? v 65 67 69 71 73 75 77 79 81 0.5 1.0 1.5 2.0 2.5 3.0 3.5 snr ? dbfs g063 10 mhz 30 mhz 70 mhz 231 mhz 100 mhz clock duty cycle ? % 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 sfdr ? dbc g064 10 mhz 231 mhz 100 mhz 30 mhz 70 mhz f s = 135 msps a in = ?1 dbfs clock input = 3 vpp
(1) (2) ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 equation 1 and equation 2 are used to estimate the required clock source jitter. where: j total = the rms summation of the clock and adc aperture jitter; j adc = the adc internal aperture jitter which is located in the data sheet; j clock = the rms jitter of the clock at the clock input pins to the adc; and f in = the analog input frequency. notice that the snr is a strong function of the analog input frequency, not the clock frequency. the slope of the clock source edges can have a mild impact on snr as well and is not taken into account for these estimates. for this reason, maximizing clock source amplitudes at the adc clock inputs is recommended, though not required (faster slope is desirable for jitter-related snr). for more information on clocking high-speed adcs, see application note slwa034 , implementing a cdc7005 low jitter clock solution for high-speed, high-if adc devices, on the texas instruments web site. recommended clock distribution chips (cdcs) are the ti cdce72010 and cdcm7005 . depending on the jitter requirements, a band pass filter (bpf) is sometimes required between the cdc and the adc. if the insertion loss of the bpf causes the clock amplitude to be too low for the adc, or the clock source amplitude is too low to begin with, an inexpensive amplifier can be placed between the cdc and the bpf, as its harmonics and wide-band noise will be reduced by the bpf. figure 75 represents a scenario where an lvcmos single-ended clock output is used from a ti cdce72010 with the clock signal path optimized for maximum amplitude and minimum jitter. the jitter of this setup is difficult to estimate and requires a careful phase noise analysis of the clock path. the bpf (and possibly a low-cost amplifier because of insertion loss in the bpf) can improve the jitter between the cdc and adc when the jitter provided by the cdc is still not adequate. the total jitter at the cdce72010 output depends largely on the phase noise of the vcxo/vco selected, as well as from the cdce72010 itself. consult the cdce72010 data sheet for proper schematic and specifications regarding allowable input and output frequency and amplitude ranges. figure 75. optimum jitter clock circuit copyright ? 2008, texas instruments incorporated submit documentation feedback 33 product folder link(s): ads5481 ads5482 ads5483 snr (dbc) = 20 log10 (2 f j ) - p in total j = (j + j ) total adc clock 2 1/2 2 clkp clkm ref 400 mhz (to transmit dac) 100 mhz (to dsp) 100 mhz (to fpga) to other 10 mhz 400 mhz 100 mhz low jitter oscillator bpf lvcmos xfmr amp amp and/or bpf optional board master reference clock (high or low jitter) vco/ vcxo cdc (clock distribution chip) ex: ti cdce72010 lvpecl or lvcmos adc ti ads548x b0268-01
digital outputs ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com the adc provides eight lvds-compatible, offset binary, ddr data outputs (2 bits per lvds output driver) and a data-ready lvds signal (dry). it is recommended to use the dry signal to capture the output data of the ads548x (use as a clock output). dry is source-synchronous to the data outputs and operates at the same frequency, creating a full-rate ddr interface that updates data on both the rising and falling edges of dry. it is recommended that the capacitive loading on the digital outputs be minimized. higher capacitance shortens the data-valid timing window. the values given for timing (see figure 1 ) were obtained with a 5-pf parasitic board capacitance to ground on each lvds line. when setting the time relationship between dry and data at the receiving device, it is generally recommended that setup time be maximized, but this partially depends on the setup and hold times of the device receiving the digital data. since dry and data are coincident, it will likely be necessary to delay either dry such that data setup time is maximized. the lvds outputs all require an external 100- ? load between each output pair in order to meet the expected lvds voltage levels. for long trace lengths, it may be necessary to place a 100- ? load on each digital output as close to the ads548x as possible and another 100- ? differential load at the end of the lvds transmission line to terminate the transmission line and avoid signal reflections. the effective load in this case reduces the lvds voltage levels by half. the current of all lvds drivers is set externally with a resistor connected between the lvdsb (lvds bias) pin and ground. normal lvds current is 3.5ma per lvds pair, set with a 10k ? external resistor. for systems with excessive load capacitance on the lvds lines, reducing the resistor value in order to increase the lvds bias current is allowed to create a stronger lvds drive capability. for systems with short traces and minimal loading, increasing the resistor in order to decrease the lvds current is allowable in order to save power. table 3 provides a sampling of lvdsb resistor values should deviation from the recommended lvds output current of 3.5ma be considered. it is not recommended to exceed the range listed in the table. if the lvds bias current is adjusted, the differential load resistance should also be adjusted to maintain voltage levels within the specification for the lvds outputs. the signal integrity of the lvds lines on the board layout should be scrutinized to ensure proper lvds signal integrity exists. table 3. setting the lvds current drive lvdsb resistor to gnd, ? lvds nominal current, ma 6k 5.6 8k 4.3 10k (value for normal recommended operation) 3.5 12k 2.8 14k 2.3 16k 2.0 18k 1.7 20k 1.5 34 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483
power supplies and sleep modes ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 the ads548x uses three power supplies. for the analog portion of the design, a 5-v and 3.3-v supply (avdd5 and avdd3) are used, while the digital portion uses a 3.3-v supply (dvdd3). the use of low-noise power supplies with adequate decoupling is recommended. linear supplies are preferred to switched supplies; switched supplies generate more noise that can be coupled to the ads548x. however, the psrr value and plot shown in figure 76 were obtained without bulk supply decoupling capacitors. when bulk (0.1 m f) decoupling capacitors are used near the supply pins, the board-level psrr is much higher than the stated value for the adc. the user may be able to supply power to the device with a less-than-ideal supply and still achieve very good performance. it is not possible to make a single recommendation for every type of supply and level of decoupling for all systems. if the noise characteristics of the available supplies are understood, a study of the psrr data for the ads548x may provide the user with enough information to select noisy supplies if the performance is still acceptable within the frequency range of interest. the power consumption of the ads548x does not change substantially over clock rate or input frequency. figure 76. psrr versus supply injected frequency two separate sleep modes are offered. they are differentiated by the amount of power consumed and the time it takes for the adc to wakeup from sleep. the light sleep mode consumes 605mw and can be used when wakeup of less than 600us is required. deep sleep consumes 70mw and requires 6ms to wakeup. see the wakeup characteristic at figure 57 . for directions on enabling these modes, see table 4 . the input clock can be in either state when the power down modes are enabled. the device can enter power-down mode whether using internal or external reference. however, the wakeup time from light sleep enabled to external reference mode is dependent on the external reference voltage and is not necessarily 0.6 ms, but should be noticeably faster than deep sleep wakeup. no specific power sequences are required. table 4. power down and reference modes mode pdwnf pin pdwns pin power consumption wakeup time adc on - internal reference low low 2.2 w on adc on - external reference high high 2.2 w on light sleep high low 605 mw when enabled 0.6 ms deep sleep low high 70 mw when enabled 6 ms copyright ? 2008, texas instruments incorporated submit documentation feedback 35 product folder link(s): ads5481 ads5482 ads5483 f in ? input frequency ? mhz ?120 ?100 ?80 ?60 ?40 ?20 0 psrr ? db 0.1 10 1k g067 1 100 avdd3v dvdd3v avdd5v
layout information powerpad package assembly process ads5481 ads5482 ads5483 slas565a ? june 2008 ? revised november 2008 ................................................................................................................................................... www.ti.com the evaluation board represents a good model of how to lay out the printed circuit board (pcb) to obtain the maximum performance from the ads548x. follow general design rules, such as the use of multilayer boards, a single ground plane for adc ground connections, and local decoupling ceramic chip capacitors. the analog input traces should be isolated from any external source of interference or noise, including the digital outputs as well as the clock traces. the clock signal traces should also be isolated from other signals, especially in applications such as high if sampling where low jitter is required. besides performance-oriented rules, care must be taken when considering the heat dissipation of the device. the thermal heatsink included on the bottom of the package should be soldered to the board as described in the powerpad package section. see the ads548x evm user guide on the ti web site for the evaluation board schematic. the powerpad package is a thermally-enhanced, standard-size ic package designed to eliminate the use of bulky heatsink and slugs traditionally used in thermal packages. this package can be easily mounted using standard pcb assembly techniques, and can be removed and replaced using standard repair procedures. the powerpad package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of the ic. this pad design provides an extremely low thermal resistance path between the die and the exterior of the package. the thermal pad on the bottom of the ic can then be soldered directly to the pcb, using the pcb as a heatsink. 1. prepare the pcb top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in the mechanical data section (at the end of this data sheet). 2. place a 6-by-6 array of thermal vias in the thermal pad area. these holes should be 13 mils (0.013 in or 0.3302 mm) in diameter. the small size prevents wicking of the solder through the holes. 3. it is recommended to place a small number of 25 mil (0.025 in or 0.635 mm) diameter holes under the package, but outside the thermal pad area, to provide an additional heat path. 4. connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a ground plane). 5. do not use the typical web or spoke via-connection pattern when connecting the thermal vias to the ground plane. the spoke pattern increases the thermal resistance to the ground plane. 6. the top-side solder mask should leave exposed the terminals of the package and the thermal pad area. 7. cover the entire bottom side of the powerpad vias to prevent solder wicking. 8. apply solder paste to the exposed thermal pad area and all of the package terminals. for more detailed information regarding the powerpad package and its thermal properties, see either the powerpad made easy application brief (slma004 ) or the powerpad thermally enhanced package application report (slma002 ), both available for download at www.ti.com . 36 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): ads5481 ads5482 ads5483
definition of specifications (4) (5) (6) ads5481 ads5482 ads5483 www.ti.com ................................................................................................................................................... slas565a ? june 2008 ? revised november 2008 the injected frequency level is translated into dbfs, the spur in the output fft is measured in dbfs, and analog bandwidth the difference is the psrr in db. the measurement the analog input frequency at which the power of the calibrates out the benefit of the board supply fundamental is reduced by 3 db with respect to the decoupling capacitors. low-frequency value. signal-to-noise ratio (snr) aperture delay snr is the ratio of the power of the fundamental (p s ) the delay in time between the rising edge of the input to the noise floor power (p n ), excluding the power at sampling clock and the actual time at which the dc and in the first five harmonics. sampling occurs. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. snr is either given in units of dbc (db to carrier) clock pulse duration/duty cycle when the absolute power of the fundamental is used the duty cycle of a clock signal is the ratio of the time as the reference, or dbfs (db to full-scale) when the the clock signal remains at a logic high (clock pulse power of the fundamental is extrapolated to the duration) to the period of the clock signal, expressed converter full-scale range. as a percentage. signal-to-noise and distortion (sinad) differential nonlinearity (dnl) sinad is the ratio of the power of the fundamental an ideal adc exhibits code transitions at analog input (p s ) to the power of all the other spectral components values spaced exactly 1 lsb apart. dnl is the including noise (p n ) and distortion (p d ), but excluding deviation of any single step from this ideal value, dc. measured in units of lsb. common-mode rejection ratio (cmrr) cmrr measures the ability to reject signals that are presented to both analog inputs simultaneously. the sinad is either given in units of dbc (db to carrier) injected common-mode frequency level is translated when the absolute power of the fundamental is used into dbfs, the spur in the output fft is measured in as the reference, or dbfs (db to full-scale) when the dbfs, and the difference is the cmrr in db. power of the fundamental is extrapolated to the effective number of bits (enob) converter full-scale range. enob is a measure in units of bits of converter temperature drift performance as compared to the theoretical limit temperature drift (with respect to gain error and based on quantization noise: offset error) specifies the change from the value at enob = (sinad ? 1.76)/6.02 the nominal temperature to the value at t min or t max . it is computed as the maximum variation the gain error parameters over the whole temperature range divided gain error is the deviation of the adc actual input by t min ? t max . full-scale range from its ideal value, given as a percentage of the ideal input full-scale range. total harmonic distortion (thd) thd is the ratio of the power of the fundamental (p s ) integral nonlinearity (inl) to the power of the first five harmonics (p d ). inl is the deviation of the adc transfer function from a best-fit line determined by a least-squares curve fit of that transfer function. the inl at each analog input value is the difference between the actual transfer function and this best-fit line, measured in units of thd is typically given in units of dbc (db to carrier). lsb. two-tone intermodulation distortion (imd3) offset error imd3 is the ratio of the power of the fundamental (at offset error is the deviation of output code from frequencies f 1 , f 2 ) to the power of the worst spectral mid-code when both inputs are tied to component at either frequency 2f 1 ? f 2 or 2f 2 ? f 1 ). common-mode. imd3 is given in units of either dbc (db to carrier) when the absolute power of the fundamental is used power-supply rejection ratio (psrr) as the reference, or dbfs (db to full-scale) when the psrr is a measure of the ability to reject frequencies power of the fundamental is extrapolated to the present on the power supply. converter full-scale range. copyright ? 2008, texas instruments incorporated submit documentation feedback 37 product folder link(s): ads5481 ads5482 ads5483 snr 10log 10 p s p n sinad 10log 10 p s p n p d thd 10log 10 p s p d
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) ads5481irgcr active vqfn rgc 64 2000 tbd call ti call ti ads5481irgct active vqfn rgc 64 250 tbd call ti call ti ADS5482IRGCR active vqfn rgc 64 2000 tbd call ti call ti ads5482irgct active vqfn rgc 64 250 tbd call ti call ti ads5483irgcr active vqfn rgc 64 2000 tbd call ti call ti ads5483irgcrg4 active vqfn rgc 64 2000 tbd call ti call ti ads5483irgct active vqfn rgc 64 250 tbd call ti call ti ads5483irgctg4 active vqfn rgc 64 250 tbd call ti call ti (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 15-dec-2008 addendum-page 1

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or "enhanced plastic." only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dlp? 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