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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. ads125h01 , ads125h02 sbas790 ? october 2018 ads125h0x wide-input range, 2-channel, 40-ksps, 24-bit, delta-sigma adcs with pga and voltage reference 1 1 features 1 ? precision, wide-input range, 24-bit adc ? differential input voltage range: 7 mv to 20 v ? absolute input voltage range: 15.5 v ? high impedance pga: 1 g ? pga gain: 0.125 to 128 ? high accuracy: ? offset drift: 5 nv/ c ? gain drift: 1 ppm/ c ? linearity: 2 ppm ? data rate: 2.5 to 40000 sps ? 2.5-v reference ? simultaneous 50-hz and 60-hz rejection mode ? single-cycle settling mode ? signal and reference voltage monitors ? cyclic redundancy check (crc) ? two reference inputs (h02) ? sensor excitation current sources (h02) ? four general-purpose inputs/outputs (h02) ? 5-mm 5-mm vqfn package 2 applications ? wide common-mode voltage measurements ? 10-v analog input plc modules ? test and measurement equipment ? lab instrumentation 3 description the ads125h01 and ads125h02 (ads125h0x) are 2-channel, 24-bit, 40-ksps, delta-sigma ( ) adcs with an integrated 18-v programmable gain amplifier (pga). the devices also include a voltage reference and features to enhance data reliability such as crc and signal monitors. the adcs provide a complete, high-resolution measurement solution over a wide range of common-mode voltage, with differential input voltage ranges from 7 mv to 20 v. the adcs are comprised of an 18-v pga providing gain of 0.125 to 128, a 24-bit modulator, programmable digital filter, and an internal reference. the pga inputs are high-impedance (1 g ) and accommodate high common-mode voltages with no external attenuation required. the devices support 1 differential or 2 single-ended inputs. the flexible digital filter is programmable for single- cycle settled conversions while providing simultaneous 50-hz and 60-hz line cycle rejection. signal and reference monitors, a temperature sensor, and crc data verification enhance data reliability. the ads125h01 and ads125h02 are pin compatible. the devices are available in a 5-mm 5- mm vqfn package and are specified over the ? 40 c to +125 c temperature range. device information (1) part number package body size (nom) ads125h0x vqfn (32) 5.00 mm 5.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. functional block diagram 24-bit ? adc pga input mux digital filter serial interface and crc verification cs2 dout/drdy sclk start clock mux clkin refout ref monitor signal monitors buf aincom temp sensor ads125h01 ads125h02 ref mux 2.5-v ref ain0 ain1 internal oscillator din -15 v 15 v reset supply read 5 v (a) 5 v (d) idac1 idac2 gpio control ads125h02 only gpio2 gpio3 refp1/gpio0 refn1/gpio1 drdy sensor exc. currents refp0 refn0 (a) (d) cs1 advance information tools & software technical documents ordernow productfolder support &community
2 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ....................... 6 6.4 thermal information .................................................. 6 6.5 electrical characteristics ........................................... 7 6.6 timing requirements .............................................. 10 6.7 switching characteristics ........................................ 11 7 parameter measurement information ................ 14 7.1 noise performance ................................................. 14 8 detailed description ............................................ 18 8.1 overview ................................................................. 18 8.2 functional block diagram ....................................... 18 8.3 feature description ................................................. 20 8.4 device functional modes ....................................... 33 8.5 programming .......................................................... 40 8.6 register map ........................................................... 48 9 application and implementation ........................ 61 9.1 application information ............................................ 61 9.2 typical application .................................................. 62 9.3 initialization setup ................................................... 65 10 power supply recommendations ..................... 66 10.1 power-supply decoupling ..................................... 66 10.2 analog power-supply clamp ................................ 66 10.3 power-supply sequencing .................................... 66 11 layout ................................................................... 67 11.1 layout guidelines ................................................. 67 11.2 layout example .................................................... 68 12 device and documentation support ................. 69 12.1 related links ........................................................ 69 12.2 receiving notification of documentation updates 69 12.3 community resources .......................................... 69 12.4 trademarks ........................................................... 69 12.5 electrostatic discharge caution ............................ 69 12.6 glossary ................................................................ 69 13 mechanical, packaging, and orderable information ........................................................... 69 4 revision history date revision notes october 2018 * * advance information
3 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and functions rhb package: ads125h02 32-pin vqfn top view advance information 32 refn0 9 cs2 1 refp0 24 idac1 31 refp1/gpio0 10 cs1 2 capp 23 idac2 30 refn1/gpio1 11 sclk 3 capn 22 nc 29 gpio2 12 din 4 avdd 21 nc 28 gpio3 13 drdy 5 agnd 20 hv_avdd 27 ain1 14 dout/drdy 6 refout 19 hv_avss 26 ain0 15 bypass 7 reset 18 clkin 25 aincom 16 dgnd 8 start 17 dvdd not to scale thermal pad
4 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated pin functions pin i/o description no. ads125h01 ads125h02 1 refp0 refp0 analog input reference input 0 positive 2 capp capp analog output pga output p; connect a 1-nf c0g dielectric capacitor from capp to capn 3 capn capn analog output pga output n; connect a 1-nf c0g dielectric capacitor from capp to capn 4 avdd avdd analog low-voltage analog power supply (5 v) 5 agnd agnd analog analog ground. connect to adc ground plane 6 refout refout analog output 2.5-v reference output; connect a 10- f capacitor to agnd 7 reset reset digital input reset; active low 8 start start digital input conversion start, active high 9 cs2 cs2 digital input serial interface chip select 2; active low 10 cs1 cs1 digital input serial interface chip select 1; active low 11 sclk sclk digital input serial interface shift clock 12 din din digital input serial interface data input 13 drdy drdy digital output data ready indicator; active low 14 dout/ drdy dout/ drdy digital output serial interface data output and data ready indicator (active low) 15 bypass bypass analog output 2-v subregulator output; connect a 1- f capacitor to dgnd 16 dgnd dgnd digital digital ground. connect to adc ground plane 17 dvdd dvdd digital digital power supply (3 v to 5 v) 18 clkin clkin digital input 1: internal oscillator: connect to dgnd 2: external clock: apply clock input 19 hv_avss hv_avss analog high-voltage negative analog power supply 20 hv_avdd hv_avdd analog high-voltage positive analog power supply 21,22 nc nc ? no connection. electrically float or tie to agnd. 23 nc idac2 analog output ads125h01: no connection. electrically float or tie to agnd ads125h02: current source 2 output 24 nc idac1 analog output ads125h01: no connection. electrically float or tie to agnd ads125h02: current source 1 output 25 aincom aincom analog input analog input common (single-ended common) 26 ain0 ain0 analog input analog input 0 27 ain1 ain1 analog input analog input 1 28 nc gpio3 digital input/output ads125h01: no connection. electrically float or tie to agnd ads125h02: general-purpose input/output 3 29 nc gpio2 digital input/output ads125h01: no connection. electrically float or tie to agnd ads125h02: general-purpose input/output 2 30 nc refn1/gpio1 analog/digital input/output ads125h01: no connection. electrically float or tie to agnd ads125h02: reference input 1 negative and general-purpose input/output 1 31 nc refp1/gpio0 analog/digital input/output ads125h01: no connection. electrically float or tie to agnd ads125h02: reference input 1 positive and general-purpose input/output 0 32 refn0 refn0 analog input reference input 0 negative thermal pad exposed thermal pad; connect to dgnd. see recommended pcb land pattern at end of document. advance information
5 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings min max unit power-supply voltage hv_avdd to hv_avss ? 0.3 38 v hv_avss to agnd ? 20 0.3 avdd to agnd -0.3 6 dvdd to dgnd ? 0.3 6 agnd to dgnd ? 0.1 0.1 analog input voltage ain0, ain1, aincom hv_avss ? 0.3 hv_avdd + 0.3 v gpio[3:0], refp[1:0], refn[1:0], idac[2:1] agnd ? 0.3 avdd + 0.3 digital input voltage cs1, cs2, sclk, din , start, reset, clkin, drdy, dout/ drdy dgnd ? 0.3 dvdd + 0.3 v input current continuous (input voltage specification exceeded) ? 10 10 ma temperature junction, t j 150 c storage, t stg ? 60 150 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) tbd v charged-device model (cdm), per jedec specification jesd22-c101 (2) tbd advance information
6 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) the full available differential input voltage range is limited under certain operating conditions. see pga input range for details. 6.3 recommended operating conditions over operating ambient temperature range (unless otherwise noted) min nom max unit power supply high-voltage analog power supplies hv_avdd to hv_avss 10 36 v hv_avss to agnd ? 18 0 hv_avdd to agnd avdd 36 low-voltage analog power supply avdd to agnd 4.75 5 5.25 v digital power supply dvdd to dgnd 2.7 5.25 v signal inputs v (ainx) absolute input voltage see pga input range v v in differential input voltage range (1) v in = v ainp - v ainn -20 v ref / gain 20 v voltage reference inputs v ref reference voltage input v ref = v (refpx) ? v (refnx) 0.9 avdd v v (refnx) negative reference voltage agnd ? 0.05 v (refpx) ? 0.9 v v (refpx) positive reference voltage v (refnx) + 0.9 avdd + 0.05 v general-purpose input/outputs (gpios) input voltage agnd avdd v digital inputs (other than gpios) input voltage dgnd dvdd v external clock f (clk) frequency 2.5 to 25600 sps 1 7.3728 8 mhz 40000 sps 1 10.24 10.75 duty cycle 40% 60% temperature range t a operating ambient temperature ? 45 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report . 6.4 thermal information thermal metric (1) ads125h0x unit rhb (vqfn) 32 pins r ja junction-to-ambient thermal resistance 35.2 c/w r jc(top) junction-to-case (top) thermal resistance 19.0 c/w r jb junction-to-board thermal resistance 15.8 c/w jt junction-to-top characterization parameter 0.3 c/w jb junction-to-board characterization parameter 15.7 c/w r jc(bot) junction-to-case (bottom) thermal resistance 8.0 c/w advance information
7 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) input current in chop mode operation scales with the data rate. see graph tbd. (2) normal-mode rejection ratio performance is dependent on the digital filter configuration. (3) common-mode rejection ratio is specified at 60 hz. (4) power-supply rejection ratio is specified at dc. 6.5 electrical characteristics minimum and maximum specifications apply from t a = ? 40 c to +125 c. typical specifications are at t a = 25 c. all specifications are at hv_avdd = 15 v, hv_avss = ? 15 v, avdd = 5 v, dvdd = 3.3 v, v ref = 2.5 v, f clk = 7.3728 mhz, data rate = 20 sps and gain = 1 v/v, (unless otherwise noted) parameter test conditions min typ max unit analog inputs absolute input current v (ainx) = 0 v 0.5 na absolute input current drift 10 pa/ c differential input current v in = 2.5 v standard mode 0.1 na chop mode (1) 5 differential input current drift v in = 2.5 v, t a < 105 c 10 pa/ c differential input impedance 1 g crosstalk 1 v/v pga gain 0.125, 0.1875, 0.25, 0.5, 1, 2, 4, 8, 16, 32 ,64,128 v/v anti-alias filter 230 khz performance resolution no missing codes 24 bits dr data rate 2.5 40000 sps noise performance see table 1 and table 2 inl integral nonlinearity gain = 0.125 to 32 2 10 ppm gain = 64, 128 6 v os offset voltage chop mode off, t a = 25 c -30 + 300 / gain 10 + 100 / gain 30 + 300 / gain v chop mode on, t a = 25 c -0.5 + 0.5 / gain 0.5 / gain 0.5 + 0.5 / gain after calibration on the level of noise offset voltage drift chop mode off 200 / gain tbd nv/ c chop mode on 5 / gain tbd ge gain error t a = 25 c, all gains 0.1% 0.7% after calibration on the level of noise gain drift all gains 1 4 ppm/ c nmrr normal-mode rejection ratio (2) see table 7 cmrr common-mode rejection ratio (3) data rate = 20 sps 130 db data rate = 400 sps 85 100 psrr power-supply rejection ratio (4) hv_avdd, hv_avss 2 15 v/v avdd 5 50 dvdd 3 20 voltage reference inputs absolute input current 250 na input current vs voltage 15 na/v input current drift 0.2 na/ c input impedance differential 30 m advance information
8 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) minimum and maximum specifications apply from t a = ? 40 c to +125 c. typical specifications are at t a = 25 c. all specifications are at hv_avdd = 15 v, hv_avss = ? 15 v, avdd = 5 v, dvdd = 3.3 v, v ref = 2.5 v, f clk = 7.3728 mhz, data rate = 20 sps and gain = 1 v/v, (unless otherwise noted) parameter test conditions min typ max unit (5) soldered to pcb using recommended pcb layout pattern and using reflow profile per jedec standard j-std-020d.1 (6) voltage reference hysteresis measured by operating the device at 25 c cycling the device to 0 c and 105 c and returning the device to 25 c. (7) see pga monitor for details. internal voltage reference (5) voltage 2.5 v initial error t a = 25 c tbd 0.2% tbd temperature drift t a = 0 c to 85 c 5 tbd ppm/ c t a = ? 40 c to 125 c 8 tbd long term drift t a = 85 c, 1st 1000 hr tbd ppm thermal hysteresis (6) first 0 c to 105 c cycle 70 ppm second 0 c to 105 c cycle 25 output current ? 10 10 ma load regulation 20 v/ma start-up time settling to 0.001% final value 100 ms temperature sensor voltage t a = 25 c 122.4 mv temperature coefficient 420 v/ c excitation current sources (idacs) currents 50, 100, 250, 500, 750, 1000, 1500, 2000, 2500, 3000 a compliance range all currents agnd avdd ? 1.1 v absolute error all currents ? 5% 0.7% 5% match error same current magnitudes ? 1.5% 0.1% 1.5% different current magnitudes 1% temperature drift absolute 100 ppm/ c matched values 5 tbd pga monitors (7) input low threshold hv_avss + 2 v input high threshold hv_avdd ? 2 v output low threshold hv_avss + 2 v output high threshold hv_avdd ? 2 v reference monitor low voltage threshold 0.4 0.6 v internal oscillator f clk frequency 2.5 to 25600 sps operation 7.3728 mhz 40000 sps operation 10.24 accuracy 0.5% 2% general-purpose input/outputs (gpio) v oh high-level output voltage i oh = 1 ma 0.8 avdd v v ol low-level output voltage i ol = ? 1 ma 0.2 avdd v v ih high-level input voltage 0.7 avdd avdd v v il low-level input voltage agnd 0.3 avdd v input hysteresis 0.5 v advance information
9 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) minimum and maximum specifications apply from t a = ? 40 c to +125 c. typical specifications are at t a = 25 c. all specifications are at hv_avdd = 15 v, hv_avss = ? 15 v, avdd = 5 v, dvdd = 3.3 v, v ref = 2.5 v, f clk = 7.3728 mhz, data rate = 20 sps and gain = 1 v/v, (unless otherwise noted) parameter test conditions min typ max unit digital input/output (other than gpio) v oh high-level output voltage i oh = 1 ma 0.8 dvdd v i oh = 8 ma 0.75 dvdd v ol low-level output voltage i ol = ? 1 ma 0.2 dvdd v i ol = ? 8 ma 0.2 dvdd v ih high-level input voltage 0.7 dvdd dvdd v v il low-level input voltage dgnd 0.3 dvdd v input hysteresis 0.1 v input leakage 1 a power supply i hv_avdd i hv_avss hv_avdd, hv_avss supply current 1.1 1.8 ma i avdd avdd supply current 2.8 4.6 ma additional avdd supply current (by function) voltage reference 0.2 ma 40000 sps operation 1 current sources as programmed a i dvdd dvdd supply current 0.5 0.7 ma 40000-sps operation 0.7 0.9 p d power dissipation 50 80 mw advance information
10 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.6 timing requirements over operating the ambient temperature range and dvdd = 2.7 v to 5.25 v. min max unit serial interface t d(cssc) delay time, first sclk rising edge after cs1 or cs2 falling edge 50 ns t su(di) setup time, din valid before sclk falling edge 25 ns t h(di) hold time, din valid after sclk falling edge 25 ns t c(sc) sclk period 97 ns t w(sch), t w(scl) pulse duration, sclk high or low 40 ns t d(sccs) delay time, last sclk falling edge before cs1 or cs2 rising edge 50 ns t w(csh) pulse duration, cs1 or cs2 high to reset interface 25 ns reset t w(rstl) pulse duration, reset low 4 1 / f clk conversion control t w(sth) pulse duration, start high 4 1 / f clk t w(stl) pulse duration: start low 4 1 / f clk t su(stdr) set-up time, start low or stop command before drdy low to stop next conversion (continuous mode) 100 1 / f clk t h(drsp) hold time, start low or stop command after drdy low to continue next conversion (continuous mode) 150 1 / f clk advance information
11 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.7 switching characteristics over operating the ambient temperature range and dvdd = 2.7 v to 5.25 v. dout/ drdy load: 20 pf || 100 k to dgnd, (unless otherwise noted) parameter min typ max unit serial interface t w(drh) pulse duration: drdy high 16 1/f clk t p(csdo) propagation delay time, cs1 or cs2 falling edge to dout/ drdy driven 0 50 ns t p(scdo1) propagation delay time, sclk rising edge to valid dout/ drdy 40 ns t h(scdo1) hold time, sclk rising edge to invalid dout/ drdy 0 ns t h(scdo2) hold time, last sclk falling edge to invalid dout/ drdy data output function 15 ns t p(scdo2) propagation delay time, last sclk falling edge to dout/ drdy data ready function 110 ns t p(csdoz) propagation delay time, cs1 or cs2 rising edge to dout/ drdy high impedance 50 ns reset t p(rscn) propagation delay time, reset rising edge or reset command to conversion start 512 1/f clk t p(prcm) propagation delay time, power on threshold voltage to adc communication 2 16 1/f clk t p(cmcn) propagation delay time, adc communication to conversion start 512 1/f clk ac excitation t d(acx) delay time, phase-to-phase blank period 8 1/f clk t c(acx) acx period 2 t stdr conversion control t p(stdr) propagation delay time, start pin high or start command to drdy high 2 1/f clk figure 1. serial interface timing requirements (1) drdy = data ready function at end of command. (2) data = data output function during command. figure 2. serial interface switching characteristics cs1 sclk din t w(csh) t c(sc) t w(sch) t su(di) t h(di) t w(scl) t d(sccs) t d(cssc) cs2 advance information sclk cs1 dout/drdy t p(csdo) t p(csdoz) t h(scdo1) t p(scdo1) data drdy t w(drh) drdy drdy (1) t h(scdo2) t p(scdo2) cs2
12 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 3. conversion control timing requirements figure 4. power-up characteristics figure 5. reset pin and reset command timing requirements avdd - avss 1 v (typ) 3.5 v (typ) drdy begin adc communication dvdd 1 v (typ) dout/drdy start of 1 st conversion conversion status v bypass all supplies reach thresholds t p(cmcn) t p(prcm) serial command start stop start drdy t w(sth) t w(stl) t p(stdr) t su(drst) t h(drsp) stop reset t w(rstl) conversion status t p(rscn) reset start reset command advance information
13 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 6. ac-excitation timing characteristics figure 7. timing reference dvdd dgnd ? dvdd 50% t d , t h , t p, t w, t c acx1 acx1 acx2 acx2 t d(acx) t d(acx) t c(acx) advance information
14 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 parameter measurement information 7.1 noise performance the ads125h0x noise performance depends on configuration: data rate, pga gain, digital filter configuration, and chop mode. all these parameters influence noise performance. the two largest factors affecting noise performance are data rate and gain factor. since the noise profile is predominantly white (flat vs frequency), deceasing the data rate proportionally decreases total noise. since the noise of the pga is lower than that of the adc, increasing the gain reduces noise when treated as an input-referred quantity. noise performance also depends on the digital filter and chop mode. as the order of the digital filter increases, the noise bandwidth correspondingly decreases, which results in lower noise. as a result of two-point data averaging in chop mode, noise performance improves by 2 compared to the normal operating mode. table 1 shows noise performance for gains 0.125 to 2. table 2 show noise performance for gains 4 to 128. the noise performance data are in units of v rms (rms = root mean square) under the conditions listed. values in parenthesis are peak-to-peak values. effective resolution (bits) and noise-free resolution (resolution with no code flicker) performance data are calculated using equation 1 : effective resolution or noise-free bits resolution (bits) = ln (fsr / e n ) / ln (2) where ? fsr = full scale range = 2 v ref / gain (see pga input range for conditions that limit fsr) ? e n = input-referred voltage noise (use rms value to calculate effective resolution, use p-p value to calculate noise-free resolution) (1) the data shown in the noise performance tables represent typical adc performance at t a = 25 c with chop mode disabled. the noise-performance data are the standard deviation and peak-to-peak computations of the adc data. the noise data are acquired with inputs shorted, based on consecutive adc readings for a period of ten seconds or 8192 data points, whichever occurs first. because of the statistical nature of noise, repeated noise measurements may yield higher or lower noise performance results. long periods of data acquisition may result in increased peak-to-peak noise results. table 1. noise in v rms ( v p-p ) at t a = 25 c, 2.5-v reference, gain = 0.125 to 2 data rate (sps) filter mode gain (v/v) 0.125 0.1875 0.25 0.5 1 2 2.5 fir 1.3 (4.8) 0.89 (3.6) 0.69 (2.1) 0.49 (1.9) 0.37 (1.5) 0.17 (0.67) 2.5 sinc1 1.1 (4.2) 0.6 (2.4) 0.57 (2.4) 0.39 (1.5) 0.29 (1) 0.15 (0.63) 2.5 sinc2 1 (3.6) 0.68 (2) 0.44 (1.8) 0.32 (1) 0.26 (0.97) 0.12 (0.52) 2.5 sinc3 1.1 (3) 0.67 (2) 0.49 (1.5) 0.32 (1) 0.24 (0.89) 0.11 (0.41) 2.5 sinc4 0.98 (3.6) 0.64 (2) 0.48 (1.2) 0.3 (1) 0.26 (0.97) 0.11 (0.41) 5 fir 1.7 (6.6) 1.2 (4.8) 0.93 (4.2) 0.57 (2.5) 0.45 (2) 0.24 (1.2) 5 sinc1 1.5 (6.6) 0.98 (3.6) 0.77 (3.6) 0.53 (2.2) 0.4 (1.9) 0.2 (0.93) 5 sinc2 1.3 (4.8) 0.91 (4) 0.68 (2.4) 0.44 (1.8) 0.35 (1.6) 0.18 (0.82) 5 sinc3 1.2 (4.8) 0.83 (3.2) 0.62 (2.4) 0.39 (1.6) 0.3 (1.3) 0.16 (0.75) 5 sinc4 1.2 (3.6) 0.75 (3.2) 0.54 (2.1) 0.38 (1.5) 0.27 (1.2) 0.14 (0.56) 10 fir 2.4 (11) 1.6 (7.9) 1.2 (5.7) 0.82 (4.3) 0.69 (3.3) 0.34 (1.7) 10 sinc1 1.9 (9.5) 1.4 (6.8) 1.1 (5.4) 0.7 (3.4) 0.55 (2.7) 0.3 (1.5) 10 sinc2 1.7 (8.9) 1.2 (5.6) 0.9 (4.5) 0.56 (2.7) 0.47 (2.3) 0.24 (1.2) 10 sinc3 1.5 (6.6) 1.1 (5.2) 0.89 (4.2) 0.54 (2.7) 0.46 (2.5) 0.24 (1.1) 10 sinc4 1.5 (6.6) 0.99 (4.4) 0.79 (3.6) 0.49 (2.4) 0.39 (1.9) 0.2 (1) 16.6 sinc1 2.6 (11) 1.7 (8.7) 1.4 (6.6) 0.87 (4.5) 0.72 (3.5) 0.37 (2) 16.6 sinc2 2.1 (10) 1.5 (7.5) 1.1 (5.7) 0.78 (3.7) 0.62 (3.2) 0.32 (1.6) 16.6 sinc3 1.9 (9.5) 1.4 (7.2) 1.1 (5.1) 0.72 (3.6) 0.54 (2.5) 0.27 (1.3) 16.6 sinc4 1.8 (7.7) 1.3 (6.4) 0.97 (4.8) 0.65 (3.1) 0.48 (2.5) 0.24 (1.2) 20 fir 3 (15) 2.1 (11) 1.8 (8.6) 1.1 (5.2) 0.89 (4.8) 0.46 (2.6) advance information
15 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated noise performance (continued) table 1. noise in v rms ( v p-p ) at t a = 25 c, 2.5-v reference, gain = 0.125 to 2 (continued) data rate (sps) filter mode gain (v/v) 0.125 0.1875 0.25 0.5 1 2 20 sinc1 2.7 (13) 1.9 (9.5) 1.5 (7.5) 0.97 (5.5) 0.76 (4.2) 0.43 (2.3) 20 sinc2 2.2 (11) 1.5 (7.2) 1.3 (6) 0.83 (4.2) 0.69 (3.7) 0.35 (1.8) 20 sinc3 2.1 (10) 1.6 (8.3) 1.2 (5.4) 0.77 (4) 0.64 (3.1) 0.31 (1.6) 20 sinc4 2 (9.5) 1.3 (6.8) 1.1 (4.8) 0.65 (3.1) 0.56 (2.7) 0.28 (1.4) 50 sinc1 4.1 (24) 2.9 (17) 2.3 (14) 1.5 (7.7) 1.2 (7.5) 0.64 (3.7) 50 sinc2 3.2 (18) 2.3 (12) 1.9 (11) 1.3 (7) 1.1 (5.8) 0.54 (3.1) 50 sinc3 3.3 (18) 2.2 (13) 1.8 (9.2) 1.2 (6.7) 0.93 (5.3) 0.49 (3) 50 sinc4 3.1 (17) 2 (11) 1.6 (8.3) 1 (5.8) 0.87 (4.7) 0.43 (2.4) 60 sinc1 4.5 (27) 3.1 (17) 2.4 (13) 1.6 (9.2) 1.4 (8.3) 0.69 (3.8) 60 sinc2 3.8 (23) 2.6 (14) 2.1 (11) 1.4 (7.3) 1.2 (5.9) 0.57 (3.1) 60 sinc3 3.4 (19) 2.3 (13) 1.8 (9.2) 1.3 (6.9) 1 (5.4) 0.54 (3.1) 60 sinc4 3.3 (18) 2.1 (12) 1.9 (9.8) 1.2 (6.6) 0.95 (5.2) 0.52 (2.8) 100 sinc1 5.6 (34) 4.1 (23) 3.3 (20) 2.1 (12) 1.8 (9.7) 0.91 (5.7) 100 sinc2 4.9 (30) 3.4 (21) 2.7 (16) 1.8 (11) 1.5 (8.7) 0.75 (4.4) 100 sinc3 4.4 (26) 3.1 (18) 2.5 (14) 1.7 (10) 1.3 (8.2) 0.69 (4.2) 100 sinc4 4.1 (24) 2.9 (17) 2.3 (14) 1.5 (8.5) 1.3 (7.7) 0.63 (4) 400 sinc1 12 (74) 8.1 (55) 6.4 (43) 4.3 (27) 3.6 (25) 1.8 (11) 400 sinc2 9.3 (60) 6.7 (44) 5.3 (32) 3.5 (23) 2.9 (19) 1.5 (10) 400 sinc3 8.6 (54) 6.2 (39) 4.9 (32) 3.2 (20) 2.7 (17) 1.4 (9.1) 400 sinc4 8 (52) 5.6 (37) 4.5 (30) 3 (20) 2.5 (16) 1.3 (8.3) 1200 sinc1 20 (140) 14 (98) 11 (75) 7.3 (48) 6 (40) 3.1 (20) 1200 sinc2 17 (110) 12 (78) 9.2 (62) 6.1 (41) 5 (33) 2.6 (18) 1200 sinc3 15 (100) 11 (72) 8.4 (56) 5.6 (37) 4.6 (31) 2.4 (16) 1200 sinc4 14 (95) 9.9 (68) 7.8 (51) 5.2 (37) 4.3 (29) 2.2 (15) 2400 sinc1 27 (200) 19 (140) 15 (110) 10 (72) 8.3 (60) 4.2 (30) 2400 sinc2 23 (180) 16 (120) 13 (97) 8.7 (62) 7 (53) 3.6 (26) 2400 sinc3 21 (160) 15 (110) 12 (94) 7.9 (59) 6.5 (50) 3.3 (23) 2400 sinc4 20 (140) 14 (100) 11 (78) 7.3 (53) 6 (43) 3.1 (22) 4800 sinc1 37 (270) 26 (200) 21 (160) 14 (110) 11 (83) 5.6 (42) 4800 sinc2 33 (250) 23 (170) 18 (140) 12 (88) 9.8 (73) 5 (40) 4800 sinc3 31 (230) 21 (150) 17 (130) 11 (83) 9 (65) 4.7 (36) 4800 sinc4 29 (220) 20 (150) 16 (120) 11 (81) 8.5 (63) 4.4 (33) 7200 sinc1 44 (330) 31 (230) 24 (180) 16 (120) 13 (98) 6.5 (48) 7200 sinc2 39 (300) 28 (210) 22 (170) 14 (100) 12 (90) 5.9 (46) 7200 sinc3 37 (280) 26 (200) 21 (160) 13 (100) 11 (82) 5.5 (41) 7200 sinc4 35 (260) 25 (180) 20 (150) 13 (95) 10 (81) 5.3 (41) 14400 sinc5 53 (430) 36 (290) 29 (220) 18 (140) 14 (120) 7.4 (58) 19200 sinc5 72 (560) 50 (390) 39 (320) 23 (180) 17 (130) 8.8 (71) 25600 sinc5 150 (1300) 100 (870) 79 (640) 42 (350) 26 (220) 13 (110) 40000 sinc5 250 (2000) 160 (1300) 120 (1000) 65 (530) 37 (310) 19 (150) advance information
16 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated table 2. noise in v rms ( v p-p ) at t a = 25 c, 2.5-v reference, gain = 4 to 128 data rate (sps) filter mode gain (v/v) 4 8 16 32 64 128 2.5 fir 0.082 (0.35) 0.051 (0.2) 0.032 (0.14) 0.027 (0.11) 0.027 (0.1) 0.029 (0.12) 2.5 sinc1 0.088 (0.35) 0.05 (0.19) 0.024 (0.089) 0.024 (0.089) 0.023 (0.098) 0.024 (0.1) 2.5 sinc2 0.059 (0.24) 0.037 (0.14) 0.021 (0.084) 0.018 (0.072) 0.017 (0.076) 0.019 (0.076) 2.5 sinc3 0.06 (0.24) 0.034 (0.13) 0.019 (0.075) 0.017 (0.07) 0.016 (0.073) 0.018 (0.075) 2.5 sinc4 0.054 (0.19) 0.034 (0.13) 0.019 (0.075) 0.016 (0.065) 0.015 (0.062) 0.016 (0.069) 5 fir 0.12 (0.52) 0.071 (0.33) 0.046 (0.21) 0.038 (0.19) 0.039 (0.17) 0.037 (0.18) 5 sinc1 0.11 (0.48) 0.061 (0.28) 0.038 (0.18) 0.029 (0.14) 0.029 (0.15) 0.029 (0.13) 5 sinc2 0.093 (0.43) 0.048 (0.21) 0.029 (0.14) 0.024 (0.11) 0.026 (0.12) 0.023 (0.1) 5 sinc3 0.081 (0.41) 0.044 (0.2) 0.03 (0.13) 0.023 (0.1) 0.022 (0.1) 0.022 (0.11) 5 sinc4 0.066 (0.3) 0.043 (0.2) 0.027 (0.13) 0.022 (0.093) 0.022 (0.11) 0.021 (0.096) 10 fir 0.19 (1) 0.099 (0.51) 0.064 (0.36) 0.053 (0.29) 0.051 (0.3) 0.054 (0.3) 10 sinc1 0.16 (0.82) 0.086 (0.46) 0.054 (0.3) 0.045 (0.22) 0.043 (0.21) 0.044 (0.23) 10 sinc2 0.12 (0.56) 0.068 (0.36) 0.044 (0.23) 0.037 (0.2) 0.034 (0.18) 0.033 (0.18) 10 sinc3 0.11 (0.52) 0.066 (0.31) 0.042 (0.21) 0.032 (0.17) 0.032 (0.16) 0.032 (0.16) 10 sinc4 0.096 (0.45) 0.059 (0.31) 0.039 (0.2) 0.032 (0.17) 0.031 (0.16) 0.03 (0.15) 16.6 sinc1 0.19 (1) 0.11 (0.56) 0.075 (0.38) 0.054 (0.3) 0.055 (0.29) 0.056 (0.31) 16.6 sinc2 0.16 (0.89) 0.086 (0.4) 0.054 (0.27) 0.044 (0.22) 0.049 (0.24) 0.046 (0.24) 16.6 sinc3 0.15 (0.73) 0.084 (0.41) 0.053 (0.27) 0.041 (0.22) 0.04 (0.22) 0.041 (0.2) 16.6 sinc4 0.13 (0.67) 0.076 (0.39) 0.053 (0.29) 0.042 (0.24) 0.04 (0.21) 0.036 (0.17) 20 fir 0.24 (1.2) 0.14 (0.72) 0.088 (0.45) 0.072 (0.38) 0.071 (0.37) 0.074 (0.37) 20 sinc1 0.22 (1.1) 0.12 (0.58) 0.079 (0.41) 0.064 (0.32) 0.061 (0.32) 0.06 (0.34) 20 sinc2 0.18 (1) 0.1 (0.57) 0.062 (0.34) 0.049 (0.25) 0.049 (0.26) 0.047 (0.29) 20 sinc3 0.16 (0.89) 0.089 (0.48) 0.063 (0.32) 0.046 (0.22) 0.045 (0.21) 0.045 (0.23) 20 sinc4 0.15 (0.82) 0.083 (0.41) 0.056 (0.29) 0.045 (0.23) 0.042 (0.22) 0.046 (0.24) 50 sinc1 0.35 (2.1) 0.19 (1.1) 0.12 (0.69) 0.097 (0.52) 0.096 (0.57) 0.098 (0.58) 50 sinc2 0.28 (1.6) 0.15 (0.84) 0.099 (0.56) 0.075 (0.43) 0.077 (0.43) 0.076 (0.46) 50 sinc3 0.25 (1.5) 0.14 (0.75) 0.093 (0.51) 0.074 (0.41) 0.07 (0.38) 0.071 (0.37) 50 sinc4 0.23 (1.4) 0.13 (0.76) 0.087 (0.47) 0.066 (0.37) 0.065 (0.35) 0.065 (0.37) 60 sinc1 0.38 (2.2) 0.21 (1.2) 0.14 (0.79) 0.11 (0.57) 0.1 (0.59) 0.1 (0.6) 60 sinc2 0.3 (1.7) 0.17 (0.93) 0.11 (0.66) 0.085 (0.47) 0.084 (0.49) 0.083 (0.49) 60 sinc3 0.27 (1.6) 0.15 (0.79) 0.097 (0.53) 0.078 (0.43) 0.078 (0.43) 0.076 (0.42) 60 sinc4 0.27 (1.6) 0.14 (0.89) 0.092 (0.5) 0.075 (0.46) 0.076 (0.4) 0.073 (0.4) 100 sinc1 0.49 (2.8) 0.27 (1.5) 0.17 (1) 0.14 (0.81) 0.14 (0.88) 0.13 (0.81) 100 sinc2 0.39 (2.3) 0.22 (1.4) 0.14 (0.87) 0.11 (0.63) 0.11 (0.69) 0.11 (0.66) 100 sinc3 0.35 (2.1) 0.2 (1.2) 0.13 (0.75) 0.1 (0.63) 0.1 (0.61) 0.1 (0.69) 100 sinc4 0.32 (2) 0.18 (1.2) 0.13 (0.73) 0.094 (0.57) 0.092 (0.56) 0.093 (0.57) 400 sinc1 0.94 (6) 0.53 (3.5) 0.34 (2.1) 0.27 (1.8) 0.27 (1.7) 0.27 (1.8) 400 sinc2 0.78 (5.2) 0.44 (3.1) 0.29 (1.8) 0.22 (1.4) 0.22 (1.4) 0.22 (1.4) 400 sinc3 0.72 (4.6) 0.4 (2.6) 0.26 (1.6) 0.2 (1.3) 0.2 (1.3) 0.2 (1.3) 400 sinc4 0.67 (4.2) 0.37 (2.4) 0.24 (1.6) 0.19 (1.2) 0.19 (1.2) 0.19 (1.1) 1200 sinc1 1.6 (12) 0.91 (6.3) 0.59 (4.1) 0.46 (3.1) 0.45 (3.1) 0.45 (3.1) 1200 sinc2 1.3 (9.3) 0.76 (5.2) 0.49 (3.2) 0.39 (2.6) 0.38 (2.6) 0.38 (2.6) 1200 sinc3 1.2 (8.2) 0.69 (4.7) 0.45 (3.1) 0.35 (2.4) 0.35 (2.4) 0.35 (2.2) 1200 sinc4 1.2 (7.6) 0.64 (4.3) 0.41 (2.7) 0.33 (2.3) 0.32 (2.2) 0.32 (2.3) 2400 sinc1 2.2 (17) 1.2 (8.9) 0.81 (5.8) 0.64 (4.5) 0.62 (4.5) 0.62 (4.6) 2400 sinc2 1.9 (14) 1.1 (7.7) 0.68 (5) 0.54 (3.9) 0.54 (3.9) 0.54 (4) advance information
17 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated table 2. noise in v rms ( v p-p ) at t a = 25 c, 2.5-v reference, gain = 4 to 128 (continued) data rate (sps) filter mode gain (v/v) 4 8 16 32 64 128 2400 sinc3 1.7 (14) 0.97 (7.1) 0.62 (4.4) 0.49 (3.5) 0.48 (3.4) 0.49 (3.5) 2400 sinc4 1.6 (12) 0.91 (6.7) 0.59 (4.1) 0.46 (3.5) 0.46 (3.4) 0.46 (3.4) 4800 sinc1 3 (23) 1.6 (13) 1.1 (7.8) 0.83 (6.2) 0.83 (6.2) 0.82 (6.1) 4800 sinc2 2.6 (20) 1.5 (12) 0.95 (7.2) 0.75 (5.6) 0.74 (5.4) 0.73 (5.5) 4800 sinc3 2.4 (19) 1.4 (10) 0.89 (6.4) 0.69 (5) 0.68 (5.2) 0.69 (5.5) 4800 sinc4 2.3 (17) 1.3 (9.8) 0.82 (6.2) 0.64 (5) 0.65 (4.9) 0.64 (4.9) 7200 sinc1 3.3 (25) 1.9 (15) 1.2 (9) 0.95 (7) 0.94 (6.9) 0.94 (7.1) 7200 sinc2 3.1 (24) 1.7 (13) 1.1 (8.7) 0.87 (6.6) 0.86 (6.5) 0.86 (6.4) 7200 sinc3 2.9 (22) 1.6 (12) 1.1 (7.9) 0.83 (6.1) 0.82 (6.2) 0.82 (6.4) 7200 sinc4 2.8 (21) 1.6 (12) 1 (7.7) 0.79 (5.8) 0.78 (6) 0.78 (5.8) 14400 sinc5 3.8 (29) 2.1 (17) 1.4 (11) 1.1 (8.4) 1.1 (8.1) 1 (8.4) 19200 sinc5 4.6 (36) 2.5 (20) 1.6 (13) 1.2 (9.6) 1.2 (9.3) 1.2 (9.5) 25600 sinc5 6.7 (56) 3.6 (29) 2.1 (17) 1.5 (13) 1.4 (12) 1.4 (12) 40000 sinc5 9.6 (80) 5 (43) 2.9 (23) 2 (16) 1.8 (15) 1.8 (15) advance information
18 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 detailed description 8.1 overview the ads125h01 and ads125h02 are 2-channel (configurable as two single-ended input channels or one differential input channel), 20-v differential, 15.5-v absolute voltage input, 24-bit, 40000-sps, delta-sigma ( ) adcs. the devices also include a programmable gain amplifier (pga), monitors and voltage reference. the adcs provide complete, high-accuracy, one-chip measurement solutions over a wide range of common-mode voltages, including 10-v and 20-ma transmitters, strain-gauge sensors, thermocouples, and resistance temperature detectors (rtd). the ads125h02 is backward compatible to the ads125h01. the ads125h02 includes two sensor excitation current sources (idacs), four gpio ports, and one additional reference input. key features of the adc are: ? 20-v differential, 15.5-v absolute input voltage range ? high input impedance pga and high-resolution, 24-bit adc ? 2.5-v voltage reference ? internal oscillator ? signal and voltage reference monitors ? temperature sensor ? spi compatible serial interface with crc error checking ? one or two external voltage reference inputs (ads125h01 or ads125h02, respectively) ? two current sources (ads125h02) ? four gpio with ac-excitation (ads125h02) 8.2 functional block diagram analog inputs (ain0, ain1, aincom) connect to the input multiplexer (mux) for input channel selection. the adc supports one differential or two single-ended input configurations. the input channel multiplexer is powered by the high-voltage analog power supplies. the programmable gain amplifier (pga) follows the input multiplexer. the pga is high input impedance, cmos differential input ? differential output, programmable gain and programmable attenuation amplifier. in attenuation setting, the pga translates the high-level input voltage to the low-level (5-v) voltage range of the adc. in gain setting, the pga amplifies the low-level input voltage to the input range of the adc. the pga output connects to pins capp and capn. the adc anti-alias filter is formed by pga output resistors and the external capacitor. key nodes of the pga are monitored for linear operation. bits in the status register are set when the pga overrange condition is detected. advance information 24-bit ? adc input mux digital filter serial interface and crc verification cs2 dout/drdy sclk start clock mux clkin refout ref monitor signal monitors buf aincom temp sensor dgnd ref mux 2.5-v ref ain0 ain1 internal oscillator din hv_avss hv_avdd reset supply monitor agnd avdd dvdd idac1 idac2 gpio control ads125h02 gpio2 gpio3 refp1/gpio0 refn1/gpio1 drdy refp0/n0 ldo bypass 2-v digital core avdd pga input/output nodes cs1 pga capp/n
19 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated functional block diagram (continued) the delta-sigma modulator measures the input voltage relative to the reference voltage to produce the 24-bit conversion result. the input range of the adc is v ref / gain. the digital filter averages and decimates the modulator output data to produce the final, down-sampled conversion result. the sinc filter is programmable (sinc1 through sinc5) allowing optimization of conversion time, noise and line-cycle rejection. the finite impulse response (fir) filter mode provides single-cycle settled data while simultaneously rejecting 50/60-hz frequencies at data rate of 20 sps. the adc reference voltage is internal (2.5 v) or external reference. the refout pin is the buffered, 2.5-v reference output. the reference is monitored for out-of-range operation. the ads125h02 provides two voltage reference input pin pairs. the ads125h02 includes two current sources (idac1, idac2), that operate from the 5-v analog power supply. the idacs provide excitation current for resistive sensors (for example, rtd). additionally, the ads125h02 provides four gpio ports. the gpios control external multiplexers and input and output of general-purpose logic signals. the adc has an internal temperature sensor to monitor device temperature. the high-voltage power supply voltage is available for readback verification through the adc. the spi-compatible serial interface is used to read the conversion data and for adc configuration. communication is validated by a crc. the serial interface consists of the following signals: cs1, cs2, sclk, din and dout/ drdy. the dual function dout/ drdy is the serial data output and the data ready functions combined into one pin. drdy is the dedicated data ready output. the adc clock is either the internal oscillator or external. the external clock is selected automatically. the clock frequency is 7.3728 mhz (10.24 mhz in 40000 sps operation). adc conversions are controlled by the start pin or by the start command. the adc is programmable for continuous mode or one-shot conversions. the adc is automatically reset at power-up, by the reset input or by the reset command. the input signal multiplexer and pga are powered by the high-voltage power supplies (hvavdd and hv_avss). the high-voltage power supplies are configurable to either bipolar or unipolar modes (up to 18 v, or up to 36 v). the modulator, voltage reference and excitation current sources are powered by the avdd power supply (5 v). the digital i/o is powered by dvdd (3 v to 5 v range). an internal sub-regulator powers the adc digital core. a external bypass capacitor is required to connect to the sub-regulator output (bypass). advance information
20 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3 feature description the following sections describe the ads125h0x functional blocks. 8.3.1 analog inputs as shown in figure 8 , the analog inputs of the adc consist of esd protection diodes and input multiplexer. the multiplexer supports three external input and three internal measurement configurations. figure 8. analog input diagram 8.3.1.1 esd diodes esd diodes are incorporated to protect the adc inputs from possible esd events occurring during the manufacturing process and during pcb assembly when manufactured in an esd-controlled environment. for system-level esd protection, consider the use of external esd protection devices for pins that are exposed to esd, including the analog inputs. if either input is driven below hv_avss ? 0.3 v, or above hv_avdd + 0.3 v, the internal protection diodes may conduct. if these conditions are possible, input current may flow into the inputs. use external clamp diodes, series resistors, or both to limit the input current to the specified maximum value. advance information aincom ain0 ain1 hv_avdd esd diodes v ainp v ainn pga hv_avss adc hv supply n temp sensor n v com ain0 ain1 aincom negative multiplexer temp sensor p v com ain0 ain1 aincom positive multiplexer hv supply p
21 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 8.3.1.2 input multiplexer the input multiplexer selects the signal for measurement. the adc supports two single-ended measurements (ain0 ? aincom, or ain1 ? aincom) and one differential input measurement (ain1 ? ain0). the multiplexer is programmed by the mux[2:0] bits of the mode4 register (address = 10h). use the multiplexer to select the inputs as listed in table 3 . table 3. input multiplexer settings mux[2:0] bits of register mode4 (10h) measurement (p ? n) 000 ain1 ? ain0 001 ain0 ? ain1 (reserved for use with final silicon) 010 ain1 ? aincom 011 ain0 ? aincom 100 hv supply readback: (hv_avdd ? hv_avss) / 36 101 pga inputs connected to v com : (hv_avdd + hv_avss) / 2 (default) 110 temperature sensor 111 reserved 8.3.2 temperature sensor the adc has an internal temperature sensor. the temperature sensor is comprised of two internal diodes with one diode having 80 times the current density of the other. the difference in current density of the diodes yields a differential output voltage that is proportional to absolute temperature. to measure the temperature sensor, write 110b to select the temperature sensor and then start a new adc conversion. equation 2 shows how to convert the temperature sensor reading to degrees celsius ( c): temperature ( c) = [(temperature reading ( v) ? 122,400) / 420 v/ c] + 25 c (2) when measuring the temperature sensor, set the gain equal to 1 and disable the chop and ac-excitation modes. as a result of the low package-to-pcb thermal resistance, the internal temperature closely tracks the pcb temperature. be aware that device self-heating increases the internal temperature relative to the surrounding pcb. 8.3.3 high-voltage power-supply readback read the high-voltage power supply by selection through the input multiplexer. the supply voltage is internally divided by 36 for measurement. equation 3 shows the supply voltage scaling. high-voltage power supply (v) = (hv_avdd ? hv_avss) / 36 (3) measure the high-voltage power supply using the internal or external reference. to measure, disable chop and ac-excitation modes. write the 100b to the multiplexer control bits to select the input multiplexer and then start a new conversion. 8.3.4 internal v com connection (default) for this multiplexer configuration, the external inputs are open and the pga inputs connect to an internal v com voltage as defined: (hv_avdd + hv_avss) / 2. use this mode to measure the adc noise performance and offset voltage, or to short the inputs for offset calibration. be aware that shorting the inputs to the system yield the best calibration results. short the v com input connection by writing the 101b to the multiplexer control register. using the desired adc configuration, start a new conversion with the inputs shorted. advance information
22 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.5 pga the pga is a low-noise, programmable gain and programmable attenuation, cmos differential-input, differential- output amplifier. the pga operates in gain or attenuation mode depending on the programming. program the pga for gain mode when the signal is less than the reference voltage. program the pga for attenuation mode when signal is greater than the reference voltage. figure 9 shows the pga block diagram. the pga consists of two stages. the first stage is a high input impedance, cmos differential input ? differential output, noninverting input amplifier. the stage is powered by the high-voltage analog power supplies (hv_avdd and hv_avss). the first stage provides gain of 1 v/v to 128 v/v. the second stage is differential input ? differential output, inverting amplifier powered by the low-voltage analog supply (avdd). the second stage provides attenuations from 0.5 v/v to 0.125 v/v. the common-mode voltage of the second stage is regulated to avdd / 2. the second stage output drives the adc inputs. the output connects to the capp and capn pins. connect an external 1-nf capacitor to these pins to form the adc antialias filter. the filter also provides a bypass for the modulator sampling pulses. capp and capn nodes are sensitive to interference from noise. as a result, place the capacitor close to the pins using short, direct traces. avoid running clock traces or other digital traces in the vicinity of these pins. amplifiers a1 and a2 are protected by inverse-parallel diodes connected across the amplifier inputs. the diodes are in addition to the input esd-protection diodes. when the signal to the pga is out-of-range, causing the amplifiers to saturate, the diodes may conduct resulting in current flow through the inputs. additionally, high dv/dt signal conditions, such as caused by switching of a signal multiplexer, may cause a transient turn-on of the protection diodes. use an rc filter on the pga inputs to limit the dv/dt of the signal to eliminate transient diode turn-on. the pga incorporates filters to improve rejection by rfi and emi noise interference. key nodes of the pga input and output circuit are monitored for possible out-of-range condition. if an out-of-range condition is detected, the monitors set appropriate alarm bits in the status register. figure 9. pga block diagram 8.3.5.1 pga input range the reference voltage and the pga gain (attenuation) determine the full-scale, differential input range of the adc. table 4 lists full-scale input range verses gain (attenuation) when operating with a 2.5-v reference. the full-scale input range scales with the reference voltage. the table shows examples of system-level ranges for differential and single-ended input configurations. the example ranges shown include margin for overrange. the high resolution afforded by the adc provides accurate measurements for unipolar input, single-ended configurations with low loss of resolution. advance information capp + 8 pf + 8 pf v ainp v ainn capn 375 375 400 8 pf 8 pf a1 a2 1 nf c0g adc + + a3 a4 pga monitor avdd / 2 v ainp v ainn 400 8 pf hv_avss hv_avdd agnd avdd pga monitor pga monitor pga monitor
23 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) v ref = 2.5 v. hv_avdd and hv_avss = 18 v. (2) bipolar supply operation (3) maximum differential input range is limited to 20 v table 4. full-scale voltage range gain[2:0] bits gain (v/v) full scale input range (1) example differential range example single-ended range (2) 0000 0.125 20 v (3) 18 v 0 v to 15.5 v 0001 0.1875 13.3 v 10 v 0 v to 10 v 0010 0.25 10 v 8 v 0 v to 8 v 0011 0.5 5 v 4 v 0 v to 4 v 0100 1 2.5 v 2 v 0 v to 2v 0101 2 1.25 v 1 v 0 v to 1 v 0110 4 0.625 v 0.5 v 0 v to 0.5 v 0111 8 0.312 v 0.25v 0 v to 0.25 v 1000 16 0.156 v 0.125 v 0 v to 0.125 v 1001 32 0.078 v 0.062 v 0 v to 0.062 v 1010 64 0.039 v 0.031 v 0 v to 0.031 v 1011 128 0.019 v 0.015 v 0 v to 0.015 v as with many amplifiers, the pga has limits for the maximum input voltage that must not be exceeded. the absolute input voltage is defined as the signal and common-mode voltages combined. the maximum input voltage depends on the pga gain, the maximum expected differential voltage (v in ), and the minimum expected high-voltage power supply. for linear operation of the pga, maintain the absolute input voltage within range, as given by equation 4 : absolute input voltage: hv_avss + 2.5 + v in (gain ? 1) / 2 < v (ainx) < hv_avdd ? 2.5 ? v in (gain ? 1) / 2 where ? for gain < 1, use gain = 1 in the equation ? v (ainx) = absolute input voltage ? v in = maximum differential input voltage = v ainp ? v ainn (4) the full available differential input voltage is also limited under certain operating conditions. the first condition is operation with reference voltage > avdd - 1 v (all gains and attenuations). in this case, the differential input voltage is limited to v in < (avdd - 1 v) / gain. additionally, the maximum differential input voltage is limited to 20 v, irrespective of gain (attenuation) factor or reference voltage. the relationship between pga input to pga output is shown in figure 10 and figure 11 . in attenuation mode, the first pga stage is configured as a unit-gain follower. the second pga stage attenuates the differential input and establishes the common-mode output voltage of the signal to avdd / 2. in gain mode, first pga stage amplifies the differential signal. the output voltage of each pga stage must be maintained within the voltage headroom as shown in the shaded areas of the figures. figure 10. pga - attenuation mode advance information hv_avss hv_avdd 2.5 v hv_avss + 2.5 v v inp v inn v inp v in = v inp - v inn pga input pga first stage output hv_avdd pga second stage output avdd avdd 0.5 v agnd agnd + 0.5 v v inn avdd/2 + v in a*dlq / 2 avdd/2 - v in a*dlq / 2 avdd/2
24 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 11. pga - gain mode 8.3.5.2 pga monitor the pga has a linear operating range that must not be exceeded, otherwise the conversion data are not valid. the adc includes pga monitors that flag when the amplifier is in a overload condition. as shown in figure 12 , the input and output nodes of the pga first stage are monitored by high and low voltage detectors. the low threshold is hv_avdd ? 2 v and the high threshold is hv_avss + 2 v. see figure 13 . there are four nodes that are monitored, each with high/low alarm states for a total of 8 monitor flags that are reported in the status byte. monitor for the occurrence of a possible pga overload condition by polling the stat12 bit (bit 4) of the status0 byte. this flag indicates if one or more pga alarm flags are set or if a crc-2 error occurred. poll status1 and status2 registers (11h and 12h) to determine the source of the error. if the pga is in an overload condition, the flag bits of the status1 register are set. the pga status flags are latched in the status1 register. the flags are reset by the read operation (clear-on-read operation). the pga overload flags, crc1err and crc2err flags must be cleared to clear the global error flag, stat12. see table 43 for the description of the pga alarm bits. the pga monitors are fast-responding, analog comparators. therefore, the monitors are capable of detecting short-transient overload conditions. be aware that short duration pga overload events may not result in clipped conversion values because of the data integration operations (averaging) of the digital filter. be aware that certain input overload conditions may trigger input alarms without necessarily triggering the corresponding output alarms. figure 12. pga monitors figure 13. pga monitor thresholds 8.3.6 reference voltage the adc reference voltage is either 2.5-v internal, one of two external reference pin pairs, or the avdd power supply (5 v). the reference voltage is defined as v ref = v refp ? v refn , where v refp and v refn are the positive and negative reference voltages, respectively. the polarity of v ref must always be positive. figure 14 shows the block diagram of the reference multiplexer. hv_avss hv_avdd 2.5 v hv_avss + 2.5 v v inp + v in a (gain 1) / 2 v inn v inp v in = v inp - v inn pga input pga first stage output hv_avdd pga second stage output avdd avdd 0.5 v agnd agnd + 0.5 v v inn - v in a (gain 1) / 2 avdd/2 + v in a*dlq / 2 avdd/2 - v in a*dlq / 2 avdd/2 positive input, high condition positive input, low condition positive (+) negative (-) positive (+) negative (-) negative input, high condition negative input, low condition first stage positive output, high condition first stage positive output, low condition first stage negative output, high condition first stage negative output, low condition pga-2 pga-1 high condition hv_avdd hv_avdd t 2 v hv_avss + 2 v hv_avss low condition pga node voltage advance information
25 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) the internal reference requires a 10- f capacitor connected to the refout and agnd pins. (2) ads125h02 only provides the second reference input pin pairs. figure 14. reference multiplexer diagram program rmuxp[1:0] and rmuxn[1:0] bits of the ref register to select the positive and negative reference voltages, respectively. the positive reference options are internal reference positive, external refp0, external refp1, or avdd. the negative selections are internal reference negative, external refn0, external refn1, or agnd. the reference voltage is monitored for low voltage conditions. see reference monitor . 8.3.6.1 internal reference the adc includes a precision 2.5-v reference. program the reference multiplexer bits rmuxp[1:0] and rmuxn[1:0] to "00" to select the internal reference. the ref_enb bit of the ref register controls the reference bias (default = off). enable the reference if using the current sources. a 10- f capacitor is required between the refout and agnd pins in order to filter reference noise. the capacitor is not required if not using the internal reference. be aware of avdd inrush current when the reference is enabled as a result of charging the 10- f refout capacitor. also, when the reference is enabled, be aware of the time for reference stabilization before beginning conversions or before calibrating the adc. refout is the reference output and agnd is the reference return. use a star layout connection for the reference return and make this connection close to the agnd pin. 8.3.6.2 external reference use an external reference by applying the reference voltage to one of the reference input pin pairs. the reference inputs are differential with positive and negative inputs. program the reference multiplexer bits rmuxp[1:0] and rmuxn[1:0] to "10" or "11" to select inputs (refp0, refn0) and (refp1, refn1), respectively. pins refp1, refn1 are available with ads125h02 only. follow the specified absolute and differential reference voltage operating conditions. see recommended operating conditions . use a 10-nf bypass capacitor across the reference input pins to filter noise. be aware that the reference inputs have input current that lead to voltage errors if large reference impedances are present. when the impedances are present, consider the impact of the error to the reference voltage. 8.3.6.3 avdd power-supply reference use the avdd power supply as reference by setting the reference multiplexer bits rmuxp[1:0] and rmuxn[1:0] to "01" (default mode of operation). for 6-wire load cell applications with excitation sense connections, or ac- excitation mode, connect the sense voltage to the reference inputs and program the adc for external reference operation. advance information refp0 refp1/gpio0 refn0 refn1/gpio1 agnd refout 2.5-v internal avdd rmuxn[1:0] bits 1:0 of ref (register address = 06h) refenb bit 4 of ref (register address = 06h) adc v refp v refn (1) 01 10 11 00 0 = internal ref off (default) 1 = internal ref on (2) (2) rmuxp[1:0] bits 3:2 of ref (register address = 06h) 01 10 11 00 buf reference monitor 10 f +
26 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.6.4 reference monitor the adc incorporates a reference monitor to detect a low or missing reference voltage. as shown in figure 15 and figure 16 , if the reference voltage (v ref = v refp ? v refn ) is below 0.4 v, the refalm bit is set in the status0 byte. the alarm is read only and resets at the next conversion after the condition is removed. use the reference monitor to detect a missing or failed reference voltage. to implement the reference alarm, use a 100-k resistor across the reference inputs. the resistor biases the p and n reference inputs to 0 v if either input is not connected. poll bit 3 (refalm) of the status0 byte to determine if the reference alarm is set. figure 15. reference monitor figure 16. reference monitor threshold 8.3.7 current sources (idac1 and idac2) the ads125h02 incorporates two current sources designed to provide excitation current to rtd, thermistor, diode and other sensor types that require constant current biasing. the current source outputs are on pins idac1 and idac2. the voltage compliance range is governed by the avdd analog supply (5 v). the currents are individually programmed over the 50 a to 3000 a range. as shown in figure 17 , the i_mux register controls the connection to the pins. figure 17. current source output diagram enable the internal voltage reference to operate the current sources. double the current value or produce an intermediate current value by connecting the current source output pins together. maintain the compliance voltage of the current sources as specified in electrical characteristics . 0.4 v agnd ref low condition reference voltage advance information idac1 idac2 0000: off 0001: 50 a 0010: 100 a 0011: 250 a 0100: 500 a 0101: 750 a 0110: 1000 a 0111: 1500 a 1000: 2000 a 1001: 2500 a 1010: 3000 a i_mag1[3:0] bits 3:0 of i_mag (register address = 0eh) i_mag2[3:0] bits 7:4 of i_mag (register address = 0eh) avdd avdd i_mux1[3:0] bits 3:0 of i_mux (register address = 0dh) 1000: current source 1 connected to idac1 pin 1001: current source 1 connected to idac2 pin 1111: open i_mux2[3:0] bits 3:0 of i_mux (register address = 0dh) 1000: current source 2 connected to idac1 pin 1001: current source 2 connected to idac2 pin 1111: open x status0 byte 7 6 5 4 3 2 1 0 0.4 v refalm refp0 refn0 100 k + _ ref mux _ + + _ external reference
27 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.8 general-purpose input and outputs (gpios) the ads125h02 provides four gpio pins (gpio3 through gpio0), two of which are multiplexed with the external reference refp1 and refn1 input pins. the gpio are digital inputs and outputs with values that are read and written by the gpio_dat bits of the mode3 register . the gpio input and output levels are referred to the 5-v analog supply (avdd and agnd). the input threshold values between values logic 0 and logic 1 is avdd / 2 (typical). see figure 18 . bits gpio_con[3:0] set the gpio connection to the designated pin (1 = connect). gpio_dir bits program the direction of the gpio as input (1) or output (0). bits gpio_dat[3:0] are the data values for the gpio. observe that if a gpio pin is programmed as an output, the value read is the register data that is written. the gpio provides the output drive signals of the ac-excitation mode. see ac-excitation mode . figure 18. gpio block diagram 8.3.9 adc modulator the modulator is an inherently stable, fourth-order, 2 + 2 pipelined modulator. the modulator samples the analog input voltage at a high sample rate (f mod = f clk / 8) and converts the analog input to a ones density bit stream for processing by the digital filter. 8.3.10 digital filter the digital filter processes the modulator output data to produce the high-resolution conversion result. the digital filter low-pass filters and decimates the data (data rate reduction), which yields the final data output. by adjusting the type of filtering, tradeoffs are made between resolution, data rate, and line cycle rejection. the digital filter has two operating modes: sin (x) / x (sinc) mode and finite impulse response (fir) mode (see the block diagram of figure 19 ). the sinc mode provides data rates of 2.5 sps through 40000 sps with selectable filter order of sinc1 through sinc5. the fir filter provides single-cycle settled conversions and simultaneous rejection of 50-hz and 60-hz signal interference frequencies with data rates of 2.5 sps through 20 sps. refp1/gpio0 gpio_con[3:0] bits 7:4 of mode2 (register address = 04h) gpio_dir[3:0] bits 3:0 of mode2 (register address = 04h) gpio_dat[3:0] bits 3:0 of mode3 (register address = 05h) refn1/gpio1 gpio2 gpio3 gpio[0] gpio[1] gpio[2] gpio[3] + avdd/2 agnd avdd write data read data mux read select 1 0 0 = no connect (default) 1 = connect 0 = output (default) 1 = input 0 = v gpiox is low (default) 1 = v gpiox is high gpio 1 of 4 advance information
28 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 19. digital filter block diagram 8.3.10.1 sinc filter mode the sinc filter consists of two stages: a variable-decimation sinc5 filter followed by a variable-decimation, variable-order sinc filter. the first stage sinc5 filter averages and down-samples the modulator data (f clk / 8) to produce 40000, 25600, 19200 and 14400 sps by using decimation ratios of 32, 36, 48, and 64, respectively. these data outputs bypass the second filter stage and as a result have response characteristics of the first-stage sinc5 filter. the second stage receives the first stage output data at 14400 sps and filters/decimates the data to yield data rates of 7200 sps to 2.5 sps. the second stage is a programmable order sinc filter. the data rate is programmed by the dr[4:0] bits of register mode0. the filter mode is programmed by the filter[2:0] bits of register mode0 (see figure 40 ). 8.3.10.1.1 sinc filter frequency response the digital filter reduces noise present in the signal and noise from within the adc. adjusting the filter by changing the data rate and filter order changes the filter bandwidth. through these changes, tradeoffs are made among the filter attributes (noise, bandwidth and conversion latency). as shown in figure 20 and figure 21 , the first-stage sinc5 filter has frequency response nulls occurring at n x f data = where n = 1, 2, 3 and so on. at the null frequencies, the filter has zero gain. figure 20. sinc frequency response (19200 sps) figure 21. sinc frequency response (14400 sps) the second stage superimposes additional nulls to the frequency response with the nulls that are produced by the first stage. the first of the superimposed nulls occur at the output data rate, and by nulls occurring at multiples of the data rate. frequency (khz) amplitude (db) 0 10 20 30 40 50 60 70 80 90 100 110 120 -160 -140 -120 -100 -80 -60 -40 -20 0 d002 frequency (khz) amplitude (db) 0 10 20 30 40 50 60 70 80 90 100 110 120 -160 -140 -120 -100 -80 -60 -40 -20 0 d001d001 sinc 5 filter sinc n filter modulator fir averager fir filter section filter mux sinc filter section to offset/gain calibration 40000 sps to 14400 sps 7200 sps to 2.5 sps 20 sps 10 sps 5 sps 2.5 sps f clk / 8 ( = data rate reduction) advance information
29 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 22 shows the frequency response of the combined filter stages at 2400 sps. this data rate has five equally-spaced nulls residing between the larger nulls at 14400 hz multiples that are produced by the first stage. this frequency response is similar to that of data rates 2.5 sps to 7200 sps. figure 23 shows the frequency response nulls at 10 sps. figure 22. sinc frequency response (2400 sps) figure 23. sinc frequency response (10 sps) figure 24 and figure 25 show the frequency response of data rates 50 sps and 60 sps, respectively. the frequency response is plotted to the 50-hz, 12th harmonic (10th harmonic for 60 hz). the signal's 50-hz or 60- hz fundamental and harmonic noise are reduced by increasing the filter order of the second-stage. figure 24. sinc frequency response (50 sps) figure 25. sinc frequency response (60 sps) figure 26 and figure 27 plot the detailed frequency response of 50-sps and 60-sps data rates and show various orders of the sinc filter. the high-order sinc filter increases the frequency width of the null, which improves line cycle rejection. as shown in the plots, the best 50-hz or 60-hz rejection occurs using the sinc4 order. advance information frequency (hz) amplitude (db) 0 50 100 150 200 250 300 350 400 450 500 550 600 -160 -140 -120 -100 -80 -60 -40 -20 0 d005 sinc1 sinc2 sinc3 sinc4 frequency (hz) amplitude (db) 0 10 20 30 40 50 60 70 80 90 100 110 120 -160 -140 -120 -100 -80 -60 -40 -20 0 d004 sinc1 sinc2 sinc3 sinc4 frequency (khz) amplitude (db) 0 5 10 15 20 25 30 35 40 45 -160 -140 -120 -100 -80 -60 -40 -20 0 d003 sinc1 sinc2 sinc3 sinc4 frequency (hz) amplitude (db) 0 60 120 180 240 300 360 420 480 540 600 -160 -140 -120 -100 -80 -60 -40 -20 0 d006 sinc1 sinc2 sinc3 sinc4
30 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 26. sinc frequency response, detailed (50 sps) figure 27. sinc frequency response, detailed (60 sps) the sinc filter has an overall low-pass response that rolls off high-frequency components of the signal. the bandwidth of the filter depends on the output data rate and the order of the output data rate. the overall system bandwidth is the combined responses of the digital filter, the pga anti-alias filter, and external filters. table 5 lists the ? 3-db bandwidth of the sinc filter. be aware of the reduced signal bandwidth pertaining to the high-order sinc filters. table 5. sinc filter bandwidth -3-db bandwidth (hz) data rate (sps) sinc1 sinc2 sinc3 sinc4 sinc5 2.5 1.10 0.80 0.65 0.58 ? 5 2.23 1.60 1.33 1.15 ? 10 4.43 3.20 2.62 2.28 ? 16.6 7.38 5.33 4.37 3.80 ? 20 8.85 6.38 5.25 4.63 ? 50 22.1 16.0 13.1 11.4 ? 60 26.6 19.1 15.7 13.7 ? 100 44.3 31.9 26.2 22.8 ? 400 177 128 105 91.0 ? 1200 525 381 314 273 ? 2400 1015 751 623 544 ? 4800 1798 1421 1214 1077 ? 7200 2310 1972 1750 1590 ? 14400 ? ? ? ? 2940 19200 ? ? ? ? 3920 25600 ? ? ? ? 5227 40000 ? ? ? ? 8167 8.3.10.2 fir filter the finite impulse response (fir) filter is a coefficient based filter that provides an overall low-pass filter function. the filter provides simultaneous rejection of 50-hz and 60-hz line cycle frequencies and harmonics at data rates of 2.5, 5, 10 and 20 sps. the conversion latency of the fir filter is a single cycle. (see table 8 for latency of all filter settings). as shown in figure 19 , the fir filter section receives data from the second-stage sinc filter at 600 hz. the fir filter section decimates by 30 to yield the output data rate of 20 sps. a first-order variable average (sinc1) yields 10 sps, 5 sps, and 2.5 sps. as shown in figure 28 and figure 29 , the fir filter frequency response has a series of response nulls that are placed close to 50 hz and 60 hz. the response nulls repeat near the harmonics of 50 hz and 60 hz. frequency (hz) ampliude (db) 55 56 57 58 59 60 61 62 63 64 65 -160 -140 -120 -100 -80 -60 -40 -20 0 d010 sinc1 sinc2 sinc3 sinc4 frequency (hz) amplitude (db) 45 46 47 48 49 50 51 52 53 54 55 -160 -140 -120 -100 -80 -60 -40 -20 0 d009 sinc1 sinc2 sinc3 sinc4 advance information
31 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 28. fir frequency response (20 sps) figure 29. fir frequency response detail (20 sps) figure 30 shows the fir filter response at 10 sps. as a result of the variable average, new frequency nulls are superimposed to the nulls shown in figure 28 . the first of the combined response nulls occur at 10 hz. additional nulls occur at folded frequencies around multiples of 20 hz. the first of the 10 sps folded null frequencies are seen in figure 30 at 10 hz, 30 hz, 70 hz, 90 hz, and so on. figure 30. fir frequency response (10 sps) similar to the response of the sinc filter, the overall fir filter frequency has a low-pass response that rolls off high frequencies. the response is such that the fir filter limits the bandwidth of the input signal. the signal bandwidth depends on the output data rate. table 6 lists the ? 3-db filter bandwidth of the fir filter. the total system bandwidth is the combined response of the digital filter, the pga anti-alias filter, and external filters. table 6. fir filter bandwidth data rate (sps) ? 3-db bandwidth (hz) 2.5 1.2 5 2.4 10 4.7 20 13 frequency (hz) amplitude (db) 0 30 60 90 120 150 180 210 240 270 300 -160 -140 -120 -100 -80 -60 -40 -20 0 d013 frequency (hz) amplitude (db) 0 30 60 90 120 150 180 210 240 270 300 -160 -140 -120 -100 -80 -60 -40 -20 0 d011 frequency (hz) amplitude (db) 40 45 50 55 60 65 70 -160 -140 -120 -100 -80 -60 -40 -20 0 d012 advance information
32 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.10.3 50-hz and 60-hz normal mode rejection to reduce 50-hz and 60-hz noise interference, configure the conversion period to reject the noise at 50 hz and 60 hz. 50-hz and 60-hz noise rejection depends on the filter type and filter order. table 7 summarizes the 50-hz and 60-hz noise rejection versus data rate and filter type. the table values are based on 2% and 6% tolerance of noise frequency to adc clock frequency. for the sinc filter mode, 50-hz and 60-hz noise rejection is increased by increasing the order of the filter. common mode noise is also rejected at these frequencies. table 7. 50-hz and 60-hz normal mode rejection digital filter amplitude (db) data rate (sps) filter type 50 hz ( 2%) 60 hz ( 2%) 50 hz ( 6%) 60 hz ( 6%) 2.5 fir ? 113 ? 99 ? 88 ? 80 2.5 sinc1 ? 36 ? 37 ? 40 ? 37 2.5 sinc2 ? 72 ? 74 ? 80 ? 74 2.5 sinc3 ? 108 ? 111 ? 120 ? 111 2.5 sinc4 ? 144 ? 148 ? 160 ? 148 5 fir ? 111 ? 95 ? 77 ? 76 5 sinc1 ? 34 ? 34 ? 30 ? 30 5 sinc2 ? 68 ? 68 ? 60 ? 60 5 sinc3 ? 102 ? 102 ? 90 ? 90 5 sinc4 ? 136 ? 136 ? 120 ? 120 10 fir ? 111 ? 94 ? 73 ? 68 10 sinc1 ? 34 ? 34 ? 25 ? 25 10 sinc2 ? 68 ? 68 ? 50 ? 50 10 sinc3 ? 102 ? 102 ? 75 ? 75 10 sinc4 ? 136 ? 136 ? 100 ? 100 16.6 sinc1 ? 34 ? 21 ? 24 ? 21 16.6 sinc2 ? 68 ? 42 ? 48 ? 42 16.6 sinc3 ? 102 ? 63 ? 72 ? 63 16.6 sinc4 ? 136 ? 84 ? 96 ? 84 20 fir ? 95 ? 94 ? 66 ? 66 20 sinc1 ? 18 ? 34 ? 18 ? 24 20 sinc2 ? 36 ? 68 ? 36 ? 48 20 sinc3 ? 54 ? 102 ? 54 ? 72 20 sinc4 ? 72 ? 136 ? 72 ? 96 50 sinc1 ? 34 ? 15 ? 24 ? 15 50 sinc2 ? 68 ? 30 ? 48 ? 30 50 sinc3 ? 102 ? 45 ? 72 ? 45 50 sinc4 ? 136 ? 60 ? 96 ? 60 60 sinc1 ? 13 ? 34 ? 12 ? 24 60 sinc2 ? 27 ? 68 ? 24 ? 48 60 sinc3 ? 40 ? 102 ? 36 ? 72 60 sinc4 ? 53 ? 136 ? 48 ? 96 advance information
33 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.4 device functional modes 8.4.1 conversion control the start pin or the start command controls the conversions. if using commands to control conversions, keep the start pin low to avoid contention between the pin and commands. commands take affect on the 32nd falling sclk edge. see switching characteristics for details on conversion control timing. the adc has two conversion control operating modes: continuous-conversion mode and pulse-conversion mode. the continuous-conversion mode performs conversions indefinitely until the user stops the conversions. pulse- conversion mode performs one conversion and then stops. the convrt (bit 4 of the mode1 register ) programs the mode. 8.4.1.1 continuous-conversion mode this conversion mode performs continuous conversions until the user stops conversions. to start conversions, take the start pin high or send the start command. drdy is driven high when the conversion is started. drdy is driven low when the conversion data are ready. conversion data is available to read at that time. take the start pin low or send a stop command to stop conversions. when conversions are stopped, the conversion in progress runs to completion. to restart a conversion that is in progress, toggle the start pin low- then-high or send a new start command. 8.4.1.2 pulse-conversion mode in pulse-conversion mode, the adc performs one conversion when start is taken high or when the start command is sent. when the conversion completes, further conversions stop. the drdy output is driven high to indicate the conversion is in progress and is driven low when the conversion data are ready. conversion data is read at that time. to restart a conversion in progress, toggle the start pin low-then-high or send a new start command. driving start low or sending the stop command does not interrupt the current conversion. 8.4.1.3 conversion latency the digital filter averages data from the modulator to produce the conversion result. the individual stages of the digital filter must have settled data to provide fully-settled output data. the order and the decimation ratio of the digital filter determines the amount of data averaged which affects the latency of the conversion data. the fir and sinc1 filter modes are zero latency because the adc provides the conversion result in one conversion cycle. latency time is an important consideration for data throughput in multiplexed applications. table 8 lists the conversion latency values of the adc. conversion latency is defined as the time from the start of the first conversion by taking the start pin high or sending the start command to when the conversion data is ready. the adc is designed to provide fully settled data under this condition. the conversion latency values listed in table 8 include the programmable start-conversion delay = 50 us before the digital filter starts but does include overhead time for final data processing. after the first conversion completes in continuous conversion mode, the period of the next conversions are equal to 1 / f data . the first conversion latency in chop and ac- excitation modes are twice the values listed in table 8 . the period of the next conversions are equal to the values listed in table 8 . advance information
34 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated device functional modes (continued) (1) chop mode off, conversion-start time delay = 50 s (delay[3:0] = 0001) table 8. conversion latency data rate (sps) conversion latency (t (stdr) (1) (ms) sinc1 sinc2 sinc3 sinc4 sinc5 fir 2.5 400.4 800.4 1,200 1,600 ? 402.2 5 200.4 400.4 600.4 800.4 ? 202.2 10 100.4 200.4 300.4 400.4 ? 102.2 16.6 60.35 120.4 180.4 240.4 ? ? 20 50.35 100.4 150.4 200.4 ? 52.22 50 20.35 40.42 60.42 80.42 ? ? 60 17.02 33.76 50.42 67.09 ? ? 100 10.35 20.42 30.42 40.42 ? ? 400 2.855 5.424 7.924 10.42 ? ? 1200 1.188 2.091 2.924 3.758 ? ? 2400 0.771 1.258 1.674 2.091 ? ? 4800 0.563 0.8409 1.049 1.258 ? ? 7200 0.494 0.702 0.841 0.980 ? ? 14400 ? ? ? ? 0.424 ? 19200 ? ? ? ? 0.337 ? 25600 ? ? ? ? 0.271 ? 40000 ? ? ? ? 0.179 ? if the input signal changes during the conversion phase, the conversion data are a mix of old and new data, as shown in figure 31 . after an input change, the number conversion periods required to provide fully-settled output data are calculated by dividing conversion latency by the nominal period plus one conversion period. in chop mode and ac-excitation modes, use twice the latency values. figure 31. input change during conversions 8.4.1.4 start-conversion delay at the start of a conversion, the adc provides a programmable delay to allow for pga settling or to provide delay for input and configuration changes. the default value is 50 s. 50 s provides settling time for the pga anti-aliasing filter. use additional delay time as needed to provide settling time of external components. the latency values listed in table 8 are with start-conversion delay value = 0 s. as an alternative to this parameter, delay the start of conversion after input and configuration changes. start-conversion delay is an important consideration when operating in ac-excitation mode. in this mode, the signal and reference inputs are reversed for each conversion, and as a result, this parameter allows for settling of the pga anti-alias filter and external filter components. as a general guideline, set the delay time to approximately 15 times the time constant of the signal and reference filters. drdy pin v in = v ainp - v ainn old v in new v in old data mix of old data and new data fully settled new data advance information
35 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.4.2 chop mode the pga and modulator are chopper-stabilized at high frequency to reduce offset voltage, offset voltage drift and 1/f noise. these artifacts are modulated to high frequency and removed by the digital filter. although chop reduces offset to very low levels, an optional, lower speed chop mode virtually removes all traces of offset errors. in this mode, the adc alternates the polarity of consecutive conversions by reversing the input signal. the adc subtracts the results of two, alternate-phase conversions to yield the final conversion data. the results of subtraction removes the offset. be aware that chop mode is available only for the ain0 and ain1 inputs. see figure 32 for the chop mode block diagram. figure 32. chop mode v ofs models the internal offset voltage. chop operation is as follows: internal conversion c1 : ain1 ? ain0 + v ofs (first output withheld) internal conversion c2 : ain0 ? ain1 + v ofs output 1 = (c1 ? c2) / 2 = ain1 ? ain0 internal conversion c3: ain1 ? ain0 + v ofs output 2 = (c3 ? c2) / 2 = ain1 ? ain0 internal conversion c4: ain0 ? ain1 + v ofs output 3 = (c3 ? c4) / 2 = ain1 ? ain0 the sequence repeats for all conversions. be aware that chop mode changes the normal data rate. the order of the sinc filter determines the new data rate. as table 8 shows, the new data rate is equal to 1 / latency and the first conversion latency is 2 latency. the consequence averaging two data readings in chop reduces noise by 2. divide the noise data in and by 1.4 for the new noise performance data in chop mode. the null frequency(s) of the digital filter response do not change in chop mode. new null frequencies are appear at multiples of f data / 2. v ofs adc pga adc digital filter + - chop control conversion output mux chop switch chop[1:0] bits 6:5 of mode1 (register address = 03h) 00: normal mode 01: chop mode 10: 2-wire ac excitation mode 11: 4-wire ac excitation mode ain0 ain1 offset cal full-scale cal advance information
36 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.4.3 ac-excitation mode there are several methods to provide the excitation supply to a resistive bridge: voltage or current, and dc or ac. ac method can be a sine wave or switched dc voltage or current. constant dc voltage and is the most common technique. ac excitation in this context refers to reversing the polarity of a dc excitation voltage by the use of external switching components. similar in operation to chop mode, the result of voltage reversal removes offset voltage from the bridge, including residual offset voltage of the adc itself. the ads125h02 provides the signals to drive the external components to reverse the bridge voltage. the timing of the drive signals is synchronized to the adc conversion phase. during one conversion phase, the voltage polarity is positive. on the alternate conversion phases the voltage polarity is negative. the adc compensates the negative polarity by reversing the internal reference voltage. the adc subtracts the data corresponding to the positive and negative phases to mathematically remove offset voltage from the input. the adc output drive signals are non-overlapping to avoid bridge commutation that otherwise can occur during voltage reversal. the ac excitation switching rate is the same as the conversion latency values listed in table 8 . this switch rate avoids unnecessary fast switching. see figure 6 for output drive timing. table 9 shows the ac-excitation drive signals and the associated gpio pins. program the ac-excitation mode using the chop[1:0] bits in the mode1 register . ac excitation is programmed for two-wire or four-wire operation. for two-wire operation, the adc provides two drive signals. if required, use two external inverters to derive four signals to drive discrete transistors. the gpio drive levels are referred to the 5-v analog supply. be aware that ac-excitation mode changes the normal data rate. see chop mode for details of the new data rate. see for operational details. table 9. ac-excitation drive pins device pin gpio 2-wire mode (chop[1:0] = 10) 4-wire mode (chop[1:0] = 11) refp1/gpio0 gpio[0] acx1 acx1 refn1/gpio1 gpio[1] acx2 acx2 gpio2 gpio[2] acx1 gpio3 gpio[3] acx2 8.4.4 clock mode operate the adc with an external clock or with the internal oscillator. for external clock operation, apply the clock signal to clkin. the adc detects the presence of the external clock and selects the clock automatically. the frequency of the external clock depends on the data rate used. see table 10 . be sure the external clock is free of overshoot and glitches. a source-termination resistor placed at the clock buffer often helps reduce overshoot. for internal clock operation, connect clkin to dgnd. be aware of the accuracy of the internal oscillator as shown in electrical characteristics . the internal oscillator begins operating immediately at device power-on. read the clock bit in the status0 register to verify the clock mode. table 10. external clock vs data rate data rate clock frequency 2.5 to 25600 sps 7.3728 mhz 40000 sps 10.24 mhz 8.4.5 reset the adc is reset in three ways: 1) power-on reset 2) reset pin 3) reset command at reset, the serial interface, conversion-control logic, digital filter and register map values are reset. the reset bit of the status0 register is set to indicate reset occurs. clear the bit to detect the next device reset. if the start pin is high after reset, the adc begins conversions. advance information
37 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.4.5.1 power-on reset at power-on, the adc is reset and 2 16 f clk cycles later is ready for communication after all the supply voltages cross the respective reset voltage thresholds. until this time, drdy is held low . drdy is then driven high to indicate when adc communication begins. the conversion cycle starts 512 / f clk cycle after drdy asserts high. figure 4 shows the power-on reset behavior. 8.4.5.2 reset by pin reset the adc by taking the reset pin low for a minimum four f clk cycles, and then return the pin high. after reset, the conversion starts 512 / f clk cycles later. see figure 5 for reset pin timing. 8.4.5.3 reset by command reset the adc through the serial interface by the reset command. toggle cs1 high-to-low first, to reset the serial interface before sending the command. after reset, the conversion starts 512 / f clk cycles later. see figure 5 for reset command timing. 8.4.6 calibration the adc incorporates calibration registers and associated commands to calibrate offset and full-scale errors. calibrate the adc by using calibration commands, or calibrate by writing to the calibration registers directly (user calibration). to calibrate by command, send the offset or full-scale calibration commands. to user calibrate, write to the calibration registers with values based on collecting conversion data. perform offset calibration before full- scale calibration. 8.4.6.1 offset and full-scale calibration use the offset and full-scale (gain) registers to correct offset or full-scale errors, respectively. as shown in figure 33 , the offset calibration register is subtracted from the output data before multiplication by the full-scale register, which is divided by 400000h. after the calibration operation, the final value of the output data is clipped to 24 bits. figure 33. calibration block diagram equation 5 shows the internal calibration. final output data = (pre data ? ofcal[2:0]) fscal[2:0] / 400000h (5) 8.4.6.1.1 offset calibration registers the offset calibration word is 24 bits, consisting of three 8-bit registers, as listed in table 11 . the offset value is subtracted from the conversion result. the offset value is in two's-complement format with a maximum positive value equal to 7fffffh and a maximum negative value equal to 800000h. a register value equal to 000000h has no offset correction. although the calibration registers provide a wide range of offset values, the input signal cannot exceed 106% of the precalibrated range. otherwise, the adc is overranged. table 12 lists example values of the offset register. + ofcal[2:0] registers (register addresses = 07h, 08h, 09h) v ainp 1/400000h fscal[2:0] registers (register addresses = 0ah, 0bh, 0ch) - digital filter adc adc output data clipped to 24 bits final output v ainn advance information
38 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated table 11. offset calibration registers register byte order address bit order ofcal0 lsb 07h b7 b6 b5 b4 b3 b2 b1 b0 (lsb) ofcal1 mid 08h b15 b14 b13 b12 b11 b10 b9 b8 ofcal2 msb 09h b23 (msb) b22 b21 b20 b19 b18 b17 b16 table 12. offset calibration register values ofcal[2:0] register value offset calibrated output value 000001h ffffffh 000000h 000000h ffffffh 000001h 8.4.6.1.2 full-scale calibration registers the full-scale calibration word is 24 bits consisting of three 8-bit registers, as listed in table 13 . the full-scale calibration value is straight binary and normalized to a unity-gain at a value of 400000h. table 14 lists register values for selected gain factors. gain errors greater than unity are corrected by full-scale values less than 400000h. although the calibration registers provide a wide range of possible values, the input signal must not exceed 106% of the precalibrated input range. otherwise, the adc is overranged. table 13. full-scale calibration registers register byte order address bit order fscal0 lsb 0ah b7 b6 b5 b4 b3 b2 b1 b0 (lsb) fscal1 mid 0bh b15 b14 b13 b12 b11 b10 b9 b8 fscal2 msb 0ch b23 (msb) b22 b21 b20 b19 b18 b17 b16 table 14. full-scale calibration register values fscal[2:0] register value gain factor 433333h 1.05 400000h 1 3ccccch 0.95 8.4.6.2 offset calibration (ofscal) the offset calibration command corrects offset errors. to calibrate offset errors, short the inputs to the adc or short the inputs to the system. when the command is sent, the adc averages 16 conversion results to reduce conversion noise to improve calibration accuracy. when calibration is complete, the adc performs one conversion using the new calibration value. the new calibration value is written to the offset calibration register. 8.4.6.3 full-scale calibration (gancal) the full-scale calibration command corrects gain errors. to calibrate, apply a positive calibration voltage to the adc, wait for the signal to settle, and then send the command. the adc averages 16 conversion results to reduce conversion noise to improve calibration accuracy. the adc computes the full-scale calibration value so that the applied calibration voltage is scaled to equal positive full scale output code. the computed result is written to the calibration register. the adc performs one new conversion using the new calibration value. advance information
39 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) nominal clock frequency. chop and ac-excitation modes are disabled. 8.4.6.4 calibration command procedure use the following calibration procedure using the calibration commands. the register-lock mode must be unlock prior to using the calibration commands. when calibrating at power-on, make sure the reference voltage has stabilized. perform offset calibration operation prior to full-scale calibration. 1. select the desired input channel, gain, reference mode and related adc configurations as required. 2. apply the appropriate calibration signal (zero or full-scale) to the system inputs. 3. take the start pin high or send the start command to start conversions. drdy is driven high. 4. before the first conversion completes, send the appropriate calibration command. keep cs1 low. otherwise, the command is cancelled. do not send other commands during the calibration period. 5. the calibration time depends on the data rate and digital filter mode. see table 15 . drdy is driven low when calibration is complete. as a result, offset or full-scale calibration registers are updated with new values. new conversion data is available immediately using the new calibration value. table 15. calibration time (ms) data rate (sps) filter mode (1) sinc1 sinc2 sinc3 sinc4 sinc5 fir 2.5 6801 7601 8401 9201 ? 6805 5 3401 3801 4201 4601 ? 3405 10 1701 1901 2101 2300 ? 1705 16.6 1021 1141 1261 1381 ? ? 20 850.7 951 1051 1151 ? 854.5 50 340.9 380.9 421 460.9 ? ? 60 284.1 317.7 350.9 384.4 ? ? 100 170.8 190.9 210.9 230.8 ? ? 400 43.27 48.43 53.42 58.41 ? ? 1200 14.93 16.72 18.4 20.07 ? ? 2400 7.845 8.816 9.643 10.48 ? ? 4800 4.302 4.858 5.276 5.692 ? ? 7200 3.123 3.534 3.815 4.095 ? ? 14400 ? ? ? ? 1.941 ? 19200 ? ? ? ? 1.49 ? 25600 ? ? ? ? 1.133 ? 40000 ? ? ? ? 0.738 ? 8.4.6.5 user calibration procedure to user calibrate, apply the calibration voltage, acquire conversion data, and compute the calibration value. write the computed value to the corresponding calibration registers. before starting calibration, preset the offset and full-scale registers to 000000h and 400000h, respectively. to offset calibrate, short the inputs to the system and average n number of the conversion data. averaging conversion data reduces noise to increase calibration accuracy. write the average value of the conversion data to the offset registers. to gain calibrate using a full-scale calibration signal, temporarily reduce the full scale register 95% to avoid output clipped codes (set fscal[2:0] to 3ccccch). acquire n number of conversions and average the conversions to increase calibration accuracy. compute the full-scale calibration value as shown in equation 6 : full-scale calibration value = (expected code / actual code 400000h where ? expected code = 799998h using full-scale calibration signal and 95% precalibration scale factor (6) advance information
40 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.5 programming 8.5.1 serial interface the spi-compatible serial interface reads conversion data, configuration of registers, and control of the adc. the crc is used to validate error-free transmission of input and output data. the serial interface consists of the following control signals: cs1, cs2, sclk, din, and dout / drdy. most microcontroller spi peripherals can operate with the adc. the interface operates in spi mode 1, where cpol = 0 and cpha = 1. in spi mode 1, sclk idles low and data are updated or changed on sclk rising edges; data are latched or read on sclk falling edges. timing details of the spi protocol are found in figure 1 and figure 2 . 8.5.1.1 chip select ( cs1 and cs2) cs1 and cs2 are active-low inputs that enable the device for communication. the device has two serial interfaces, one for the pga and one for the adc. the interfaces are selected (active) by asserting the individual chip selects low ( cs1 or cs2). cs1 is used to access the device adc registers, conversion data and to send control commands. cs2 is used to access the device pga registers. the device is designed such that operationally, cs1 and cs2 can be combined together to access both adc or pga registers. however, when the device is used in environments where high noise levels are present, control cs2 independently from cs1 when accessing the pga registers. that is, assert cs1 separately low when accessing the adc registers and assert cs2 separately low when accessing pga registers. see figure 34 for the chip select control options. figure 34. chip select control options when controlling chip select in either combined or individual control modes, use cs1 to access conversion data and for adc control commands. chip select must be low during the entire data transaction. when chip select is taken high, the serial interfaces reset, sclk activity is ignored (blocking applicable commands), and if both cs1 and cs2 are high, dout/ drdy enters the high-impedance state. drive both chip selects high between command operations. the data ready output ( drdy) remains active independent of the state of chip select. 8.5.1.2 serial clock (sclk) sclk is an input that clocks data into and out of the adc. output data is updated on the rising edge of sclk and input data latches on the falling edge of sclk. return sclk low after the data operation is completed. sclk is a schmidt-triggered input designed to improve noise immunity. even though sclk is noise resistant, keep sclk noise-free as possible to avoid unintentional sclk transitions. avoid ringing and overshoot on the sclk input. use a series termination resistor at the sclk drive pin to reduce ringing. 8.5.1.3 data input (din) din is the adc serial data input. din inputs commands and register data to the adc. input data latches on the falling edge of sclk. 8.5.1.4 data output/data ready (dout/ drdy) dout/ drdy pin is a dual-function output pin. the two functions are data output and conversion-data ready. the functionality changes depending on whether there is a read data operation in progress. during a read data operation, the function of the pin is data output. after the read operation is completed, the function of the pin returns to conversion-data ready. data is updated on the sclk rising edge, therefore the user latches the data on the falling edge. be aware that cs1 must be low for dout/ drdy to provide the data ready function. when both chip selects are high, dout/ drdy enters the high-impedance mode (tri-state). advance information cs1 cs2 ads125h0x controller i/o cs1 cs2 ads125h0x controller i/o i/o
41 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated programming (continued) 8.5.2 data ready ( drdy) drdy asserts low to indicate that new conversion data are ready for readback. the operation of drdy depends on the mode (continuous or pulse) and whether or not the conversion data are retrieved. 8.5.2.1 drdy in continuous-conversion mode in continuous-conversion mode, drdy is driven high when conversions are started and is driven low when conversion data are ready. during data readback, drdy returns high, which signals completion of the read operation. if the conversion data are not read, drdy pulses high 16 f clk cycles prior to the next falling edge. to read back the current (old) conversion data before the next conversion completes, send the read data command 16 f clk cycles prior to the next drdy falling edge. if the readback command is sent less than 16 f clk cycles prior to the drdy falling edge, either old or new conversion data is provided. whether old or new data provided for readback depends on the timing of the command. in the case that old data are provided, the assertion of drdy corresponding to the new data is delayed until after the read data operation has completed. in this case, the drdy bit of the status0 byte is cleared to indicate the old data has been read. in the case that new conversion data are provided, drdy transitions low with no delay. in this case, the drdy bit of the status0 byte is set to 1 to indicate new data is read. to ensure readback of new conversion data, wait until drdy asserts low before starting the data read operation. 8.5.2.2 drdy in pulse-conversion mode drdy is driven high at conversion start and is driven low when the conversion data are ready. drdy remains low until a new conversion is started. figure 35 shows drdy operation with and without data retrieval in two conversion modes. figure 35. drdy operation 8.5.2.3 data ready by software polling software polling of when data is ready is an option to replace hardware polling of drdy. to software poll, read the status0 byte and poll the drdy bit. in order to not miss conversion data when in free-running operation, poll the bit at least as often as the period of the data rate. if the drdy bit is set, then conversion data is new since the last data read operation. if the drdy bit is clear, conversion data is not new since the last data read operation. in this case, the previous conversion data are returned. advance information (continuous-conversion mode) start (continuous-conversion mode) (pulse-conversion mode) command start start stop drdy - with data retrieval drdy w/o data retrieval drdy w or w/o data retreival stop
42 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated programming (continued) (1) ideal (calibrated) output code 8.5.3 conversion data conversion data are is read by the rdata command. to read data, take cs1 low and issue the read data command. the conversion data field consists of an optional status0 byte, three data bytes, and the crc byte. the crc byte is computed over the combination of status0 byte and conversion data bytes. see rdata command for details to read conversion data. 8.5.3.1 main status byte (status0) the status byte contains information on the operating state of the adc. the status0 byte is optionally included with the conversion data by enabling the statenb bit of the mode3 register . read the status0 register directly to read status information without the need to read conversion data with the optional embedded status information. 8.5.3.2 conversion data format the conversion data are 24 bits, in two's-complement format to represent positive and negative values. the data begins with the most significant bit (sign bit) first. the data are scaled so that v in = 0 v results in an uncalibrated code value of 000000h, positive full scale input is equal to an uncalibrated value of 7fffffh and negative full scale input is equal to an uncalibrated code value of 800000h; see table 16 for the code values. the data are clipped to 7fffffh and 800000h during positive and negative signal overdrive, respectively. table 16. adc conversion data codes description input signal (v) 24-bit conversion data (1) positive full scale v ref / gain (2 23 ? 1) / 2 23 7fffffh 1 lsb v ref / (gain 2 23 ) 000001h zero scale 0 000000h ? 1 lsb ? v ref / (gain 2 23 ) ffffffh negative full scale ? v ref / gain 800000h advance information
43 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.5.4 crc cyclic redundancy check (crc) is an error detection byte value that detects communication errors to and from the host and adc. crc is the division remainder of the payload data by the prescribed crc polynomial. the payload data is 1, 2, 3 or 4 bytes depending on the data transfer operation. the host computes the crc over the two required command bytes and appends the crc to the command string (3rd byte). a 4th, zero-value byte completes the command field to the adc. the adc performs the crc calculation and compares the result to the crc transmitted by the host. if the host and adc crc values match, the command executes and the adc responds by transmitting the valid crc during the 4th byte of the command. if the operation is data read, the adc responds with a second crc that is computed for the requested data byte payload. the response data payload is 1, 3, or 4 bytes depending on the type of operation. if the host and adc crc values do not match, the command does not execute and the adc responds with an inverted crc value, calculated over the received command bytes. the inverted crc is intended to signal the host of the failed operation. the host terminates transmission of further bytes to stop the command operation. the crc1err bit is set in the status0 register when a error pertaining to adc registers occur. stat12 and crc2err flags are set when an error pertaining to pga registers occur. the adc is ready to accept the next command after all required bytes are transmitted when no crc error occurs, or after a crc error occurs when terminated at the end of the 4th command byte. the crc data byte is the 8-bit remainder of the bitwise exclusive-or (xor) of the argument by a crc polynomial. the crc polynomial is based on the crc-8-atm (hec) polynomial: x 8 + x 2 + x + 1. the nine binary polynomial coefficients are: 100000111. the following is a general procedure to compute the crc value: 1. left shift the concatenated one, two, three, or four byte argument (if required) to create a new 40-bit data value (the starting data value). the shifted data is padded with ones to the right of the argument. 2. align the msb of the crc polynomial (100000111) to the left-most, logic-one value of the data. 3. perform an xor operation on the data value with the aligned crc polynomial. the xor operation creates a new, shorter length value. the bits of the data values that are not in alignment with the crc polynomial drop down and append to the right of the new xor result. 4. when the xor result is less than 100000000b, the procedure ends, yielding the 8-bit crc value. otherwise, continue with the xor operation shown in step 2 using the current data value. the number of loop iterations depends on the value of the initial data. the following sections detail the input and output data of each command. in the descriptions that follow, these crc mnemonics apply: ? crc-2 : input crc of command bytes 1 and 2. except for wreg command, the value of byte 2 is arbitrary ? out crc-1 : output crc of one register data byte ? out crc-2: output crc of two command bytes, inverted value if input crc error detected ? out crc-3: output crc of three conversion data bytes ? out crc-4: output crc of three conversion data bytes plus status0 byte ? echo byte 1: echo of received input byte 1 ? echo byte 2: echo of received input byte 2 advance information
44 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) cs1 addresses the adc block. cs2 addresses the pga block (2) excluding the write-register command, the value of the second byte is arbitrary (any value) but is included in the crc calculation. (3) rrh = 5-bit register address. 8.5.5 commands commands are used to read conversion data, control the device, and read and write register data. see table 17 for the list of commands and the corresponding command byte sequence. only send the commands that are listed in table 17 . the column labeled block shows the corresponding adc or pga block within the device that applies to the commands. cs1 addresses the adc register block, cs2 addresses the pga register block. see chip select ( cs1 and cs2) for the description of chip select operation. the adc validates the command operation by the crc sent from the host. if a crc error occurs, the adc rejects the command. table 17. command byte summary mnemonic block (1) description byte 1 byte 2 (2) byte 3 byte 4 control commands nop adc, pga no operation 00h arbitrary crc-2 00h reset adc reset 06h arbitrary crc-2 00h start adc start conversion 08h arbitrary crc-2 00h stop adc stop conversion 0ah arbitrary crc-2 00h read data command rdata adc read conversion data 12h arbitrary crc-2 00h calibration commands ofscal adc offset calibration 16h arbitrary crc-2 00h gancal adc gain calibration 17h arbitrary crc-2 00h register commands rreg adc, pga read register data 20h + rrh (3) arbitrary crc-2 00h wreg adc, pga write register data 40h + rrh (3) register data crc-2 00h protection commands lock adc, pga register data lock f2h arbitrary crc-2 00h unlock adc, pga register data unlock f5h arbitrary crc-2 00h 8.5.5.1 general command format the adc executes the command after transmission of the 4th byte in the sequence. the value of the second command byte is arbitrary but is included in the crc calculation (two-byte crc payload). forcing chip select high before the command has completed results in termination of the command. figure 36 is an example of the register write operation by writing data to register address 02h (command opcode 42h). the host calculates crc of the two command bytes. out crc-2 byte is the output (adc calculated) crc based on the received command bytes. because the example shows access to register address = 02h which belongs to the adc register block, take cs1 low, or optionally, both cs1 and cs2 low. the first byte output from the adc is always 0ffh. the chip select input must be toggled between command operations. figure 36. register write command sequence (address = 02h) advance information cs1, cs2 1 sclk 9 17 25 dout/drdy din 42h reg data echo byte 2 out crc-2 ffh echo byte 1 crc-2 00h
45 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated the following sections detail the input and output byte sequence corresponding to each command. see the crc section for the notation used for crc. 8.5.5.2 nop command this command is no operation. use the nop command to validate the crc response byte and error detection without affecting normal operation. table 18 shows the nop command byte sequence. table 18. nop command direction byte 1 byte 2 byte 3 byte 4 din 00h arbitrary crc-2 00h dout/ drdy ffh echo byte 1 echo byte 2 out crc-2 8.5.5.3 reset command the reset command resets adc operation and resets all registers to default. see reset by command for details. table 19 lists the reset command byte sequence. table 19. reset command direction byte 1 byte 2 byte 3 byte 4 din 06h arbitrary crc-2 00h dout/ drdy ffh echo byte 1 echo byte 2 out crc-2 8.5.5.4 start command this command starts a conversions. see conversion control for details. table 20 lists the start command byte sequence. table 20. start command direction byte 1 byte 2 byte 3 byte 4 din 08h arbitrary crc-2 00h dout/ drdy ffh echo byte 1 echo byte 2 out crc-2 8.5.5.5 stop command this command is used to stop conversions. see conversion control for details. table 21 lists the stop command byte sequence. table 21. stop command direction byte 1 byte 2 byte 3 byte 4 din 0ah arbitrary crc-2 00h dout/ drdy ffh echo byte 1 echo byte 2 out crc-2 8.5.5.6 rdata command this command reads conversion data. because the data are buffered, the data can be read at any time during the conversion sequence. if data is read near the completion of the conversion phase, old or new conversion data are returned. see data ready ( drdy) for details. the response data of the adc varies in length depending on inclusion of the optional status0 byte. see conversion data format for details of the format of the conversion data. figure 37 lists the rdata command byte sequence that includes the status0 byte. advance information
46 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) optional status0 byte shown (2) out crc-4 (4-byte crc = status0 + data) if status0 byte is included in the data packet table 22. rdata command direction byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 byte 8 byte 9 din 12h arbitrary crc-2 00h 00h 00h 00h 00h 00h dout/ drdy ffh echo byte 1 echo byte 2 out crc-2 status0 (1) msb data mid data lsb data out crc-3 or out crc-4 (2) figure 37. conversion data read operation 8.5.5.7 ofscal command this command is used for offset calibration. see calibration for details. table 23 lists the ofscal command byte sequence. table 23. ofscal command direction byte 1 byte 2 byte 3 byte 4 din 16h arbitrary crc-2 00h dout/ drdy ffh echo byte 1 echo byte 2 out crc-2 8.5.5.8 gancal command this command is used for gain calibration. see calibration for details. table 24 lists the gancal command byte sequence. table 24. gancal command direction byte 1 byte 2 byte 3 byte 4 din 17h arbitrary crc-2 00h dout/ drdy ffh echo byte 1 echo byte 2 out crc-2 8.5.5.9 rreg command use the rreg command to read register data. take cs1 low to access registers within the adc register block. take cs2 low to access registers within the pga register block (see register map for the register block map). register data are read one byte at a time using the rreg command for each operation. add the register address (rrh) to the base opcode (20h) to complete the command byte (20h + rrh). table 25 lists the rreg command byte sequence. the adc responds with the register data byte, most significant bit first. data for registers addressed outside the range is 00h. out crc-2 is the output crc corresponding to the received command bytes. out crc-1 is the output crc corresponding to the single register data byte. table 25. rreg command direction byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 din 20h + rrh arbitrary crc-2 00h 00h 00h dout/ drdy ffh echo byte 1 echo byte 2 out crc-2 register data out crc-1 cs1 1 sclk 9 17 25 dout/drdy din 12h echo byte 2 out crc-2 ffh echo byte 1 arbitrary 33 status0 crc-2 00h 00h 41 49 msb data 00h 00h 00h mid data lsb data 57 65 out crc-4 00h advance information
47 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.5.5.10 wreg command use the wreg command to write register data. take cs1 low to access registers within the adc register block. take cs2 low to access registers within the pga register block (see register map for the register block map). the wreg command writes the register data one byte at a time using the wreg command for each operation. add the register address (rrh) to the base opcode (40h) to complete the command byte (40h + rrh). table 22 lists the wreg command byte sequence. writing to certain registers results in conversion restart. table 29 lists the affected registers. do not write to registers outside the address range. register-write access is enabled and disabled by the unlock and lock commands, respectively. the default mode is register unlock. see lock command . table 26. wreg command direction byte 1 byte 2 byte 3 byte 4 din 40h + rrh register data crc-2 00h dout/ drdy ffh echo byte 1 echo byte 2 out crc-2 8.5.5.11 lock command use the lock command to prevent write operations with unintended data. the adc register blocks and pga register blocks are locked and unlocked from write access by assertion of the corresponding chip select. locking the registers disables register write-access including the calibration registers. the default mode is unlock. register reads are allowed in lock mode. table 27 lists the lock command byte sequence. table 27. lock command direction byte 1 byte 2 byte 3 byte 4 din f2h arbitrary crc-2 00h dout/ drdy ffh echo byte 1 echo byte 2 out crc-2 8.5.5.12 unlock command use the unlock command to allow writing register data. the adc register blocks and pga register blocks are locked and unlocked from write access by assertion of the corresponding chip select. register unlock allows register write access including calibration registers. table 28 lists the unlock command byte sequence. table 28. unlock command direction byte 1 byte 2 byte 3 byte 4 din f5h arbitrary crc-2 00h dout/ drdy ffh echo byte 1 echo byte 2 out crc-2 advance information
48 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6 register map the register map consists of 19 single-byte registers. collectively, the registers are used to configure the adc to the desired operating mode. access the registers by using the rreg and wreg commands (register-read and register-write, respectively). register data are accessed one register byte at a time for each command operation. the register addresses are assigned to either the adc register block or to the pga register block. cs1 selects registers within the adc register block 1. cs2 selects registers within the pga register block. at power-on, the registers reset to default values, as shown in the default column of table 29 . changing the data of certain registers results in restart of conversions in progress. the adc restart column in table 29 lists these registers. table 29. register map summary (rrh) register default restart block bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h id xxh adc dev_id[3:0] rev_id1[3:0] 01h status0 01h adc lock1 crc1err 0 stat12 refalm drdy clock reset 02h mode0 24h yes adc dr[4:0] filter[2:0] 03h mode1 01h yes adc 0 chop[1:0] convrt delay[3:0] 04h mode2 00h adc gpio_con[3:0] gpio_dir[3:0] 05h mode3 00h adc 0 statenb 0 0 gpio_dat[3:0] 06h ref 05h yes adc 0 0 0 refenb rmuxp[1:0] rmuxn[1:0] 07h ofcal0 00h adc ofc[7:0] 08h ofcal1 00h adc ofc[15:8] 09h ofcal2 00h adc ofc[23:16] 0ah fscal0 00h adc fsc[7:0] 0bh fscal1 00h adc fsc[15:8] 0ch fscal2 40h adc fsc[23:16] 0dh i_mux ffh adc i_mux2[3:0] i_mux1[3:0] 0eh i_mag 00h adc i_mag2[3:0] i_mag1[3:0] 0fh reserved 00h adc 00h 10h mode4 50h pga 0 mux[2:0] gain[3:0] 11h status1 xxh pga pga_onl pga_onh pga_opl pga_oph pga_inl pga_inh pga_ipl pga_iph 12h status2 0xh pga 0 0 lock2 crc2err rev_id2[3:0] 8.6.1 device identification (id) register (address = 00h) [reset = xxh] id is shown in figure 38 and described in table 30 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset (2) reset values are dependent on the device. figure 38. id register (1) (2) 7 6 5 4 3 2 1 0 dev_id[3:0] rev_id1[3:0] r-xh r-xh table 30. id register field descriptions bit field type reset description 7:4 dev_id[3:0] r xh device id 0100: ads125h01 0110: ads125h02 3:0 rev_id1[3:0] r xh revision id1 there are two revision id fields: rev_id1 and rev_id2. the revision ids can change without notification advance information
49 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.2 main status (status0) register (address = 01h) [reset = 01h] status0 is shown in figure 39 and described in table 31 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset figure 39. status0 register (1) 7 6 5 4 3 2 1 0 lock1 crc1err 0 stat12 refalm drdy clock reset r-0h r/w-0h r-0h r-0h r-0h r-0h r-xh r/w-1h table 31. status0 register field descriptions bit field type reset description 7 lock1 r 0h adc register block lock1 status this bit indicates the lock status of the adc section register block. writes to the adc register block are locked by the lock command and unlocked by the unlock command. 0: adc section registers not locked (default) 1: adc section registers block locked see table 44 for the pga section of the register block status 6 crc1err r/w 0h adc register block crc1 error indicates crc1 error to commands addressing the adc block of the device. write 0 to clear the crc1 error. 0: no crc1 error to adc block of device 1: crc1 error to the adc block of the device see table 44 for the pga section crc error status 5 0 r 0h reserved always write 0. 4 stat12 r 0h stat12 error flag indicates one or more error bits are logged to the pga error registers status1 or status2. read the status1 and status2 registers to determine the source of the error. this bit clears after the errors are cleared. 0: no error 1: error logged to the status1 or status2 registers 3 refalm r 0h reference alarm this alarm is set if the reference voltage is < 0.4 v. the alarm updates at each new conversion cycle (auto-reset). 0: no reference low alarm 1: reference low alarm 2 drdy r 0h data ready indicates new conversion data. 0: conversion data not new since the last data read 1: conversion data new since the last data read 1 clock r xh clock indicates internal or external clock mode. the adc automatically selects the clock mode. 0: adc clock is internal 1: adc clock is external 0 reset r/w 1h reset indicates adc reset has occurred. clear the bit to detect the next device reset. 0: no reset 1: reset (default) advance information
50 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.3 mode 0 (mode0) register (address = 02h) [reset = 24h] mode0 is shown in figure 40 and described in table 32 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset figure 40. mode0 register (1) 7 6 5 4 3 2 1 0 dr[4:0] filter[2:0] r/w-4h r/w-4h table 32. mode0 register field descriptions bit field type reset description 7:3 dr[4:0] r/w 4h data rate select the data rate 00000: 2.5 sps 00001: 5 sps 00010: 10 sps 00011: 16. 6 sps 00100: 20 sps (default) 00101: 50 sps 00110: 60 sps 00111: 100 sps 01000: 400 sps 01001: 1200 sps 01010: 2400 sps 01011: 4800 sps 01100: 7200 sps 01101: 14400 sps 01110: 19200 sps 01111: 25600 sps 10000 - 11111: 40000 sps (f clk = 10.24 mhz) 2:0 filter[2:0] r/w 4h digital filter (see digital filter ) select the digital filter mode 000: sinc1 001: sinc2 010: sinc3 011: sinc4 100: fir (default) 101 -111: reserved advance information
51 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.4 mode 1 (mode1) register (address = 03h) [reset = 01h] mode1 is shown in figure 41 and described in table 33 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset figure 41. mode1 register (1) 7 6 5 4 3 2 1 0 0 chop[1:0] convrt delay[3:0] r/w-0h r/w-0h r/w-0h r/w-1h table 33. mode1 register field descriptions bit field type reset description 7 0 r/w 0h reserved always write 0 6:5 chop[1:0] r/w 0h chop and ac-excitation modes select the chop or ac-excitation operating modes. see chop mode and ac-excitation mode . 00: normal mode (default) 01: chop mode 10: 2-wire ac-excitation mode (ads125h02 only) 11: 4-wire ac-excitation mode (ads125h02 only) 4 convrt r/w 0h conversion mode select the adc conversion mode. see conversion control 0: continuous conversions (default) 1: pulse (one shot) conversion 3:0 delay[3:0] r/w 1h conversion start delay program the time delay at conversion start. see start- conversion delay 0000: 0 us (not for 25600 sps or 40000 sps operation) 0001: 50 s (default) 0010: 59 s 0011: 67 s 0100: 85 s 0101: 119 s 0110: 189 s 0111: 328 s 1000: 605 s 1001: 1.16 ms 1010: 2.27 ms 1011: 4.49 ms 1100: 8.93 ms 1101: 17.8 ms 1110 - 1111: reserved advance information
52 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.5 mode 2 (mode2) register (address = 04h) [reset = 00h] mode2 is shown in figure 42 and described in table 34 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset figure 42. mode2 register (1) 7 6 5 4 3 2 1 0 gpio_con[3:0] gpio_dir[3:0] r/w-0h r/w-0h (1) ads125h02 only table 34. mode2 register field descriptions (1) bit field type reset description 7 gpio_con[3] r/w 0h gpio[3] pin connection connect gpio[3] to pin gpio3 0: gpio[3] not connected to gpio3 (default) 1: gpio[3] connected to gpio3 6 gpio_con[2] r/w 0h gpio[2] pin connection connect gpio[2] to pin gpio2 0: gpio[2] not connected to gpio2 (default) 1: gpio[2] connected to gpio2 5 gpio_con[1] r/w 0h gpio[1] pin connection connect gpio[1] to pin refn1/gpio1 0: gpio[1] not connected to refn1/gpio1 (default) 1: gpio[1] connected to refn1/gpio1 4 gpio_con[0] r/w 0h gpio[0] pin connection connect gpio[0] to pin refp1/gpio0 0: gpio[0] not connected to refp1/gpio0 (default) 1: gpio[0] connected to refp1/gpio0 3 gpio_dir[3] r/w 0h gpio[3] pin direction configure gpio[3] as a gpio input or gpio output to pin gpio3 0: gpio[3] is an output (default) 1: gpio[3] is an input 2 gpio_dir[2] r/w 0h gpio[2] pin direction configure gpio[2] as a gpio input or gpio output to pin gpio2 0: gpio[2] is an output (default) 1: gpio[2] is an input 1 gpio_dir[1] r/w 0h gpio[1] pin direction configure gpio[1] as a gpio input or gpio output to pin refn1/ gpio1 0: gpio[1] is an output (default) 1: gpio[1] is an input 0 gpio_dir[0] r/w 0h gpio[0] pin direction configure gpio[0] as a gpio input or gpio output to pin refp1/gpio0 0: gpio[0] is an output (default) 1: gpio[0] is an input advance information
53 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.6 mode 3 (mode3) register (address = 05h) [reset = 00h] mode3 is shown in figure 43 and described in table 35 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset figure 43. mode3 register (1) 7 6 5 4 3 2 1 0 0 statenb 0 0 gpio_dat[3:0] r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h (1) ads125h02 only table 35. mode3 register field descriptions bit field type reset description 7 0 r/w 0h reserved always write 0h 6 statenb r/w 0h status0 byte enable enable the status0 byte for inclusion during conversion data read operation 0: exclude status0 byte during conversion data read (default) 1: include status0 byte during conversion data read 5,4 0 r/w 0h reserved always write 0h 3 gpio_dat[3] r/w 0h gpio[3] data (1) read or write the gpio data on pin gpio3 0: gpio[3] is low (default) 1: gpio[3] is high 2 gpio_dat[2] r/w 0h gpio[2] data (1) read or write the gpio data on pin gpio2 0: gpio[2] is low (default) 1: gpio[2] is high 1 gpio_dat[1] r/w 0h gpio[1] data (1) read or write the gpio data on pin refn1/gpio1 0: gpio[1] is low (default) 1: gpio[1] is high 0 gpio_dat[0] r/w 0h gpio[0] data (1) read or write the gpio data on pin refp1/gpio0 0: gpio[0] is low (default) 1: gpio[0] is high advance information
54 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.7 reference configuration (ref) register (address = 06h) [reset = 05h] ref is shown in figure 44 and described in table 36 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset figure 44. ref register (1) 7 6 5 4 3 2 1 0 0 0 0 refenb rmuxp[1:0] rmuxn[1:0] r/w-0h r/w-0h r/w-0h r/w-0h r/w-1h r/w-1h (1) ads125h02 only table 36. ref register field descriptions bit field type reset description 7:5 0 r/w 0h reserved always write 0h 4 refenb r/w 0h internal reference enable enable the internal reference 0: internal reference disabled (default) 1: internal reference enabled 3:2 rmuxp[1:0] r/w 1h reference positive input (see reference voltage ) select the positive reference input 00: internal reference positive 01: avdd (default) 10: refp0 external 11: refp1/gpio0 external (1) 1:0 rmuxn[1:0] r/w 1h reference negative input (see reference voltage ) select the negative reference input 00: internal reference negative 01: agnd (default) 10: refn0 external 11: refn1/gpio1 external (1) advance information
55 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.8 offset calibration (ofcalx) registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h] ofcalx is shown in figure 45 and described in table 37 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset figure 45. ofcal0, ofcal1, ofcal2 registers (1) 7 6 5 4 3 2 1 0 ofc[7:0] r/w-00h 15 14 13 12 11 10 9 8 ofc[15:8] r/w-00h 23 22 21 20 19 18 17 16 ofc[23:16] r/w-00h table 37. ofcal0, ofcal1, ofcal2 registers field description bit field type reset description 23:0 ofc[23:0] r/w 000000h offset calibration these three registers are the 24-bit offset calibration word. the offset calibration is in two's-complement data format. the offset value is subtracted from the conversion result before the full- scale operation. 8.6.9 full-scale calibration (fscalx) registers (address = 0ah, 0bh, 0ch) [reset = 00h, 00h, 40h] fscalx is shown in figure 46 and described in table 38 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset figure 46. fscal0, fscal1, fscal2 registers (1) 7 6 5 4 3 2 1 0 fscal[7:0] r/w-00h 15 14 13 12 11 10 9 8 fscal[15:8] r/w-00h 23 22 21 20 19 18 17 16 fscal[23:16] r/w-40h table 38. fscal0, fscal1, fscal2 registers field description bit field type reset description 23:0 fscal[23:0] r/w 400000h full-scale calibration these three registers are the 24-bit full scale calibration word. the full-scale calibration is in straight binary data format. the full-scale value is divided by 400000h and multiplied with the conversion data. the scaling operation occurs after the offset operation. advance information
56 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.10 current source multiplexer (i_mux) register (address = 0dh) [reset = ffh] i_mux is shown in figure 47 and described in table 39 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset figure 47. i_mux register (1) 7 6 5 4 3 2 1 0 i_mux2[3:0] i_mux1[3:0] r/w-fh r/w-fh (1) ads125h02 only table 39. i_mux register field descriptions (1) bit field type reset description 7:4 i_mux2[3:0] r/w fh current source 2 output multiplexer select idac2 pin connection 0000 - 0111: no connection 1000: connect current source 2 to pin idac1 1001: connect current source 2 to pin idac2 1010 -1111: no connection (default = 1111) 3:0 i_mux1[3:0] r/w fh current source 1 output multiplexer select idac1 pin connection 0000 - 0111: no connection 1000: connect current 1 to pin idac1 1001: connect current 1 to pin idac2 1010 - 1111: no connection (default = 1111) 8.6.11 current source magnitude (i_mag) register (address = 0eh) [reset = 00h] i_mag is shown in figure 48 and described in table 40 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset figure 48. i_mag register (1) 7 6 5 4 3 2 1 0 i_mag2[3:0] i_mag1[3:0] r/w-0h r/w-0h advance information
57 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) ads125h02 only table 40. i_mag register field descriptions (1) bit field type reset description 7:4 i_mag2[3:0] r/w 0h current source 2 magnitude select current source 2 magnitude 0000: off (default) 0001: 50 a 0010: 100 a 0011: 250 a 0100: 500 a 0101: 750 a 0110: 1000 a 0111: 1500 a 1000: 2000 a 1001: 2500 a 1010: 3000 a 1011 - 1111: off 3:0 i_mag1[3:0] r/w 0h current source 1 magnitude select current source 1 magnitude 0000: off (default) 0001: 50 a 0010: 100 a 0011: 250 a 0100: 500 a 0101: 750 a 0110: 1000 a 0111: 1500 a 1000: 2000 a 1001: 2500 a 1010: 3000 a 1011 - 1111: off 8.6.12 reserved (reserved) register (address = 0fh) [reset = 00h] reserved is shown in figure 49 and described in table 41 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset figure 49. reserved register (1) 7 6 5 4 3 2 1 0 00h r/w-00h table 41. reserved register field descriptions bit field type reset description 7:0 0 r 0h reserved bits always write 00h advance information
58 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.13 mode4 (mode4) register (address = 10h) [reset = 50h] mode4 is shown in figure 50 and described in table 42 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset figure 50. mode4 register (1) 7 6 5 4 3 2 1 0 0 mux[2:0] gain[3:0] r/w-0h r/w-5h r/w-0h table 42. mode4 register field descriptions bit field type reset description 7 0 r 0h reserved always write 0h 6:4 mux[2:0] r/w 5h input multiplexer input multiplexer control 000: ain1 ? ain0 001: ain0 ? ain1 (reserved for use with final silicon) 010: ain1 ? aincom 011: ain0 ? aincom 100: hv supply readback (hv_avdd ? hv_avss) / 36 101: internal short to v com (hv_avdd + hv_avss) / 2 (default) 110: temperature sensor reading 111: reserved 3:0 gain[3:0] r/w 0h pga gain pga gain setting 0000: 0.125 v/v (default) 0001: 0.1875 v/v 0010: 0.25 v/v 0011: 0.5 v/v 0100: 1 v/v 0101: 2 v/v 0110: 4 v/v 0111: 8 v/v 1000: 16 v/v 1001: 32 v/v 1010: 64 v/v 1011: 128 v/v 1100 - 1111: reserved advance information
59 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.14 pga alarm (status1) register (address = 11h) [reset = xxh] status1 is shown in figure 51 and described in table 43 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset figure 51. status1 register (1) 7 6 5 4 3 2 1 0 pga_onl pga_onh pga_opl pga_oph pga_inl pga_inh pga_ipl pga_iph r-xxh table 43. status1 register field descriptions bit field type reset description 7 pga_onl r xh pga output negative low alarm the bit is cleared on register read (clear-on-read) 0: no alarm 1: alarm active 6 pga_onh r xh pga output negative high alarm the bit is cleared on register read (clear-on-read) 0: no alarm 1: alarm active 5 pga_opl r xh pga output positive low alarm the bit is cleared on register read (clear-on-read) 0: no alarm 1: alarm active 4 pga_oph r xh pga output positive high alarm the bit is cleared on register read (clear-on-read) 0: no alarm 1: alarm active 3 pga_inl r xh pga input negative low alarm the bit is cleared on register read (clear-on-read) 0: no alarm 1: alarm active 2 pga_inh r xh pga input negative high alarm the bit is cleared on register read (clear-on-read) 0: no alarm 1: alarm active 1 pga_ipl r xh pga input positive low alarm the bit is cleared on register read (clear-on-read) 0: no alarm 1: alarm active 0 pga_iph r xh pga input positive high alarm the bit is cleared on register read (clear-on-read) 0: no alarm 1: alarm active advance information
60 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.6.15 status 2 (status2) register (address = 12h) [reset = 0xh] status2 is shown in figure 52 and described in table 44 . return to register map summary . (1) legend: r/w = read/write; r = read only; -n = value after reset figure 52. status2 register (1) 7 6 5 4 3 2 1 0 0 0 lock2 crc2err rev_id2[3:0] r/w-0h r/w-0h r-0h r/w-0h r/w-xh table 44. status2 register field descriptions bit field type reset description 7:6 0 r/w 0h reserved always write 0 5 lock2 r 0h pga register block lock2 status this bit indicates the lock status of the pga section of the register block. writes to the pga register block are locked by the lock command and unlocked by the unlock command. 0: pga registers not locked (default) 1: pga registers block locked see table 31 for the adc section of the register block status 4 crc2err r/w 0h crc2 error indicates a crc2 error to the pga section of the device. crc2 error is latched until cleared by the user. write 0 to clear the error. 0: no error 1: crc2 error 3:0 rev_id2[3:0] r x revision id2 revision id 2 field. the revision id1 and id2 can change without notification. advance information
61 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information 9.1.1 input range linear operation of the pga requires that the maximum and minimum input signal voltage is not exceeded. the following example shows how to verify the adc input range specification. for this example, the input signal is 10 v with 15% overrange. the negative input lead of the sensor is connected to agnd. the adc gain is 0.1875 v/v using a 2.5-v reference voltage and 15 v power supplies with 5% tolerance. the summary of conditions to verify the adc range are: ? v (ainx_max) = 11.5 v ? v (ainx_min) = ? 11.5 v ? v (aincom) = agnd ? hv_avdd = 14.25 v ? hv_avss = ? 14.25 v ? gain = 0.1875 ? v ref = 2.5 v evaluation of equation 4 , (case of gain < 1) results in: ? 11.75 v < ? 11.5 v and 11.5 v < 11.75 v the inequality is satisfied, and as a result, the absolute input voltage is within the adc input range requirement. 9.1.2 input overload observe the input overvoltage precautions as shown in the esd diodes section. if an overvoltage condition occurs on an unused channel, the overvoltage channel may crosstalk to the measurement channel. one solution is to externally clamp the inputs with low-forward voltage diodes as shown in figure 53 . the external diodes shunt the overvoltage current flow around the adc inputs. be aware of the reverse leakage current that can cause measurement errors. figure 53. optional diode clamps hv_avdd schottky diode ainx hv_avss i fault schottky diode i fault 15 v hv_avss 0.3 v > v clamp > hv_avdd + 0.3 v ads125h0x r lim -15 v 40 v zener diode advance information
62 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) 9.1.2.1 input dv/dt use an rc filter on the device inputs to limit the signal dv/dt at the adc inputs. filtering the dv/dt of the signal prevents transient turn-on the amplifier''s protection diodes. 9.1.3 unused inputs and outputs ? analog input to minimize input leakage current of the measurement channel, connect the unused input to hv_avdd. be sure to connect unused reference inputs to avdd, and do not connect to the hv power supplies. ? analog outputs refout does not require a capacitor if the internal reference is not used. otherwise, refout requires the 10- f capacitor that connects to agnd. ? digital i/o not all connections to the digital i/o are required. all unused digital inputs must be tied high or low to dvdd or dgnd, as appropriate. do not float (tri-state) the digital inputs or power supply leakage current can occur. the following is a summary of digital i/o with optional connections: ? clkin: tie clkin low to operate the adc using the internal oscillator. connect to a clock source for external clock operation. ? start: tie start low to control conversions by command. tie start high to free-run conversions. ? reset: tie reset high if desired. the adc is reset at power on and is reset by the reset command. ? drdy: the data ready function is provided by the dout/ drdy pin. this functionality is only available when cs1 is low. alternatively, data ready is determined by software polling of the drdy bit within the status0 byte. leave drdy disconnected when using either method. ? gpio program unused gpio as outputs. if gpio is programmed as inputs, the gpio must not be allowed to float or power supply leakage current may result. 9.2 typical application figure 54 shows an circuit example of a 10 v analog input plc module utilizing the ads125h02. the 10 v input signal from the field transmitter is first clamped by external esd diodes to help protect the adc inputs. the positive input signal is connected to the adc input ain1 through an rc filter to help filter rfi interference that may be picked up in noisy environments. the resistor also acts to limit input current in the event of an overvoltage or during loss of module power when the signal is present. the negative input signal is connected to input ain0, which is also connected to agnd. the adc is programmed to measure between inputs ain1 and ain0. this input configuration allows the input voltage to swing 10 v to ? 10 v above and below agnd. in this example, the high voltage adc power supply voltage is 15 v. 15 v power supply operation allows an input signal headroom of up to 12.5 v. using reference voltage = 2.5 v and gain = 0.1875, yields a nominal lull scale input range = 13.3 v, except as limited by the input signal headroom. if the internal reference is used, connect a 10- f capacitor to the refout as shown. otherwise, apply an external reference to pins refp0 and refn0. a 100-k resistor biases the differential reference voltage to 0 v in the event the reference fails. the resistor allows the adc to detect a failed or missing reference voltage condition. the excitation current sources and gpio are not used in this example and are left unconnected. the adc internal clock is activated by connecting the clkin input pin to ground. the serial interface and adc control lines are connected the host. the zener diode clamps the high-voltage supply (hv_avdd - hv_avss) to 40 v to provide protection to the adc from possible over-voltage supply conditions. advance information
63 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) figure 54. 10 v analog input plc module 9.2.1 design requirements table 45 shows the design goals of the analog input plc module. the adc's programmability allows tradeoffs of sample rate, conversion noise and conversion latency. table 46 shows the design parameters of the analog input plc module. table 45. design goals design goal value accuracy (0 c to 85 c) 0.1 % basic resolution > 0.01% sample rate > 20000 sps conversion latency < 500 us hv_avss ain1 ain0 hv_avdd 15 v ads125h02 refp0 refn0 100 k ? 10 nf capp capn 1 nf c0g 10 nf -15 v p f 40 v 0.1 p f 0.1 p f 5 k esd protection aincom 27 26 25 2 3 20 19 avdd 4 refout 6 1 32 10 v input 5 v 2.5 v reference 5 v optional agnd dgnd 16 5 dvdd p f 17 bypass p f 15 reset 7 start 8 5 v cs2 9 cs1 10 sclk 11 din 12 dout/drdy 13 drdy 14 clkin 18 to host control 47 47 47 47 idac1 24 idac2 23 refp1/gpio0 31 refn1/gpio1 30 gpio2 29 gpio3 28 0.1 p f 10 p f 10 p f nc 22 nc 21 advance information
64 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated table 46. design parameters design parameter value input signal range 10 v over range 12 v input impedance > 100 m over voltage tolerance 35 v 9.2.2 detailed design procedure a key consideration in the design of an analog input module is to evaluate the adc parameters that affect accuracy for operation over the specified temperature range. table 47 shows the key adc parameters that effect accuracy. the values shown in table 47 are after calibration at t a = 25 c. as summarized by the total accuracy calculation, the target accuracy value of 0.1% is met by the adc. be aware the maximum values of adc parameters are estimates values. contact texas instruments to obtain the final maximum values. table 47. adc accuracy parameter accuracy over 0 c to 105 c offset drift 0.001% gain drift 0.03% reference drift 0.06% total accuracy 0.091% table 1 shows the conversion noise performance data for gain = 0.1875 expressed as an input-referred noise quantity. the table shows various tradeoffs among gain, sample rate and order of the digital filter order. noise performance is optimize for a given design by considering the various parameters. in this example, the configuration of the adc that yields the lowest noise while meeting the sample rate and settling time requirement is 25600 sps, gain = 0.1875 v/v (default sinc5 filter mode). this data rate yields conversion latency value of 250 us. the input-referred noise under this adc configuration is < 100 uv rms. the adc noise yields basic resolution of 100 uv / 10 v = 0.001% the adc gain is programmed to gain = 0.1875 v/v, when used with a 2.5-v reference yields a nominal adc input range of 2.5 v / 0.1875 = 13.3 v, except in this example using 15-v power supplies, the input signal headroom is limited to 12.5 v (excluding tolerance of the 15-v power supplies). the input range satisfies the overrange design target requirement of 12 v. since the adc input is a cmos-input buffer, the input impedance is typically 1 g . advance information
65 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.3 initialization setup figure 55 is a general configuration and measurement procedure. figure 55. adc configuration and measurement procedure advance information power on /* drdy is held low at power-on until ready for communicatio n set reset high /* reset must be high for operation start high? n y /* if start pin is low, conversions are stopped configure the adc external clock? apply clock to clkin y /* adc automatically detects external clock n verify registers wait for reference voltage to settle set start pin high / send start command /* readback register data for verification /* the internal reference requires time to settle after power -on /* start or restart new adc conversion set start low / send stop command drdy pin low ? n y read data change adc settings ? n y /* read data at a rate faster than the data rate to avoid missed data /* for simplicity, stop conversions before register configuration hardware drdy? y read status0 register drdy bit asserted ? n n y drdy not pulsing drdy pulses at 20 hz drdy pin high? y n /* new data when drdy bit =1 /* write register data, crc verfication is optional
66 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 10 power supply recommendations the adc requires three analog power supplies (high-voltage hv_avdd and hv_avss, and low-voltage avdd) and one digital power supply (dvdd). the high voltage analog power supply configuration is either bipolar ( 5 v to 18 v) or unipolar (10 v up to 36 v, with hv_avss tied to agnd). the avdd power supply is 5 v. the digital supply range is 2.7 v to 5.25 v. avdd and dvdd can be tied together as long as the 5-v power supply is free from excessive noise and glitches that can affect conversion results. an internal ldo regulator powers the digital core by the dvdd power supply. dvdd is the digital i/o voltage. keep in mind that the gpio i/o are at avdd and agnd voltage potentials. voltage ripple produced by switch-mode power supplies may interfere with the adc conversion accuracy. use low-dropout regulators (ldos) at the switching regulator output to reduce power-supply ripple. due to charging the 10-uf external capacitor at the reference output pin (refout), be aware of the avdd in- rush current when the internal reference is enabled. be sure the avdd voltage transient droop does not exceed 4.5 v under this condition. 10.1 power-supply decoupling good power-supply decoupling is important in order to achieve optimum performance. power supplies must be decoupled close to the power supply. for the high voltage analog supply (hv_avdd and hv_avss), place a 1- f capacitor between the pins and place 0.1- f capacitors from each supply to the ground plane. connect 0.1- f and 10- f capacitors in parallel at avdd to the ground plane. connect a 1- f capacitor from dvdd to the ground plane. connect a 1- f capacitor from bypass to the ground plane. use a multilayer ceramic chip capacitors (mlccs) that offers low equivalent series resistance (esr) and equivalent series inductance (esl) characteristics for power-supply decoupling purposes. 10.2 analog power-supply clamp it is important to evaluate circumstances when an input signal is present with the adc, both powered and unpowered. when the input signal exceeds the power-supply voltage, it is possible to backdrive the analog power-supply voltage with the input signal through a conduction path of the internal esd diodes. backdriving the adc power supply can also occur when the power-supply is on. the backdrive fault-current path is illustrated in figure 53 . depending on how the power supply responds during a backdrive condition, it is possible to exceed the maximum rated adc supply voltage. the adc voltage must not be exceeded at all times. one solution is to clamp the analog supply to safe voltage using an external zener diode. 10.3 power-supply sequencing the power supplies can be sequenced in any order, but do not allow and analog or digital voltage inputs to exceed the respective analog or digital power-supplies without providing a limit to possible input fault currents. advance information
67 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 layout good layout practices are crucial to realize the full-performance of the adc. poor grounding can quickly degrade the noise performance. the following layout recommendations help provide the best results. 11.1 layout guidelines for best performance, dedicate an entire pcb layer to a ground plane and do not route any other signal traces on this layer. however, depending on restrictions imposed by specific end equipment, a dedicated ground plane may not be practical. if ground plane separation is necessary, make a direct connection of the planes at the adc. do not connect individual ground planes at multiple locations because this configuration creates ground loops. route digital traces away from the capp and capn pins, away from the refout pin, and away from all analog inputs and associated components in order to minimize interference. avoid long traces on dout/ drdy, because high capacitance on this pin can lead to increased adc noise levels. use a series resistor or a buffer if long traces are used. the internal reference output return shares the same pin as the agnd pin. to minimize coupling between the power supply and reference-return trace, route the traces separately; ideally, as a star connection to the agnd pin. use c0g capacitors on the analog inputs and for the capp to capn capacitor. use ceramic capacitors (for example, x7r grade) for the power supply decoupling capacitors. high-k capacitors (y5v) are not recommended. the refout pin requires a 10- f capacitor and can be either ceramic or tantalum type. place the required capacitors as close as possible to the device pins using short, direct traces. for optimum performance, use low-impedance connections on the ground-side connections of the bypass capacitors. when applying an external clock, be sure the clock is free of overshoot and glitches. a source-termination resistor placed at the clock buffer often helps reduce overshoot. glitches present on the clock input can lead to noise within the conversion data. advance information
68 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 11.2 layout example figure 56 shows an example layout of the ads125h02, requiring a minimum of three pcb layers. the example circuit is shown with bi-polar supply operation ( 15 v) and using the internal reference. in this example, the inner layer is dedicated to the ground plane and the outer layers are used for signal and power traces. if a four-layer pcb is used, dedicate the additional inner layer as the power plane. in this example, the adc is oriented in such a way to minimize crossover of the analog and digital signal traces. figure 56. pcb layout example 16 15 14 13 12 11 10 9 nc 24 23 22 21 20 19 18 17 25 26 27 28 29 30 31 32 to mcu 12 3 4 5 6 78 connect thermal pad to agnd avdd supply dvdd supply 1 nf (diff. - input pair) ads125h02 1 f (9-mil traces shown) adc clock options: option 2: connect external clock source to clkin option 1 : to enable internal oscillator, tie clkin to gnd nc hv_avdd hv_avss clkin dvdd aincom ain0 ain1 gpio3 gpio2 refn1/gpio1 refp1/gpio0 refn0 dgnd bypass drdy din sclk cs1 refp0 capp capn avdd agnd reset dout/ drdy 1 f 0.1 f 10 f (0805 shown) c0g refout 47 47 47 47 10 nf gpio cs2 start input signal 1 f idac1 idac2 current source 0.1 f 0.1 f 47 hv_avdd supply hv_avss supply external reference 10 nf 10 f (0805 shown) advance information
69 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 device and documentation support 12.1 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to order now. table 48. related links parts product folder order now technical documents tools & software support & community ads125h01 click here click here click here click here click here ads125h02 click here click here click here click here click here 12.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 12.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
70 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated www.ti.com package outline c 32x 0.30.2 3.45 0.1 32x 0.50.3 1 max (0.2) typ 0.050.00 28x 0.5 2x 3.5 2x 3.5 a 5.14.9 b 5.14.9 vqfn - 1 mm max height rhb0032e plastic quad flatpack - no lead 4223442/a 11/2016 pin 1 index area 0.08 c seating plane 1 8 17 24 9 16 32 25 (optional) pin 1 id 0.1 c a b 0.05 c exposed thermal pad 33 symm symm notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. the package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. scale 3.000 advance information
71 ads125h01 , ads125h02 www.ti.com sbas790 ? october 2018 product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated www.ti.com example board layout (1.475) 0.07 min all around 0.07 max all around 32x (0.25) 32x (0.6) ( 0.2) typ via 28x (0.5) (4.8) (4.8) (1.475) ( 3.45) (r0.05) typ vqfn - 1 mm max height rhb0032e plastic quad flatpack - no lead 4223442/a 11/2016 symm 1 8 9 16 17 24 25 32 symm land pattern example scale:18x notes: (continued) 4. this package is designed to be soldered to a thermal pad on the board. for more information, see texas instruments literature number slua271 (www.ti.com/lit/slua271). 5. vias are optional depending on application, refer to device data sheet. if any vias are implemented, refer to their locations shown on this view. it is recommended that vias under paste be filled, plugged or tented. 33 solder maskopening metal under solder mask solder mask defined metal solder maskopening non solder mask solder mask details defined (preferred) advance information
72 ads125h01 , ads125h02 sbas790 ? october 2018 www.ti.com product folder links: ads125h01 ads125h02 submit documentation feedback copyright ? 2018, texas instruments incorporated advance information www.ti.com example stencil design 32x (0.6) 32x (0.25) 28x (0.5) (4.8) (4.8) 4x ( 1.49) (0.845) (0.845) (r0.05) typ vqfn - 1 mm max height rhb0032e plastic quad flatpack - no lead 4223442/a 11/2016 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 33 symm metal typ based on 0.125 mm thick stencil solder paste example exposed pad 33: 75% printed solder coverage by area under package scale:20x symm 1 8 9 16 17 24 25 32
package option addendum www.ti.com 14-nov-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ads125h02irhbr preview vqfn rhb 32 3000 tbd call ti call ti -40 to 125 ads125h02irhbt preview vqfn rhb 32 250 tbd call ti call ti -40 to 125 PADS125H02IRHBR active vqfn rhb 32 250 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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