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| ,. analog w devices features ac characterized and specified 200k conversions per second 1mhz full power bandwidth 500khz full linear bandwidth 72db s/n+d (k grade) twos complement data format (bipolar mode) straight binary data format (unipolar mode) 10m!} input impedance 8-bit or 16-bit bus interface on-board reference and clock 10v unipolar or bipolar input range product description the ad1678 is a 12-bit monolithic analog-to-digital converter, consisting of a sample-hold amplifier (sha), a microprocessor compatible bus interface, a voltage reference and clock genera- tion circuitry. this product is fabricated on analog devices' bimos process, combining low power cmos logic with high precision, low noise bipolar circuits; laser-trimmed thin-film resistors provide high accuracy. the converter utilizes a recursive subranging algorithm which includes error correction and flash converter circuitry to achieve high speed and resolution. the adi678 is specified for ac (or "dynamic") parameters such as sin + d ratio, thd and imd. these parameters are impor- tant in signal processing applications as they indicate the ad 1678's effect on the spectral content of the input signa1.the ad1678 offers a choice of digital interface formats; the 12 data bits can be accessed by a 16-bit bus in a single read operation or by an 8-bit bus in two read operations (8+4), with right or left justification. data format is straight binary for unipolar mode and twos complement binary for bipolar mode. the input has a full-scale range of iov with a full power bandwidth of 1 mhz and a full linear bandwidth of 500khz. high input impedance (iom!1) allows direct connection to unbuffered sources without signal degradation. the adi678 operates from +5v and ::tl2v supplies and dissi- pates 600mw. a 28-pin plastic dip and a 0.6" wide ceramic dip are available. contact factory for surface-mount package options. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. 12 -bit 200ksps sampling auc 0 q'i:kf , , ' '. - ,,' ',;";', -20 a3 "c -40 i w c :;) -60 f- ::i ~'80 -3- --- -~ dc specifications (@+25c, vcc=+12v, vee=-12v, voo=+5v unless otherwise indicated) ad1678j ad1678k model min tvd max min tvd max accuracy resolution 12 i 12 differential linearity tmin to tmax (no missing codes) 12 12 unipolar zero error' :':4 :':4 bipolar zero error! :':4 :':4 unipolar gain errorl.2 :':3 :':3 bipolar gain erroru :':3 :':3 temperature drift (coefficients)3 unipolar zero :':2 (10) :':2 (10) bipolar zero :':2 (10) :':2 (10) unipolar gain :': 4 (20) :':4 (20) gain :':4 (20) :':4 analog input input ranges unipolar mode 0 +10 0 +10 bipolar mode 5 +5 5 +5 input resistance 10 10 input capacitance (fin= 100khz) 10 10 input settling time i 1 aperture delay 5 20 5 20 150 150 ---+---_..- internal reference voltage output voltage4 i 4.95 5.05 4.95 5.05 external load unipolar mode +1.5 i +1.5 i ma ) mode +0.5 +0.5 ma power supplies (t min to t maj operating voltages vee +11.4 + 12 + 12.6 i +11.4 + 12 + 12.6 i v vee -12.6 12 11.4 12.6 -12 -11.4 v vdd +4.5 +5 +5.5 +4.5 +5 +5.5 v operating current ice i 17 19 i 17 19 ma lee 24 26 24 26 ma idd 5 10 5 10 ma power consumption 600 - notes ] adjustable to zero; see figures 8 and 9. "includes internal voltage reference error. "includes internal voltage reference drift. 4 with maximum external load applied. specifications shown in boldface are tested on all devices at final electrical test. results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested. specifications subject to change without notice. obsolete dynamic performance -30 ~ w -40 c ~ -50 ::; "- ~ -60 -10 -20 -70 -80 -90 -100 0 50 100 input frequency-khz 150 200 figure 1. harmonic distortion vs. input frequency 50 '" l' c '" 40 z ;;; 70 60 30 20 10 0 50 100 input frequency-khz 150 200 figure 3. s/n&d vs. input frequency and amplitude -20 -100 -40 '" l' ~ -50 :> .... ~ -80 " -120 -140 0 10 20 30 40 50 60 frequency-khz 70 80 90 100 figure 5. imd plot for f'n = 9.08khz (fa), 9.58khz (fb) 90 80 70 ,10khz input 50khz input 100khz input 60 !ii 50 i c '" z 40 ;;; 30 20 10 -60 -45 -30 input amplitude db -15 figure 2. s/n&d vs. input amplitude (fsample=200ksps) ( 30 40 50 60 frequency-khz 70 80 90 100 figure 4. nonaveraged 2048 point fft at 200ksps, f'n =49. 902khz 80 70 - -0,5db input --- -40db input +5v +12v 60 '" ." i 0 50 i= " 0: c 40 + z ;;; 30 20 10 '~: 100 200 300 400 500 600 700 ripple frequency - khz 800 900 1000 figure 6. power supply rejection (fin = 10khz, fsample=200ksps, vripple=o.lv p-p) -4- ---~ [ funental fsam",-200 ksps fullscale=",5v ...................1... ................ - tho 3rd harmonic / ..j- - t 2nd harmonic , i i 20db input ... -60db input i -20 -40 w c -60 12 :;; " -80 -100 -120 -140 0 10 obsolete frequency domain testing the adi678 is tested dynamically using a sine wave input and a 2048 point fast fourier transform (fft) to analyze the result- ing output. coherent sampling is used, wherein the adc sam- pling frequency and the analog input frequency are related to each other by a ratio of integers. this ensures that an integral multiple of input cycles is captured, allowing direct fft pro- cessing without windowing or digital filtering which could mask some of the dynamic characteristics of the device. in addition, the frequencies are chosen to be "relatively prime" (no common factors) to maximize the number of different adc codes that are present in a sample sequence. the result, called prime coherent sampling, is a highly accurate and repeatable measure of the actual frequency domain response of the converter. nyquist frequency an implication of the nyquist sampling theorem, the "nyquist frequency" of a converter, is that input frequency which is one- half the sampling frequency of the converter. signal-to-noise and distortion (s/n+d) ratio sin + d is the ratio of the rms value of the measured input sig- nal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding de. the value for sin + d is expressed in decibels. ) total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels. for input signals or harmonics that are above the nyquist frequency, the aliased component is used. peak spurious or peak harmonic component the peak spurious or peak harmonic component is the largest spectral component excluding the input signal and de. this value is expressed in decibels relative to the measured input signal. intermodulation distortion (imd) with inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m+n), at sum and difference frequencies of mfa:tnfb, where m, n = 0, 1, 2, 3 . . . intermodulation terms are those for which m or n is not equal to zero. for example, the second order terms are (fa + fb) and (fa - fb) and the third order terms are (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb). the imd products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the dis- tortion terms. the two signals applied to the converter are of equal amplitude and the peak value of their sum is -o.sdb from full scale (9.44v p-p). the imd products are normalized to a ode input signal. bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input. -- the full-linear bandwidth is the input frequency at which the slew rate limit of the sample-hold-amplifier (sha) is reached. at this point, the full-scale fundamental has degraded by less than -o.ldb. beyond this frequency, distortion of the sampled input signal increases significantly. the adl678 has been designed to optimize input bandwidth, allowing the adi678 to undersample input signals with frequen- cies significantly above the converter's nyquist frequency. if the input signal is suitably band-limited, the spectral content of the input signal can be recovered. examples of applications in which this technique is used include direct digitization of audio- modulated if signals and doppler-shift measurements. aperture delay aperture delay is a measure of the sha's performance and is measured from the falling edge of the start convert (sc) to when the input signal is held for conversion. in synchronous mode, chip select (cs) should be low before sc to minimize aperture delay. aperture jitter aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the aid. input settling time settling time is a function of the sha's ability to track fast slewing signals. this is specified as the maximum time required in track mode after a full-scale step input to guarantee rated conversion accuracy. differential nonlinearity (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. for the adi678, this specification is 12 bits from t min to t max' which guarantees that all 4096 codes are present over temperature. unipolar zero error in unipolar mode, the first transition should occur at a level 1/2 lsb above analog ground. unipolar zero error is the devia- tion of the actual transition form that point. this error can be adjusted as discussed in the input connections and calibration section. bipolar zero error in the bipolar mode, the major carry transition (1111 1111 1111 to 0000 0000 0000 ) should occur at an analog value 1/2 lsb below analog ground. bipolar zero error is the deviation of the actual transition from that point. this error can be adjusted as discussed in the input connections and calibration section. gain error the last transition should occur at an analog value 1 1/2 lsb below the nominal full scale (9.9963 volts for a o-lov range, 4.9963 volts for a :tsv range). the gain error is the deviation of the actual level at the last transition from the ideal level with the zero error trimmed out. this error can be adjusted as shown in the input connections and calibration section. -5- obsolete timing so' ~td~ead. ! 1--: i i i t i i i i : trtck i : : ~: , i i i' ; tdd , ~ (data 1 '; i 1 h" . i tee t" t.. r- ~ :~td" ~ i i--- conversion #1 -i ~,~t"~ / : i i i ttc,~/ i ~ f--tad tr~ tsdr' \l conversio n r--\ r--- # 2 sha hold eoc' ~ ihold contents of dutput register data a (previdus} de db11-dba notes ,. if sync = low. state df ~ does not affect convert operation. if sync = high. ~ should be brought low before so to start a cdnversion. see the start cdnver- sion truth table for details. 2. eoc is a tristate output. see conversion status truth table for details figure 7. ad1678 conversion start & output enable timing (12-bit read mode) conversion control in synchronous mode (sync = high), both chip select (cs) and start convert (sc) must be brought low to start a conver- sion. cs should be low 50nsec (tb) before sc is brought low. in asynchronous mode (sync = low), a conversion is started by bringing sc low, regardless of the state of cs. in figure 7, the conversion start and output enable timing diagram illustrates the read-after-convert configuration. for the maximum throughput rate, see the applications section, figures loa, lob. before a conversion is started, end-of-convert (eoc) is high, and the sample-hold is in track mode. after a conversion is started, the sample-hold goes into hold mode and eoc goes low, signifying that a conversion is in progress. during the conversion, the sample-hold will go back into track mode and start acquiring the next sample. when the conversion is finished, eoc goes high and the result is loaded into the output register after a period of time tun. bringing oe low 20 nsec (td) after cs goes low makes the output register contents available on the output data bits (dbll-dbo). a period of time, tcn, is required after oe is brought high before the next sc instruction is issued. this is to allow internal logic states to reset and to guarantee minimum aperture jitter for the next conversion. in track mode, the sample-hold will settle to 2:0.01% (12 bits) in ifls maximum. the acquisition time does not affect the throughput rate as the adi678 goes back into track mode more than ifls before the next conversion. in multichannel systems, the input channel can be switched as soon as eoc goes low if the maximum throughput rate is needed. if sc is held low, the adi678 will convert continuously and the circuit of figure loa should be utilized. synchronous mode conversion timing (t min to t max) specification tcp convert pulse width tsd status delay tun update delay too output delay tcd conversion delay trp read pulse width 1 tba access time2 tdh data hold tbf float delay3 tad aperture delay tb sc delay td oe delay ( 1 200 fls ns 0 150 100 ns ns ns ns 100 10 ns ns 80 20 5 50 20 ns ns ns notes '12-bit read mode. 'measured from the falling edge of oe (lav) to the time at which the data lines cross 2av or1l4v. 'measured from the rising edge of oe (iav) to the time at which the output voltage changes by o.sv. start conversion truth table 0 '"t start conversion (not recommended) continuous conversion ( 0 0 0 mode x x x continuous conversion no conversion start conversion t. 0 notes i = high voltage level. 0 = low voltage level. x = don't care. t. = high to low transition. must stay low for t = tcp. synchronous mode mode conversion status truth table notes i - high voltage level. () - low voltage level. x - don', care. -6- 0 0 i x x 0 x 0 0 x 0 i not converting 0 x i high z either obsolete '\ hbe ~ ~ifs~ cs~ ---i is t:== i i--iba~ i i i i i tre +i ibf 14- i i ) -.i ifs i+- ilij:\ i i i i oe dbll-db4 ibf 14- , eocen eoc ad1678 output timing (8-bit read mode) ) output enable operation the data bits (dbll-dbo) are tristate outputs that are enabled by chip select (cs) and output enable (oe). cs should be low zons (ts) before oe is brought low. bits dbi (r/l) and dbo (hbe) are bidirectional. in iz-bit mode they are data output bits. in 8-bit mode they are inputs that define the format of the output register. in lz-bit mode (1z/8 = high), a single read operation accesses all lz output bits on dbll-dbo for interface to a 16-bit bus. in 8-bit mode (1z/8 = low), only dbll-db4 are used as out- put lines onto an 8-bit bus. the output is read in two steps, with the high byte read first, followed by the low byte. high byte enable (hbe) controls the output sequence. the lz-bit result can be right or left justified depending on the state of r/l. in unipolar mode (bipoff tied to agnd), the output coding is straight binary. in bipolar mode (bipoff tied to refout)' output coding is twos complement binary. end-of-convert (eoc) is a tristate output which is enabled by end-of-convert enable (eocen) in asynchronous mode, and by eocen and cs in synchronous mode. output enable (oe) must be toggled to update data in the out- put register. output enable timing (t m;n to t max> notes 's-bit read mode. lmeasured from the falling edge of oe (lav) to the time at which the data lines cross 2av or oav. - -'measured from the rising edge of oe (iav) to the time at which the output voltage changes by o.5v. ~~ r- dbn it 3k -= r 100pf high z to logic 1 5v + k i 100pf dbn high ztologico access time test 5v ~ 3k dbn~ i1opf logicotohigh z dbn~ 3kr j 10pf logic 1 to high z float delay test load circuits for bus timing specifications output enable truth tables 12-bit mode (12/8 = high) inputs - - (cs u oe) i t. output dbll-dbo high z enable lz-bit output 8-bit mode (12/8 = low) notes i = high voltage level. 0 = low voltage level. x = don't care. u = logical or. a = msb. i = lsb. t.. = high to low transition. must stay low for t= trp' 12-bit mode coding format (1 lsb=2.44mv) unipolar coding (straight binary) ~! c~-de 000...0 100...0 111...1 . alar coding was complement) output code -s.ooov -o.oozv 0 + z.soov +4.9964 100...0 111...1 000...0 010...0 011...1 -7- specification min max units tfs format setup 60 ns trp read pulse width i 150 ns tba access time2 100 ns tbf float delay3 0 ns toh data hold 10 ns ts oe delay 20 ns inputs outputs i unipolar i mode 0 0 i 0 t. bipolar i i t.. mode 0 0 t. 0 i t. obsolete name and function analog ground. analog signal input. bipolar offset. connect to agnd for + lov input unipolar mode and straight binary output coding. connect to ref out through sod resistor for :t5v input bipolar mode and twos complement binary output coding. see figures 8 and 9. chip select. active low. ) digital ground data bits 11 through 4. in l2-bit format (see 12/8 pin), these pins provide the upper 8 bits of data. in 8-bit format, these pins provide all 12 bits in two bytes (see r/l pin). active high. data bits 3 and 2. in l2-bit format, these pins provide data bit 3 and data bit 2. active high. in 8-bit format they are undefined and should be tied to v dd' in l2-bit format, data bit 1. active high. in l2-bit format, data bit o. active high. end-of-convert. eoc goes low when a conversion starts and goes high when the conversion is finished. in asynchronous mode, eoc is an open drain output and requires an external 3kd pull-up resistor. see eocen and sync pins for information on eoc gating. end-of-convert enable. enables eoc pin. active low. in 8-bit format, high byte enable. if low, output contains high byte. if high, output contains low byte. output enable. the falling edge of oe enables dbll-dbo in l2-bit format and dbll-db4 in 8-bit format. gated with cs. active low. reference input. + 5v input gives lov full scale range. +5v reference output. tied to ref in through sod resistor for normal operation. in 8-bit format, right/left justified. sets alignment of l2-bit result within l6-bit field. tied to v dd for right-justified output and tied to dgnd for left-justified output. start convert. active low. see sync pin for gating. sync control. if tied to vdd (synchronous mode), sc, eoc and eocen are gated by cs. if tied to dgnd (asynchronous mode), sc and eocen are independent of cs, and eoc is an open drain output. eoc requires an external 3kd pull-up resistor in asynchronous mode. + l2v analog power. -12v analog power. +5v digital power. twelve/eight bit format. if tied high, sets output format to 12-bit parallel. if tied low, sets output format to 8-bit multiplexed. ( ( type: ai = analog input. ao = analog output. di = digital input (ttl and sv cmos compatible). do = digital output (ttl and sv cmos compatible). all do pins are three-state drivers. p = power. outline dimensions dimensions shown in inches and (mm). 28-pin ceramic dip package (d-28a) ~ ~ . ~.: ~ . ':'~l ~ ]1. :~~~ ti '" - =f i '" '" '" 1 i .". ." j. ~ 5 i seating (317) l . 6{ . plane 1- t~"ck- ' 0.ob5 12 41) f9 -l (2.16) ~~ jt"') t 0.145 '002 ~ (3.6b) 0050j t -- f-- '0.010 0.047 '.007 if-- --i 1127) 11.19) 0.017 '.003 - 11- 0010 ,0.0 . :j (043) 011254) 11{0254 w os) lead no iident if i-- 0.6 11524} led dy dot 28-lead plastic dip package (n-28a) [~~~~~~~:::]3~ i i 0.16014.061 . -4 ::':~:;::;:, ?- rr ~ ~ 0140.3561 'j.-~ ,-",. {5.0801 max ~ r ~ ~ ~ -. 0008102031 1>: -h- -j ~ -.- o' 0.02010.5081 010512671 0.17514451 0.01510.3611 009512:411 0.12013051 0.065 {1.651 0.04511.141 lead nd 1 identified by dot dr notch. leads are soloer oippeo or tin plated alloy 42 or copper -8- ad1678 pin description pin no. type agnd 7 p ain 6 al bipoff 10 al cs 4 dl dgnd 14 p dbll-db4 26-19 do db3, db2 18, 17 do db 1 (r/l) 16 do dbo(hbe) 15 do eoc 27 do eocen 1 di hbe(dbo) 15 di oe 2 di refjn 9 ai refout 8 ao r/l(db!) 16 di sc 3 di sync 13 di vcc 11 p vee 5 p vdd 28 p 12/8 12 di obsolete pin configuration agnd i 7 ad1678 top view (not to scale) eocen i 1 . *stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. expo- sure to absolute maximum rating conditions for extended periods may affect device reliability. ) foc functional block diagram ordering guide esd sensitivity the ad1678 features input protection circuitry consisting of large "distributed" diodes and polysilicon series resistors to dissipate both high-energy discharges (human body model) and fast, low energy pulses (charged device model). per method 3015.2 of mil-std-883c, the ad1678 has been classified as a category a device. proper esd precautions are strongly recommended to avoid functional damage or performance degradation. charges as high as 4000 volts readily accumulate on the human body and test equip- ment and discharge without detection. unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before devices are removed. for further information on esd precautions, refer to analog devices' esd prevention manual. -9- absolute maximum ratings. " i with respect s ecification to min max units vee agnd -0.3 +18 v vee agnd -18 +0.3 v vo: vee -0.3 + 26.4 v vdd dgnd 0 +7 v agnd dgnd -i +1 v ain, refin agnd -12 + 12 v refin vee 0 vo: v refin vee vee 0 v digital inputs dgnd -0.5 +7 v digital outputs dgnd -0.5 vdd +0.3 v max junction temperature i 175 i c operating temperature j and k grades i 0 +70 i c storage temperature -65 + iso c lead temperature (losec max) i +300 i c mimimum sin + d @ temperature price model package 10khz, -0.5db input range (100s) ad1678jn 28-pin plastic dip 70db. 0 to + 70c $38.00 ad1678kn 28-pin plastic dip 72db" 0 to + 70c $42.00 ad1678jd 28-pin ceramic dip 70db 0 to + 70c $45.00 ad1678kd 28-pin ceramic dip 72db 0 to + 70c $50.00 obsolete application information input connections and calibration the adi678 is factory trimmed to minimize offset, gain and linearity errors. in unipolar mode, the only external component that is required is a son:,:: 1 % resistor. two resistors are required in bipolar mode. if offset and gain are not critical, even these components can be eliminated. in some applications, offset and gain errors need to be more precisely trimmed. the following sections describe the correct procedure for these various situations. bipolar range inputs the connections for the bipolar mode are shown in figure 8. in this mode, data output coding will be twos complement binary. this circuit will allow approximately :'::25mv of offset trim range (:,:: 10 lsb) and :'::0.5% of gain trim range (:'::20 lsb). either or both of the trim pots can be replaced with son:,:: 1% fixed resistors if the adl678 accuracy limits are sufficient for application. if the pins are shorted together, the additional offset and gain errors will be approximately 20 lsb. to trim bipolar zero to its nominal value, apply a signal 1/2 lsb below midrange (-1.22mv for a :'::5v range) and adjust rl until the major carry transition is located (1111 1111 1111 to 0000 0000 0000). to trim the gain, apply a signal 1 1/2 lsb below full scale (+4.9963v for a :':: 5v range) and adjust r2 to give the last positive transition (011111111110 to 01111111 1111). these trims are interactive so several iterations may be necessary for convergence. a single pass calibration can be done by substituting a bipolar offset trim (error at minus full scale) for the bipolar zero trim (error at midscale), using the same circuit. first, apply a signal 1/2 lsb above minus full scale (-4. 9988v for a :':: 5v range) and adjust rl until the minus full scale transition is located (100000000000 to 100000000001). then perform the gain error trim as outlined above. ~5v input ad1678 ~ gain adjust offset adjust 7 i agnd figure 8. bipolar input connections with gain and offset trims oto10vinput ad1678 ~ offset r1 adjust 100k 7 i agnd figure 9. unipolar input connections with gain and offset trims unipolar range inputs the connections for the unipolar mode are shown in figure 9. in this mode, data output coding will be straight binary. this circuit will allow approximately:':: 25m v of offset trim range (:,:: 10 lsb) and :'::0.5% of gain trim range (:'::20 lsb). if the standard accuracy limits of the adi678 are sufficient for the application, the gain adjust resistor (r2) can be replaced by a son:,:: 1 % fixed resistor and bipoff can be connected to ground. ( board layout designing with high resolution data converters requires careful attention to board layout. trace impedance is the first issue. a sma current through a 0.5n trace will develop a voltage drop of 2.5mv, which is 1 lsb at the 12-bit level for a lov full scale span. in addition to ground drops, inductive and capacitive cou- pling need to be considered, especially when high accuracy ana- log signals share the same board with digital signals. finally, power supplies need to be decoupled in order to filter out ac noise. analog and digital signals should not share a common path. each signal should have an appropriate analog or digital return routed close to it. using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. wide pc tracks, large gauge wire, and ground planes are highly recom- mended to provide low impedance signal paths. separate analog and digital ground planes are also desirable, with a single inter- connection point to minimize ground loops. analog signals should be routed as far as possible from digital signals and should cross them at right angles. the adi678 incorporates several features to help the user's lay- out. analog pins (vee, ain, agnd, refout' refin' bipoff, v cd are adjacent to help isolate analog from digital signals. in addition, the 10mn input impedance of ain mini- mizes input trace impedance errors. finally, ground currents have been minimized by careful circuit architecture. current through agnd is 200fla, with no code dependent variation. the current through dgnd is dominated by the return current for db11-dbo and eoc. ( supply decoupling the adi678 power supplies should be well filtered, well regu- lated, and free from high frequency noise. switching power sup- plies are not recommended due to their tendency to generate spikes which can induce noise in the analog system. decoupling capacitors should be used in very close layout prox- imity between all power supply pins and ground. a loflf tanta- lum capacitor in parallel with a o.lflf disk ceramic capacitor provides adequate decoupling over a wide range of frequencies. an effort should be made to minimize the trace length between the capacitor leads and the respective converter power supply and common pins. the circuit layout should attempt to locate the adi678, associated analog input circuitry and interconnec- tions as far as possible from logic circuitry. a solid analog ground plane around the adi678 will isolate large switching ground currents. for these reasons, the use of wire wrap circuit construction is not recommended; careful printed circuit con- struction is preferred. -10- obsolete grounding if a single ad1678 is used with separate analog and digital ground planes, connect the analog ground plane to agnd and the digital ground plane to dgnd keeping lead lengths as short as possible. then connect agnd and dgnd together at the ad1678. if multiple adi678s are used or the adi678 shares analog supplies with other components, connect the analog and digital returns together once at the power supplies rather than at each chip. this prevents large ground loops which inductively couple noise and allow digital currents to flow through the ana- log system. 200ksps read application in applications requiring the maximum throughput of the ad1678, the read circuit of figure loa is recommended. the converter is operated in its 12-bit, parallel-read mode with oe derived from eoc through an inverter. on the falling edge of oe, data from the previous conversion is latched in the con- verter's output register and is available on the data bus loons (tba) later. an external latch can then hold the data if retiming is necessary. note that in this configuration, a one-sample pipe- line delay is introduced since the data accessed corresponds to the previous conversion, rather than the most recent (see figure lob). conversion start sc 2x ls373 latch ad1678 figure 1oa. 200ksps output configuration ~5fls~ r-- conversion conversion_! sc #1 i #2 ~~ -i tep 1- i eoc oe i --i tap i-- , i ~ i i ~tbf~ j tba.- : i 0811-080 figure 10b. 200ksps 12-bit read timing interfacing the ad1678 to microprocessors the i/o capabilities of the adi678 allow direct interfacing to general purpose and dsp microprocesor buses. the asynchro- nous conversion control feature 'allows complete flexibility and control with minimal external hardware. the following examples illustrate typical adi678 interface configurations. ad1678 to tms320c25 in figure ii the adl678 is mapped into the tms320c25 i/o space. adl678 conversions are initiated by issuing an out instruction to port 8. eoc status and the conversion result are read in with an in instruction to port 8. a single wait state is inserted by generating the processor ready input from is, port 8 and msc. this configuration supports processor clock speeds of 20mhz and is capable of supporting processor clock speeds of 40mhz if a nop instruction follows each adl678 read instruction. r/w a2 a' ao c b a 74f138 g2b g1 g2a yo port8 1218 syneh +5v strb a3 is tms320c25 ready ad1678 data bus '2 figure 11. ad1678 to tms320c25 interface ad1678 to 80186 figure 12 shows the adi678 interfaced to the 80186 micropro- cessor. this interface allows the 80186's built-in dma control- ler to transfer the adl678 output into a ram based fifo buffer of any length, with no microprocessor intervention. in this application the adl678 is configured in the asynchro- . nous mode, which allows conversions to be initiated by an exter- nal trigger source independent of the microprocessor clock. after each conversion, the ad1678 eoc signal generates a dma request to channel 1 (drq1). the subsequent dma read operation resets the interrupt latch. the system designer must assign a sufficient priority to the dma channel to ensure that the dma request will be serviced before the completion of the next conversion. this configuration can be used with 6mhz and 8mhz 80186 processors. 80'86 ad1678 ale aoo-'5 a'6-19 ram wr iid de cs +5v oro' 00-011 sc external trigger figure 12. ad1678 to 80186 dma interface -11- obsolete ad1678 to z80 the ad1678 can be interfaced to the z80 processor in an i/o or memory mapped configuration. figure 13 illustrates an i/o con- figuration, where the ad1678 occupies several port addresses to allow separate polling of the eoc status and reading of the data. the lower address bit, ao, is used to select the high and low order bytes of the result. the ad1678 r/l line is tied high, resulting in right justified output data. a useful feature of the z80 is that a single wait state is automat- ically inserted during i/o operations, allowing the ad1678 to be used with z80 processors having clock speeds up to 8mhz. +5v ail sync eocen ad1678 os 50 data bus d4 - di1 12:. figure 13. ad1678 to z80 interface ad1678 to analog devices adsp-2100 figure 14 demonstrates the ad1678 interfaced to an adsp-21o0.with a clock frequency of 8mhz, and instruction execution in one 125ns cycle, the digital signal processor will support the ad1678 data memory interface with a single wait state. adsp-2100 dma 13-0 cs dms dmwr 50 dmack de ad1678 eocen clkout 12/8 dmrd dmd 15-0 data bus figure 14. ad1678 to adsp-21o0 interface at the beginning of the data memory access cycle, the processor provides a 14-bit address on the dma bus. the dms signal is then asserted, enabling a low address decode and the ad1678 cs. the processor issues dmwr which is gated with the decoded address to start conversion. the low decoded address is also or'ed with the q output of a d flip-flop to pull dmack low. this forces the adsp-2100 into a wait state for 1 clock cycle. the rising edge of clkout latches q high bringing dmack high. the conversion is complete sils later. the processor can now start a data memory access cycle to read data. for this cycle the dmrd and low decoded address are or'ed to generate oe for the converter. once again, a single wait state is inserted allowing data to be read from the bus. -12- --- cd ~ 'i c) 'i ~ n u |
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