View LTC5566_9048265.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 for more information www.linear.com/LTC5566 typical a pplica t ion fea t ures descrip t ion 300mhz to 6ghz dual programmable gain downconverting mixer the lt c ? 5566 dual programmable gain downconverting mixer is ideal for diversity and mimo receivers that require precise gain setting. each channel incorporates an active mixer and a digital if vga with 15.5db gain control range. the if gain of each channel is programmed in 0.5db steps through the spi. programmable rf input tuning via the spi or parallel control lines makes the device attractive for wideband radio applications. furthermore, a reduced power mode is available, programmed through the spi. integrated rf transformers provide single-ended 50 in - puts. the differential lo input is designed for single-ended or differential drive. the differential if output simplifies the interface to differential if filters and amplifiers. the mixers are optimized for use up to 5ghz but may be used up to 6ghz with degraded performance. dual channel mimo receiver with programmable 0.5db gain steps LTC5566 conversion gain vs rf frequency and if attenuation (0.5db gain steps) a pplica t ions n 4g and 5g mimo receivers n diversity receivers n distributed antenna systems (das) n network test/monitoring equipment n software-defined radios l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. n 12db power conversion gain n 35dbm output ip3 n 15.5db range if dvga in 0.5db steps n programmable rf input tuning n reduced power mode n 3.3v single supply n simple spi for fast development n C40c to 105c operation (t c ) n very small solution size n 32-lead (5mm 5mm) qfn package rf input frequency (ghz) 1.5 g c (db) 14 12 8 4 10 6 ?8 ?6 ?4 ?2 0 2 3.5 2.5 4.5 5566 ta01b 5 3 2 4 band 0 rf tune if = 153mhz sdi LTC5566 lpf 3.3v 3.3v 3.3v 3.3v bpf bpf 5566 ta01a if 1 ? if1 + if1 lo lo ltc6430 if 2 + if2 ? if2 ltc6430 lna lna csb rf1 rf2 clk sdo spi bpf bpf lo lo + lo ? lt c5566 5566f
2 for more information www.linear.com/LTC5566 p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltage (v dd , v cc1 , v cc2 , i f1 + , i f1 C , i f 2 + , i f2 C ) ................................................................... 4v e n1 , e n 2 , t0, t1 input voltages ...... C 0. 3v to v cc + 0.3v lo + , lo C input power ( 150mhz to 6ghz ) .......... + 10d bm rf1 , rf2 input power ( 300mhz to 6ghz ) .......... + 20 dbm lo + , lo C dc voltage .............................................. 0. 5v if dvga peak differential input voltage .................... 4v s di, clk, csb, ps input voltages ... C 0. 3v to v dd + 0.3v sdo output current ............................................. 10 ma operating temperature range (t c ) ........ C 40 c to 105 c junction temperature (t j ) .................................... 150 c storage temperature range .................. C 65 c to 150 c (notes 1, 2) 9 10 11 12 top view 33 gnd uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 32 31 30 29 28 27 26 25 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 gnd rf1 csb clk sdi sdo rf2 gnd if1 + if1 ? v dd lo + lo ? ps if2 ? if2 + t1 mo1 ? mo1 + v cc1 en1 ai1 + ai1 ? gnd t0 mo2 ? mo2 + v cc2 en2 ai2 + ai2 ? gnd t jmax = 150c, jc = 7.7c/w exposed pad (pin 33) is gnd, must be soldered to pcb lead free finish tape and reel part marking package description case temperature range LTC5566iuh#pbf LTC5566iuh#trpbf 5566 32-lead (5mm 5mm) plastic qfn C40c to 105c consult ltc marketing for parts specified with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. e lec t rical c harac t eris t ics parameter conditions min typ max units supply voltage (v cc ) l 3.0 3.3 3.6 v spi supply voltage (v dd ) l 1.6 3.6 v supply current (i cc ) one channel, full power mode both channels, full power mode one channel, reduced power mode both channels, reduced power mode shutdown l 192 384 147 294 1.2 225 450 1.9 ma ma ma ma ma spi supply current (i dd ) operating: csb = low, f clk =10mhz idle: csb = high 0.2 10 1 ma a enable and rf t uning logic inputs (en1, en2, t0, t1) internal pull-down resistors on each pin input high voltage (on) l 1.4 v input low voltage (off) l 0.5 v input current v in = v cc = 3.6v 100 a enable turn-on time 0.3 s enable turn-off t ime 0.1 s rf input tuning parallel select logic input (ps) internal pull-down resistor input high voltage (parallel enabled) l 0.7 ? v dd v input low voltage (serial enabled) l 0.3 ? v dd v input current v in = v dd = 3.6v 50 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t c = 25c. v cc = v dd = 3.3v. test circuit shown in figure 1. (note 2) o r d er i n f or m a t ion ( http://www.linear.com/product/LTC5566#orderinfo) lt c5566 5566f
3 for more information www.linear.com/LTC5566 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t c = 25c. v cc = v dd = 3.3v. test circuit shown in figure 1. (notes 3, 6) parameter conditions min typ max units spi port logic inputs (csb, clk, sdi) input high voltage l 0.7 ? v dd v input low voltage l 0.3 ? v dd v input current v in = v dd = 3.6v 25 a input hysteresis 200 mv spi port logic output (sdo) output high voltage i source = 3ma l v dd C 0.4v v output low voltage i sink = 3ma l 0.4 v output leakage current v csb = v dd = 3.6v 20 a spi port timing sdi setup time 5 ns sdi hold time 10 ns clk falling to sdo valid time c sdo = 20pf 15 ns sdo rise/fall time c sdo = 20pf 5 ns sdo enable time 10 ns sdo disable time 10 ns csb setup time 15 ns csb hold time 5 ns clk frequency c sdo = 20pf 20 mhz ac e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t c = 25 c . v cc = 3.3v, en1, en2 = high, p lo = 0dbm . test circuit shown in figure 1. (notes 3, 4, 5) parameter conditions min typ max units rf input frequency range external matching required l 300 to 6000 mhz lo input frequency range l 150 to 6000 mhz if output frequency range external matching required l 1 to 500 mhz 1db if gain rolloff relative to 100mhz gain 400 mhz if gain error at 150mhz differential; between any two 0.5db atten steps integral; over entire 15.5db if atten range 0.06 0.3 db db if phase error if = 150mhz, full 15.5db atten range if = 350mhz, full 15.5db atten range 2.4 5.5 deg deg lo input return loss single-ended, z o = 50, 150mhz to 6000mhz >10 db lo input power single-ended or differential l C6 0 6 dbm mixer if output impedance differential, 10mhz to 400mhz 300 || 1pf r || c if dvga input impedance differential, 10mhz to 400mhz 300 || 1pf r || c if dvga output impedance differential, 10mhz to 400mhz 206 || 1pf r || c rf to lo isolation rf = 300mhz to 1000mhz rf = 1000mhz to 3800mhz rf = 3800mhz to 6000mhz > 68 >50 >40 db db db rf to unbalanced if port isolation rf = 300mhz to 900mhz rf = 900mhz to 6000mhz >32 >54 db db lo to unbalanced if port leakage lo = 300mhz to 800mhz lo = 800mhz to 6000mhz 4 for more information www.linear.com/LTC5566 ac e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t c = 25 c . v cc = v dd = 3.3v, en1, en2 = high, p rf = C 8dbm /tone, p lo = 0dbm, unless otherwise noted. test circuit shown in figure 1. (notes 3, 4, 5) band 0 (see figure 1): rf = 4.5ghz, if = 153mhz, low side lo parameter conditions full pwr reduced pwr units min typ max typ rf input return loss z o = 50, 3.1ghz to 5.1ghz >10 >10 db power conversion gain 0db if atten 6db if atten 12db if atten 10.6 4.5 C1.6 10.3 4.2 C1.9 db db db conversion gain flatness rf = 4.5ghz 100mhz, lo = 4.35ghz 0.4 0.4 db conversion gain vs temperature t c = C40c to 105oc l C0.014 C0.014 db/c two-tone input 3rd order intercept (f rf = 2mhz) 0db if atten 6db if atten 12db if atten 22.0 23.6 24.1 17.8 18.7 18.9 dbm dbm dbm two-tone input 2nd order intercept (f rf = 154mhz = f im2 ) 0db to 15.5db if atten 50 46 dbm ssb noise figure 0db if atten 6db if atten 12db if atten 16.3 17.8 21.1 15.2 17.1 20.9 db db db lo to rf leakage lo = 3.1ghz to 5.2ghz 5 for more information www.linear.com/LTC5566 ac e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t c = 25 c . v cc = v dd = 3.3v, en1, en2 = high, p rf = C 8dbm /tone, p lo = 0dbm, unless otherwise noted. test circuit shown in figure 1. (notes 3, 4, 5) band 1 (see figure 1): rf = 2.6ghz, if = 153mhz, high side lo parameter conditions full pwr reduced pwr units min typ max typ rf input return loss z o = 50, 1.8ghz to 4.4ghz >12 >12 db power conversion gain 0db if atten 3db if atten 6db if atten 9db if atten 12db if atten 15db if atten 6.8 11.8 8.8 5.8 2.7 C0.3 C3.4 11.5 8.4 5.4 2.4 C0.7 C3.7 db db db db db db conversion gain flatness rf = 2.6ghz 100mhz, lo = 2.75ghz 0.5 0.5 db conversion gain vs temperature t c = C40c to 105oc l C0.013 C0.013 db/c two-tone input 3rd order intercept (f rf = 2mhz) 0db if atten 3db if atten 6db if atten 9db if atten 12db if atten 15db if atten 23.2 24.6 26.0 26.8 27.6 28.0 19.5 20.6 21.2 21.4 21.4 21.4 dbm dbm dbm dbm dbm dbm two-tone output 3rd order intercept (f rf = 2mhz) 0db if atten 3db if atten 6db if atten 9db if atten 12db if atten 15db if atten 35.0 33.4 31.8 29.5 27.3 24.6 31.0 29.0 26.6 23.8 20.7 17.7 dbm dbm dbm dbm dbm dbm two-tone input 2nd order intercept (f rf = 154mhz = f im2 ) 0db to 15.5db if atten 59 54 dbm ssb noise figure 0db if atten 3db if atten 6db if atten 9db if atten 12db if atten 15db if atten 13.3 14.1 15.3 17.0 19.3 21.7 13.0 14.0 15.3 17.2 19.5 22.1 db db db db db db ssb noise figure under blocking (2.5ghz blocker) + 2dbm blocker, 3db if atten +5dbm blocker, 3db if atten 18.7 21.1 18.3 20.9 db db lo to rf leakage lo = 1.6ghz to 4ghz 6 for more information www.linear.com/LTC5566 ac e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t c = 25 c . v cc = v dd = 3.3v, en1, en2 = 3.3v, p rf = C 8dbm /tone, p lo = 0dbm, unless otherwise noted. test circuit shown in figure 1. (notes 3, 4, 5) band 2 (see figure 1): rf = 1.9ghz, if = 153mhz, high side lo parameter conditions full pwr reduced pwr units min typ max typ rf input return loss z o = 50, 1.3ghz to 3.9ghz >10 >10 db power conversion gain 0db if atten 3db if atten 6db if atten 9db if atten 12db if atten 15db if atten 11.9 8.8 5.8 2.8 C0.3 C3.3 11.6 8.5 5.5 2.5 C0.5 C3.6 db db db db db db conversion gain flatness rf = 1.9ghz 100mhz, lo = 2.05ghz 0.5 0.5 db conversion gain vs temperature t c = C40c to 105oc l C0.013 C0.013 db/c two-tone input 3rd order intercept (f rf = 2mhz) 0db if atten 3db if atten 6db if atten 9db if atten 12db if atten 15db if atten 22.6 23.9 25.4 26.1 26.3 26.5 19.8 21.2 22.0 22.3 22.4 22.5 dbm dbm dbm dbm dbm dbm two-tone output 3rd order intercept (f rf = 2mhz) 0db if atten 3db if atten 6db if atten 9db if atten 12db if atten 15db if atten 34.5 32.7 31.2 28.9 26.0 23.2 31.4 29.7 27.5 24.8 21.9 18.9 dbm dbm dbm dbm dbm dbm two-tone input 2nd order intercept (f rf = 154mhz = f im2 ) 0db to 15.5db if atten 57 53 dbm ssb noise figure 0db if atten 3db if atten 6db if atten 9db if atten 12db if atten 15db if atten 13.0 13.9 15.2 17.0 19.3 21.8 12.1 13.2 14.7 16.7 19.2 21.8 db db db db db db ssb noise figure under blocking (1.8ghz blocker) + 2dbm blocker, 3db if atten +5dbm blocker, 3db if atten 17.6 20.4 17.4 20.0 db db lo to rf leakage lo = 1.1ghz to 3.5ghz 7 for more information www.linear.com/LTC5566 ac e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t c = 25 c . v cc = v dd = 3.3v, en1, en2 = high, p rf = C 8dbm /tone, p lo = 0dbm, unless otherwise noted. test circuit shown in figure 1. (notes 3, 4, 5) band 3 (see figure 1): rf = 850mhz, if = 153mhz, high side lo parameter conditions full pwr reduced pwr units min typ max typ rf input return loss z o = 50, 700mhz to 1.3ghz >10 >10 db power conversion gain 0db if atten 6db if atten 12db if atten 12.2 6.1 0 11.8 5.7 C0.4 db db db conversion gain flatness rf = 850mhz 75mhz, lo = 1050mhz 0.3 0.3 db conversion gain vs temperature t c = C40c to 105oc l C0.014 C0.014 db/c two-tone input 3rd order intercept (f rf = 2mhz) 0db if atten 6db if atten 12db if atten 22.0 24.7 26.2 19.5 22.3 23.3 dbm dbm dbm two-tone input 2nd order intercept (f rf = 154mhz = f im2 ) 0db to 15.5db if atten 60.0 56.5 dbm ssb noise figure 0db if atten 6db if atten 12db if atten 12.6 14.9 19.1 12.1 14.7 19.2 db db db lo to rf leakage lo = 300mhz to 1.5ghz 10 >10 db power conversion gain 0db if atten 6db if atten 12db if atten 11.7 5.6 C0.5 11.1 5.0 C1.1 db db db ssb noise figure 0db if atten 6db if atten 12db if atten 13.8 15.9 19.9 13.6 15.9 20.1 db db db two-tone input 3rd order intercept (f rf = 2mhz) 0db if atten 6db if atten 12db if atten 21.8 24.1 25.0 19.4 21.7 22.6 dbm dbm dbm channel-to-channel isolation rf = 450mhz 57 57 db note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the mixer output pins on this device are sensitive to esd greater than 750v (hbm). proper esd handling precautions must be observed. all other pins withstand 2kv. note 3: the LTC5566 is guaranteed functional over the C40c to 105c case temperature range. note 4: ssb noise figure measured with a small-signal noise source, bandpass filter and 2db matching pad on rf input, and bandpass filter on the lo input. note 5: channel-to-channel isolation is defined as the relative if output power of channel 2 to channel 1, with the rf input signal applied to rf1 while the rf2 input is 50 terminated. both channels are enabled and programmed for 3db if attenuation. note 6: spi timing guaranteed by design, not subject to test. lt c5566 5566f
8 for more information www.linear.com/LTC5566 typical p er f or m ance c harac t eris t ics test circuit shown in figure 1. p rf = C8dbm/tone, ?f = 2mhz, p lo = 0dbm, v cc = 3.3v, v dd = 3.3v, t c = 25c, unless otherwise noted. band 0: rf = 3.6ghz and 4.5ghz, if = 153mhz, low side lo conv gain and iip3 vs rf frequency 0db, 6db and 12db if attenuation ssb nf vs rf frequency 0db, 6db and 12db if attenuation rf isolation and lo leakage vs frequency 3.6ghz conv gain, iip3 and ssb nf vs lo power and case temperature 3.6ghz conv gain, iip3 and ssb nf vs if attenuation (0.5db steps) 3.6ghz conv gain vs if frequency and attenuation, swept rf/fixed lo 4.5ghz conv gain, iip3 and ssb nf vs lo power and case temperature 4.5ghz conv gain, iip3 and ssb nf vs if attenuation (0.5db steps) 4.5ghz conv gain vs if frequency and attenuation, swept rf/fixed lo rf frequency (ghz) 3.1 g c (db), iip3 (dbm) 27 23 15 7 19 11 3 ?1 ?5 4.3 4.7 5566 g01 5.1 3.9 3.5 0db iip3 g c 0db 6db 12db 6db 12db full power mode rf frequency (ghz) 3.1 ssb nf (db) 24 22 16 20 18 14 12 4.3 4.7 5566 g02 5.1 3.9 3.5 0db 6db 12db full power mode rf/lo frequency (ghz) 2.9 isolation (db) 80 70 20 60 50 40 30 10 0 lo leakage (dbm) 20 10 ?40 0 ?10 ?20 ?30 ?50 ?60 4.1 4.5 4.9 5566 g03 5.3 3.73.3 3db if attenuation full power mode rf ?lo isolation lo ?rf rf ?if + or rf ?if ? (unbalanced) channel isolation lo ?if + or lo ?if ? (unbalanced) lo input power (dbm) ?6 g c (db), iip3 (dbm), nf (db) 25 21 23 11 19 17 15 13 9 7 0 2 4 5566 g04 6 ?2?4 g c nf iip3 t c = ?40c t c = 25c t c = 85c 3db if attenuation full power mode if attenuation (db) 0 g c (db), iip3 (dbm), nf (db) 28 22 25 7 19 16 13 10 4 ?5 1 ?2 6 8 10 12 14 5566 g05 16 42 g c full power reduced power nf iip3 if frequency (mhz) 50 conv gain (db) 12 10 0 8 6 4 2 ?2 ?8 ?4 ?6 150 200 250 300 5566 g06 350 100 0db rf = 3.5ghz to 3.8ghz lo = 3.45ghz full power mode 3db 6db 9db 12db 15db lo input power (dbm) ?6 g c (db), iip3 (dbm), nf (db) 24 20 22 10 18 16 14 12 8 6 0 2 4 5566 g07 6 ?2?4 g c nf iip3 t c = ?40c t c = 25c t c = 85c 3db if attenuation full power mode if attenuation (db) 0 g c (db), iip3 (dbm), nf (db) 25 19 22 4 16 13 10 7 1 ?8 ?2 ?5 6 8 10 12 14 5566 g08 16 42 g c full power reduced power nf iip3 if frequency (mhz) 50 conv gain (db) 11 9 ?1 7 5 3 1 ?3 ?9 ?5 ?7 150 200 250 300 5566 g09 350 100 rf = 4.35ghz to 4.65ghz lo = 4.3ghz full power mode 3db 6db 9db 12db 15db 0db lt c5566 5566f
9 for more information www.linear.com/LTC5566 typical p er f or m ance c harac t eris t ics test circuit shown in figure 1. p rf = C8dbm/tone, ?f = 2mhz, p lo = 0dbm, v cc = 3.3v, v dd = 3.3v, t c = 25c, unless otherwise noted. band 1: rf = 2.6ghz, if = 153mhz, high side lo conv gain and iip3 vs rf frequency 0db, 6db and 12db if attenuation ssb nf vs rf frequency 0db, 6db and 12db if attenuation conv gain vs if frequency and if attenuation, swept rf/fixed lo 2.6ghz conv gain, iip3 and ssb nf vs lo power and case temperature 2.6ghz conv gain, iip3 and ssb nf vs if attenuation (0.5db steps) 2.6ghz rf input and if output p1db vs if attenuation isolation vs rf frequency lo leakage vs lo frequency 2.6ghz conv gain, iip3, nf and rf input p1db vs temperature rf frequency (ghz) 1.8 g c (db), iip3 (dbm) 30 27 21 15 12 9 6 24 18 3 0 ?3 3 3.4 5566 g10 3.8 2.6 2.2 iip3 g c 0db 6db 12db 6db 12db full power mode 0db rf frequency (ghz) 1.8 ssb nf (db) 22 20 14 18 16 12 10 3 3.4 5566 g11 3.8 2.6 2.2 6db 12db full power mode 0db if frequency (mhz) 50 conv gain (db) 12 10 0 8 6 4 2 ?2 ?8 ?4 ?6 150 200 250 300 5566 g12 350 100 rf = 2.4ghz to 2.7ghz lo = 2.75ghz full power mode 3db 6db 9db 12db 15db 0db lo input power (dbm) ?6 g c (db), iip3 (dbm), nf (db) 25 21 23 11 19 17 15 13 9 7 0 2 4 5566 g13 6 ?2?4 g c nf iip3 t c = ?40c t c = 25c t c = 85c 3db if attenuation full power mode if attenuation (db) 0 g c (db), iip3 (dbm), nf (db) 31 22 25 28 7 19 16 13 10 4 ?5 1 ?2 6 8 10 12 14 5566 g14 16 42 g c full power reduced power iip3 nf if attenuation (db) 0 p1db (dbm) 19 15 17 9 13 11 5 7 6 8 10 12 14 5566 g15 16 42 full power reduced power if out p1db rf in p1db rf frequency (ghz) 1.8 isolation (db) 90 80 70 60 50 40 30 3 3.4 5566 g16 3.8 2.6 2.2 3db if attenuation full power mode rf ?lo rf ?if + or rf ?if ? (unbalanced) channel isolation lo frequency (ghz) 1.6 lo leakage (dbm) ?20 ?30 ?40 ?50 ?60 ?70 2.8 3.2 3.6 5566 g17 4 2.42 lo ?rf lo ?if + or lo ?if ? (unbalanced) 3db if attenuation full power mode case temperature (c) ?45 g c (db), nf (db), iip3 (dbm), p1db (dbm) 25 23 21 19 17 15 13 11 9 7 45 75 5566 g18 105 15 ?15 3db if attenuation full power mode iip3 nf g c input p1db lt c5566 5566f
10 for more information www.linear.com/LTC5566 typical p er f or m ance c harac t eris t ics test circuit shown in figure 1. p rf = C8dbm/tone, ?f = 2mhz, p lo = 0dbm, v cc = 3.3v, v dd = 3.3v, t c = 25c, unless otherwise noted. band 1: rf = 2.6ghz, if = 153mhz, high side lo 2-tone if output power, im3 and im5 vs rf input power single-tone if output power, 2 2 and 3 3 spurs vs rf input power 2 2 and 3 3 spur suppression vs lo power v cc supply current vs supply voltage (both channels enabled) ssb nf vs rf blocker power 2.6ghz conv gain iip3 and ssb nf vs supply voltage and case temperature rf input power (dbm) ?15 output power (dbm) 20 0 10 ?20 ?10 ?40 ?30 ?60 ?70 ?50 ?90 ?80 ?6 ?3 0 3 6 9 5566 g20 12 ?9?12 if out (rf = 2.6ghz) 3lo ?3rf (rf = 2702mhz) 2lo ?2rf (rf = 2676.5mhz) lo = 2753mhz 6db if attenuation full power mode lo power (dbm) ?6 relative spur level (dbc) ?50 ?55 ?60 ?65 ?70 ?75 ?80 0 2 4 5566 g21 6 ?2?4 t c = ?40c t c = 25c t c = 85c lo = 2753mhz p rf = ?6dbm 6db if attenuation full power mode 3lo ?3rf (rf = 2702mhz) 2lo ?2rf (rf = 2676.5mhz) v cc supply voltage (v) 3 supply current (ma) 450 425 400 350 375 325 300 275 250 3.3 3.4 3.5 5566 g22 3.6 3.23.1 full power 105c 85c 55c 25c ?10c ?40c reduced power rf blocker power (dbm) ?18 ssb nf (db) 24 22 20 18 16 14 12 10 ?6 ?2 2 5566 g23 6 ?10?14 rf = 2.6ghz blocker = 2.5ghz lo = 2753mhz if attenuation = 3db full power mode p lo = ?3dbm p lo = 0dbm p lo = 3dbm v cc supply voltage (v) 3 g c (db), nf (db), iip3 (dbm) 27 21 23 25 11 19 17 15 13 9 7 3.3 3.4 3.5 5566 g24 3.6 3.23.1 g c nf t c = ?40c t c = 25c t c = 85c 3db if attenuation full power mode iip3 rf input power (dbm/tone) output power (dbm/tone) 20 0 10 ?20 ?10 ?40 ?30 ?60 ?70 ?50 ?80 ?8 ?6 ?4 ?2 0 2 4 5566 g19 6 ?10?12 im3 im5 rf1 = 2599mhz rf2 = 2601mhz lo = 2753mhz 6db if attenuation full power mode if out 7.6 8 8.4 8.8 9.2 9.6 10 0 distribution (%) 35 25 20 15 10 5 30 45 40 conversion gain (db) 5566 g25 3db if attenuation full power mode 85c 25c ?40c 22.5 23.523 24 24.5 25 25.5 26 0 distribution (%) 25 20 15 10 5 30 iip3 (dbm) 5566 g26 3db if attenuation full power mode 85c 25c ?40c 12.3 12.9 13.5 14.1 14.7 15.3 15.9 0 distribution (%) 35 25 20 15 10 5 30 45 40 ssb noise figure (db) 5566 g27 3db if attenuation full power mode 85c 25c ?40c 2.6ghz conversion gain distribution 2.6ghz iip3 distribution 2.6ghz ssb nf distribution lt c5566 5566f
11 for more information www.linear.com/LTC5566 typical p er f or m ance c harac t eris t ics test circuit shown in figure 1. p rf = C8dbm/tone, ?f = 2mhz, p lo = 0dbm, v cc = 3.3v, v dd = 3.3v, t c = 25c, unless otherwise noted. band 2: rf = 1.9ghz, if = 153mhz, high side lo conv gain and iip3 vs rf frequency 0db, 6db and 12db if attenuation ssb nf vs rf frequency 0db, 6db and 12db if attenuation conv gain vs if frequency and attenuation, swept rf/fixed lo 1.9ghz conv gain, iip3 and ssb nf vs lo power and case temperature 1.9ghz conv gain, iip3 and ssb nf vs if attenuation (0.5db steps) 1.9ghz rf input and if output p1db vs if attenuation isolation vs rf frequency lo leakage vs lo frequency 1.9ghz conv gain, iip3, nf and rf input p1db vs temperature rf frequency (ghz) 1.3 g c (db), iip3 (dbm) 30 27 21 15 24 18 12 9 6 3 0 ?3 2.5 2.9 5566 g28 3.3 2.1 1.7 iip3 g c 0db 6db 6db 12db full power mode 12db 0db rf frequency (ghz) 1.3 ssb nf (db) 22 20 14 18 16 12 10 2.5 2.9 5566 g29 3.3 2.1 1.7 0db 6db 12db full power mode if frequency (mhz) 50 conv gain (db) 12 10 0 8 6 4 2 ?2 ?8 ?4 ?6 150 200 250 300 5566 g30 350 100 rf = 1.7ghz to 2ghz lo = 2.05ghz full power mode 3db 6db 9db 12db 15db 0db lo input power (dbm) ?6 g c (db), iip3 (dbm), nf (db) 25 21 23 11 19 17 15 13 9 7 0 2 4 5566 g31 6 ?2?4 g c nf iip3 t c = ?40c t c = 25c t c = 85c 3db if attenuation full power mode if attenuation (db) 0 g c (db), iip3 (dbm), nf (db) 28 22 25 7 19 16 13 10 4 ?5 1 ?2 6 8 10 12 14 5566 g32 16 42 g c full power reduced power nf iip3 if attenuation (db) 0 p1db (dbm) 19 17 15 13 11 9 5 7 6 8 10 12 14 5566 g33 16 42 full power reduced power if out p1db rf in p1db rf frequency (ghz) 1.3 isolation (db) 90 50 80 70 60 40 30 2.5 2.9 3.3 5566 g34 2.1 1.7 rf ?if + or rf ?if ? (unbalanced) channel isolation rf ?lo 3db if attenuation full power mode lo frequency (ghz) 1.1 lo leakage (dbm) ?20 ?60 ?30 ?40 ?50 ?70 2.3 2.7 3.1 3.5 5566 g35 1.91.5 lo ?if + or lo ?if ? (unbalanced) lo ?rf 3db if attenuation full power mode case temperature (c) ?45 g c (db), nf (db), iip3 (dbm), p1db (dbm) 25 23 13 21 19 17 15 11 9 7 45 75 5566 g36 105 15 ?15 3db if attenuation full power mode nf g c iip3 input p1db lt c5566 5566f
12 for more information www.linear.com/LTC5566 typical p er f or m ance c harac t eris t ics test circuit shown in figure 1. p rf = C8dbm/tone, ?f = 2mhz, p lo = 0dbm, v cc = 3.3v, v dd = 3.3v, t c = 25c, unless otherwise noted. band 3: rf = 850mhz, if = 153mhz, high side lo conv gain and iip3 vs rf frequency 0db, 6db and 12db if attenuation ssb nf vs rf frequency 0db, 6db and 12db if attenuation conv gain vs if frequency and attenuation, swept rf/fixed lo 850mhz conv gain, iip3 and ssb nf vs lo power and case temperature 850mhz conv gain, iip3 and ssb nf vs if attenuation 850mhz rf input and if output p1db vs if attenuation rf isolation vs rf frequency lo leakage vs lo frequency 850mhz conv gain, iip3, nf and rf input p1db vs temperature rf frequency (mhz) 700 g c (db), iip3 (dbm) 30 27 21 15 24 18 12 9 6 3 0 ?3 1000 1100 1200 5566 g37 1300 900800 g c 0db 12db full power mode 12db iip3 6db 0db 6db rf frequency (mhz) 700 ssb nf (db) 22 20 21 15 18 19 17 16 13 14 12 1000 1100 5566 g38 1300 1200 900800 6db 12db full power mode 0db if frequency (mhz) 50 conv gain (db) 13 11 1 9 7 5 3 ?1 ?7 ?3 ?5 150 200 250 300 5566 g39 100 rf = 750mhz to 1ghz lo = 1050mhz full power mode 3db 6db 9db 12db 15db 0db lo input power (dbm) ?6 g c (db), iip3 (dbm) 25 21 23 11 19 17 15 13 9 7 0 2 4 5566 g40 6 ?2?4 g c nf iip3 t c = ?40c t c = 25c t c = 85c 3db if attenuation full power mode if attenuation (db) 0 g c (db), iip3 (dbm), nf (db) 28 24 8 20 16 12 4 ?4 0 6 8 10 12 14 5566 g41 16 42 g c full power reduced power nf iip3 if attenuation (db) 0 p1db (dbm) 18 16 14 12 10 8 4 6 6 9 12 5566 g42 15 3 full power reduced power if out p1db rf in p1db rf frequency (mhz) 700 isolation (db) 80 40 70 60 50 30 20 1000 1100 1200 1300 5566 g43 900800 rf ?if + or rf ?if ? (unbalanced) channel isolation rf ?lo 3db if attenuation full power mode lo frequency (mhz) 400 lo leakage (dbm) ?20 ?60 ?30 ?40 ?50 ?80 ?70 ?90 1000 1200 1400 1600 5566 g44 800600 lo ?if + or lo ?if ? (unbalanced) lo ?rf 3db if attenuation full power mode case temperature (c) ?45 g c (db), nf (db), iip3 (dbm), p1db (dbm) 25 23 13 21 19 17 15 11 9 7 45 75 5566 g45 105 15 ?15 nf iip3 input p1db g c 3db if attenuation full power mode lt c5566 5566f
13 for more information www.linear.com/LTC5566 typical p er f or m ance c harac t eris t ics test circuit shown in figure 1. p rf = C8dbm/tone, ?f = 2mhz, p lo = 0dbm, v cc = 3.3v, v dd = 3.3v, t c = 25c, unless otherwise noted. band 4: rf = 450mhz, if = 153mhz, high side lo conv gain and iip3 vs rf frequency 0db, 6db and 12db if attenuation ssb nf vs rf frequency 0db, 6db and 12db if attenuation conv gain vs if frequency and if attenuation, swept rf/fixed lo 450mhz conv gain, iip3 and ssb nf vs lo power and case temperature 450mhz conv gain, iip3 and ssb nf vs if attenuation 450mhz rf input and if output p1db vs if attenuation rf isolation vs rf frequency lo leakage vs lo frequency 450mhz conv gain, iip3, nf and rf input p1db vs temperature rf frequency (mhz) 370 g c (db), iip3 (dbm) 27 21 15 24 18 12 9 6 3 0 ?3 430 450 470 490 510 5566 g46 530 410390 g c 0db 12db full power mode 12db iip3 0db 6db 6db rf frequency (mhz) 370 ssb nf (db) 22 20 21 15 18 19 17 16 13 14 12 430 450 5566 g47 530 470 490 510 410390 6db 12db full power mode 0db lo input power (dbm) ?6 g c (db), iip3 (dbm) 25 21 23 11 19 17 15 13 9 7 0 2 4 5566 g49 6 ?2?4 g c nf iip3 t c = ?40c t c = 25c t c = 85c 3db if attenuation full power mode if attenuation (db) 0 g c (db), iip3 (dbm), nf (db) 28 24 8 20 16 12 4 ?4 0 6 8 10 12 14 5566 g50 16 42 g c full power reduced power nf iip3 if attenuation (db) 0 p1db (dbm) 18 16 14 12 10 8 4 6 4 8 12 5566 g51 16 full power reduced power if out p1db rf in p1db rf frequency (mhz) 370 isolation (db) 40 70 60 50 30 20 450 470 490 510 530 5566 g52 410 430 390 rf ?if + or rf ?if ? (unbalanced) channel isolation rf ?lo 3db if attenuation full power mode lo frequency (mhz) 200 lo leakage (dbm) ?20 ?60 ?30 ?40 ?50 ?80 ?70 ?90 500 600 700 800 5566 g53 400300 lo ?if + or lo ?if ? (unbalanced) lo ?rf 3db if attenuation full power mode case temperature (c) ?45 g c (db), nf (db), iip3 (dbm), p1db (dbm) 25 23 13 21 19 17 15 11 9 7 45 75 5566 g54 105 15 ?15 input p1db g c iip3 nf 3db if attenuation full power mode lt c5566 5566f if frequency (mhz) 90 110 130 150 170 190 210 ?7 ?5 rf = 390mhz to 510mhz ?3 ?1 1 3 5 7 9 11 13 conv gain (db) lo = 600mhz, full power mode 5566 g48 15db 12db 9db 6db 3db 0db
14 for more information www.linear.com/LTC5566 p in func t ions gnd (pins 1, 8, 16, 25, exposed pad pin 33): ground. these pins must be soldered to the rf ground plane on the circuit board. the exposed pad provides both electri - cal ground contact and thermal contact to the printed circuit board. rf1, rf2 (pins 2, 7): single-ended rf inputs for channels 1 and 2, respectively. these pins are internally biased to v cc /2 when v cc is applied. therefore, a series dc-blocking capacitor must be used. the internal matching capacitance may be adjusted in four discrete steps using the t0 and t1 control pins, or via the spi interface. csb (pin 3): serial port chip select. this cmos input activates the spi inputs when driven low. when driven high, the inputs are deactivated. see the applications section for more details. clk (pin 4): serial port clock. this cmos input clocks serial port input data on its rising edge. see the applica - tions section for more details. sdi (pin 5) : serial port data input. this cmos input is used to load serial data into the 16- bit register. see the applications section for more details. sdo (pin 6): serial port data output. this cmos three- state output presents data from the serial port during a communication burst. optionally, attach a resistor of > 200k to gnd to prevent a floating output. see the applications section for more details. t0, t1 (pins 9, 32): 2- bit rf input tuning control pins. a cmos logic high will enable the respective bit for both channels when the ps pin is high. these pins have internal 167k pull-down resistors. the rf input tuning may also be controlled through the serial port when ps is low. for serial control only, these pins should be grounded. mo2 C , mo2 + , mo1 + , mo1 C (pins 10, 11, 30, 31): open- collector differential if outputs for mixer 2 and mixer 1, respectively. these pins must be connected to v cc through pull-up inductors. typical dc current is 27ma into each pin. v cc2 , v cc1 (pins 12, 29): power supply pins for channels 2 and 1, respectively. these pins must be connected to a regulated 3.3v supply, with a bypass capacitor located close to the pins. typical dc current consumption is 41ma into each pin. en2, en1 (pins 13, 28): enable control pins for channels 2 and 1, respectively. a cmos logic high will enable each channel. these pins have internal 330k pull-down resistors, so if unconnected, both channels are shutdown. ai2 + , ai2 C , ai1 C , ai1 + (pins 14, 15, 26, 27) : differential if attenuator inputs for channel 2 and channel 1, re - spectively. these pins are internally biased to v cc /2 when v cc is applied. therefore, a series dc-blocking capacitor must be used. i f2 + , if2 C , if1 C , if1 + (pins 17, 18, 23, 24): open-collector differential if buffer outputs for channel 2 and channel 1, respectively. these pins must be connected to v cc through pull-up inductors. typical dc current is 48ma into each pin. ps (pin 19): parallel select pin for rf input tuning. a cmos logic high will enable parallel control using the t1 and t0 pins. a cmos logic low allows the spi port to set the tuning for each channel independently, while ignoring the voltage on the t1 and t0 pins. this pin has an internal 330k pull-down resistor. lo C , lo + (pins 20, 21): differential local oscillator in - put. these pins are internally connected to esd diodes to ground. therefore, series dc-blocking capacitors must be used if the lo sour ce has a dc voltage present. single-ended or differential drive may be used. each pin is internally matched to 50, even when the mixers are disabled. v dd (pin 22): power supply pin for serial interface logic. this pin must be connected to a regulated 1.8v to 3.3v supply. typical dc current consumption is less than 1ma with csb low and the clock running at 10mhz. when idle, typical current consumption is less than 500a. the sup - ply voltage on this pin defines the logic levels for the spi inputs (csb, clk and sdi), the sdo output, and the ps pin. lt c5566 5566f
15 for more information www.linear.com/LTC5566 b lock diagra m rf 5566 bd if1 + if1 ? v dd v dd lo + lo ? ps gnd v cc1 mo1 ? t1 LTC5566 mo1 + en1 ai1 + ai1 ? v cc2 mo2 ? t0 mo2 + en2 ai2 + ai2 ? gnd gnd (exposed pad) gnd 27 30 28 26 25 29 31 32 14 11 13 15 16 12 10 9 rf1 csb clk sdi sdo rf2 gnd 1 2 24 23 22 21 20 19 18 17 3 4 5 6 7 8 33 if spi bias ch 1 att control if2 ? if2 + if bias rf lo lo 5 ch 2 att control 5 por lt c5566 5566f
16 for more information www.linear.com/LTC5566 tes t c ircui t figure 1. test circuit schematic with 100 matched differential if outputs rf input tuning and external matching rf band rf frequency range (hz) parallel tune (ps = high) serial tune (via spi) (ps = low) c1 , c2 l9, l10 t1 t0 rt1[1:0], rt2[1:0] b0 3.1g to 5.1g 0 0 0 4.3pf b1 1.8g to 4.4g 0 1 1 b2 1.3g to 3.9g 1 0 2 b3 0.7g to 1.3g 1 1 3 8.2nh b4 0.39g to 0.53g 1 1 3 12pf 10nh ref des value size vendor ref des value size vendor c18, c19 1f 0603 murata 50v x5r c17 0.3pf 0201 murata 25v npo c1, c2 see table 0402 murata 50v npo l1 to l4, l11 to l14 680nh 0603 coilcraft 0603af c3, c4 2.2pf 0402 murata 50v npo l5 to l8 47nh 0402 coilcraft 0402hp c5 to c8 1nf 0201 murata 50v npo l9, l10 see table 0402 coilcraft 0402hp c9 to c16 10nf 0402 murata 50v x7r l15 to l18 33nh 0402 coilcraft 0402hp rf1 (50) c1 l9 spi bus 5577 ta02a sdi clk t0 v cc2 v cc ai2 ? ai2 + gnd 33 gnd 3 5 rf1 csb 1 gnd 7 4 6 2 8 22 20 24 18 21 19 23 17 rf2 sdo gnd 11 9 13 15 12 10 14 16 t0 mo2 ? mo2 + en2 en2 if1 + if1 ? v dd lo + lo ? ps ps if2 ? if2 + v cc1 v cc t1 t1 mo1 ? mo1 + en1 en1 gndai1 ? ai1 + 32 28 30 26 31 27 29 25 if1 (100 differential) rf2 (50) c2 l10 l11 l13 l17 l15 l5 c9 c11 c3 c8 l8 l6 l2 l4 c6 c14 lo (50) c4 c15 v cc v cc v dd (3.3v) c16 l7 l3 l1 l12 l14 if2 (100 differential) l16 l18 c12 c10 c5 c7 c13 v cc (3.3v) c19 c17 c18 fr4 top gnd dc bottom 0.062? 0.012? 0.016? fr4 ro4003c dc2460a evaluation board layers lt c5566 5566f
17 for more information www.linear.com/LTC5566 introduction the LTC5566 incorporates two identical rf-to-if down - conversion mixers driven by a common lo input. the symmetr y of the ic assures that both mixers are driven with an amplitude- and phase-coherent lo. each chan - nel includes an if dvga (digital variable gain amplifier) consisting of a programmable 15.5db range digital if attenuator with 0.5db steps, and a fixed-gain if buffer amplifier. the cascaded rf-to-if conversion gain ranges from 12db at maximum if gain, to C3.5db at minimum if gain. the if frequency response is flat within 1db from 40mhz to 300mhz, and may be modified by adjusting the values of the external pull-up inductors. the rf inputs have programmable impedance tuning which may be controlled via the spi or dedicated control lines. each channel can be programmed to a reduced power mode via the spi, resulting in a 22% power savings, with reduced linearity performance. the test circuit schematic in figure 1 shows the external components used to char - acterize the ic. the evaluation board is shown in figure 2. rf inputs a block diagram of the channel 1 rf input is shown in figure 3 (channel 2 is identical and not shown). each rf input includes programmable 2-bit rf frequency tuning, followed by an integrated transformer and a differential rf buffer amplifier. the transformer s primary winding is biased at 1.65v dc , and therefore requires an external dc-blocking capacitor. the rf input impedance match for each channel is tuned to one of three overlapping frequency bands ranging from 1.3ghz to 5ghz , by programming the rt1[1:0] and rt2 [1:0] bits (two bits for each channel). series matching capacitor, c1 , is fixed at 4.3pf for these three bands. for rf frequencies below 1.3ghz , the fourth (lowest frequency) tuning band is used in conjunction with shunt inductor l9. figure 3. rf input block diagram figure 2. evaluation board a pplica t ions i n f or m a t ion 5566 f03 par tune inputs v cc1 mux sel 1 0 1 0 mux sel 1 0 1 0 v cc2 330k 9 32 t1 t0 to ch 2 v cc1 c1 rf1 (50) rf1 l9 rf buffer LTC5566 channel 1 rf tune 1.65v dc serial tune inputs rt1[1:0] rt2[1:0] v dd 0 = ser 1 = par 2 19 ps lt c5566 5566f
18 for more information www.linear.com/LTC5566 a pplica t ions i n f or m a t ion figure 1 summarizes the rf tuning and external matching for all frequency bands. the rf input return loss for each band is shown in figure 4. as shown in figure 3, the rf input tuning may also be controlled by the parallel control lines t0 and t1 when the ps (parallel select) control line is high. the tuning bits for this method are also summarized in figure 1, where t0 is the lsb. when using parallel tuning control, both chan - nels are tuned to the same band simultaneously and the spi tuning bits are ignored. the t0 and t1 control lines have internal 167k pull-down resistors and the ps pin has an internal 330k pull-down resistor. all three pins will be pulled low if left floating, allowing the spi to control the rf tuning, although it is recommended to ground these pins if spi control is used. figure 4. rf input return loss for each band lo input a simplified schematic of the lo input is shown in figure 5. as shown, each mixer has its own lo amplifier. a dif - ferential input is provided although the ic is characterized and production-tested with single-ended drive. differential lo drive improves per formance slightly, and is recom - mended if available. each lo input is internally matched to 50 from 150mhz to 3.8ghz, requiring no external components. adding shunt capacitor c17(0.3pf), extends the lo input match up to 6ghz. esd protection diodes on figure 5. lo input schematic figure 6. lo input return loss each input limit the peak voltage swing to approximately 700mv (+7dbm), although higher lo drive, up to 10dbm will not damage the input. an external dc-blocking capacitor is only needed if the lo source has dc voltage present. the measured lo input return loss is shown in figure 6, with and without c17. rf frequency (ghz) 0.3 return loss (db) ?5 0 ?10 ?35 ?30 ?25 ?20 ?15 2.3 1.3 3.8 4.3 4.8 5566 f04 5.3 1.8 0.8 2.8 3.3 b4 b3 b2 b0 b1 t c = 25c 5566 f05 ch 1 mix lo ? lo + lo (0dbm) c17 0.3pf dc block ch 2 mix 21 20 lo frequency (ghz) 0 return loss (db) ?5 0 ?10 ?20 ?15 2 5 6 5566 f06 7 1 3 4 no ext match with c17 (0.3pf) lt c5566 5566f
19 for more information www.linear.com/LTC5566 a pplica t ions i n f or m a t ion if outputs a simplified if output schematic for channel 1, with external matching components is shown in figure 7 (channel 2 is identical, and not shown). the final output stage is differ - ential, open-collector with integrated matching resistors, capacitors and esd protection diodes. each output pin must be biased at the supply voltage (v cc ) using external chokes (l11 and l13). each pin draws approximately 48ma of dc supply current (96ma total). therefore, inductors with low dc resistance (<1), are required for the highest output ip3 and p1db. the integrated output resistors set the differential output resistance at 206. c3, l15 and l17 form a 2:1 imped - ance transformer which transforms the output to 100 differential. if a 200 output is desired, c3 is not used and the values of l15 and l17 are reduced to the values shown in table 1. c9 and c11 are dc-blocking capacitors, which may be omitted if the following stage is already dc-blocked. the standard evaluation board is built with 100 differ - ential if outputs, but also has pads which allow the use of if transformers to provide 50 single-ended outputs. to implement this, it is recommended to use the 200 matching shown in table 1 and 4 :1 if transformers. figure 16 shows the circuit schematic and measured performance using this approach. table 1. if output matching element values differential z out c3 l15, l17 9db return loss bandwidth 200* 15nh 30mhz to 440mhz 100 3.9pf 47nh 70mhz to 242mhz 2.2pf 33nh 87mhz to 352mhz 1.5pf 24nh 105mhz to 450mhz *200 differential output return loss measured with 4:1 transformer on evaluation board. the differential if output impedance vs frequency is listed in table 2. the impedances are at the package pins with no external components. measured if output return losses vs frequency for 100 differential matching is shown in figure 8. table 2. differential if output impedance vs frequency if frequency (mhz) differential impedance (r if || c if ) 10 210 || 1.10pf 50 209 || 1.09pf 100 209 || 1.04pf 150 208 || 0.97pf 200 207 || 0.94pf 300 206 || 0.92pf 400 203 || 0.93pf 500 200 || 0.91pf 600 196 || 0.91pf 700 192 || 0.91pf 800 186 || 0.91pf 900 179 || 0.90pf 1000 172 || 0.89pf figure 7. if output schematic figure 8. if output return loss (100 differential matching) + ? 5566 f07 if1 + l11 l13 l15 c9 c3 if1 out c11 l17 if1 ? v cc v cc v cc 24 23 if frequency (mhz) 50 differential return loss (db) ?10 ?5 0 ?20 ?25 ?15 ?40 ?35 ?30 350 450 5566 f08 550 150 250 1.5pf/24nh 2.2pf/33nh 3.9pf/47nh z o = 100 lt c5566 5566f
20 for more information www.linear.com/LTC5566 a pplica t ions i n f or m a t ion mixer output to if dvga interface the mixer s 300 differential output impedance matches the if dvga s 300 differential input impedance, even over normal process variation due to the monolithic imple - mentation. this assures minimal and repeatable dnl and inl over the full if attenuation range. furthermore, the mixer output and dvga input include integrated matched capacitors, which simplify the realization of a lowpass filter between the mixer and dvga. this filter attenuates undesired high frequency mixing products and lo leakage before entering the dvga. a simplified schematic of the interface for channel 1 is shown in figure 9 (channel 2 is identical and not shown). l5 and l7 connect the mixer output to the dvga input, while forming a 650mhz 3rd-order, 0.2db ripple cheby - shev lowpass filter. l1 and l3 supply dc current to the mixer and c5 and c7 are dc-blocking capacitors. figure 9. mixer to if dvga interface figure 11. 3rd-order bandpass filter realization it s also possible to implement a bandpass filter between the mixer and dvga. an example is shown in figure 11, where a 3rd-order bandpass filter is realized by changing the values of the reactive components and adding c21, c23 and l19. figure 19 shows measured conversion gain vs if output frequency using this bandpass topology. figure 10. equivalent lowpass filter schematic an equivalent ac schematic of the lowpass filter is shown in figure 10, where the mixer output and dvga input are modeled as 300 in parallel with 1pf. the mixer supply chokes and series dc blocking capacitors are ignored in this schematic. if dvga phase vs if attenuation ideally, the phase of the if output would be constant over the full if attenuation range. practically, there is some phase shift due to circuit parasitics in the attenuator. the LTC5566 s if dvga is optimized for the lowest possible phase variation (or phase error) over the full if attenuation range. phase error vs if attenuation for the complete if section is listed in table 3. table 3. if phase error vs if attenuation att (db) 150mhz 250mhz 350mhz 0 ref ref ref 3 C1.1 C1.4 C3.0 6 C1.6 C2.1 C4.2 9 C2.0 C2.8 C5.1 12 C2.2 C3.2 C5.3 15 C2.4 C3.0 C5.5 5566 f11 mo1 ? mixer out dvga in mo1 + ai1 ? ai1 + 1pf 1pf r l 300 r s 300 v cc 31 26 30 27 l5 l19 l7 c21 c5 l1 l3 c7 c23 5566 f09 mo1 ? mix out (ch 1) if att in (ch 1) mo1 + ai1 + ai1 ? v cc v cc v cc 150 2pf 2pf 150 v cc 31 30 1.65v v cc 150 2pf 2pf 150 27 26 c5, 1nf l5, 47nh l3 680nh l1 680nh c7, 1nf l7, 47nh 27ma 27ma 5566 f10 mo1 ? mo1 + ai1 ? ai1 + 1pf 1pf r l 300 r s 300 31 26 30 27 l5, 47nh l7, 47nh lt c5566 5566f
21 for more information www.linear.com/LTC5566 a pplica t ions i n f or m a t ion downconverter performance vs if attenuation rf-if conversion gain, iip3, oip3 and noise figure over the full 15.5db attenuation range is shown in figure 12. the same data is listed in table 4 with the inl and dnl at each attenuator setting. table 4. conversion gain, iip3, oip3 and ssb nf vs if attenuation (rf = 2.6ghz, if = 153mhz, high side lo) a (db) i f 1[ 4:0] i f2 [ 4:0] g c (db) ii p3 (dbm) oip3 (dbm) nf (db) dnl (db) inl (db) 0 0 11.84 23.2 35.0 13.3 0.5 1 11.32 23.3 34.6 13.4 0.03 0.03 1.0 2 10.75 23.4 34.2 13.6 0.07 0.09 1.5 3 10.24 23.6 33.8 13.7 0.01 0.10 2.0 4 9.75 24.0 33.8 13.8 C0.01 0.09 2.5 5 9.24 24.2 33.5 13.9 0.01 0.10 3.0 6 8.75 24.6 33.4 14.1 C0.01 0.09 3.5 7 8.24 24.9 33.2 14.2 0.01 0.11 4.0 8 7.75 25.1 32.8 14.4 C0.01 0.10 4.5 9 7.24 25.5 32.8 14.6 0.01 0.11 5.0 10 6.75 25.7 32.4 14.8 C0.01 0.10 5.5 11 6.23 25.9 32.1 15.0 0.01 0.11 6.0 12 5.75 26.1 31.8 15.3 C0.01 0.10 6.5 13 5.23 26.5 31.7 15.5 0.01 0.11 7.0 14 4.74 26.4 31.1 15.7 C0.01 0.10 7.5 15 4.22 26.9 31.1 15.9 0.03 0.13 8.0 16 3.73 26.7 30.4 16.2 C0.02 0.11 8.5 17 3.21 27.1 30.4 16.5 0.02 0.14 9.0 18 2.73 26.9 29.6 16.9 C0.02 0.12 9.5 19 2.20 27.4 29.6 17.2 0.03 0.14 10.0 20 1.72 27.1 28.8 17.5 C0.02 0.13 10.5 21 1.20 27.6 28.8 17.8 0.02 0.15 11.0 22 0.71 27.3 28.0 18.2 C0.01 0.14 11.5 23 0.18 27.5 27.7 18.6 0.02 0.16 12.0 24 C0.31 27.6 27.3 19.0 C0.01 0.15 12.5 25 C0.84 27.8 27.0 19.4 0.03 0.18 13.0 26 C1.33 27.3 26.0 19.8 C0.02 0.17 13.5 27 C1.85 27.9 26.1 20.2 0.03 0.19 14.0 28 C2.35 28.0 25.7 20.7 0.00 0.19 14.5 29 C2.87 28.2 25.3 21.1 0.02 0.21 15.0 30 C3.36 28.0 24.6 21.5 0.00 0.20 15.5 31 C3.89 28.1 24.2 22.0 0.03 0.23 individual stage performance the LTC5566 is characterized, specified and production- tested as a complete downconverter, from the rf inputs to the final if outputs. for some applications, it may be preferred to insert a higher selectivity if filter between the mixer and if dvga. to help with system performance calculations, the nominal performance of the mixer is shown in table 5 and the if dvga performance is listed in table 6. this information is provided for reference only as these blocks are not production-tested independently. table 5. mixer power conversion gain, iip3 and ssb nf (rf = 2.6ghz, if = 153mhz, high side lo, band 1 rf tune) full pwr mode reduced pwr mode g p (db) iip3 (dbm) nf (db) g p (db) iip3 (dbm) nf (db) C0.5 28.0 12.2 C0.7 23.0 11.8 table 6. if dvga power gain, oip3 and ssb nf (153mhz) if att (db) full p wr mode reduced pwr mode gain (db) oip3 (dbm) nf (db) gain (db) oip3 (dbm) nf (db) 0 12.0 36.4 5.7 11.8 33.2 5.6 3 9.0 35.7 9.3 8.8 33.0 9.3 6 6.0 35.7 12.3 5.8 33.1 12.3 9 3.0 35.7 15.4 2.8 32.9 15.3 12 0.0 35.4 18.4 C0.2 32.9 18.4 15 C3.0 35.0 21.4 C3.2 32.7 21.4 figure 12. downconverter rf-if conversion gain, iip3, oip3 and noise figure vs if attenuation. if attenuation (db) 0 g c (db), nf (db), iip3 (dbm), oip3 (dbm) 36 6 30 24 18 12 0 ?6 10 12 14 5566 f12 16 8642 g c nf oip3 iip3 rf = 2.6ghz if = 153mhz high side lo t c = 25c full power mode lt c5566 5566f
22 for more information www.linear.com/LTC5566 a pplica t ions i n f or m a t ion enable inputs figure 13 shows a schematic of the channel 1 enable in- terface. channel 2 is identical and not shown. as shown, the positive esd diodes for e n1 are connected to v cc1 . the positive esd diodes for channel 2 are connected to v cc2 (not shown). to enable a channel, the applied volt - age must be greater than 1.4v. an applied voltage less than 0.5v will disable the channel. if the enable function is not needed, the enable pin can be connected directly to the adjacent v cc pin. if left floating, the internal 330k pull-down resistor will disable the channel. the voltage on the enable pins should never exceed v cc by more than 0.3v , otherwise supply current may be sourced through the upper esd diodes. under no circumstances should voltage be applied to the enable pins before supply voltage is applied to the v cc pins. if this occurs, damage to the ic may result. spi description if dvga attenuator control, rf input tuning and reduced power mode for each downconverter channel is pro - grammed through the 3-wire spi consisting of csb, clk and sdi. a fourth pin, sdo, is a serial output available to read out the contents of the registers. the sdo pin may also be used to daisy-chain multiple spi interfaces on a single bus. for example, in an 8-channel mimo receiver application, all four LTC5566 dual downconverters can be programmed with a single, 64-bit load, while sharing a common csb line. a block diagram of the spi is shown in figure 14. as shown, it is a 16- bit double-buffered fifo slave architecture, with 8-bits for each channel. logic levels for the digital inputs and sdo output are 1.8v to 3.3v cmos compatible, de - termined by the supply voltage on the v dd pin. an internal por (power-on-reset) connected to the v dd pin, resets all 16 bits to logic 0 at power-up, or when v dd drops below 0.9v and then rises back above 1.2v. the por requires approximately 100s to reset the registers. spi programming data transfers to the part are accomplished by first tak - ing csb low to enable the port. then, serial input data on sdi is captured on the rising edge of clk and shifted into a 16- bit shift register, msb first. serial data from the registers is driven out to sdo on the clocks falling edge. the communication burst is terminated by taking csb high. the rising edge on csb will then latch the shift- registers contents into a 16-bit buffer d-latch. the buffer latch prevents the downconverters gain, rf input tuning and power mode from changing while data is loaded. see figure 15 for timing details. when csb is high, the clock and data inputs are internally gated off, minimizing current consumption when not se - lected, and the sdo output is high impedance. however, it is recommended that the serial interface signals should remain idle between data transfers to avoid digital noise coupling into the rf signal paths. figure 13. channel 1 enable pin interface supply voltage ramping fast ramping of the supply can cause a current glitch in the internal esd protection circuits. depending on the supply inductance, this could result in a supply voltage transient that exceeds the maximum rating. a supply voltage ramp time greater than 1ms is recommended. 5566 f13 v cc1 en1 250 330k 29 28 ch 1 bias lt c5566 5566f
23 for more information www.linear.com/LTC5566 a pplica t ions i n f or m a t ion figure 14. spi block diagram figure 15. spi timing diagram 5566 f14 sdi clk csb (lsb) d0 d1 v dd (msb) d15 dqdq dqdq rb sdo 16-bit latch por d[7:0] (ch 1) d[15:8] (ch 2) rb rb rb rb ? ? ? d0 d15 5566 f15 clk sdi t enable t delay t rise,fall t hold t disable t hold(csb) t setup t setup(csb) sdo csb lt c5566 5566f
24 for more information www.linear.com/LTC5566 a memory map of the register contents is shown in table 7, with detailed bit descriptions in table 8. each register s default power -up value is also shown in t able 8, which is: ? 0db if attenuation (maximum gain) ? full power mode ? rf inputs tuned to band 0 (highest frequency) table 7. serial port register contents channel 2 (8 bits) msb d15 d14 d13 d12 d11 d10 d9 d8 rp2 rt 2 [1] rt2 [0] if2[4] if2[3] if2[2] if2[1] if2[0] channel 1 (8 bits) d7 d6 d5 d4 d3 d2 d1 lsb d0 rp1 rt 1 [1] rt1 [0] if1[4] if1[3] if1[2] if1[1] if1[0] table 8. serial port register bit field summary bits description default if1[4:0] ch. 1 if attenuator control 00000 (max gain) rt1 [1:0] ch. 1 rf tuning 00 (band 0) rp1 ch. 1 reduced power 0 (full power) if2[4:0] ch. 2 if attenuator control 00000 (max gain) rt2 [1:0] ch. 2 rf tuning 00 (band 0) rp2 ch. 2 reduced power 0 (full power) spurious output levels spurious output levels vs harmonics of the rf and lo are tabulated in table 9. the spur levels were measured using the test circuit shown in figure 1, with an rf input power of C6dbm and 6db of if attenuation. table 9a shows the relative spur levels in full power mode and tables 9b shows the relative spur levels in reduced power mode. the mixer spur levels are insensitive to the if attenuation setting. the spur frequencies can be calculated using the follow - ing equation: f spur = (m ? f rf ) C (n ? f lo ) table 9. if output spur levels (dbc). (rf = 2.6ghz, p rf = C6dbm, if = 153mhz, high side lo, p lo = 0dbm, 6db if attenuation, t c = 25c) table 9a. full power mode n 0 1 2 3 4 5 6 7 m 0 C52 * * C80 C79 C79 * 1 * 0 * * * * C80 C80 2 * * C68 * * * * C80 3 * * * C77 * * * * 4 * * * * * * * * 5 * * * * * * * * 6 C80 * * * * * * * 7 * C80 * * * * * * *less than C80dbc table 9b. reduced power mode n 0 1 2 3 4 5 6 7 m 0 C52 * * C80 C79 C78 * 1 * 0 * * * * C80 C80 2 * * C68 * * * * C79 3 * * * C72 * * * * 4 * * * * * * * * 5 * * * * * * * * 6 C79 * * * * * * * 7 * C80 * * * * * * *less than C80dbc rf and lo port s-parameters s11 vs frequency for the rf and lo port are listed in table 10. data is shown for all four rf tuning states. the data is referenced to the ic pin with no external matching. a pplica t ions i n f or m a t ion lt c5566 5566f
25 for more information www.linear.com/LTC5566 a pplica t ions i n f or m a t ion table 10. rf and lo port s11 rf input lo input (single-ended) rt = 00 rt = 01 rt = 10 rt = 11 freq (mhz) mag angle () mag angle () mag angle () mag angle () mag angle () 200 0.77 C160.1 0.77 C160.1 0.77 C160.1 0.77 C160.1 0.29 C61.1 300 0.72 179 0.71 178 0.72 178 0.71 178 0.21 C63.5 400 0.68 167 0.65 167 0.67 167 0.66 167 0.18 C65.2 500 0.64 160 0.61 160 0.63 160 0.62 160 0.17 C66.2 600 0.61 154 0.57 155 0.60 154 0.59 155 0.16 C68.7 700 0.60 149 0.55 150 0.58 149 0.56 150 0.16 C71.8 800 0.58 146 0.52 147 0.56 146 0.54 146 0.16 C75.0 900 0.57 142 0.49 144 0.54 142 0.52 143 0.16 C77.9 1000 0.56 139 0.47 142 0.53 139 0.50 140 0.16 C81.3 1500 0.51 124 0.36 136 0.46 126 0.40 130 0.16 C102.8 2000 0.46 110 0.26 143 0.37 113 0.29 124 0.19 C128.6 2500 0.39 91.5 0.24 165 0.26 100 0.19 133 0.24 C142.9 3000 0.32 68.7 0.31 172 0.14 89 0.17 160 0.26 C154.6 3500 0.24 40.0 0.38 167 0.04 119 0.23 172 0.28 C175.1 4000 0.11 C3.0 0.47 158 0.15 C174 0.34 168 0.35 165.4 4500 0.11 C139 0.54 148 0.30 174 0.45 157 0.42 156.9 5000 0.29 173 0.58 139 0.43 158 0.52 147 0.42 147.3 5500 0.40 153 0.61 135 0.50 147 0.57 141 0.43 127.5 5800 0.46 137 0.65 129 0.55 137 0.61 133 0.45 115.0 6000 0.48 128 0.66 125 0.56 130 0.62 129 0.47 108.8 figure 16. test circuit and measured conversion gain using 200 output matching with a 4:1 if transformer to realize a 50 single-ended if output rf to if conv gain vs if frequency 200 output with 4:1 transformer 5566 f16a ? LTC5566 680nh v cc 680nh mo1 + mo1 ? ai1 ? ai1 + lo if1 + if1 ? rf1 rf1 (5 0) rf1 (50 ) 4.3pf 1nf 1nf 47nh 47nh if 680nh 15nh 15nh v cc 680nh 10nf 10nf 4:1 lt c5566 5566f 15db if output frequency (mhz) 50 100 150 200 250 300 350 ?8 rf = 2.4ghz to 2.7ghz ?6 ?4 ?2 0 2 4 6 8 10 12 lo = 2.75ghz conv gain (db) 5566 f16b band 1 0db 3db 6db 9db 12db
26 for more information www.linear.com/LTC5566 typical a pplica t ions figure 18. measured performance using 5.8ghz rf input matching conv gain, iip3 and nf vs lo power conv gain vs if frequency and if attenuation swept rf / fixed lo conv gain and iip3 vs rf frequency 0db, 6db and 12db if attenuation figure 17. 5.8ghz input matching 5.8ghz rf application the LTC5566 s rf inputs are optimized for operation up to 5ghz , but may be used up to 6ghz with degraded performance. figure 17 shows an example where the rf input is matched for 5.8ghz operation. the rf tuning bits are set to rt1 [1:0] = 00 for the lowest internal capacitance (i.e. highest frequency operation). the measured performance is summarized in figure 18. 5566 f17 LTC5566 (channel 1 shown) rf1 0.15pf rf 5.8ghz (50) 0.55pf 2 rf frequency (mhz) 5650 g c (db), iip3 (dbm) 35 25 30 0 20 15 10 5 ?5 ?10 5800 5850 5900 5566 f18a 5950 5750 5700 g c 0db iip3 0db if attenuation 6db 12db if = 153mhz low side lo p lo = 0dbm full power mode 12db 6db lo input power (dbm) ?6 conversion gain (db) 5 4 3 2 1 0 iip3 (dbm), nf (db) 30 28 26 24 22 20 2 4 5566 f18b 6 0?2?4 g c nf iip3 rf = 5.8ghz if = 153mhz low side lo 3db if attenuation full power mode if frequency (mhz) 50 conversion gain (db) 5 3 ?7 1 ?1 ?3 ?5 ?9 ?15 ?11 ?13 150 200 250 300 5566 f18c 350 100 0db rf = 5.65ghz to 5.95ghz lo = 5.6ghz, p lo = 0dbm 3db 6db 9db 12db 15db lt c5566 5566f
27 for more information www.linear.com/LTC5566 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www.linear.com/product/LTC5566#packaging for the most recent package drawings. 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) lt c5566 5566f
28 for more information www.linear.com/LTC5566 ? linear technology corporation 2017 lt 0117 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC5566 r ela t e d p ar t s typical a pplica t ion part number description comments infrastructure ltc5569 300mhz to 4ghz dual active downconverting mixer 2db gain, 26.7dbm iip3 and 11.7db nf at 1950mhz, 3.3v/180ma supply ltc6430 high linearity differential rf/if amplifier 51dbm oip3 at 240mhz, 100 differential ltc6409 10ghz gbw differential amplifier dc-coupled, 48dbm oip3 at 140mhz, 1.1nv/hz input noise density ltc6412 31db linear analog vga 35dbm oip3 at 240mhz, continuous gain range C14db to 17db ltc5544 4ghz to 6ghz downconverting mixer family 7.4db gain, >25dbm iip3, 11.3db nf, 3.3v/200ma supply lt5554 ultralow distortion if digital vga 48dbm oip3 at 200mhz, 2db to 18db gain range, 0.125db gain steps ltc5576 3ghz to 8ghz active upconverting mixer 25dbm oip3, C0.6db gain, C154dbm/hz output noise floor, C36dbm lo leakage ltc5548 2ghz to 14ghz wideband microwave mixer up- or down-conversion, 21.4dbm iip3 at 9ghz, 0dbm lo drive, if bandwidth dc to 6ghz ltc5549 2ghz to 14ghz wideband microwave mixer up- or down-conversion, 22.8dbm iip3 at 12ghz, 0dbm lo drive, integrated balun with if bw = 500mhz to 6ghz ltc5593 dual 2.3ghz to 4.5ghz downconverting mixer 8.5db gain, 27.7dbm iip3, 9.5db noise figure rf pll/synthesizer with vco ltc6946 low noise, low spurious integer-n pll with integrated vco 373mhz to 5.79ghz, C157dbc/hz wb phase noise floor, C100dbc/hz closed-loop phase noise ltc6948 low noise, low spurious frac-n pll with integrated vco 373mhz to 6.39ghz, C157dbc/hz wb phase noise floor, C274dbc/hz normalized in-band 1/f noise adcs ltc2145-14 14-bit, 125msps 1.8v dual adc 73.1db snr, 90db sfdr, 95mw/ch power consumption ltc2185 16-bit, 125msps 1.8v dual adc 76.8db snr, 90db sfdr, 185mw/channel power consumption ltc2158-14 14-bit, 310msps 1.8v dual adc, 1.25ghz full- power bandwidth 68.8db snr, 88db sfdr, 362mw/ch power consumption, 1.32v p-p input range figure 19. test circuit and measured conversion gain with 3rd-order bandpass interstage filter 5566 f19a ? LTC5566 mo1 + mo1 ? ai1 ? ai1 + lo if1 + if1 ? rf1 rf1 (5 0) 4.3pf l1, l3 = 91nh c5, c7 = 4.3pf c21, c23 = 3.3pf l5, l7, l19 = 180nh 3rd-order chebyshev bpf 0.2db passband ripple f 0 = 190mhz, bw = 155mhz 680nh v cc 680nh 2.2pf if 33nh 33nh 10nf if1 (100 diff) 10nf v cc l5 l19 l7 l1 l3 c5 c7 c21 c23 rf to if conv gain vs if frequency with 190mhz bp interstage filter lt c5566 5566f 3.7ghz 0db 3db 6db 9db 12db 15db if output frequency (mhz) 30 100 rf = 3.465?3.965ghz 600 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 6 lo = 3.435ghz 12 conv gain (db) 5566 f19 if = 30?530mhz 0db to 15db if atten band 0 rf = 3.55ghz rf =

▲Up To Search▲

Price & Availability of LTC5566

	To Download LTC5566 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .