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| fn9257 rev 2.00 page 1 of 14 march 7, 2008 fn9257 rev 2.00 march 7, 2008 ISL8104 8v to 14v, single-phase synchronous buck pulse-width modulation (pwm) controller with integrated gate drivers datasheet the ISL8104 is a 8v to 14v synchronous pwm controller with integrated mosfet drivers. the controller features the ability to safely start-up int o prebiased output loads and provides protection against o vercurrent fault events. overcurrent protection is implemented using top-side mosfet r ds(on) sensing, eliminating the need for a current sensing resistor. the ISL8104 employs voltage -mode control with dual-edge modulation to achieve fast trans ient response. the operating frequency is adjustable from 50khz to 1.5mhz with full (0% to 100%) pwm duty cycle capabi lity. the error amplifier features a 15mhz ( typ) gain-bandwidth product and 6v/s slew rate enabling high converter bandwidth. the output voltage of the conve rter can be regulated to as low as 0.597v with a tol erance of 1.0% over the commercial temperature range (0c to +70c), and 1.5% over industrial temperatur e range (-40c to +85c). provided in the qfn package , a ss pin and refin pin enable supply sequencing and vo ltage tracking functionality. pinouts features ? +8v 5% to +14v 10% bias voltage range - 1.5v to 15.4v i nput voltage range ? 0.597v internal reference voltage - ? 1.0% over the commercial temperature range - ? 1.5% over the industrial temperature range ? voltage-mode pwm control with dual-edge modulation ? 14v high speed n-channel mosfet gate drivers - 2.0a source/3a sink at 14 v bottom-side gate drive - 1.25a source/2a sink a t 14v top-side gate drive ? fast transient response - 15mhz (typ) gain-bandwidth e rror amplifier with 6v/s slew rate - full 0% to 100% duty cycle support ? programmable operating frequency from 50khz to 1.5mhz ? lossless programmable o vercurrent protection - top-side mosfets r ds(on) sensing - ~120ns blanking time ? sourcing and sinking current capability ? support for start-up into prebiased loads ? soft-start done and an ext ernal reference pin for tracking applications are available in the qfn package ? pb-free available (rohs compliant) applications ? test and measurement instruments ? distributed dc/dc power architecture ? industrial applications ? telecom/datacom applications ISL8104 (16 ld qfn) top view ISL8104 (14 ld soic) top view ssdone ss comp fb en refin fset pgnd pvcc tgate tsoc lx vcc gnd bgate boot 1 3 4 15 16 14 13 2 12 10 9 11 6 578 ss comp fb en gnd fset pgnd vcc tgate 12 13 14 11 10 9 8 1 2 3 4 5 7 6 tsoc lx pvcc bgate boot ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL8104cbz* 8104cbz 0 to +70 14 ld soic m14.15 ISL8104ibz* 8104ibz -40 to +85 14 ld soic m14.15 ISL8104crz* 81 04crz 0 to +70 16 ld 4x4 qfn l16.4x4 ISL8104irz* 81 04irz -40 to +85 16 ld 4x4 qfn l16.4x4 ISL8104eval1z evaluation board ISL8104eval2z evaluation board *add -t suffix for tape and re el. please refer to tb347 for d etails on reel specifications. note: these intersil pb-free plas tic packaged products employ special pb-free material sets; m olding compounds/die attach mat erials and 100% matte tin plate plus anneal - e3 termination finish, w hich is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb- free products are msl classif ied at pb-free peak reflow temperatures that meet or exceed the pb-fre e requirements of ipc/jedec j std-020.
fn9257 rev 2.00 page 2 of 14 march 7, 2008 ISL8104 block diagram soft-start boot tgate gnd fb and fault logic comp pgnd bgate ea pwm pvcc vcc gate control logic internal regulator oscillator fset 30 ? a ssdone ss power-on reset (por) (qfn only) refin v ref = 0.597 v reference en (qfn only) tsoc 200 a source ocp lx 6 a ISL8104 fn9257 rev 2.00 page 3 of 14 march 7, 2008 typical application wit h single power supply typical application with separated power supplies ISL8104 +8v to +14v q1 q2 comp fb gnd vcc boot tgate bgate l out c hfin c bin c boot c hfout c bout r 2 r 1 c 1 c 2 c f1 d boot v out pgnd pvcc c f2 refin ss r 0 c ss r fset r 3 c 3 ssdone r filter r tsoc c tsoc tsoc lx fset (qfn only) (qfn only) en l in v in ISL8104 +8v to +14v q1 q2 comp fb gnd vcc boot tgate bgate l out c hfin c bin c boot c hfout c bout r 2 r 1 c 1 c 2 c f1 d boot v out pgnd pvcc c f2 refin ss r 0 c ss r fset r 3 c 3 ssdone r tsoc c tsoc tsoc lx fset (qfn only) (qfn only) en v cc +1.5v to +15.4v v in r filter ISL8104 fn9257 rev 2.00 page 4 of 14 march 7, 2008 absolute maximum ratings thermal information supply voltage, v pvcc , v vcc . . . . . . . . . . . . . gnd - 0.3v to +16v enable voltage, v en . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +16v soft-start done voltage, v ssdone . . . . . . . . . . gnd - 0.3v to +16v tsoc voltage, v tsoc . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +16v boot voltage, v boot . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +36v lx voltage, v lx . . . . . . . . . . . . . . . . v boot - 16v to v boot + 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 5.0v esd rating esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 2 operating conditions supply voltage, v vcc . . . . . . . . . . . . . . . . .+8v ? 5% to +14v ? 10% supply voltage, v pvcc . . . . . . . . . . . . . . . .+8v ? 5% to +14v ? 10% boot to phase voltage, v boot - v lx . . . . . . . . . . . . . . . . . ISL8104 fn9257 rev 2.00 page 5 of 14 march 7, 2008 functional pin description (qfn/soic) ss (pin 1/3) connect a capacitor from this pi n to ground. this capacitor, along with an internal 30a current source, sets the soft-start interval of the converter. comp (pin 2/4) and fb (pin 3/5) comp and fb are the available external pins of the error amplifier. the fb pin is the in verting input of the error amplifier and the comp pin is the error amplifier output. these pins are used to com pensate the voltage-control feedback loop of the converter. en (pin 4/6) this pin is a ttl compatible input. pull this pin below 0.8v to disable the converter. in shutdown the soft-start pin is discharged and the tgate and bgate pins are held low. refin (qfn only pin 5) upon enable if refin is less than 2.2v, the external reference pin is used as the cont rol reference instead of the internal 0.597v reference. an internal 6a pull-up to 5v is provided for disabling this functionality. gnd (pin 6/7) signal ground for th e ic. all voltage levels are measured with respect to this pin. oscillator trim test frequency r fset = open v vcc = 12 175 200 220 khz total variation (note 4) 8k ? < r fset to gnd < 200k ?? - ? 15 - % ramp amplitude ? v osc r fset = open 1.7 1.9 2.15 v p-p ramp bottom (note 4) -1- v error amplifier dc gain (note 4) r l = 10k ? , c l = 100pf - 88 - db gain-bandwidth product (note 4) gbwp r l = 10k ? , c l = 100pf - 15 - mhz slew rate (note 4) sr r l = 10k ? , c l = 100pf - 6 - v/ ? s comp source current (note 4) i compsrc -2-ma comp sink current (note 4) i compsnk -2-ma gate drivers top-side drive source current (note 4) i t_source v boot - v lx = 14v, 3nf load - 1.25 - a top-side drive source impedance r t_source 90ma source current - 2.0 - ? top-side drive sink current (note 4) i t_sink v boot - v lx = 14v, 3nf load - 2 - a top-side drive sink impedance r t_sink 90ma source current - 1.3 - ? bottom-side drive source current (note 4) i b_source v pvcc = 14v, 3nf load - 2 - a bottom-side drive source impedance r b_source 90ma source current - 1.3 - ? bottom-side drive sink current (note 4) i b_sink v pvcc = 14v, 3nf load - 3 - a bottom-side drive sink impedance r b_sink 90ma source current - 0.94 - ? protection tsoc current i tsoc t j = 0 c to +70 c 180 200 220 ? a t j = -40 c to +85 c 176 200 224 ? a tsoc measurement offset (note 4) ocp offset tsoc = 1.5v to 15.4v - ? 10 - mv soft-start soft-start current i ss 22 30 38 ? a ssdone low output voltage (qfn only) i ssdone = 2ma - - 0.30 v electrical specifications recommended operating conditions, unless otherwise noted, speci fications in bold are valid for process, temperature, and line operating conditions. (continued) parameter symbol test conditions min typ max units ISL8104 fn9257 rev 2.00 page 6 of 14 march 7, 2008 lx (pin 7/8) this pin connects to the source of the top-side mosfet and the drain of the bottom-side mo sfet. this pin represents the return path for the top-si de gate driver . during normal switching, this pin is used f or top-side current sensing. tgate (pin 8/9) connect tgate to the top-side mosfet gate. this pin provides the gate drive for the top-side mosfet. boot (pin 9/10) this pin provides bias to the top-side mosfet driver. a bootstrap circuit may be used to create a boot voltage suitable to drive a standard n-channel mosfet. pgnd (pin 10/11) this is the power ground connection. t ie the bottom-side mosfet source and board ground to this pin. bgate (pin 11/12) connect bgate to the bottom-side mosfet gate. this pin provides the gate drive for the bott om-side mosfet. pvcc (pin 12/13) provide an 8v to 14v bias supply for the bottom-side gate drive to this pin. this pin should be bypassed with a capacitor to pgnd. vcc (pin 13/14) provide an 8v to 14v bias supply for the chip to this pin. the pin should be bypassed with a capacitor to gnd. fset (pin 14/1) this pin provides oscillator s witching frequency adjustment. by placing a resistor (r fset ) from this pi n to gnd, the switching frequency is set from between 200khz and 1.5mhz according to equation 1: alternately ISL8104s switchi ng frequency can be lowered from 200khz to 50khz by con necting the fset pin with a resistor to vcc a ccording equation 2: tsoc (pin 15/2) the current limit is programmed by connecting this pin with a resistor and capacitor to the d rain of the top-side moseft. a 200a current source develops a voltage across the resistor which is then compar ed with the voltage developed across the top-side mosfet. a blanking period of 120ns is provided for noise immunity. ssdone (qfn only pin 16) provides an open drain signa l at the end of soft-start. functional description initialization the ISL8104 automatically initi alizes upon receipt of power. special sequencing of the inpu t supplies is not necessary. the power-on reset (por) fun ction continually monitors the bias voltage at the vcc pi n and the driver input on the pvcc pin. when the voltages at vcc and pvcc exceed their rising por thresholds, a 30a current source driving the ss pin is enabled. upon th e ss pin exceeding 1v, the ISL8104 begins ramping the non-in verting input of the error amplifier from gnd to the system refer ence. during initialization the mosfet d rivers pull tgate to lx and bgate to pgnd. soft-start during soft-start, an internal 30a current source charges the external capacitor (c ss ) on the ss pin up to ~4v. if the ISL8104 is utilizing the internal reference, then as the ss pin s voltage ramps from 1v to 3v, the soft-start function scales the r fset k ? ?? 6500 f s khz ?? 200 khz ?? C ------------------------------------------------------- 1.3 C ?? ?? k ? ? (r fset to gnd) (eq. 1) r fset k ? ?? 55000 200 khz ?? f s khz ?? C ------------------------------------------------------- 70 + ?? ?? k ? ? (r fset to vcc) (eq. 2) figure 1. r fset resistance vs frequency 10k 100k 1m switching frequency (hz) resistance (k ? ) 10 100 1000 r fset pullup to vcc r fset pull-down to gnd figure 2. bias supply current vs frequency 100k 200k 300k 400k 500k 600k 700k 800k 900k 1m 80 70 60 50 40 30 20 10 0 i pvcc+vcc (ma) switching frequency (hz) c gate = 1000pf c gate = 3300pf c gate = 10pf ISL8104 fn9257 rev 2.00 page 7 of 14 march 7, 2008 reference input (positive term inal of error am p) from gnd to vref (0.597v nominal). if the ISL8104 is utilizing an externally supplied reference, when the voltage on the ss pin reaches 1v, the internal referen ce input (into the error amp) ramps from gnd to the externally supplied reference at the same rate as the voltage on the ss pin. figure 3 shows a typical soft-start interval. the rise time of the output voltag e is, therefore, dependent upon the value of the soft-start capacitor, c ss . if the internal referenc e is used, then the soft-start capacitance val ue can be calculated through equation 3: if an external reference i s used then the soft-start capacitance can be calcul ated through equation 4: prebiased load start-up drivers are held in tri-state (tgate pulled to lx, bgate pulled to pgnd) at the beginnin g of a soft-start cycle until two pwm pulses are detected. the bottom-side mosfet is turned on first to provide for chargi ng of the bootstrap capacitor. this method of driv er activation provides support for start-up into prebiased loads by not activating the drivers until the control loop has entered its li near region, thereby substantially reducing output transients that would otherwise occur had the drivers been activated at the beginning of the soft-start cycle. ssdone soft-start done is only availabl e in the 16 ld qfn packaging option of the ISL8104. when the so ft-start pin reaches 4v, an open drain signal is provided to support sequencing requirements. ssdone is deasse rted by disabling of the part, including pulling ss low, and by por and ocp events. oscillator the oscillator is a triangular wa veform, providing for leading and falling edge modulation. the peak-to-peak of the ramp amplitude is set at 1.9v and varies as a function of frequency. at 50khz the peak to peak amp litude is approximately 1.8v while at 1.5mhz it is approximately 2.2v. in the event the regulator operates at 100% duty cycle for 64 c lock cycles an automatic boot cap refresh circuit will activate turning on bgate for approximately 1/2 of a clock cycle. overcurrent protection the ocp function is enabled wit h the drivers at start-up. ocp is implemented via a resistor (r tsoc ) and a capacitor (c tsoc ) connecting the tsoc pin and the drain of the top-side moseft. an internal 200 m a current source develops a voltage across r tsoc , which is then compared with the voltage developed acro ss the top-side mosfet at turn on as measured at the lx pin. when the voltage drop across the mosfet exceeds t he voltage drop across the resistor, a sourcing ocp event occurs. c tsoc is placed in parallel with r tsoc to smooth the voltage across r tsoc in the presence of switchi ng noise on th e input bus. a 120ns blanking period is us ed to reduce the current sampling error due to leadin g-edge switching noise. an additional simultaneous 120ns low pass filter is used to further reduce measurem ent error due to noise. ocp faults cause the regul ator to disable (top- and bottom-side drives disabled, ssdone pulled low, soft-start capacitor discharged) itself for a fixed pe riod of time, after which a normal soft-start sequence is initiated. if the voltage on the ss pin is already at 4v and an ocp is detected, a 30 ? a current sink is immediatel y applied to the ss pin. if an ocp is detected during soft-sta rt, the 30a current sink will not be applied until the voltage on the ss pin has reached 4v. this current sink discharges the c ss capacitor in a linear fashion. once the voltage on the ss pin has reached approximately 0v, the normal soft-start sequence is initiated. if the fault is still present on the subsequent restart, the isl81 04 c ss 30 ? at ss ? 2v ---------------------------- = (eq. 3) c ss 30 ? at ss ? v refext ---------------------------- = (eq. 4) figure 3. typical soft-start interval v en v out v ss t ss figure 4. typical overcurrent protection v ssdone v ss i load t hiccup i ocp ISL8104 fn9257 rev 2.00 page 8 of 14 march 7, 2008 will repeat this process in a hiccup mode. figure 4 shows a typical reaction to a repeated overcurrent condition that places the regulator in a hi ccup mode. if the regulator is repeatedly tripping overcurr ent, the hiccup period can be approximated by equation 5: the ocp trip point varies mainly due to mosfet r ds(on) variations and layout noise conc erns. to avoid overcurrent tripping in the normal operating load range, find the r ocset resistor from the foll owing equations with: 1. the maximum r ds(on) at the highest junction temperature 2. the minimum i tsoc from the specification table determine the overcurrent t rip point greater than the maximum output continuous cu rrent at maximum inductor ripple current. high speed mosfet gate driver the integrated dri ver has the same drive capability and feature as the inter sils 12v gate driver, isl6612. the pwm tri-state feature hel ps prevent a negative transient on the output voltage when t he output is being shut down. this eliminates the schottky diode that is used i n some systems for protecting the loads from reversed-output-voltage damage. see the isl6612 data sheet fn9153 for specification parameters that are not defined in the current ISL8104 electrical specifications table on page 4. reference input the refin pin allows the user to bypass the internal 0.597v reference with an external reference. if refin is not above ~2.2v, the external reference pin is used as the control reference instead of the internal 0.597v reference. when not using the external reference opt ion, the refin pin should be left floating. an internal 6a pull-up keeps this refin pin above 2.2v in this situation. internal reference and system accuracy the internal reference is set to 0.597v. the total dc system accuracy of the system is to be within 1.5% over the industrial temperature range. system accu racy includes error amplifier offset, and reference error. the use of refin may add up to 3mv of offset error into the sy stem (as the error amplifier offset is trimmed ou t via the internal s ystem reference). application guidelines layout considerations as in any high frequen cy switching converter, layout is very important. switching current fr om one power device to another can generate voltage transient s across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances s hould be minimized by using wide, short printed circuit traces. the critical components should be located as close toget her as possible using ground plane construction or single point grounding. a multi-layer printed circuit board is recommended. figure 5 shows the critical components of the converter. note that capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer (usually a middle layer of the pc board) for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer a s a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the lx terminals to the output ind uctor short. t hiccup 24vc ss ?? 30 ? a ------------------------------- - = (eq. 5) r tsoc i oc_source i ? 2 ---- - + ?? ?? r ? ds on ?? i tsoc n t ? --------------------------------------------------------------- ------------------ - = n t number of top-side mosfets = r tsoc i oc_source r ? ds on ?? 200 ? a --------------------------------------------------------------- - = simple ocp equation detailed ocp equation ? i = v in - v out f sw l out ? ------------------------------- - v out v in --------------- - ? f sw regulator switching frequency = (eq. 6) v out island on power plane layer island on circuit and/or power plane layer l out c out c in vin key figure 5. printed circuit board power planes and islands via connection to ground plane load q 1 q 2 +14v c bp_vcc c bp_pvcc c in c ss ISL8104 tgate lx gnd pvcc bgate vcc boot ss pgnd trace sized for 3a peak current short trace, minimum impedance ISL8104 fn9257 rev 2.00 page 9 of 14 march 7, 2008 the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layer s for the lx nodes . use the remaining printed circuit layers fo r small signal wiring. locate the ISL8104 within 2 to 3 inches of the mosfets, q 1 and q 2 (1 inch or less for 500khz or higher operation). the circuit traces for th e mosfets gate and source connections from the ISL8104 must be size d to handle up to 3a peak current. minimize any leakage cu rrent paths on the ss pin and locate the capacitor, c ss close to the ss pin as the internal current source is only 30 a. provide local v cc decoupling between vcc and gnd pins. locate the capacitor, c boot as close as practical to the boot pin and the phase node. compensating the converter this section highlights the des ign consideration for a voltage mode controller requiring external compensation. to address a broad range of applications, a type-3 feedback network is recommended (see figure 6). figure 7 highlights the voltag e-mode control loop for a synchronous-rectified buck conv erter. the output voltage is regulated to the reference voltage level. the error amplifier output is compared with the oscillator triangle wave to provide a pulse-width modulat ed wave with an amplitude of v in at the lx node. the pwm wave is smoothed by the output filter. the out put filter capacitor banks equivalent series resistance is represent ed by the series resistor esr. the modulator transfe r function is the small-signal transfer function of v out /v comp . this function is dominated by a dc gain and shaped by the output filter, with a double pole break frequency at f lc and a zero at f ce . for the purpose of this analysis, l and dcr rep resent the output inductance and its dcr, while c and esr rep resents the total output capacitance and its equivalent series resistance. the compensation network consi sts of the error amplifier (internal to the ISL8104) and the external r 1 to r 3 , c 1 to c 3 components. the goal of the compensation network is to provide a closed loop transfer function with high 0db crossing frequency (f 0 ; typically 0.1 to 0.3 of f sw ) and adequate phase margin (better than 45). phas e margin is the difference between the closed loop phase at f 0db and 180. the equations that follow relate the compensation networks poles, zeros and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 , and c 3 ) in figures 6 and 7. use the following guidelines for locating the poles and zeros of the compensation network: 1. select a value for r 1 (1k ? to 10k ? , typically). calculate value for r 2 for desired converter bandwidth (f 0 ). if setting the output voltage to be equal to the reference set voltage as shown in figure 7 , the design procedure can be followed as prese nted in equation 8. as the ISL8104 supports 100% duty cycle, d max equals 1. the ISL8104 uses a fixed ramp amplitude (v osc ) of 1.9v, equation 8 simplifies to equation 9: 2. calculate c 1 such that f z1 is placed at a fraction of the f lc , at 0.1 to 0.75 of f lc (to adjust, change the 0.5 factor in equation 10 to the desired number). the higher the quality factor of the output filter a nd/or the higher the ratio f ce /f lc , the lower the f z1 frequency (to maximize phase boost at f lc ). 3. calculate c 2 such that f p1 is placed at f ce . 4. calculate r 3 such that f z2 is placed at f lc . calculate c 3 such that f p2 is placed below f sw (typically, 0.3 to 1.0 figure 6. compensation configuration for the ISL8104 circuit ISL8104 comp c 1 r 2 r 1 fb vout c 2 r 3 c 3 figure 7. voltage-mode buck converter compensation design - + e/a vref comp c 1 r 2 r 1 fb c 2 r 3 c 3 l c v in pwm circuit half-bridge drive oscillator esr external circuit ISL8104 v out v osc dcr tgate lx bgate gnd f lc 1 2 ? lc ? ? --------------------------- = f ce 1 2 ? c esr ?? --------------------------------- = (eq. 7) r 2 v osc r 1 f 0 ?? d max v in f lc ?? ---------------------------------------------- = (eq. 8) r 2 1.9 r 1 f 0 ?? v in f lc ? ------------------------------- = (eq. 9) c 1 1 2 ? r 2 0.5 f lc ?? ? ---------------------------------------------- - = (eq. 10) c 2 c 1 2 ? r 2 c 1 f ce 1 C ??? -------------------------------------------------------- = (eq. 11) ISL8104 fn9257 rev 2.00 page 10 of 14 march 7, 2008 times f sw ). f sw represents the switching frequency of the regulator. change the numeri cal factor (0.7) below to reflect desired placement of this pole. placement of f p2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the hf ripple component at the comp pin and minimizing resultant duty cycle jitter. it is recommended that a mat hematical model be used to plot the loop response. check the loop gain against the error amplifiers open-loop gain. verify phase margin results and adjust as necessary. equation 13 describes the frequency response of the modulator (g mod ), feedback compensation (g fb ) and closed-loop response (g cl ): compensation break frequency equations figure 8 shows an asymptotic plot of the dc/dc converters gain vs frequency. the actual modu lator gain has a high gain peak dependent on the quality fact or (q) of the output filter, which is not shown. using the pr eviously mentioned guidelines should yield a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 against the capabilities of the error amp lifier. the closed loop gain, g cl , is constructed on the log- log graph of figure 8 by adding the modulator gain, g mod (in db), to the feedback compensation gain, g fb (in db). this is equivalent to multiplying the modulator t ransfer function and the compensation transfer funct ion and then plotting the resulting gain. a stable control loop has a gai n crossing with close to a -20db/decade slope and a phase margin greater than 45. include worst case component variations when determining phase margin. the mathemati cal model presented makes a number of approxim ations and is generally not accurate at frequencies approaching or e xceeding half t he switching frequency. when designing c ompensation networks, select target crossover frequencies in the range of 10% to 30% of the switching frequency, f sw . component selection guidelines output capacitor selection an output capacitor is requir ed to filter the output and supply the load transient current. t he filtering requirements are a function of the switching frequ ency and the ripple current. the load transient requirement s are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirement s are generally met with a mix of capacitors and careful layout. for applications that have transient load rates above 1a/ns, high frequency capacitors initia lly supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. use only specialized low-es r capacitors intended for switching-regulator applicati ons for the bulk capacitors. the bulk capacitors esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electroly tic capacitor's esr value is related to the case size with lower esr available in larger case sizes. however, the equi valent series inductance (esl) of these capacitors incr eases with case size and can reduce the usefulness of the ca pacitor to high slew-rate r 3 r 1 f sw f lc ---------- - 1 C -------------------- = c 3 1 2 ? r 3 0.7 f sw ?? ? ---------------------------------------------- - = (eq. 12) g mod f ?? d max v in ? v osc ------------------------------ - 1sf ?? esr c ?? + 1sf ?? esr dcr + ?? c ?? s 2 f ?? lc ?? ++ --------------------------------------------------------------- -------------------------------------------- ? = g fb f ?? 1sf ?? r 2 c 1 ?? + sf ?? r 1 c 1 c 2 + ?? ?? ---------------------------------------------------- ? = 1sf ?? r 1 r 3 + ?? c 3 ?? + 1sf ?? r 3 c 3 ?? + ?? 1sf ?? r 2 c 1 c 2 ? c 1 c 2 + -------------------- - ?? ?? ?? ?? + ?? ?? ?? ? --------------------------------------------------------------- ---------------------------------------------------------- g cl f ?? g mod f ?? g fb f ?? ? = where s f ?? ? 2 ? fj ?? = (eq. 13) f z1 1 2 ? r 2 c 1 ?? ------------------------------ - = f z2 1 2 ? r 1 r 3 + ?? c 3 ?? ------------------------------------------------- = f p1 1 2 ? r 2 c 1 c 2 ? c 1 c 2 + -------------------- - ?? -------------------------------------------- - = f p2 1 2 ? r 3 c 3 ?? ------------------------------ - = (eq. 14) 0 f p1 f z2 open loop e/a gain f z1 f p2 f lc f ce compensation gain gain frequency modulator gain figure 8. asymptotic bode plot of converter gain closed loop gain 20 r2 r1 ------- - ?? ?? log log log f 0 g mod g fb g cl 20 d max v ? in v osc ---------------------------------- log ISL8104 fn9257 rev 2.00 page 11 of 14 march 7, 2008 transient loading. unfortunat ely, esl is not a specified parameter. work with your ca pacitor supplier and measure the capacitors impedance with frequency to select a suitable component. in most cases, multipl e electrolytic c apacitors of small case size perform bette r than a single large case capacitor. output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimi ze the converters response time to the load transient. the inductor value determines the converters ripple current and the ripple voltage is a function of the ripple current. the rippl e voltage and current are approximated by equation 15: increasing the value of inductan ce reduces the ripple current and voltage. however, the large inductance values reduce the converters response tim e to a load transient. one of the parameters limiting the converters response to a load transient is the time required to change the inductor curr ent. given a sufficiently fast cont rol loop design, the ISL8104 will provide either 0% or 100% dut y cycle in response to a load transient. the response time is th e time required to slew the inductor current from an initial current value to the transient current level. during this interval the difference between the inductor current and the transient current level must be suppli ed by the output capacitor. minim izing the response time can minimize the output capacitance required. the response time to a transi ent load is different for the application of load and the remov al of load. equation 16 gives the approximate response time i nterval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. with a +5v input source, the worst case response time c an be either at the application or removal of load and depende nt upon the output voltage setting. be sure to check bot h of these equations at the minimum and maximum output levels for the worst case response time. input capacitor selection use a mix of input bypass cap acitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time q1 turn s on. place the small ceramic capacitors physically close to the mosfets and between the drain of q 1 and the source of q 2 . the important paramet ers for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select a bulk capaci tor with voltage and current ratings above the maximum i nput voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage, a voltage rating of 1.5 times greater is a conservativ e guideline. the rms current rat ing requirement for the input capacitor of a buck regulator is approximately 1/2 the dc load current. for a through hole design, sever al electrolytic capacitors (panasonic hfq series or nichicon pl series or sanyo mv-gx or equivalent) may be needed. for s urface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capaci tors must be capable of handling the surge-current at power-up. the tps series available from avx, and the 593d series from sprague are both surge current tested. mosfet selection/considerations the ISL8104 requires at least 2 n-channel power mosfets. these should be selected based upon r ds(on) , gate supply requirements, and thermal management requirements. in high-current applications, the mosfet power dissipation, package selection and heatsi nk are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. at a 300khz switching frequency, the conduction losses are the largest component of power dissipation for both the top-side and the bottom-side mosfets. these losses are di stributed between the two mosfets according to duty factor (see the following equations). only the top-side mosfet exhibits switching losses, since the schottky rectif ier clamps the switching node before the synchronous rectifier turns on. equation 17 assumes linear volta ge-current transitions and does not adequately model power loss due to the reverse-recovery of the bottom-side mosfets body diode. the gate-charge losses are di ssipated by the ISL8104 and don't heat the mosfets. how ever, large gate-charge increases the swit ching interval, t sw which increases the top-side mosfet switching losses. ensure that both mosfets are within their max imum junction temperature at high ambient temperature by cal culating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. standard-gate mosfets are no rmally recommended for use with the ISL8104. however, logi c-level gate mo sfets can be ? v out = ? i x esr ? i = v in - v out fs x l ------------------------------- - v out v in --------------- - ? (eq. 15) t fall l o i tran ? v out ------------------------------ - = t rise l o i tran ? v in v out C ------------------------------- - = (eq. 16) p top-side = i o 2 x r ds(on) x d + 1 2 io x v in x t sw x f sw p bottom-side = i o 2 x r ds(on) x (1 - d) where: d is the duty cycle = v o / v in , t sw is the switching interval, and f sw is the switching frequency. (eq. 17) ISL8104 fn9257 rev 2.00 page 12 of 14 march 7, 2008 used under special circumstance s. the input voltage, top-side gate drive level, and the mosf ets absolute gate-to-source voltage rating determine whet her logic-level mosfets are appropriate. figure 9 shows the top-side gate drive (boot pin) supplied by a bootstrap circuit from +14v . the boot capacitor, c boot develops a floating supply voltage referenced to the lx pin. this supply is refreshed each c ycle to a voltage of +14v less the boot diode drop (v d ) when the bottom-side mosfet, q 2 turns on. a mosfet can only be used for q 1 if the mosfets absolute gate-to-source voltage rating exceeds the maximum voltage applied to +14v. for q 2 , a logic-level mosfet can be used if its absolute gate-to-so urce voltage rating also exceeds the maximum voltage applied to +14v. figure 10 shows the t op-side gate drive su pplied by a direct connection to +14v. this op tion should only be used in converter systems where the ma in input voltage is +5vdc or less. the peak top-side ga te-to-source voltage is approximately +14v less the input supply. for +5v main power and +14vdc for the bias, the g ate-to-source voltage of q 1 is 9v. a logic-level mosfet is a good choice for q 1 and a logic- level mosfet can be used for q 2 if its absolute gate-to- source voltage rating exceeds the maximum voltage applied to pvcc. this method reduces the number of required external components, but does not provi de for immunity to phase node ringing during turn on and may result in lower system efficiency. schottky selection rectifier d2 is a clamp that c atches the negativ e inductor swin g during the dead time between turning off the bottomside mosfet and turning on the top-side mosfet. the diode must be a schottky type to prevent t he lossy parasitic mosfet body diode from conducting. it is acceptable to omit the diode and l et the body diode of the bottom-side mosfet clamp the negative inductor swing, but efficiency c ould slightly decrease as a res ult. the diode's rated reverse breakdown voltage must be greater than the maximum input voltage. +14v pgnd ISL8104 gnd bgate tgate boot +1.2v to +14v figure 9. top-side gate drive - bootstrap option note: v g-s ? v cc - v d note: v g-s ? pvcc c boot d boot q1 q2 pvcc +14v d2 + - v d + - lx +14v pgnd bgate tgate boot +5v or less figure 10. top-side gate drive - direct v cc drive option note: v g-s ? v cc - 5v note: v g-s ? pvcc q1 q2 pvcc +14v d2 ISL8104 gnd + - fn9257 rev 2.00 page 13 of 14 march 7, 2008 ISL8104 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2006-2007. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not ex ceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m ? m14.15 (jedec ms-012-ab issue c) 14 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3367 0.3444 8.55 8.75 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n14 147 ? 0 o 8 o 0 o 8 o - rev. 0 12/93 ISL8104 fn9257 rev 2.00 page 14 of 14 march 7, 2008 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l16.4x4 16 lead quad flat no-lead plastic package (compliant to jedec mo-220-vggc issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.35 5, 8 d 4.00 bsc - d1 3.75 bsc 9 d2 1.95 2.10 2.25 7, 8 e 4.00 bsc - e1 3.75 bsc 9 e2 1.95 2.10 2.25 7, 8 e 0.65 bsc - k0.25 - - - l 0.50 0.60 0.75 8 l1 - - 0.15 10 n162 nd 4 3 ne 4 3 p- -0.609 ? --129 rev. 5 5/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & ? are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm. |
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