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complete 1 6 - bit ccd/cis signal processor data sheet ad80066 features 16- bit , 24 msps analog - to - digital converter (adc) 4 - channel operation up to 24 mhz (6 mhz/channel) 3 - channel operation up to 24 mhz (8 mhz/channel) selectable input range : 3 v or 1.5 v peak - to - peak i nput clamp circuitry correlated double sampling 1 ~6 programmable gain 300 mv programmable offset internal voltage reference multiplexed byte - wide output optional single - byte output mode 3 - w ire serial digital interface 3 v/5 v digital i/o compatibility power dissipation : 490 mw at 24 mhz operation reduced powe r mode and sleep mode available 28- lead ssop package applications flatbed document scanners film scanners digital color copiers multifunction peripherals general description the ad80066 is a complete analog signal processor for imaging applications. it features a 4 - channel architecture designed to sample and condition the outputs of linear charged coupled device ( ccd ) or contact image sensor ( cis ) arrays. each channel consists of an input clamp, correlated double sampler (cds), offset digital - to - analog converter ( dac ) , and programmable gain amplifier (pga) , multiplexed to a high performance 16 - bit adc . for maximum flexibility, the ad80066 can be configured as a 4 - channel, 3 - channel, 2 - channel, or 1 - channel device. the cds amplifiers can be disab led for use with sensors that do not require cds , such as cis and cmos sensors. the 16 - bit digital output is multiplexed into an 8 - bit output word, which is accessed using two read cycl es. there is an optional single - byte output mode. the internal registe rs are pro grammed through a 3 - wire serial i nterface and enable adjustment of the gain, offset, and operating mode. the ad80066 operates from a 5 v power supply, typically consumes 490 mw of powe r, and is packaged in a 28 - lead ssop. functional block dia gram dout (d[0:7]) sclk sload sdata adcclk offset avdd avss cml avdd capt capb ad80066 drvdd drvss gain registers offset registers 4:1 mux 16-bit adc ch . a ch . b ch . c ch . d 8 16 ch . a ch . b ch . c ch . d 6 9 pga pga pga cd s cd s cd s avss vind vinc vinb vina cd s digital control interface input clamp bias 9-bit dac 9-bit dac 9-bit dac 9-bit dac pga configuration register mux register cdsclk2 cdsclk1 band gap reference 16:8 mux 08552-001 figure 1. rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed b y analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 analog devices, inc. all rights reserved. technical support www.analog.com
ad80066 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 analog specifications ................................................................... 3 digital specifications ................................................................... 4 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 11 terminology .................................................................................... 12 theory of ope ration ...................................................................... 13 4 - channel cds mode ................................................................ 13 4 - channel sha mode ................................................................ 13 1 - channel cds mode ............................................................... 13 1 - channel sha mode ............................................................... 13 internal register map .................................................................... 14 internal register details ................................................................ 15 configuration register .............................................................. 15 mux register ............................................................................... 15 pga gain registers ................................................................... 15 offset registers ........................................................................... 15 circuit operation ........................................................................... 17 analog inputs cds mode ...................................................... 17 external input coupling capacit ors ........................................ 17 analog inputs sha mode ...................................................... 18 programmable gain amplifiers (pga) .................................. 18 applications information .............................................................. 19 circuit and layout recommendations ................................... 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 4/15 rev. a to rev. b change s to figure 7 .......................................................................... 7 4 / 10 revision a : initial version rev. b | page 2 of 20
data sheet ad80066 specifications analog specification s t min to t max , avdd = 5 v, drvdd = 5 v, cds mode, f adcclk = 24 mhz, f cdsclk1 = f cdsclk2 = 6 mhz, pga gain = 1, unless otherwise noted. table 1 . parameter min typ max unit maximum conversion rate 4 - channel mode with cds 24 msps 3 - channel mode with cds 24 msps 2 - channel mode with cds 24 msps 1 - channel mode with cds 12 msps accuracy (entire signal path) adc resolution 16 bits integral nonlinearity (inl) +20/ ? 5 lsb differential nonlinearity (dnl) 0.5 lsb no missing codes guaranteed analog inputs input signal range 1 1.5/3.0 v p -p allowable reset transient 1 2.0 v input limits 2 avss ? 0.3 avdd + 0.3 v input capacitance 10 pf input bias current 10 na amplifiers pga gain range 1 5.9 v/v pga gain resolution 2 64 steps pga gain monotonicity guaranteed programmable offset range ? 305 +295 mv programmable offset resolution 512 steps programmable offset monotonicity guaranteed noise and crosstalk total output noise at pga minimum 9.5 lsb rms total output noise at pga maximum 35 lsb rms channel - to - channel crosstalk @ 24 msps 70 db @ 12 msps 90 db power supply rejection avdd = 5 v 0.25 v 0.1 % fsr voltage reference ( t a = 25c) capt ? capb 0.75 v temperature range operating 0 70 c storage ? 65 +150 c power supplies avdd 4.5 5.0 5.25 v drvdd 3.0 3.3 5.25 v operating current avdd 95 ma drvdd 4 ma power - down mode current 300 a rev. b | page 3 of 20
ad80066 data sheet parameter min typ max unit power dissipation 4 - channel mode at 24 mhz 490 mw 1 - channel mode at 12 mhz 300 mw 4 - channel mode at 8 mhz, slow power mode 3 165 mw 1 the linear input signal range is up to 3 v p - p when the ccd reference level is clamped to 3 v by the ad80066 input clamp (see figure 2 ). 2 the pga gain is approximately linear - in - db but varies nonlinearly with register code (s ee the programmable gain amplifiers (pga) section for more information) . 3 measured with bit d1 of the configuration register set high for 8 mhz, low power operation. 2v typ reset transient avdd = 5v 3v bias set by input clamp 1.5v or 3v p-p max input signal range gnd 08552-002 figure 2. input signal with the ccd reference level clamped to 3 v digital specifications t min to t max , avdd = 5 v, drvdd = 5 v, cds mode, f adcclk = 24 mhz, f cdsclk1 = f cdsclk2 = 6 mhz, c l = 10 pf, unless otherwise noted. table 2 . parameter symbol min typ max unit logic inputs high level input voltage v ih 2.0 v low level input voltage v il 0.8 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs (drvdd = 5 v) high level output voltage (i oh = 2 ma) v oh 4.5 v low level output voltage (i ol = 2 ma) v ol 0.5 v logic outputs (drvdd = 3 v) high level output voltage (i oh = 2 ma) v oh 2.5 v low level output voltage (i ol = 2 ma) v ol 0.5 v rev. b | page 4 of 20
data sheet ad80066 timing specification s t min to t max , avdd = 5 v, drvdd = 5 v. table 3 . parameter symbol min typ max unit clock parameters 4 - channel pixel rate t pra 166 ns 1 - channel pixel rate t prb 83 ns adcclk pulse width t adc c lk 20 ns cdsclk1 pulse width t c1 15 ns cdsclk2 pulse width t c2 15 ns cdsclk1 falling 1 to cdsclk2 rising t c1c2 0 ns adcclk falling to cdsclk2 rising t adc2 0 ns cdsclk2 rising to adcclk rising t c2adr 5 ns cdsclk2 falling 1 to adcclk falling t c2adf 20 ns cdsclk2 falling 1 to cdsclk1 rising t c2c1 5 ns aperture delay for cds clocks t ad 2 ns serial interface maximum sclk frequency, write operation f sclk 50 mhz maximum sclk frequency, read operation f sclk 25 mhz sload to sclk setup time t ls 5 ns sclk to sload hold time t lh 5 ns sdata to sclk rising setup time t ds 2 ns sclk rising to sdata hold time t dh 2 ns sclk falling to sdata valid t rdv 10 ns data output output delay t od 8 ns latency (pipeline delay) 3 ( fixed ) cycles 1 cdsclk x falling edges should not occur within the first 10 ns following an adcclk edge. timing diagrams analog inputs cdsclk1 cdsclk2 adcclk output data (d[7:0]) pixel n (a,b,c,d) p ixel (n + 1) t ad t ad t c2adf t c2adr t adc2 t od t adcclk t adcclk high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte high byte high byte low byte c(n ? 2) b(n ? 2) c(n ? 2) d(n ? 2) d(n ? 2) a(n ? 1) a(n ? 1) b(n ? 1) b(n ? 1) c(n ? 1) c(n ? 1) d(n ? 1) d(n ? 1) a(n) a(n) b(n) t pra t c2c1 t c1c2 t c2 t c1 08552-003 figure 3. 4 - channel cds mode timing rev. b | page 5 of 20
ad80066 data sheet t od t adcclk t adcclk analog inputs cdsclk1 cdsclk2 adcclk output data (d[7:0]) pixel n (a, b, c) pixel (n + 1) pixel (n + 2) t ad t ad t pra t c2c1 t c1 t c2 t c1c2 t c2adf t c2adr t adc2 high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte b(n ? 2) a(n ? 2) b(n ? 2) c(n ? 2) c(n ? 2) a(n ? 1) a(n ? 1) b(n ? 1) b(n ? 1) c(n ? 1) c(n ? 1) a(n) a(n) b(n) b(n) 08552-004 figure 4. 3 - channel cds mode timing ch 1 (n ? 2) ch 2 (n ? 2) ch 1 (n ? 1) ch 2 (n ? 1) ch 1 (n) analog inputs cdsclk1 cdsclk2 adcclk output data (d[7:0]) pixel n pixel (n + 1) pixel (n + 2) t ad t ad t pra t c2c1 t c1 t adcclk t adcclk t c2 t c1c2 t c2adr t c2adf t adc2 high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte 08552-005 figure 5. 2 - channel cds mode timing rev. b | page 6 of 20
data sheet ad80066 analog inputs cdsclk1 pixel n pixel (n + 1) pixel (n + 2) cdsclk2 adcclk output data (d[7:0]) notes 1. in 1-channel cds mode. the cdsclk1 falling edge and the cdsclk2 rising edge must occur while adcclk is low. low byte high byte high byte low byte high byte low byte 08552-006 t ad t c1 t ad t c2adr t od t c1c2 pixel (n ? 4) t c2adf t adcclk t adcclk t c2 pixel (n ? 4) pixel (n ? 3) pixel (n ? 3) pixel (n ? 2) pixel (n ? 2) t c2c1 t prb figure 6. 1 - channel cds mode timing pixe l n (a, b, c, d) t a d t c2 t c2adf t adc2 t c2adr t adcclk t adcclk t od c(n ? 2) d(n ? 2) d(n ? 2) a(n ? 1) a(n ? 1) a(n) a(n) b(n) b(n) high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte high byte low byte t p r a p i xe l (n + 1 ) analog inputs cdsclk2 adcclk output d at a (d[7:0]) b(n ? 1) b(n ? 1) c(n ? 1) c(n ? 1) d(n ? 1) d(n ? 1) 08552-007 figure 7. 4 - channel sha mode timing rev. b | page 7 of 20
ad80066 data sheet rev. b | page 8 of 20 analog inputs cdsclk2 adcclk output data (d[7:0]) t od pixel n t ad high byte low byte low byte high byte high byte low byte pixel (n ? 4) pixel (n ? 4) pixel (n ? 3) pixel (n ? 3) pixel (n ? 2) pixel (n ? 2) t c2adr t c2 t prb t c2adf t adcclk t adcclk 0 8552-008 pixel (n + 1) figure 8. 1-channel sha mode timing t od t od high byte (db[15:8]) high byte (db[15:8]) low byte (db[7:0]) low byte (db[7:0]) high byte (db[15:8]) adcclk output data (d[7:0]) low byte (db[7:0]) pixel n pixel n 0 8552-009 pixel ( n + 1) pixel ( n + 1) pixel ( n + 2) pixel ( n + 3) figure 9. digital output data timing t od adcclk output data (d[7:0]) pixel n pixel (n + 1) high byte (db[15:8]) high byte (db[15:8]) high byte (db[15:8]) 08552-010 pixel (n + 2) figure 10. single-byte mode digital output data timing t lh d8 d7 d6 d5 d4 d3 d2 d1 d0 t ds t ls t dh a0 a2 r/w sdata a1 sclk sload a3 0 8552-011 figure 11. serial write operation timing t lh d8 d7 d6 d5 d4 d3 d2 d1 d0 t rdv t ls a1 a3 a2 sdata sclk s load a0 r/w 08552-012 figure 12. serial re ad operation timing
data sheet ad80066 absolute maximum rat ings table 4 . parameter with respect to rating vin x , capt, capb avss ?0.3 v to avdd + 0.3 v digital inputs avss ?0.3 v to avdd + 0.3 v sdata drvss ?0.3 v to drvdd avdd avss ?0.5 v to +6.5 v drvdd drvss ?0.5 v to +6.5 v avss drvss ?0.3 v to +0.3 v digital outputs (d[7:0]) drvss ?0.3 v to drvdd + 0.3 v temperature junction 150c storage ?65c to +150c lead (10 sec) 300c stresses at or above those listed under absolute maximum ratings may caus e permanent damage to the product . this is a stress rating only; fu nctional operation of the product at these or any other conditions above those indicated in the operational section of this specification is no t implied. operation beyond the maximum ope rating conditions for ex tended periods may affect product reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 5 . thermal resistance package type ja jc unit 28- lead , 5.3 mm ssop 109 39 c/w esd caution rev. b | page 9 of 20
ad80066 data sheet rev. b | page 10 of 20 pin configuration and fu nction descriptions ad80066 top view (not to scale) avdd avss d6 d5 d4 d3 d2 d1 (lsb) d0 cdsclk1 cdsclk2 adcclk drvdd drvss (msb) d7 vina offset vinb cml vinc capt capb vind avdd sload sclk sdata avss 1 2 3 4 28 27 26 25 5 6 7 24 23 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 08552-013 figure 13. pin configuration table 6. pin function descriptions pin no. mnemonic type 1 description 1 avdd p 5 v analog supply. 2 cdsclk1 di cds reference level sampling clock. 3 cdsclk2 di cds data level sampling clock. 4 adcclk di adc sampling clock. 5 drvdd p digital output driver supply (3 v or 5 v). 6 drvss p digital output driver ground. 7 d7 (msb) do data output msb. adc db15 high byte; adc db7 low byte. 8 d6 do data output. adc db14 high byte; adc db6 low byte. 9 d5 do data output. adc db13 high byte; adc db5 low byte. 10 d4 do data output. adc db12 high byte; adc db4 low byte. 11 d3 do data output. adc db11 high byte; adc db3 low byte. 12 d2 do data output. adc db10 high byte; adc db2 low byte. 13 d1 do data output. adc db9 high byte; adc db1 low byte. 14 d0 (lsb) do data output lsb. adc db8 high byte; adc db0 low byte. 15 sdata di/do serial interface data input/output. 16 sclk di serial interface clock input. 17 sload di serial interface load pulse. 18 avdd p 5 v analog supply. 19 avss p analog ground. 20 vind ai analog input, d channel. 21 capb ao adc bottom reference voltage decoupling. 22 capt ao adc top reference voltage decoupling. 23 vinc ai analog input, c channel. 24 cml ao internal bias level decoupling. 25 vinb ai analog input, b channel. 26 offset ao clamp bias level decoupling. 27 vina ai analog input, a channel. 28 avss p analog ground. 1 ai = analog input, ao = analog output, di = digital input, do = digital output, and p = power.
data sheet ad80066 rev. b | page 11 of 20 typical performance characteristics 0 64,000 25,600 12,800 38,400 51,200 0 ?1.0 1.0 0.5 ?0.5 adc output code dnl (lsb) 08552-014 figure 14. typical dnl performance pga register value (decimal) 0 015 output noise (lsb) 25 50 30 45 63 10 5 15 20 45 30 35 40 08552-015 figure 15. output noise vs. pga gain 0 64,000 25,600 12,800 38,400 51,200 5 ?5 15 10 0 adc output code inl (lsb) 08552-016 figure 16. typical inl performance
ad80066 data sheet terminology integral nonlinearity (inl) integral nonlinearity error refers to the deviation of each individual code from a line drawn from zero scale through positive full scale. the point used as zero scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinear ity (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value; therefore, every code must have a finite width. no missing codes guaranteed to 16- bit resolution indicates that all 65,536 codes must be present over all operating ranges. offset error the first adc code transition should occur at a level ? lsb above the nominal zero - scale voltage. the offset error is the deviation of the actual first code transition level from the ideal level. gain err or the last code transition should occur for an analog value 1? lsb below the nominal full - scale voltage. gain error is the deviation of the actual difference between the first and last code transitions and the ideal difference between the first and last c ode transitions. input - referred noise the rms output noise is measured using histogram techniques. the standard deviation of the adc output codes is calculated in lsb and converted to an equivalent voltage, using the relationship 1 lsb = 1.5 v/65,536 = 23 v. the noise is then referred to the input of the ad80066 by dividing by the pga gain. channel -to - channel crosstalk in an ideal 3 - channel system, the signal in one channel does not influence the signal level of another channel. the channel - to - channel crosstalk specification is a measure of the change that occurs in one channel as the other two channels are varied. in the ad80066 , one channel is grounded and the other two channels are exercised with full - scale input signals. the change in the output codes from the first channel is measured and compared with the result when all three channels are grounded. the difference is the channel - to - channel crosstalk, stated in lsb. aperture delay the aperture delay is the delay that occurs from when a sampling edge is applied to the ad80066 until the actual sample of the input signal is held. both cdsclk1 and cdsclk2 sample the input signal during the transition from high to low; therefore, the aperture delay is measured from each falling edge of the clock to when the internal sample is take n. power supply rejection the power supply rejection specifies the maximum full - scale change that occurs from the initial value when the supplies are varied over the specified limits. rev. b | page 12 of 20
data sheet ad80066 theory of operation the ad80066 can be operated in several different modes , including 4 - channel cds mode, 4 - channel sha mode, 1 - channel cds mode, and 1 - channel sha mode. each mode is s elected by programming the configuration register through the serial interface. for more information on cds or sha mode operation, see the circuit operation section. 4 - channel cds mode in 4 - channel cds mode, the ad80066 simultaneously samples the a, b, c, and d input voltages from the ccd outputs. the sampling points for each cds are controlle d by cdsclk1 and cdsclk2 (see figure 17 and figure 18 ). the cdsclk1 falling edge samples the reference level of the ccd waveform, and the cdsclk2 falling edge samples the data level of the ccd wave - form. each cds amplifier outputs the difference between the ccd reference level and the data level . the output voltage of each cds amplifier is then level - shifted by an offset dac. the voltages are scaled by the four pgas before being multiplexed through the 1 6 - bit adc. the adc sequentially samples the pga outputs on the falling edges of adcclk. the offset a nd gain values for the a, b, c, and d channels are programmed using the serial interface. the order in which the channels are switched through the multiplexer is selected by programming the mux register. timing for this mode is shown in figure 3 . the falling edge of cdsclk2 should occur coincident with or before the rising edge of adcclk. however, this is not required to satisfy the minimum timing constr aints. the rising edge of cdsclk2 should not occur before the previous falling edge of adcclk, as shown by t adc2 . the output data latency is 3 adcclk cycles. 4 - channel sha mode in 4 - channel sha mode, the ad80066 simultaneously samples the a, b, c, and d input voltages. the sampling point is controlled by cdsclk2. the falling edge of cdsclk2 samples the input waveforms on each channel. the output voltages from the three shas are modified by the of fset dacs and then scaled by the four pgas. the outputs of the pgas are then multiplexed through the 1 6 - bit adc. the adc sequentially samples the pga outputs on the falling edges of adcclk. the input signal is sampled with respect to the voltage applied to the offset pin (see figure 19 ). with the offset pin grounded, a 0 v input corresponds to the zero - scale output of the adc . the offset pin can also be used as a coarse offset adjustment pin. a voltage applied to this pin is subtracted from the voltages applied to the a, b, c, and d inputs in the first amplifier stage of the ad80066 . t he input clamp is disabled in this mode. for more information, see the analog inputs sha mode section. the offset and gain values for the a, b, c, and d channels are p rogrammed using the serial interface. the order in which the channels are switched through the multiplexer is selected by programming the mux register. timing for this mode is shown in figure 7 . the cdsclk1 pin should be grounded in this mode. although not required, the falling edge of cdsclk2 should occur coincident with or before the rising edge of adcclk. the rising edge of cdsclk2 should not occur before the previous falling edge of adcclk, as shown by t adc2 . the output data latency is 3 adcclk cycles. 1 - channel cds mode the 1 - channel cds mode operates in the same way as the 4 - channel cds mode , except the multiplexer remains fixed . o nly the channel specified in the mux register is processed. timing for this mode is shown in figure 6 . 1 - channel sha mode the 1 - channel sha mode operates in the same way as the 4 - channel sha mode, except the multiplexer remains fixed . only the channel specified in the mux register is processed. timing for this mode is shown in figure 8 . the cdsclk1 pin should be grounded in this mode of operation. rev. b | page 13 of 20
ad80066 data sheet internal registe r map table 7 . internal register map address data bits register name a3 a2 a1 a0 d8 d7 d6 d5 d4 d3 d2 d1 d0 configuration 0 0 0 0 0 0 0 vref 2/1 byte cds on input range fast/ slow power on mux 0 0 0 1 0 0 0 0 ch. order c h . a c h . b c h . c c h . d gain a 0 0 1 0 0 0 0 msb lsb gain b 0 0 1 1 0 0 0 msb lsb gain c 0 1 0 0 0 0 0 msb lsb gain d 0 1 0 1 0 0 0 msb lsb offset a 0 1 1 0 msb lsb offset b 0 1 1 1 msb lsb offset c 1 0 0 0 msb lsb offset d 1 0 0 1 msb lsb rev. b | page 14 of 20
data sheet ad80066 internal register de tails configuration register the configuration register controls the ad80066 operating mode and bias levels. the d8, d7, and d6 bits should always be set low. bit d2 sets the full - scal e input voltage range of the ad80066 adc to either 3 v (high) or 1.5 v (low). bit d5 controls the internal vol tage reference. if the ad80066 internal voltage refe rence is used, this bit is set low. setting bit d5 high disables the internal voltage reference, allowing an external voltage reference to be used. setting bit d3 low enables the cds mode of operation and setting this bit high enables the sha mode of opera tion. if bit d4 is set high, the 16 - bit adc output is multiplexed into two bytes. the most significant byte is output on the adcclk rising edge, and the least significant byte is output on the adcclk falling edge (see figure 10) . if bit d1 is set high, the ad80066 is con - figured for slow operation (8 m hz) to reduce power consumption. bit d0 controls the power - down mode. setting bit d0 low places the ad80066 into a very low power sleep mode. all register contents are retained while the ad80066 is in the power - down state. mux register the mux register controls the sampling channel order in the ad80066 . the d8, d7, d6, and d5 bits should always be set low. bit d4 is used when operating in 4 - channel mode. setting bit d4 low sequences the multiplexer to sample the a channel first, and then the b, c, and d channel s . when in this mode, the cdsclk2 pulse always resets the multiplexer to sample the a channel first. when bit d4 is set high , the channel order is reversed to d, c, b, and a. the cdsclk2 pulse always resets the multiplexer to sample the d channel first. bits d [ 3 :0 ] are used when operating in 1 - channel mode. bit d3 is set high to sample the a channel. bit d2 is set high to sample the b channel. bit d1 is set high to sample the c channel. bit d0 is set high to sample the d channel . the multiplexer remains stationary in 1 - channel mode. pga gain registers there are four pga registers for individ ually programming the gain for the a, b, c, and d channels. the d8, d7, and d6 bits in each register must be set low, and the d5 through d0 bits control the gain range in 64 increments. see figure 22 for the pga gain vs. the pga register value . the coding for the pga registers is straight binary, with a word of all 0s corresponding to the minimum gain setting (1) and a word of all 1s corr esponding to the maximum gain setting (5.9). offset registers there are four offset registers for individually programming the offset in the a, b, c, and d channels. the d8 through d0 bits control the offset range from ?300 mv to +300 mv in 512 incre - ment s. the coding for the offset registers is sign magnitude, with d8 as the sign bit. table 11 shows the offset range as a function of the d8 through d0 bits . table 8 . configuration register settings d8 d7 d6 d5 d4 d3 d2 d1 d0 set to 0 set to 0 set to 0 internal voltage reference 2/1 byte output cds operation input range fast/ slow power mode 1 = disabled 1 = one byte 1 = sha mode 1 = 3 v 1 = 8 mhz 1 = on ( normal ) 0 = enabled 1 0 = two bytes 1 0 = cds mode 1 0 = 1.5 v 1 0 = 24 mhz 1 0 = off 1 1 pow er - on default. table 9 . mux register settings d8 d7 d6 d5 d4 d3 d2 d1 d0 set to 0 set to 0 set to 0 set to 0 mux order channel a channel b channel c channel d 1 = d , c , b , a 1 = channel used 1 = channel used 1 = channel used 1 = channel used 0 = a, b, c, d 1 0 = not used 1 0 = not used 1 0 = not used 1 0 = not used 1 1 power - on default . table 10 . pga gain register settings (msb) (lsb) d8 1 d7 1 d6 1 d5 d4 d3 d2 d1 d0 gain (v/v) gain (db) 0 0 0 0 0 0 0 0 0 2 1.0 0.0 0 0 0 0 0 0 0 0 1 1.013 0.12 0 0 0 1 1 1 1 1 0 5.56 14.9 0 0 0 1 1 1 1 1 1 5.9 15.56 1 must be set to 0. 2 power - on default. rev. b | page 15 of 20
ad80066 data sheet table 11 . offset register settings (msb) (lsb) d8 d7 d6 d5 d4 d3 d2 d1 d0 offset (mv) 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 +1.2 0 1 1 1 1 1 1 1 1 +30 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ?1.2 1 1 1 1 1 1 1 1 1 ?300 1 power - on default value. rev. b | page 16 of 20
data sheet ad80066 rev. b | page 17 of 20 circuit operation analog inputscds mode figure 17 shows the analog input configuration for the cds mode of operation. figure 18 shows the internal timing for the sampling switches. the ccd reference level is sampled when cdsclk1 transitions from high to low, opening s1. the ccd data level is sampled when cdsclk2 transitions from high to low, opening s2. s3 is then closed, generating a differential output voltage that represents the difference between the two sampled levels. the input clamp is controlled by cdsclk1. when cdsclk1 is high, s4 closes and the internal bias voltage is connected to the analog input. the bias voltage charges the external 0.1 f input capacitor, level-shifting the ccd signal into the input common-mode range of the ad80066 . the time constant of the input clamp is determined by the internal 5 k resistance and the external 0.1 f input capacitance. ad80066 s1 s2 2pf s3 2pf cml cml avdd s4 5k ? 1.7k ? offset c in 0.1f ccd signal 0.1f 1f + 3v 2.2k ? 6.9k ? vina 0 8552-017 figure 17. cds mode input configuration (all four channels are identical) cdsclk1 cdsclk2 q3 (internal) s1, s4 closed s1, s4 closed s2 closed s2 closed s3 closed s3 closed s3 open s2 open s1, s4 open 08552-018 figure 18. cds mode in ternal switch timing external input coupling capacitors the recommended value for the input coupling capacitors is 0.1 f. although it is possible to use a smaller capacitor, this larger value is preferable for several reasons: ? signal attenuation: the input coupling capacitor creates a capacitive divider using the input capacitance from an integrated cmos circuit, which, in turn, attenuates the ccd signal level. cin should be large relative to the 10 pf input capacitance of the ic in order to minimize this effect. ? linearity: some of the input capacitance of a cmos ic is junction capacitance, which varies nonlinearly with applied voltage. if the input coupling capacitor is too small, the attenuation of the ccd signal varies nonlinearly with signal level. this degrades the system linearity performance. ? sampling errors: the internal 2 pf sampling capacitors retain a memory of the previously sampled pixel. there is a charge redistribution error between cin and the internal sample capacitors for larger pixel-to-pixel voltage swings. as the value of cin is reduced, the resulting error in the sampled voltage increases. with a cin value of 0.1 f, the charge redistribution error is less than 1 lsb for a full-scale, pixel- to-pixel voltage swing.
ad80066 data sheet rev. b | page 18 of 20 analog inputssha mode figure 19 shows the analog input configuration for the sha mode of operation. figure 20 shows the internal timing for the sampling switches. the input signal is sampled when cdsclk2 transitions from high to low, opening s1. the voltage on the offset pin is also sampled on the falling edge of cdsclk2, when s2 opens. s3 is then closed, generating a differential output voltage that represents the difference between the sampled input voltage and the offset voltage. the input clamp is disabled during sha mode operation. ad80066 s1 2pf s3 cml input signal s2 2pf cml offset optional dc offset (or connect to gnd) vina vinb vinc vind a b c d cml cml cml cml cml cml 08552-019 figure 19. sha mode input configuration (all four channels are identical) cdsclk2 q3 (internal) s1, s2 closed s1, s2 closed s3 closed s3 closed s3 open s1, s2 open 08552-020 figure 20. sha mode internal switch timing figure 21 shows how the offset pin can be used in a cis application for coarse offset adjustment. many cis signals have dc offsets ranging from several hundred millivolts to more than 1 v. by connecting the appropriate dc voltage to the offset pin, the large dc offset is removed from the cis signal. then, the signal can be scaled using the pga to maximize the dynamic range of the adc. ad80066 offset a offset vina vinb vinc 0.1f avdd voltage reference from cis module r1 b offset c offset dc offset r2 sha sha sha 08552-021 figure 21. sha mode used with external dc offset programmable gain amplifiers (pga) the ad80066 uses one pga for each channel. each pga has a gain range from 1 (0 db) to 5.8 (15.5 db), adjustable in 64 steps. figure 22 shows the pga gain as a function of the pga register value. although the gain curve is approximately linear-in-db, the gain in v/v varies nonlinearly with register code, following the equation ? ? ? ? ? ? ? ? ? 63 63 4.91 5.9 g gain where g is the decimal value of the gain register contents and varies from 0 to 63. gain (v/v) 5.9 pga register value (decimal) 0 gain (db) 1 5 12 9 6 3 0 5.0 4.0 3.0 2.0 1.0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 63 08552-022 figure 22. pga gain transfer function
data sheet ad80066 applications information circuit and layout r ecommendations figure 23 shows the recommended circuit configuration for 4 - channel cds mod e operation. the recommended input coupling capacitor value is 0.1 f (see the analog inputs cds mode section). a single ground plane is recommended for the ad80066 . a separate power supply can be used for drvdd, the digital driver supply, but this supply pin should still be decoupled to the same ground plane as the rest of the ad80066 . the loading of the digital outputs should be minimized, either by using short traces to the digital asic or by using external digital buffers. to minimize the effect of digital transients during major output code transitions, the falling edge of cdsclk2 should occur coincident with or before the rising edge of adcclk (see figure 3 through figure 8 for timing). all 0.1 f decoupling capacitors should be located as close as possible to the a d80066 pins. when operating in 1 - channel mode, the unused analog inputs should be grounded. figure 24 shows the recommended circuit configuration for 4 - channel sha mode. all of the previously explained consid - erations also apply to this configuration, except that the analog input signals are directly connected to the ad80066 without the use of coupling capacitors. before connecting the signals, t he analog input signals must be dc - biased between 0 v and 1.5 v or 3 v (see the analog inputs sha mode section). clock inputs top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad80066 avdd avss a input data inputs 3.3v 5v 5v serial interface vina offset vinb cml vinc capt capb vind avss avdd sload sclk sdata cdsclk1 cdsclk2 adcclk drvdd drvss (msb) d7 d6 d5 d4 d3 d2 d1 (lsb) d0 c input d input b input 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 1.0f 0.1f 0.1f 10f 0.1f 0.1f 08552-023 figure 23 . recommended circuit configuration, 4 - channel cds mode 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2 clock inputs avdd data inputs 3.3v 5v cdsclk1 cdsclk2 adcclk drvdd drvss (msb) d7 d6 d5 d4 d3 d2 d1 (lsb) d0 0.1 f 0.1 f top view (not to scale) ad80066 a input 5v serial interface c input d input b input 0.1 f 0.1 f 0.1 f 10 f 0.1 f 0.1 f avss vina offset vinb cml vinc capt capb vind avss avdd sload sclk sdata 08552-024 figure 24 . recommended circuit configuration, 4 - channel sha mode (analog inputs sampled with respect to ground) rev. b | page 19 of 20
ad80066 data sheet outline dimensions compliant t o jedec s t andards mo-150-ah 060106- a 28 15 14 1 10.50 10.20 9.90 8.20 7.80 7.40 5.60 5.30 5.00 sea ting plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarit y 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 25 . 28 - lead shrink small outline package [ssop] (rs - 28) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad80066 k rsz 0c to 70c 28- lead ssop rs -28 ad80066k rszrl 0c to 70c 28- lead ssop rs -28 1 z = rohs compliant part. ? 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08552 - 0- 4/15(b) rev. b | page 20 of 20

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