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| integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 1 a plus make your production a-plus voice otp ic ap8 90 42 C 42sec a plus integrated circuits inc. sales e-mail: sales@aplusinc.com.tw address: 3 f-10, no. 32, sec. 1, chenggung rd., taipei, taiwan 115, r.o.c. (115) ???^?? 32 ? 3 ? 10. tel: 886-2-2782-9266 fax: 886-2-2782-9255 website : http: //www.aplusinc.com.tw technology e-mail: service@aplusinc.com.tw
integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 2 features standard cmos process. embedded 1m eprom. 42 sec voice length at 6 khz sampling and 4-bit adp cm compression. maximum 32 voice groups combination of voice building blocks to extend play back duration. 960 table entries are available for voice block com binations. user selectable pcm or adpcm data compress. two triggering modes are available by whole chip op tion during voice compilation. - key trigger mode C combinations of s1 ~ s8 to tr igger up to 32 voice groups; sbt for sequential trigger of the beginning 16 voice gr oups.. - cpu parallel trigger mode C combinations of s1 ~s 5 with sbt goes high to strobe start the voice playback. voice group trigger options: edge / level; hold / u n-hold; retrigger / non-retrigger. whole chip options: ramp / no-ramp; output options; key / cpu trigger mode. 16ms (@ 8khz sampling rate) debounce time for both key cpu trigger mode. rst pin set to hihg to stop playback at once. three user programmable outputs for stop plus, busy signal and flashing led. built-in oscillator to control sampling frequency w ith an external resistor. 2.2v C 3.6v single power supply and < 5ua low stand -by current. pwm vout1 and vout2 drive speaker directly. d/a cout to drive speaker through an external bjt. development system support voice compilation and op tions selection. description aP89042 high performance voice otp is fabricated wi th standard cmos process with embedded 1m bits eprom. it can store up to 42 sec voice messag es with 4-bit adpcm compression at 6khz sampling rate. 8-bit pcm is also available as user selectable option. two trigger modes, simple key trigger mode and parallel cpu trigger mode facilita te different user interface. user selectable triggering and output signal options provide maximu m flexibility to various applications. built-in resistor controlled oscillator, 8-bit current mode d/a output and pwm direct speaker driving output minimize the number of external components. pc con trolled programmer and developing software are available. integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 3 pin configurations pin names pin playback mode otp program mode description 1 s8 - trigger pin (input with internal pull-down) 2 out1 oeb programmable output (i/o pin) 3 vout1 - pwm output to drive speaker directly 4 vout2 - pwm output to drive speaker directly 5 vss vss power ground 6 out2 io programmable output (i/o pin) 7 out3 - programmable output (i/o pin) 8 cout - d/a current output 9 osc aclk oscillator input 10 s5 s5 trigger pin (input with internal pull-down ) 11 s6 s6 trigger pin (input with internal pull-down ) 12 vpp vpp supply voltage for otp programming 13 s1 s1 trigger pin (input with internal pull-down ) 14 s2 s2 trigger pin (input with internal pull-down ) 15 vdd vdd positive power supply 16 s3 s3 trigger (input with internal pull-down) 17 s4 s4 trigger (input with internal pull-down) 18 sbt pgm trigger pin (input with internal pull-do wn) 19 rst dclk reset pin (input with internal pull-dow n) 20 s7 s7 trigger pin (input with internal pull-down ) dip / sop 300 mil s8 out1 vout1 vout2 vss out2 out3 cout 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 s1 s3 s2 vdd s4 sbt rst s7 osc s5 9 10 12 11 s6 vpp integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 4 pin descriptions s1 ~ s8 input trigger pins: - s1 to s8 is used to trigger the 32 voice groups i n both key and cpu parallel trigger mode. - in otp programming mode, s1 to s7 are used as pro gram enable pins. sbt input trigger pin: - in key trigger mode, this pin is trigger pin to t rigger the playback of voice groups one by one sequentially. - in cpu parallel command mode, this pin is used as address strobe to latch the input from s1 to s5 and starts the voice playback. - in otp programming mode, this pin is used as pgm signal. vdd power supply pin. vss power ground pin vout1 and vout2 digital pwm output pins which can drive speaker and buzzer directly for voice playback. osc during voice playback, an external resistor is conn ected between this pin and the vdd pin to set the sampling frequency. in otp programming mode, t his is the aclk input signal. vpp connection to vdd is required during voice playback . in otp programming mode, this pin is connected to a separate 6.5v power supply. out1, out2 and out3 - in key trigger mode and cpu parallel command mode , these pins are user programmable pins for the stop pulse, busy and led signals. - during otp programming, out1 serves as oeb while out2 serves as data io. cout analog 8-bit current mode d/a output for voice play back rst chip reset in playback mode or dclk pin in otp prog ramming mode. integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 5 voice section combinations voice files created by the pc base developing syste m are stored in the built-in eprom of the aP89042 chip as a number of fixed length voice bloc ks. voice blocks are then selected and grouped into voice groups for playback. up to 32 voice gro ups are allowed. a voice block table is used to store the information of combinations of voice bloc ks and then group them together to form voice group. chip aP89042 memory size 1m bits max no. of voice block 252 no. of bytes per voice block 512 max. no. of voice group 32 no. of voice table entries 960 voice length (@ 6khz 4-bit adpcm) 42 sec example of voice block combination assume here we have three voice files, they are ho w are you?, sound effect and music. each of the voice file is divided into a number of fixed le ngth voice block and stored into the memory. voice file 1 - how are you? is stored in voice bl ock b0 to b12. voice file 2 - sound effect is stored in voice bloc k b13 to b15. voice file 3 - music is voice block b16 to b40. voice blocks are grouped together using voice table to form voice group for playback: group no. voice group contents voice table entries group 1 how are you? b0 b12 group 2 sound effect + how are you? b13 b15 + b 0 b12 group 3 how are you? + music b0 b12 + b16 b40 group 4 music b16 b40 voice data compression voice file data is stored in the on-chip eprom as e ither 4-bit adpcm or 8-bit pcm format. voice data stored as 4-bit adpcm provides 2:1 data compre ssion which can save 50% of memory space. on the other hand, voice data are stored as 8-bit p cm format means no data compression is employed but voice playback quality will be better. integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 6 programmable options in both key trigger mode and cpu parallel trigger m ode, user can select different trigger functions and output signals to be sent out from the pins out 1, out2 and out3. options affect all voice group playback are called whole chip options. options only affect the playback of individual voice group are called group options. whole chip options key or cpu parallel trigger mode. ramp-up-down enable or disable: when cout is used for playback, ramp-up-down should be enabled. this function eliminates the pop noise at the beginning and end of voice playback. when vout1 and vout2 are used to drive speaker dire ctly, ramp-up-down should be disabled. fig. 1 ramp-up-down enable fig.2 ramp-up-do wn disable output options: this option sets up the three output pins out1 and out2 to send out different signals during voice playback. four settings are allowed: out1 out2 out3 option 1 led2 led1 busy option 2 stop led1 led2 option 3 led1 busy stop option 4 led1 busy /busy note: stop plus and busy must be set to enable in o rder to have stop plus and busy high to come out. fig. 3 output waveforms integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 7 group options user selectable options that affect each individual group are called group options. they are: edge or level trigger unholdable or holdable trigger re-triggerable or non-retriggerable stop pulse disable or enable fig. 4 to fig. 9 show the voice playback with diffe rent combination of triggering mode and the relationship between outputs and voice playback. fig. 4 level, unholdable, non-retriggerable fig. 5 level holdable fig. 6 sbt sequential trigger with level holdable and unholdable integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 8 fig. 7 edge, unholdable, non-retrigger fig. 8 edge, holdable fig. 9 sbt sequential trigger with edge holdable a nd unholdable integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 9 overlap trigger is supported with level/unholdable trigger options: fig. 10 overlap trigger integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 10 trigger modes there are two triggering modes available with ap890 42. key or cpu trigger modes are determined by setting the eporm programmable options during voice data compilation. key trigger mode with this trigger mode, up to 32 voice groups are t riggered by setting s1 to s8 to high or nc (not connected) in different combinations. each voice g roup can have its only independent trigger options (see fig. 4, 5, 7 and 8 for trigger options definition). voice groups can also be triggered sequentially by setting sbt pin to high. cpu parallel trigger mode in this mode, s1 to s5 are set to high or low accor ding to the table above and followed by setting the sbt input pin to high, the corresponding voice group will be triggered. trigger options defined in fig. 4, 5, 7 and 8 are v alid for this mode. fig. 11 cpu parallel trigger mode note that sbt pin cannot be used as single button s equential trigger in this mode. in stead, it acts as a strobe input to clock-in the data input from s1 t o s5 into the chip. integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 11 key trigger mode up to 32 voice groups can be triggered by s1 to s8. voice group s1 s2 s3 s4 s5 s6 s7 s8 1 high nc nc nc nc nc nc nc 2 nc high nc nc nc nc nc nc 3 nc nc high nc nc nc nc nc 4 nc nc nc high nc nc nc nc 5 nc nc nc nc high nc nc nc 6 nc nc nc nc nc high nc nc 7 nc nc nc nc nc nc high nc 8 nc nc nc nc nc nc nc high 9 high high nc nc nc nc nc nc 10 nc high high nc nc nc nc nc 11 nc nc high high nc nc nc nc 12 nc nc nc high high nc nc nc 13 nc nc nc nc high high nc nc 14 nc nc nc nc nc high high nc 15 nc nc nc nc nc nc high high 16 high nc nc nc nc nc nc high 17 high high high nc nc nc nc nc 18 nc high high high nc nc nc nc 19 nc nc high high high nc nc nc 20 nc nc nc high high high nc nc 21 nc nc nc nc high high high nc 22 nc nc nc nc nc high high high 23 high nc nc nc nc nc high high 24 high high nc nc nc nc nc high 25 high high high high nc nc nc nc 26 nc high high high high nc nc nc 27 nc nc high high high high nc nc 28 nc nc nc high high high high nc 29 nc nc nc nc high high high high 30 high nc nc nc nc high high high 31 high high nc nc nc nc high high 32 high high high nc nc nc nc high integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 12 cpu trigger mode up to 32 voice groups can be triggered by supplying address to [s5:s1] with sbt as strobe signal. voice group s8 s7 s6 s5 s4 s3 s2 s1 1 nc nc nc 0 0 0 0 0 2 nc nc nc 0 0 0 0 1 3 nc nc nc 0 0 0 1 0 4 nc nc nc 0 0 0 1 1 5 nc nc nc 0 0 1 0 0 6 nc nc nc 0 0 1 0 1 7 nc nc nc 0 0 1 1 0 8 nc nc nc 0 0 1 1 1 9 nc nc nc 0 1 0 0 0 10 nc nc nc 0 1 0 0 1 11 nc nc nc 0 1 0 1 0 12 nc nc nc 0 1 0 1 1 13 nc nc nc 0 1 1 0 0 14 nc nc nc 0 1 1 0 1 15 nc nc nc 0 1 1 1 0 16 nc nc nc 0 1 1 1 1 17 nc nc nc 1 0 0 0 0 18 nc nc nc 1 0 0 0 1 19 nc nc nc 1 0 0 1 0 20 nc nc nc 1 0 0 1 1 21 nc nc nc 1 0 1 0 0 22 nc nc nc 1 0 1 0 1 23 nc nc nc 1 0 1 1 0 24 nc nc nc 1 0 1 1 1 25 nc nc nc 1 1 0 0 0 26 nc nc nc 1 1 0 0 1 27 nc nc nc 1 1 0 1 0 28 nc nc nc 1 1 0 1 1 29 nc nc nc 1 1 1 0 0 30 nc nc nc 1 1 1 0 1 31 nc nc nc 1 1 1 1 0 32 nc nc nc 1 1 1 1 1 integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 13 block diagram absolute maximum ratings symbol rating unit v dd - v ss -0.5 ~ +4.5 v v in v ss - 0.3 integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 15 ac characteristics ( t a = 0 to 70 , v dd = 3.3v, v ss = 0v, 8khz sampling ) symbol parameter min. typ. max. unit note t kd key trigger debounce time 16 ? ? ms 1 t kd key trigger debounce time C retrigger 24 ? ? ms 1 t up ramp up time 0 128/fs ?? s 3 t dn ramp down time 0 ?? 256/fs s 3 t kdd key trigger delay after ramp down ?? 0 ?? ms t stpd stop pulse output delay time ? ? 256 s t stpw stop pulse width ? 64 ? ms 1 t bd busy signal output delay time ? ? 100 ns t bh busy signal output hold time ? 100 ? ns t ash address set-up / hold time 100 ? ? ns t sbtw sbt stroke pulse width 16 ? ? ms 1 t ledc led flash frequency ? 3 ? hz 2 notes : 1. this parameter is inversely proportional to the sampling frequency. 2.this parameter is proportional to the sampling frequency. 3. fs is sampling frequency in hz s1~s8, sbt cout stop busy t kd t bh t bd t dn t kdd t up t stpd t stpw cpu parallel mode sbt t ash addr. s1~s5 t ash t sbtw key trigger mode integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 16 oscillator resistance table sampling frequency r osc r osc sampling frequency khz kohm kohm khz 4.90 300 140 11.00 5.26 290 130 11.76 5.88 280 120 12.50 6.09 270 110 13.33 6.33 260 100 14.51 6.67 250 91 15.63 6.85 240 82 16.95 7.14 230 75 18.18 7.46 220 68 19.23 7.70 210 62 20.83 8.06 200 56 22.22 8.47 190 51 23.81 8.93 180 43 25.00 9.26 170 9.80 160 10.42 150 note: the data in the above tables are within 3% ac curacy and measured at v dd = 3.0v. oscillator frequency is subjected to ic lot to lot variation. integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 17 typical applications key trigger mode fig. 12 using 3.3v battery fig. 13 using 4.5v battery vdd,vp vss 4.5v rst s1 s2 s3 s8 sbt osc 0.1uf c r os c t cout 8 1/4w speaker 8 / 16 speaker vout1 vout2 out1 ht7335 output driving of ht ldo: ht7136 (30ma, 3.6v) ht7133 (30ma, 3.3v) ht7536 (100ma, 3.6v) ht7335 (250ma, 3.5v) ? ? ? ? ? ? rb vdd,vp vss 3.3v rst s1 s2 s3 s8 sbt osc 0.1uf c r os c t cout rb 8 1/4w speaker 8 / 16 speaker vout1 vout2 out1 ? ? ? ? ? ? integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 18 cpu parallel mode fig. 14 5v cpu control with cout note: 1. c1 is capacitor from 0.1uf to 4.7uf depends on t he kind of vdd source and sound loudness. 2. rb is base resistor from 120 ohm to 390 ohm depe nds on vdd value and transistor gain. 3. t is an npn transistor with beta larger than 150 . 4. reference value for the above components are c = 2.2uf, rb = 390 ohm and t = 8050d. 5. refer to the oscillator resistor table for suita ble value of rosc. integrated circuits inc. aP89042 ver5.0 a ug 23, 2010 19 bonding diagram bonding pad size: 80um x 90um mode pad must be not connected. pad name location (x,y) pad name location (x,y) vdd 2199.83, 1276.99 vss 173.70, 358.65 mode 1918.34, 1281.99 out2 173.70, 138.00 s3 1652.19, 1281.99 out3 439.31, 138.00 s4 1448.56, 1281.99 cout 642.94, 138.00 sbt 1182.62, 1281.99 osc 1276.09, 138.00 rst 978.99, 1281.99 s5 1745.66, 138.00 s7 713.23, 1281.99 s6 1949.29, 138.00 s8 509.60, 1281.99 vpp 2200.12, 299.45 out1 243.99, 1281.99 s1 2200.09, 834.58 vout1 173.70, 1014.23 s2 2200.09, 1038.21 vout2 713.70, 614.27 |
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