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| kinetis k28f mcu sub-family high performance arm? cortex?-m4 mcu with 2 mb flash, 1 mb sram, 2 usb controllers (high-speed and full- speed), sdram controller, quadspi interface and power management controller with core voltage bypass. k28f extends the kinetis micontroller portfolio with large embedded memory, advanced external memory interfaces, performance, and peripheral integration while maintaining a high level of software compatibility with previous kinetis devices: ? the extended memory resources include a total of 2 mb of programmable flash and 1 mb of embedded sram which can be used to support application needs for data logging and rich human to machine interfaces with displays ? the power management controller with core voltage bypass enables the use of an external pmic to maximize the power efficiency of the system ? k28f enables memory expansion leveraging the sdram controller and quadspi interface for execution-in-place (xip) from an external serial nor flash ? both the usb high-speed and crystal-less full-speed controllers integrate a phy to reduce bom cost ? the integrated smart peripherals such as low-power uarts and timers operate in very low-power modes to optimize battery life of the system performance ? up to 150 mhz arm cortex-m4 based core with dsp instructions and single precision floating point unit (fpu) memories and memory expansion ? 2 mb dual bank program flash and 1 mb sram ? 8 kb i/d + 8 kb system cache ? 32-bit external bus interface (flexbus) ? 32-bit sdram controller ? dual quadspi interface with execution-in-place (xip) ? supports sdr and ddr serial flash and octal configurations ? 32 kb boot rom with built-in bootloader system and clocks ? 32-ch asynchronous dma ? multiple low-power modes ? memory protection unit with multi-master protection ? 3 to 32 mhz main crystal oscillator ? 32 khz low power crystal oscillator ? 48 mhz internal reference ? hardware and software watchdogs human-machine interface ? up to 120 general-purpose input/output (gpios) analog modules ? power management control (pmc) with core voltage bypass ? one 16-bit sar adcs, two 6-bit dac and one 12-bit dac ? two analog comparators (cmp) containing a 6-bit dac and programmable reference input ? 1.2 v voltage reference timers ? one 4-ch 32-bit periodic interrupt timer ? two 16-bit low-power timer pwm modules ? two 8-ch motor control/general purpose/pwm timers ? two 2-ch quadrature decoder/general purpose timers ? real-time clock with independent 3.6 v power domain ? programmable delay block operating characteristics ? temperature range (ambient): -40 to 105c (bga) temperature range (ambient):-40 to 85c (wlcsp) mk28fn2m0cau15r mk28fn2m0vmi15 169 mapbga (mi) 9 x 9 x 1.28 mm pitch 0.65 mm 210 wlcsp (au) 6.9 mm x 6.9 x 0.6 mm pitch 0.4 mm nxp semiconductors K28P210M150SF5 data sheet: technical data rev. 4, 03/2017 nxp reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
security ? hardware random-number generator ? memory mapped crypto acceleration unit(mmcau): des, 3-des, aes, sha-1, sha-256 and md5 accelerator ? cyclic redundancy check (crc) target applications ? wearables ? low-end graphic display system ? cost-optimized multi-standard wireless smart home hubs ? home automation devices ? consumer accessories ? main v dd voltage and flash write voltage range:1.71 vC3.6 v ? v dd_core : 1.17 vC1.47 v ? independent v ddio_e (quadspi):1.71 vC3.6 v ? independent v bat (rtc): 1.71 vC3.6 v ? i/o voltage range (v dd ): 1.71 vC3.6 v communication interfaces ? two usb controllers:crystal-less full-/low-speed + transceiver host and device; high-/full-/low-speed + phy host and device ? secure digital host controller (sdhc) ? two i2s modules, four i2c modules and five low- power uart modules ? four spi modules (spi3 supports more than 40 mbps) ? 32-ch programmable module (flexio) to emulate various serial, parallel or custom interfaces ordering information 1 part number embedded memory package type maximum number of i\o's flash sram mk28fn2m0vmi15 2 mb 1 mb 169 mapbga 120 mk28fn2m0cau15r 2 mb 1 mb 210 wlcsp 120 1. to confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search. device revision number device mask set number sim_sdid[revid] jtag id register[prn] 2n96t 0010 0010 related resources type description resource fact sheet the fact sheet gives overview of the product key features and its uses. k2x fact sheet reference manual the reference manual contains a comprehensive description of the structure and function (operation) of a device. K28P210M150SF5rm 1 data sheet the data sheet includes electrical characteristics and signal connections. this document chip errata the chip mask set errata provides additional or corrective information for a particular device mask set. kinetis_k_2n96t 1 package drawing package dimensions are provided in package drawings. ? mapbga 169-pin: 98asa00628d 1 ? wlcsp 210-pin: 98asa01002d 1 1. to find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors cryptographic accelerator (cau) trace port jtag & serial wire swj-dp tpiu arm cortex m4 ppb ahb-ap etm dsp fpu nvic itm fpb dwt system icode dcode 256 kbyte 256 kbyte sram mux cache 8 kbyte m0 m1 8 kbyte m3 m2 m4 pit wic rtc osc osc irc 48 mhz mcg irc 4 mhz pll fll dma mux x2 edma esdhc usb/ fs/ls dcd crossbar switch (xbs) system memory protection unit (mpu) s1 s5 s0 qspi boot rom flash controller sdramc flexbus s2 s3 bme2 rgpio ahb to ips 0 ahb to ips 1 pitpdb spi x4 6-bit dac & cmp x2 flexio 16-bit adc vref i2c x4 lpuart x5 flextimer x4 trng cmt tpm x2 crc 12-bit dac i2s x2 rtc low-power timer x2 pmc with bypass 512 kbyte ocram s6 usb vreg usb hs/fs/ ls hs dcd m5 x128 flash 512 kbyte 512 kbyte 4 kbyte eeram 512 kbyte 512 kbyte pll s4 figure 1. k28f block diagram kinetis k28f mcu sub-family, rev. 4, 03/2017 3 nxp semiconductors table of contents 1 ratings.................................................................................... 5 1.1 thermal handling ratings................................................. 5 1.2 moisture handling ratings................................................ 5 1.3 esd handling ratings....................................................... 5 1.4 voltage and current maximum ratings............................. 5 1.4.1 recommended power-on-reset (por) sequencing ......................................................... 6 2 general................................................................................... 7 2.1 ac electrical characteristics............................................. 7 2.2 nonswitching electrical specifications.............................. 7 2.2.1 voltage and current operating requirements....... 7 2.2.2 hvd, lvd and por operating requirements...... 8 2.2.3 voltage and current operating behaviors............. 9 2.2.4 power mode transition operating behaviors........ 11 2.2.5 power consumption operating behaviors............ 12 2.2.6 electromagnetic compatibility (emc) specifications....................................................... 23 2.2.7 designing with radiated emissions in mind.......... 23 2.2.8 capacitance attributes......................................... 23 2.3 switching specifications................................................... 23 2.3.1 device clock specifications.................................. 23 2.3.2 general switching specifications......................... 24 2.4 thermal specifications..................................................... 25 2.4.1 thermal operating requirements......................... 25 2.4.2 thermal attributes................................................ 26 3 peripheral operating requirements and behaviors.................. 27 3.1 core modules.................................................................. 27 3.1.1 debug trace timing specifications........................ 27 3.1.2 jtag electricals.................................................. 28 3.2 clock modules................................................................. 31 3.2.1 mcg specifications.............................................. 31 3.2.2 irc48m specifications......................................... 34 3.2.3 oscillator electrical specifications........................ 35 3.2.4 32 khz oscillator electrical characteristics........... 37 3.3 memories and memory interfaces................................... 37 3.3.1 quadspi ac specifications................................. 37 3.3.2 flash electrical specifications.............................. 43 3.3.3 flexbus switching specifications.......................... 45 3.3.4 sdram controller specifications......................... 47 3.4 analog............................................................................. 50 3.4.1 adc electrical specifications............................... 50 3.4.2 cmp and 6-bit dac electrical specifications....... 54 3.4.3 12-bit dac electrical characteristics.................... 56 3.4.4 voltage reference electrical specifications.......... 59 3.5 timers.............................................................................. 60 3.6 communication interfaces............................................... 60 3.6.1 usb voltage regulator electrical specifications.. 61 3.6.2 usb full speed transceiver and high speed phy specifications............................................... 62 3.6.3 usb dcd electrical specifications....................... 62 3.6.4 dspi switching specifications (limited voltage range).................................................................. 63 3.6.5 dspi switching specifications (full voltage range).................................................................. 66 3.6.6 inter-integrated circuit interface (i2c) timing...... 68 3.6.7 lpuart switching specifications........................ 70 3.6.8 sdhc specifications............................................ 70 3.6.9 i2s switching specifications................................. 72 4 dimensions............................................................................. 78 4.1 obtaining package dimensions....................................... 78 5 pinout...................................................................................... 78 5.1 k28f signal multiplexing and pin assignments.............. 78 5.2 recommended connection for unused analog and digital pins........................................................................ 79 5.3 k28f pinouts................................................................... 80 6 ordering parts......................................................................... 80 6.1 determining valid orderable parts.................................... 80 7 part identification..................................................................... 81 7.1 description....................................................................... 81 7.2 format............................................................................. 81 7.3 fields............................................................................... 81 7.4 example........................................................................... 82 8 terminology and guidelines.................................................... 82 8.1 definitions........................................................................ 82 8.2 examples......................................................................... 83 8.3 typical-value conditions.................................................. 83 8.4 relationship between ratings and operating requirements.................................................................... 84 8.5 guidelines for ratings and operating requirements.......... 84 9 revision history...................................................................... 85 4 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 1 ratings 1.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level (for v-temp variant) 3 1 msl moisture sensitivity level (for c-temp variant) 1 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model -2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 105c -100 +100 ma 3 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 3. determined according to jedec standard jesd78, ic latch-up test . 1.4 voltage and current maximum ratings ratings kinetis k28f mcu sub-family, rev. 4, 03/2017 5 nxp semiconductors symbol description min. max. unit v dd_core 1 internal digital logic supply voltage C 0.3 1.47 v v dd digital supply voltage for ports a, b,c,d C0.3 3.8 v v dda analog supply voltage C 0.3 3.8 v v ddio_e v ddio_e is an independent voltage supply for porte 2 C0.3 3.8 v v bat rtc supply voltage C0.3 3.8 v i dd digital supply current 300 ma i d maximum current single pin limit (digital output pins) C25 25 ma v regin usb regulator input C0.3 6.0 v v usb0_dx usb0_dp and usb_dm input voltage C0.3 3.63 v v usb1_dpx usb1_dp and usb1_dm input voltage C0.3 3.63 v 1. v dd_core must not exceed v dd on power up or power down 2. v ddio_e is independent of the v dd domain and can operate at a voltage independent of v dd . 1.4.1 recommended power-on-reset (por) sequencing ? v dd /v ddio_e and v dd_core figure 2. v dd_core / v dd powering sequence ratings 6 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 2 general 2.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% v il input signal v ih fall time high low rise time midpoint1 the midpoint is v il + (v ih - v il ) / 2 figure 3. input signal measurement reference all digital i/o switching characteristics assume: 1. output pins ? have c l =15 pf loads, ? are slew rate disabled, and ? are normal drive strength 2. input pins ? have their passive filter disabled (portx_pcrn[pfe]=0) 2.2 nonswitching electrical specifications 2.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd_core (run) core and digital logic supply voltage for run mode 1.17 1.32 v v dd_core (hsrun) core and digital logic supply voltage for hsrun 1.33 1.47 v table continues on the next page... general kinetis k28f mcu sub-family, rev. 4, 03/2017 7 nxp semiconductors table 1. voltage and current operating requirements (continued) symbol description min. max. unit notes v dd digital supply voltage for ports a, b, c,d 1.71 3.6 v v ddio_e digital supply voltage for port e 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v bat rtc battery supply voltage 1.71 3.6 v v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v ih_e input high voltage ? 2.7 v v ddio_e 3.6 v ? 1.7 v v ddio_e 2.7 v 0.7 v ddio_e 0.75 v ddio_e v v v il_e input low voltage ? 2.7 v v ddio_e 3.6 v ? 1.7 v v ddio_e 2.7 v 0.35 v ddio_e 0.3 v ddio_e v v v hys input hysteresis 0.06 v dd v v hys_e input hysteresis 0.06 v ddio_e v i icio i/o pin negative dc injection current single pin ? v in < v ss -0.3v -5 ma 1 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins ? negative current injection -25 ma v odpu pseudo open drain pullup voltage level v dd v dd v 2 v ram v dd_core voltage required to retain ram 1.14 1.47 v v rfvbat v bat voltage required to retain the vbat register file v por_vbat v 1. all i/o pins are internally clamped to v ss through an esd protection diode. there is no diode connection to v dd or v ddio_e . if v in is less than -0.3v, a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(-0.3-v in )/|i icio |. the actual resistor value should be an order of magnitude higher to tolerate transient voltages. 2. open drain outputs must be pulled to vdd. general 8 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 2.2.2 hvd, lvd and por operating requirements table 2. v dd supply hvd, lvd and por operating requirements symbol description min. typ. max. unit notes v hvdh high voltage detect (high trip point) 3.72 v v hvdl high voltage detect (low trip point) 3.46 v v por falling vdd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 60 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 40 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising threshold is the sum of falling threshold and hysteresis voltage note there is no lvd circuit for v ddio_e and v dd_core domain. table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage 0.8 1.1 1.5 v general kinetis k28f mcu sub-family, rev. 4, 03/2017 9 nxp semiconductors 2.2.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. typ. 1 max. unit notes v oh output high voltage normal drive strength io group 1 ? 2.7 v v bat 3.6 v, i oh = -5 ma ? 1.71 v v bat 2.7 v, i oh = -2.5 ma io groups 2 and 3 ? 2.7 v v dd 3.6 v, i oh = -10 ma ? 1.71 v v dd 2.7 v, i oh = -5 ma io group 4 ? 2.7 v v ddio_e 3.6 v, i oh = -5 ma ? 1.71 v v ddio_e 2.7 v, i oh = -2.5 ma v bat C 0.5 v bat C 0.5 v dd C 0.5 v dd C 0.5 v ddio_e C 0.5 v ddio_e C 0.5 v v v v v v 2 , 3 output high voltage high drive strength io group 3 ? 2.7 v v dd 3.6 v, i oh = -20 ma ? 1.71 v v dd 2.7 v, i oh = -10 ma io group 4 ? 2.7 v v ddio_e 3.6 v, i oh = -15 ma ? 1.71 v v ddio_e 2.7 v, i oh = -7.5 ma v dd C 0.5 v dd C 0.5 v ddio_e C 0.5 v ddio_e C 0.5 v v v v 2 i oht output high current total for all ports 100 ma v ol output low voltage normal drive strength io group 1 ? 2.7 v v bat 3.6 v, i ol = -5 ma ? 1.71 v v bat 2.7 v, i ol = -2.5 ma io groups 2 and 3 ? 2.7 v v dd 3.6 v, i ol = -10 ma ? 1.71 v v dd 2.7 v, i ol = -5 ma io group 4 ? 2.7 v v ddio_e 3.6 v, i ol = -5 ma ? 1.71 v v ddio_e 2.7 v, i ol = -2.5 ma 0.5 0.5 0.5 0.5 0.5 0.5 v v v v v v 2 , 4 , 5 output low voltage high drive strength io group 3 ? 2.7 v v dd 3.6 v, i ol = -20 ma ? 1.71 v v dd 2.7 v, i ol = -10 ma io group 4 ? 2.7 v v ddio_e 3.6 v, i ol = -15 ma ? 1.71 v v ddio_e 2.7 v, i ol = -7.5 ma 0.5 0.5 0.5 0.5 v v v v 2 , 4 i olt output low current total for all ports 100 ma i in input leakage current 6 , 7 , 8 table continues on the next page... general 10 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors table 4. voltage and current operating behaviors (continued) symbol description min. typ. 1 max. unit notes v dd domain pins ? v ss v in v dd porte pins ? v ss v in v ddio_e v bat domain pins ? v ss v in v bat 0.002 0.002 0.002 0.5 0.5 0.5 a a a r pu internal pullup resistors(except rtc_wakeup pins) 20 50 k? 9 r pd internal pulldown resistors (except rtc_wakeup pins) 20 50 k? 10 1. typical values characterized at 25c and v dd = 3.6v unless otherwise noted. 2. io group 1 includes v bat domain pins: rtc_wakeup_b. io group 2 includes v dd domain pins: porta, portb, portc, and portd, except pta4. io group 3 includes v dd domain pins: ptb0, ptb1, ptc3, ptc4, ptd4, ptd5, ptd6, and ptd7. io group 4 includes v ddio_e domain pins: porte. 3. pta4 has lower drive strength: i oh = -5 ma for high v dd range; i oh = -2.5 ma for low v dd range. 4. open drain outputs must be pulled to v dd . 5. pta4 has lower drive strength: i ol = 5ma for high v dd range; i ol = 2.5ma for low v dd range. 6. v dd domain pins include adc, cmp, and reset_b inputs. measured at v dd = 3.6v. 7. porte analog input voltages cannot exceed v ddio_e supply when v dd v ddio_e . porte analog input voltages cannot exceed v dd supply when v dd ? v ddio_e . 8. v bat domain pins include extal32, xtal32, and rtc_wakeup_b pins. 9. measured at minimum supply voltage and v in = v ss 10. measured at minimum supply voltage and v in = v dd 2.2.4 power mode transition operating behaviors all specifications except t por , and vllsx C> run recovery times in the following table assume this clock configuration: ? cpu and system clocks = 100 mhz ? bus clock = 50 mhz ? flexbus clock = 50 mhz ? flash clock = 25 mhz ? mcg mode=fei table 5. power mode transition operating behaviors symbol description min. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v and vdd_core reaches 1.17 v to execution of the first instruction across the operating temperature range of the chip. 1200 s table continues on the next page... general kinetis k28f mcu sub-family, rev. 4, 03/2017 11 nxp semiconductors table 5. power mode transition operating behaviors (continued) symbol description min. max. unit notes ? vlls2 C> run 103 s ? vlls3 C> run 103 s ? lls2 C> run 6.3 s ? lls3 C> run 6.3 s ? vlps C> run 5.4 s ? stop C> run 5.4 s 2.2.5 power consumption operating behaviors figure 4. power supplies of k28f the k28f device has several power supplies and the total current consumption of the device is the accumulative result of each individual power supplies current consumption, dependent on the power mode of operation. (run, hsrun, vlpr, stop, vlls3 etc.). idd_mcu_total = iddc + idd + iddio_e + idd_vbat + idda + idd_usb when calculating the total mcu current consumption considerations to external loads on the following should be made: ? on top of the devices idd current consumption, external loads applied to ports a,b,c and d need to be considered general 12 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors ? iddio_e current consumption is significantly dependent on external loads applied to port e pins, and the internal current consumption in the device is negligible compared to idd. ? the usb_vreg provides a 3.3 v output which can drive loads of upto 150 ma need to be considered. the maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). table 6 details the iddc values observed through the vdd_core supply and table 7 details the idd values observed through the vdd supply. table 6. power consumption operating behaviors (through vdd_core) symbol description min. typ. max. unit notes i dda analog supply current see note ma 1 i ddc_run run mode current all peripheral clocks disabled, code of while(1) loop executing from internal flash at 1.2 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 31.0 37.9 42.7 51.9 35.1 51.6 63.6 85.7 ma 2 i ddc_run run mode current all peripheral clocks enabled, code of while(1) loop executing from internal flash at 1.2 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 41.6 48.0 52.6 61.1 47.1 65.5 78.4 100.9 ma 2 i ddc_runco run mode current in compute operation - 120 mhz core / 24 mhz flash / bus clock disabled, code of while(1) loop executing from internal flash at 1.2 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 28.5 35.5 40.3 49.5 32.4 48.4 60.1 81.6 ma 3 i ddc_hsrun high-speed run mode current all peripheral clocks disabled, code of while(1) loop executing from internal flash at 1.4 v ? @ 25c ? @ 70c 42.6 53.5 49.6 74.9 ma 4 table continues on the next page... general kinetis k28f mcu sub-family, rev. 4, 03/2017 13 nxp semiconductors table 6. power consumption operating behaviors (through vdd_core) (continued) symbol description min. typ. max. unit notes ? @ 85c ? @ 105c 59.7 71.7 91.3 121.0 i ddc_hsrun high-speed run mode current all peripheral clocks enabled, code of while(1) loop executing from internal flash at 1.4 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 54.3 65.7 71.5 82.6 63.3 91.9 109.8 139.0 ma 4 i ddc_hsrunco high-speed run mode current in compute operation C 150 mhz core/ 25 mhz flash / bus clock disabled, code of while(1) loop executing from internal flash at 1.4 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 40.5 50.7 57.1 68.7 47.2 70.9 87.2 115.7 ma 3 i ddc_wait wait mode high frequency current at 1.2 v all peripheral clocks disabled ? @ 25c ? @ 70c ? @ 85c ? @ 105c 15.6 23.2 28.3 38.1 17.7 31.6 42.2 62.8 ma 2 i ddc_wait wait mode reduced frequency current at 1.2 v all peripheral clocks disabled ? @ 25c ? @ 70c ? @ 85c ? @ 105c 7.0 15.0 20.3 30.5 7.9 20.4 30.3 50.4 ma 5 i ddc_vlpr very-low-power run mode current at 1.2 v all peripheral clocks disabled, code of while(1) loop executing out of internal flash ? @ 25c ? @ 70c ? @ 85c ? @ 105c 1.2 2.6 3.8 6.2 3.9 7.1 9.7 15.0 ma 6 table continues on the next page... general 14 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors table 6. power consumption operating behaviors (through vdd_core) (continued) symbol description min. typ. max. unit notes i ddc_vlpr very-low-power run mode current at 1.2 v all peripheral clocks enabled, code of while(1) loop executing out of internal flash ? @ 25c ? @ 70c ? @ 85c ? @ 105c 1.7 3.1 4.3 6.7 5.5 8.5 11.0 16.2 ma 6 i ddc_vlprco very-low-power run mode current in compute operation - 4 mhz core / 1 mhz flash / bus clock disabled, code of while(1) loop executing from internal flash at 1.2 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 1.1 2.5 3.7 6.1 3.6 6.9 9.5 14.8 ma 7 i ddc_pstop2 stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 mhz bus at 1.2 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 4.4 9.8 13.0 15.7 14.2 26.5 33.4 37.9 ma 3 i ddc_vlpw very-low-power wait mode current at 1.2 v all peripheral clocks disabled ? @ 25c ? @ 70c ? @ 85c ? @ 105c 0.759 2.2 3.3 5.8 2.5 5.9 8.6 14.0 ma 6 i ddc_vlpw very-low-power wait mode current at 1.2 v all peripheral clocks enabled ? @ 25c ? @ 70c ? @ 85c ? @ 105c 1.2 2.7 3.8 6.3 4.0 7.2 9.8 15.1 ma 6 i ddc_stop stop mode current at 1.2 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 0.749 3.4 5.4 9.1 1.9 7.5 11.3 18.7 ma table continues on the next page... general kinetis k28f mcu sub-family, rev. 4, 03/2017 15 nxp semiconductors table 6. power consumption operating behaviors (through vdd_core) (continued) symbol description min. typ. max. unit notes i ddc_vlps very-low-power stop mode current at 1.2 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 0.452 2.2 3.4 5.8 1.2 4.9 7.4 12.4 ma i ddc_lls3 low leakage stop mode current at 1.2 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 15.6 129.0 244.9 535.0 30.3 189.5 347.8 737.3 a i ddc_lls2 low leakage stop mode current at 1.2 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 4.3 33.8 62.8 135.6 8.7 57.3 104.0 205.8 a 8 i ddc_vlls3 very low-leakage stop mode 3 current at 1.2 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 13.5 112.1 212.5 460.2 26.0 159.7 294.7 621.6 a i ddc_vlls2 very low-leakage stop mode 2 current at 1.2 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 0.552 6.1 10.5 24.7 0.9 8.2 14.2 32.3 a 8 i dd_vbat average current with rtc and 32 khz disabled @ 3.0 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 0.266 0.595 0.933 2.2 0.319 0.750 1.3 2.8 a i dd_vbat average current when cpu is not accessing rtc registers @ 1.8 v a 9 general 16 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors table 6. power consumption operating behaviors (through vdd_core) symbol description min. typ. max. unit notes ? @ 25c ? @ 70c ? @ 85c ? @ 105c 0.454 0.724 1.1 2.0 0.546 0.897 1.4 2.6 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. 2. 120 mhz core and system clock, 60 mhz bus and flexbus clock, and 24 mhz flash clock. mcg configured for pee mode. 3. mcg configured for pee mode. 4. 150 mhz core and system clock, 50 mhz bus and flexbus clock, and 25 mhz flash clock. mcg configured for pee mode. 5. 25 mhz core and system clock, 25 mhz bus and flexbus clock, and 25 mhz flash clock. mcg configured for fei mode 6. 4 mhz core, system, flexbus, and bus clock and 1 mhz flash clock. mcg configured for blpe mode. code executing from flash. 7. mcg configured for blpe mode. 8. by default, this mode only has 32 k of sram enabled. 9. includes 32 khz oscillator current and rtc operation. table 7. power consumption operating behaviors (through vdd) symbol description min. typ. max. unit notes i dd_run run mode current all peripheral clocks disabled, code of while(1) loop executing from internal flash @ 3.0 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 ma 1 i dd_run run mode current all peripheral clocks enabled, code of while(1) loop executing from internal flash @ 3.0 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 ma 1 i dd_runco run mode current in compute operation - 120 mhz core / 24 mhz flash / bus clock disabled, code of while(1) loop executing from internal flash at 3.0 v ? @ 25c ? @ 70c 1.5 1.5 1.6 1.7 ma 2 table continues on the next page... general kinetis k28f mcu sub-family, rev. 4, 03/2017 17 nxp semiconductors table 7. power consumption operating behaviors (through vdd) (continued) symbol description min. typ. max. unit notes ? @ 85c ? @ 105c 1.6 1.6 1.7 1.7 i dd_hsrun run mode current all peripheral clocks disabled, code of while(1) loop executing from internal flash @ 3.0 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 ma 3 i dd_hsrun run mode current all peripheral clocks enabled, code of while(1) loop executing from internal flash @ 3.0 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 ma 3 i dd_hsrunco hsrun mode current in compute operation C 150 mhz core/ 25 mhz flash / bus clock disabled, code of while(1) loop executing from internal flash at 3.0 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 ma 2 i dd_wait wait mode high frequency current at 3.0 v all peripheral clocks disabled ? @ 25c ? @ 70c ? @ 85c ? @ 105c 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 ma 1 i dd_wait wait mode reduced frequency current at 3.0 v all peripheral clocks disabled ? @ 25c ? @ 70c ? @ 85c ? @ 105c 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 ma 4 table continues on the next page... general 18 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors table 7. power consumption operating behaviors (through vdd) (continued) symbol description min. typ. max. unit notes i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled ? @ 25c ? @ 70c ? @ 85c ? @ 105c 24.9 31.2 39.6 63.9 48.0 70.1 84.5 157.5 a 5 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled ? @ 25c ? @ 70c ? @ 85c ? @ 105c 25.2 31.5 40.0 64.3 48.6 70.6 85.0 158.4 a 5 i dd_vlprco very-low-power run mode current in compute operation - 4 mhz core / 0.8 mhz flash / bus clock disabled, while(1) code executing from internal flash at 3.0 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 8.3 14.4 22.7 47.0 16.0 32.3 48.5 115.8 a 6 i dd_pstop2 stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 mhz bus at 3.0 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 1.8 1.8 1.9 1.9 3.5 4.1 3.9 4.6 ma 2 i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks disabled ? @ 25c ? @ 70c ? @ 85c ? @ 105c 24.9 31.0 39.2 63.7 47.8 69.5 83.6 157.0 a 5 i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks enabled ? @ 25c ? @ 70c 25.0 31.2 48.1 70.0 a 5 table continues on the next page... general kinetis k28f mcu sub-family, rev. 4, 03/2017 19 nxp semiconductors table 7. power consumption operating behaviors (through vdd) (continued) symbol description min. typ. max. unit notes ? @ 85c ? @ 105c 39.6 63.9 84.3 157.5 i dd_stop stop mode current at 3.0 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 159.3 173.8 181.4 251.2 279.3 341.8 358.4 735.0 a i dd_vlps very-low-power stop mode current at 3.0 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 3.1 8.5 15.2 36.9 5.6 12.0 19.4 43.9 a i dd_lls3 low leakage stop mode current at 3.0 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 2.9 7.2 13.2 33.4 4.7 9.2 16.1 39.4 a i dd_lls2 low leakage stop mode current at 3.0 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 2.9 7.2 13.2 33.4 4.7 9.2 16.1 39.4 a 7 i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v ? @ 25c ? @ 70c ? @ 85c ? @ 105c 2.2 4.7 8.1 18.8 3.4 6.4 10.6 23.8 a i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v ? @ 25c ? @ 70c 2.2 4.5 3.3 6.1 a 7 general 20 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors table 7. power consumption operating behaviors (through vdd) symbol description min. typ. max. unit notes ? @ 85c ? @ 105c 7.7 17.5 10.0 22.0 1. 120 mhz core and system clock, 60 mhz bus and flexbus clock, and 24 mhz flash clock. mcg configured for pee mode. 2. mcg configured for pee mode. 3. 150 mhz core and system clock, 50 mhz bus and flexbus clock, and 25 mhz flash clock. mcg configured for pee mode. 4. 25 mhz core and system clock, 25 mhz bus and flexbus clock, and 25 mhz flash clock. mcg configured for fei mode. 5. 4 mhz core, system, flexbus, and bus clock and 1 mhz flash clock. mcg configured for blpe mode. code executing from flash. 6. mcg configured for blpe mode. 7. by default, this mode has only 32k of sram enabled. below table list the current consumption adders for different sram configurations from the lls2/vlls2 (typ) idd values using a 32 kb sram retention referenced in table 6 . table 8. lls2/vlls2 additional typical iddc current consumption adders ram array retained @ 25c @ 85c @ 105c unit lls2 ram2: 32 kb 0.5 10.8 21.3 a ram3: 32 kb 0.5 11.0 21.5 a ram4: 32 kb 0.4 10.7 21.0 a ram5: 128 kb 1.4 28.1 57.6 a ram6: 64 kb 0.6 15.2 30.5 a ram7: 192 kb 2.1 41.1 85.1 a ram8: 256 kb 2.8 53.0 109.9 a ram9: 256 kb 2.3 53.5 110.9 a vlls2 ram2: 32 kb 0.5 9.1 19.7 a ram3: 32 kb 0.5 8.5 18.0 a ram4: 32 kb 0.5 8.1 16.8 a ram5: 128 kb 1.5 26.6 57.1 a ram6: 64 kb 0.8 12.9 27.1 a ram7: 192 kb 2.3 40.2 86.6 a ram8: 256 kb 3.0 52.9 114.3 a ram9: 256 kb 3.0 53.1 114.8 a general kinetis k28f mcu sub-family, rev. 4, 03/2017 21 nxp semiconductors table 9. low power mode peripheral adders typical value symbol description temperature (c) unit -40 25 50 70 85 105 i irefsten4mhz 4 mhz internal reference clock (irc) adder. measured by entering stop or vlps mode with 4 mhz irc enabled. 56 56 56 56 56 56 a i irefsten32khz 32 khz internal reference clock (irc) adder. measured by entering stop mode with the 32 khz irc enabled. 52 52 52 52 52 52 a i erefsten4mhz external 4 mhz crystal clock adder. measured by entering stop or vlps mode with the crystal enabled. 206 228 237 245 251 258 ua i erefsten32khz external 32 khz crystal clock adder by means of the osc0_cr[erefsten and erefsten] bits. measured by entering all modes with the crystal enabled. vlls3 lls2 lls3 vlps stop 440 490 490 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 580 680 680 680 680 na i cmp cmp peripheral adder measured with cmp enabled using the 6-bit dac and a single external input for compare. includes 6-bit dac power consumption. 22 22 22 22 22 22 a i rtc rtc peripheral adder measured with external 32 khz crystal enabled by means of the rtc_cr[osce] bit and the rtc alarm set for 1 minute. includes erclk32k (32 khz external crystal) power consumption. 432 357 388 475 532 810 na i lpuart lpuart peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. mcgirclk (4 mhz internal reference clock) oscerclk (4 mhz external crystal) 66 214 66 234 66 246 66 254 66 260 66 268 a i bg bandgap adder when bgen bit is set and device is placed in vlpx, lls, or vllsx mode. 45 45 45 45 45 45 a i adc adc peripheral adder combining the measured values at v dd and v dda by placing the device in stop or vlps mode. adc is configured for low power mode using the internal clock and continuous conversions. 366 366 366 366 366 366 a general 22 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 2.2.6 electromagnetic compatibility (emc) specifications emc measurements to ic-level iec standards are available from nxp on request. 2.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions. 1. go to nxp.com 2. perform a keyword search for emc design. 2.2.8 capacitance attributes table 10. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf 2.3 switching specifications 2.3.1 device clock specifications table 11. device clock specifications symbol description min. max. unit notes high speed run mode f sys system and core clock 150 mhz normal run mode (and high speed run mode unless otherwise specified above) f sys system and core clock 120 mhz system and core clock when full speed usb in operation 20 mhz f sys_usbhs system and core clock when high speed usb in operation 100 mhz f bus bus clock 75 mhz f b_clk flexbus clock 75 mhz f flash flash clock 28 mhz table continues on the next page... general kinetis k28f mcu sub-family, rev. 4, 03/2017 23 nxp semiconductors table 11. device clock specifications (continued) symbol description min. max. unit notes f lptmr lptmr clock 25 mhz vlpr mode 1 f sys system and core clock 4 mhz f bus bus clock 4 mhz f b_clk flexbus clock 4 mhz f flash flash clock 1 mhz f erclk external reference clock 16 mhz f lptmr_pin lptmr clock 25 mhz f i2s_mclk i2s master clock 12.5 mhz f i2s_bclk i2s bit clock 4 mhz 1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. 2.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, lpuart, cmt, timers, and i 2 c signals. table 12. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 , 2 nmi_b pin interrupt pulse width (analog filter enabled) asynchronous path 100 ns gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 50 ns 3 external reset_b input pulse width (digital glitch filter disabled) 100 ns port rise and fall time (high drive strength) ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew disabled ? 1.71 v dd 2.7 v ? 2.7 v dd 3.6 v 34 16 10 8 ns ns ns ns 4 , 5 port rise and fall time (low drive strength) ? slew enabled 34 ns 6 , 7 table continues on the next page... general 24 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors table 12. general switching specifications (continued) symbol description min. max. unit notes ? 1.71 v dd 2.7 v ? 2.7 v dd 3.6 v ? slew disabled ? 1.71 v dd 2.7 v ? 2.7 v dd 3.6 v 16 7 5 ns ns ns port rise and fall time (high drive strength) ? slew enabled ? 1.71 v ddio_e 2.7 v ? 2.7 v ddio_e 3.6 v ? slew disabled ? 1.71 v ddio_e 2.7 v ? 2.7 v ddio_e 3.6 v 34 16 7 5 ns ns ns ns 5 , 8 port rise and fall time (low drive strength) ? slew enabled ? 1.71 v ddio_e 2.7 v ? 2.7 v ddio_e 3.6 v ? slew disabled ? 1.71 v ddio_e 2.7 v ? 2.7 v ddio_e 3. 6v 34 16 7 5 ns ns ns ns 7 , 8 1. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run modes. 2. the greater synchronous and asynchronous timing must be met. 3. this is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in stop, vlps, lls, and vllsx modes. 4. ptb0, ptb1, ptc3, ptc4, ptd4, ptd5, ptd6, and ptd7. 5. 75 pf load. 6. ports a, b, c, and d. 7. 25 pf load. 8. port e pins only. 2.4 thermal specifications general kinetis k28f mcu sub-family, rev. 4, 03/2017 25 nxp semiconductors 2.4.1 thermal operating requirements table 13. thermal operating requirements (for v-temp range) symbol description min. max. unit notes t j die junction temperature C40 125 c t a ambient temperature C40 105 c 1 1. maximum t a can be exceeded only if the user ensures that t j does not exceed the maximum. the simplest method to determine t j is: t j = t a + r ja x chip power dissipation table 14. thermal operating requirements (for c-temp range) symbol description min. max. unit notes t j die junction temperature C40 95 c t a ambient temperature C40 85 c 1 1. maximum t a can be exceeded only if the user ensures that t j does not exceed the maximum. the simplest method to determine t j is: t j = t a +r ja x chip power dissipation 2.4.2 thermal attributes table 15. thermal attributes board type symbol description 210 wlcsp 169 mapbga unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 68.5 56.8 c/w 1 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 32.1 27.1 c/w 1 single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 52.3 41 c/w 1 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 27.2 22.4 c/w 1 r jb thermal resistance, junction to board 16.0 10.4 c/w 2 r jc thermal resistance, junction to case 1.3 7.1 c/w 3 jt thermal characterization parameter, junction to package top outside center (natural convection) 0.2 0.2 c/w 4 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) with the single layer board horizontal. board meets jesd51-9 specification. 2. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board . general 26 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 3. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) . 3 peripheral operating requirements and behaviors 3.1 core modules 3.1.1 debug trace timing specifications table 16. debug trace operating behaviors symbol description min. max. unit t cyc clock period frequency dependent mhz t wl low pulse width 2 ns t wh high pulse width 2 ns t r clock and data rise time 3 ns t f clock and data fall time 3 ns t s data setup 1.5 ns t h data hold 1.0 ns traceclk t r t wh t f t cyc t wl figure 5. trace_clkout specifications th ts ts th trace_clkout trace_d[3:0] figure 6. trace data specifications peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 27 nxp semiconductors 3.1.2 jtag electricals table 17. jtag limited voltage range electricals symbol description min. max. unit operating voltage 2.7 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 25 50 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 20 10 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 2.0 ns j7 tclk low to boundary scan output data valid 28 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1 ns j11 tclk low to tdo data valid 19 ns j12 tclk low to tdo high-z 17 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns table 18. jtag full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 20 40 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan 50 ns table continues on the next page... peripheral operating requirements and behaviors 28 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors table 18. jtag full voltage range electricals (continued) symbol description min. max. unit ? jtag and cjtag ? serial wire debug 25 12.5 ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 2.0 ns j7 tclk low to boundary scan output data valid 30.6 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1.0 ns j11 tclk low to tdo data valid 19.0 ns j12 tclk low to tdo high-z 17.0 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns j2 j3 j3 j4 j4 tclk (input) figure 7. test clock input timing peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 29 nxp semiconductors j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 8. boundary scan (jtag) timing j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 9. test access port timing peripheral operating requirements and behaviors 30 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors j14 j13 tclk trst figure 10. trst timing 3.2 clock modules 3.2.1 mcg specifications table 19. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25 c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz i ints internal reference (slow clock) current 20 a t irefsts [o: ] internal reference (slow clock) startup time 32 s f dco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.3 0.6 %f dco 1 f dco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim only 0.2 0.5 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over voltage and temperature 1 2 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0C70c 0.5 1 %f dco 1 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal vdd and 25c 4 mhz f intf_t internal reference frequency (fast clock) user trimmed at nominal vdd and 25 c 3 5 mhz i intf internal reference (fast clock) current 25 a t irefsts [l: ] internal reference startup time (fast clock) 10 15 s f loc_low loss of external clock minimum frequency range = 00 ext clk freq: above (3/5)f int never reset (3/5) x f ints_t khz table continues on the next page... peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 31 nxp semiconductors table 19. mcg specifications (continued) symbol description min. typ. max. unit notes ext clk freq: between (2/5)fint and (3/5)f int maybe reset (phase dependency) ext clk freq: below (2/5)f int always reset f loc_high loss of external clock minimum frequency range = 01, 10, or 11 ext clk freq: above (16/5)f int never reset ext clk freq: between (15/5)f int and (16/5)f int maybe reset (phase dependency) ext clk freq: below (15/5)f int always reset (16/5) x f ints_t khz fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco_ut dco output frequency range untrimmed low range (drs=00, dmx32=0) 640 f ints_ut 16.0 23.04 26.66 mhz 2 mid range (drs=01, dmx32=0) 1280 f ints_ut 32.0 46.08 53.32 mid-high range (drs=10, dmx32=0) 1920 f ints_ut 48.0 69.12 79.99 high range (drs=11, dmx32=0) 2560 f ints_ut 64.0 92.16 106.65 low range (drs=00, dmx32=1) 732 f ints_ut 18.3 26.35 30.50 mid range (drs=01, dmx32=1) 1464 f ints_ut 36.6 52.70 60.99 mid-high range (drs=10, dmx32=1) 2197 f ints_ut 54.93 79.09 91.53 high range (drs=11, dmx32=1) 2929 f ints_ut 73.23 105.44 122.02 f dco dco output frequency range low range (drs=00) 640 f fll_ref 20 20.97 25 mhz 3 , 4 mid range (drs=01) 40 41.94 50 mhz table continues on the next page... peripheral operating requirements and behaviors 32 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors table 19. mcg specifications (continued) symbol description min. typ. max. unit notes 1280 f fll_ref mid-high range (drs=10) 1920 f fll_ref 60 62.91 75 mhz high range (drs=11) 2560 f fll_ref 80 83.89 100 mhz f dco_t_dmx3 2 dco output frequency low range (drs=00) 732 f fll_ref 23.99 mhz 5 , 6 mid range (drs=01) 1464 f fll_ref 47.97 mhz mid-high range (drs=10) 2197 f fll_ref 71.99 mhz high range (drs=11) 2929 f fll_ref 95.98 mhz j cyc_fll fll period jitter ? f dco = 48 mhz ? f dco = 98 mhz 180 150 ps t fll_acquire fll target frequency acquisition time 1 ms 7 pll f pll_ref pll reference frequency range 8 16 mhz f vcoclk_2x vco output frequency 180 360 mhz f vcoclk pll output frequency 90 180 mhz f vcoclk_90 pll quadrature output frequency 90 180 mhz i pll pll operating current ? vco @ 176 mhz (f pll_ref = 8 mhz, vdiv multiplier = 22, prdiv divide=1) 1.1 ma 8 i pll pll operating current ? vco @ 360 mhz (f pll_ref = 8 mhz, vdiv multiplier = 45, prdiv divide=1) 2 ma 8 j cyc_pll pll period jitter (rms) ? f vco = 180 mhz ? f vco = 360 mhz 100 75 ps ps 9 j acc_pll pll accumulated jitter over 1s (rms) ? f vco = 180 mhz ? f vco = 360 mhz 600 300 ps ps 9 d unl lock exit frequency tolerance 4.47 5.97 % t pll_lock lock detector detection time 150 10 -6 + 1075(1/ f pll_ref ) s 10 peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 33 nxp semiconductors 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. this applies when sctrim at value (0x80) and scftrim control bit at value (0x0). 3. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 4. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation ( f dco_t ) over voltage and temperature should be considered. 5. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=1. 6. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. excludes any oscillator currents that are also consuming power while pll is in operation. 9. this specification was obtained using a nxp developed pcb. pll jitter is dependent on the noise characteristics of each pcb and results will vary. 10. this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.2.2 irc48m specifications table 20. irc48m specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i dd48m supply current 520 a f irc48m internal reference frequency 48 mhz f irc48m_ol_lv open loop total deviation of irc48m frequency at low voltage (vdd=1.71 v-1.89 v) over temperature ? regulator disable (usb_clk_recover_irc_en[reg_en]=0) ? regulator enable (usb_clk_recover_irc_en[reg_en]=1) 0.5 0.5 1.0 1.5 %f irc48m f irc48m_ol_hv open loop total deviation of irc48m frequency at high voltage (vdd=1.89 v-3.6 v) over temperature ? regulator enable (usb_clk_recover_irc_en[reg_en]=1) 0.5 1.0 %f irc48m f irc48m_cl closed loop total deviation of irc48m frequency over voltage and temperature 0.1 %f host 1 j cyc_irc48m period jitter (rms) 35 150 ps t irc48mst startup time 2 3 s 2 1. closed loop operation of the irc48m is only feasible for usb device operation; it is not usable for usb host operation. it is enabled by configuring for usb device, selecting irc48m as usb clock source, and enabling the clock recover function (usb_clk_recover_irc_ctrl[clock_recover_en]=1, usb_clk_recover_irc_en[irc_en]=1). 2. irc48m startup time is defined as the time between clock enablement and clock availability for system use. enable the clock by one of the following settings: ? usb_clk_recover_irc_en[irc_en]=1, or ? mcg_c7[oscsel]=10, or ? sim_sopt2[pllfllsel]=11 peripheral operating requirements and behaviors 34 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 3.2.3 oscillator electrical specifications 3.2.3.1 oscillator dc electrical specifications table 21. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 600 200 300 950 1.2 1.5 na a a a ma ma 1 i ddosc supply current high gain mode (hgo=1) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 7.5 500 650 2.5 3.25 4 a a a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low- power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) table continues on the next page... peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 35 nxp semiconductors table 21. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes 0 k v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c, internal capacitance = 20 pf 2. see crystal or resonator manufacturer's recommendation 3. c x ,c y can be provided by using either the integrated capacitors or by using external components. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 3.2.3.2 oscillator frequency specifications table 22. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low- frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high- frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 750 ms 1 , 2 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. proper pc board layout procedures must be followed to achieve specifications. peripheral operating requirements and behaviors 36 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 2. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. note the 32 khz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 3.2.4 32 khz oscillator electrical characteristics 3.2.4.1 32 khz oscillator dc electrical specifications table 23. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m c para parasitical capacitance of extal32 and xtal32 5 7 pf v pp 1 peak-to-peak amplitude of oscillation 0.6 v 1. when a crystal is being used with the 32 khz oscillator, the extal32 and xtal32 pins should only be connected to required oscillator components and must not be connected to any other devices. 3.2.4.2 32 khz oscillator frequency specifications table 24. 32 khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32.768 khz t start crystal start-up time 1000 ms 1 f ec_extal32 externally provided input clock frequency 32.768 khz 2 v ec_extal32 externally provided input clock amplitude 700 v bat mv 2 , 3 1. proper pc board layout procedures must be followed to achieve specifications. 2. this specification is for an externally supplied clock driven to extal32 and does not apply to any other clock input. the oscillator remains enabled and xtal32 must be left unconnected. 3. the parameter specified is a peak-to-peak value and v ih and v il specifications do not apply. the voltage of the applied clock must be within the range of v ss to v bat . 3.3 memories and memory interfaces peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 37 nxp semiconductors 3.3.1 quadspi ac specifications ? all data is based on a negative edge data launch from the device and a positive edge data capture, as shown in the timing diagrams in this section. ? measurements are with a load of 15 pf (1.8 v) and 35 pf (3 v) on output pins. input slew: 1 ns ? timings assume a setting of 0x0000_000x for quadspi _smpr register (see the reference manual for details). the following table lists the quadspi delay chain read/write settings. refer the device reference manual for register and bit descriptions. table 25. quadspi delay chain read/write settings mode quadspi registers notes quadspi_mcr[dq s_en] quadspi_soccr[ soccfg] quadspi_mcr[sc lkcfg] quadspi_flshcr[ tdh] sdr yes 3fh 5 no delay of 63 buffer and 64 mux ddr yes 3fh 1 2 delay of 63 buffer and 64 mux hyperflash rds driven from flash 0h no 2 delay of 1 mux sdr mode 1 2 3 tck tcss tcsh tis tih clock sfck cs data in figure 11. quadspi input timing (sdr mode) diagram note ? the below timing values are with default settings for sampling registers like quadspi_smpr. peripheral operating requirements and behaviors 38 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors ? a negative time indicates the actual capture edge inside the device is earlier than clock appearing at pad. ? the below timing are for a load of 15 pf (1.8 v) and 35 pf (3 v) or output pads ? all board delays need to be added appropriately ? input hold time being negative does not have any implication or max achievable frequency table 26. quadspi input timing (sdr mode) specifications symbol parameter value unit min max t is setup time for incoming data 4 - ns t ih hold time requirement for incoming data 1.5 - ns 1 2 3 toh tov tck tcss tcsh clock sfck cs data out figure 12. quadspi output timing (sdr mode) diagram table 27. quadspi output timing (sdr mode) specifications symbol parameter value unit min max t ov output data valid - 2.8 ns t oh output data hold -1.4 - ns t ck sck clock period - 100 mhz t css chip select output setup time 2 - ns t csh chip select output hold time -1 - ns note for any frequency setup and hold specifications of the memory should be met. peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 39 nxp semiconductors ddr mode 1 2 3 tck tcss tcsh tis tih clock sfck cs data in figure 13. quadspi input timing (ddr mode) diagram note ? numbers are for a load of 15 pf (1.8 v) and 35 pf (3 v) ? the numbers are for setting of hold condition in register quadspi_smpr[ddrsnp] table 28. quadspi input timing (ddr mode) specifications symbol parameter value unit min max t is setup time for incoming data 4 (without learning) - ns 1 (with learning) t ih hold time requirement for incoming data 1.5 - ns peripheral operating requirements and behaviors 40 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 1 2 3 tck tcss tcsh tov toh clock sfck cs data out figure 14. quadspi output timing (ddr mode) diagram table 29. quadspi output timing (ddr mode) specifications symbol parameter value unit min max t ov output data valid - 4.5 ns t oh output data hold 1.5 - ns t ck sck clock period - 75 (with learning) mhz - 45 (without learning) t css chip select output setup time 2 - clk(sck) t csh chip select output hold time -1 - clk(sck) hyperflash mode peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 41 nxp semiconductors ts min rds di[7:0] th min figure 15. quadspi input timing (hyperflash mode) diagram table 30. quadspi input timing (hyperflash mode) specifications symbol parameter value unit min max ts min setup time for incoming data 2 - ns th min hold time requirement for incoming data 2 - ns ck ck 2 t ho t dvo tclk skmax tclk skmin output invalid data figure 16. quadspi output timing (hyperflash mode) diagram table 31. quadspi output timing (hyperflash mode) specifications symbol parameter value unit min max tdv max output data valid - 4.3 ns table continues on the next page... peripheral operating requirements and behaviors 42 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors table 31. quadspi output timing (hyperflash mode) specifications (continued) symbol parameter value unit min max tho output data hold 1.3 - ns tclk skmax ck to ck2 skew max - t/4 + 0.5 ns tclk skmin ck to ck2 skew min t/4 - 0.5 - ns note maximum clock frequency = 75 mhz. 3.3.2 flash electrical specifications this section describes the electrical characteristics of the flash memory module. 3.3.2.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 32. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm8 program phrase high-voltage time 7.5 18 s t hversscr erase flash sector high-voltage time 13 113 ms 1 t hversblk512k erase flash block high-voltage time for 512 kb 413 3616 ms 1 1. maximum time based on expectations at cycling end-of-life. 3.3.2.2 flash timing specifications commands table 33. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk512k read 1s block execution time ? 512 kb program flash 1.8 ms t rd1sec4k read 1s section execution time (4 kb flash) 100 s 1 t pgmchk program check execution time 95 s 1 t rdrsrc read resource execution time 40 s 1 t pgm8 program phrase execution time 90 150 s erase flash block execution time 2 table continues on the next page... peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 43 nxp semiconductors table 33. flash command timing specifications (continued) symbol description min. typ. max. unit notes t ersblk512k ? 512 kb program flash 435 3700 ms t ersscr erase flash sector execution time 15 115 ms 2 t pgmsec1k program section execution time (1 kb flash) 5 ms t rd1all read 1s all blocks execution time 6.7 ms t rdonce read once execution time 30 s 1 t pgmonce program once execution time 90 s t ersall erase all blocks execution time 1750 14,800 ms 2 t vfykey verify backdoor access key execution time 30 s 1 t ersallu erase all blocks unsecure execution time 1750 14,800 ms 2 t swapx01 t swapx02 t swapx04 t swapx08 t swapx10 swap control execution time ? control code 0x01 ? control code 0x02 ? control code 0x04 ? control code 0x08 ? control code 0x10 200 90 90 90 150 150 30 150 s s s s s 1. assumes 25mhz or greater flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3.3.2.3 flash high voltage current behaviors table 34. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 3.5 7.5 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 3.3.2.4 reliability specifications table 35. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 peripheral operating requirements and behaviors 44 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40c t j 125c. 3.3.3 flexbus switching specifications all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. the following timing numbers indicate when data is latched or driven onto the external bus, relative to the flexbus output clock (fb_clk). all other timing relationships can be derived from these values. table 36. flexbus limited voltage range switching specifications num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation fb_clk mhz fb1 clock period 1/fb_clk ns fb2 address, data, and control output valid 11.8 ns fb3 address, data, and control output hold 1.0 ns 1 fb4 data and fb_ta input setup 11.9 ns fb5 data and fb_ta input hold 0.0 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fb_cs n , fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. table 37. flexbus full voltage range switching specifications num description min. max. unit notes operating voltage 1.71 3.6 v frequency of operation fb_clk mhz fb1 clock period 1/fb_clk ns fb2 address, data, and control output valid 12.6 ns fb3 address, data, and control output hold 1.0 ns 1 fb4 data and fb_ta input setup 12.5 ns fb5 data and fb_ta input hold 0 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fb_cs n , fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 45 nxp semiconductors address address data tsiz aa=1 aa=0 aa=1 aa=0 fb3 fb5 fb4 fb4 fb5 fb1 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] fb2 read timing parameters electricals_read.svg s0 s1 s2 s3 s0 s0 s1 s2 s3 s0 figure 17. flexbus read timing diagram peripheral operating requirements and behaviors 46 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] write timing parameters electricals_write.svg figure 18. flexbus write timing diagram 3.3.4 sdram controller specifications following figure shows sdram read cycle. peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 47 nxp semiconductors a[23:0] sras d[31:0] actv nop sdram_cs [1:0] read column clkout 0 dramw bs [3:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 d1 d2 d4 d6 d5 d4 1 1 nop d4 row d3 pre d0 scas dacr[casl] = 2 figure 19. sdram read timing diagram table 38. sdram timing (full voltage range) num characteristic 1 symbol min max unit operating voltage 1.71 3.6 v frequency of operation clkout mhz d0 clock period 1/clkout ns 2 d1 clkout high to sdram address valid t chdav - 11.2 ns d2 clkout high to sdram control valid t chdcv 11.1 ns d3 clkout high to sdram address invalid t chdai 1.0 - ns d4 clkout high to sdram control invalid t chdci 1.0 - ns d5 sdram data valid to clkout high t ddvch 12.0 - ns d6 clkout high to sdram data invalid t chddi 1.0 - ns d7 3 clkout high to sdram data valid t chddvw - 12.0 ns d8 3 clkout high to sdram data invalid t chddiw 1.0 - ns 1. all timing specifications are based on taking into account, a 25 pf load on the sdram output pins. 2. clkout is same as fb_clk, maximum frequency can be 75 mhz peripheral operating requirements and behaviors 48 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 3. d7 and d8 are for write cycles only. table 39. sdram timing (limited voltage range) num characteristic 1 symbol min max unit operating voltage 2.7 3.6 v frequency of operation clkout mhz d0 clock period 1/clkout ns 2 d1 clkout high to sdram address valid t chdav - 11.1 ns d2 clkout high to sdram control valid t chdcv 11.1 ns d3 clkout high to sdram address invalid t chdai 1.0 - ns d4 clkout high to sdram control invalid t chdci 1.0 - ns d5 sdram data valid to clkout high t ddvch 11.3 - ns d6 clkout high to sdram data invalid t chddi 1.0 - ns d7 3 clkout high to sdram data valid t chddvw - 11.1 ns d8 3 clkout high to sdram data invalid t chddiw 1.0 - ns 1. all timing specifications are based on taking into account, a 25 pf load on the sdram output pins. 2. clkout is same as fb_clk, maximum frequency can be 75 mhz 3. d7 and d8 are for write cycles only. following figure shows an sdram write cycle. peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 49 nxp semiconductors a[23:0] sras scas 1 d[31:0] actv pallnop sdram_cs [1:0] write row column clkout dramw bs [3:0] d1 d2 d4 d8 d4 0 1 2 3 4 5 6 7 8 9 10 11 12 d7 nop 1 dacr[casl] = 2 d4 d3 d2 d4 d0 figure 20. sdram write timing diagram 3.4 analog 3.4.1 adc electrical specifications the 16-bit accuracy specifications listed in table 40 and table 41 are achievable on the differential pins adcx_dp0, adcx_dm0. all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. peripheral operating requirements and behaviors 50 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 3.4.1.1 adc operating conditions table 40. adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd C v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss C v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v v refl adc reference voltage low v ssa v ssa v ssa v v adin input voltage ? 16-bit differential mode ? all other modes vrefl vrefl 31/32 vrefh vrefh v c adin input capacitance ? 8-bit / 10-bit / 12-bit modes 4 5 pf r adin input series resistance 2 5 k r as analog source resistance (external) 13-bit / 12-bit modes f adck < 4 mhz 5 k 3 f adck adc conversion clock frequency 13-bit mode 1.0 18.0 mhz 4 c rate adc conversion rate 13-bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ks/s 5 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz, unless otherwise stated. typical values are for reference only, and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. to achieve the best results, the analog source resistance must be kept as low as possible. the results in this data sheet were derived from a system that had < 8 analog source resistance. the r as /c as time constant should be kept to < 1 ns. 4. to use the maximum adc conversion clock frequency, cfg2[adhsc] must be set and cfg1[adlpc] must be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool . peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 51 nxp semiconductors r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 21. adc input impedance equivalency diagram 3.4.1.2 adc electrical characteristics table 41. adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.7 0.2 C1.1 to +1.9 C0.3 to 0.5 lsb 4 5 inl integral non-linearity ? 12-bit modes 1.0 C2.7 to +1.9 lsb 4 5 table continues on the next page... peripheral operating requirements and behaviors 52 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors table 41. adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes ? <12-bit modes 0.5 C0.7 to +0.5 e fs full-scale error ? 12-bit modes ? <12-bit modes C4 C1.4 C5.4 C1.8 lsb 4 v adin = v dda 5 e q quantization error ? 13-bit modes 0.5 lsb 4 enob effective number of bits 16-bit differential mode ? avg = 32 ? avg = 4 16-bit single-ended mode ? avg = 32 ? avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 thd total harmonic distortion 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 -94 -85 db db 7 sfdr spurious free dynamic range 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 82 78 95 90 db db 7 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c 8 v temp25 temp sensor voltage 25 c 706 716 726 mv 8 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 53 nxp semiconductors 8. adc conversion clock < 3 mhz typical adc 16-bit differential enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 1211 hardware averaging disabled averaging of 4 samples averaging of 8 samples averaging of 32 samples figure 22. typical enob vs. adc_clk for 16-bit differential mode 3.4.2 cmp and 6-bit dac electrical specifications table 42. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a table continues on the next page... peripheral operating requirements and behaviors 54 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors table 42. comparator and 6-bit dac electrical specifications (continued) symbol description min. typ. max. unit inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd C0.6 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to cmp_daccr[dacen], cmp_daccr[vrsel], cmp_daccr[vosel], cmp_muxcr[psel], and cmp_muxcr[msel]) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 00 01 10 hystctr setting 0.1 10 11 vin level (v) cmp hystereris (v) 3.1 2.82.5 2.2 1.91.61.3 1 0.70.4 0.05 0 0.01 0.02 0.03 0.08 0.07 0.06 0.04 figure 23. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 0) peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 55 nxp semiconductors 00 01 10 hystctr setting 10 11 0.1 3.12.82.5 2.2 1.91.61.3 1 0.70.4 0.1 0 0.02 0.04 0.06 0.18 0.14 0.12 0.08 0.16 vin level (v) cmp hysteresis (v) figure 24. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 1) 3.4.3 12-bit dac electrical characteristics 3.4.3.1 12-bit dac operating requirements table 43. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 3.6 v v dacr reference voltage 1.13 3.6 v 1 c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be v dda or v refh . 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac. peripheral operating requirements and behaviors 56 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 3.4.3.2 12-bit dac operating behaviors table 44. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 150 a i dda_dach p supply current high-speed mode 700 a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high- speed mode 0.7 1 s 1 v dacoutl dac output voltage range low high- speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c a c offset aging coefficient 100 v/yr rop output resistance (load = 3 k) 250 sr slew rate -80h f7fh 80h ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 v/s ct channel to channel cross talk -80 db bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0 + 100 mv to v dacr ?100 mv 3. the dnl is measured for 0 + 100 mv to v dacr ?100 mv 4. the dnl is measured for 0 + 100 mv to v dacr ?100 mv with v dda > 2.4 v 5. calculated by a best fit curve from v ss + 100 mv to v dacr ? 100 mv peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 57 nxp semiconductors 6. v dda = 3.0 v, reference select set for v dda (dacx_co:dacrfs = 1), high power mode (dacx_c0:lpen = 0), dac set to 0x800, temperature range is across the full range of the device digital code dac12 inl (lsb) 0 500 1000 1500 2000 2500 3000 3500 4000 2 4 6 8 -2 -4 -6 -8 0 figure 25. typical inl error vs. digital code peripheral operating requirements and behaviors 58 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors temperature c dac12 mid level code voltage 25 55 85 105 125 1.499 -40 1.4985 1.498 1.4975 1.497 1.4965 1.496 figure 26. offset at half scale vs. temperature 3.4.4 voltage reference electrical specifications table 45. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 3.6 v t a temperature operating temperature range of the device c c l output load capacitance 100 nf 1 , 2 1. c l must be connected to vref_out if the vref_out functionality is being used for either an internal or external reference. 2. the load capacitance should not exceed +/-25% of the nominal specified c l value over the operating temperature range of the device. peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 59 nxp semiconductors table 46. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c 1.190 1.195 1.200 v 1 v out voltage reference output user trim 1.1945 1.195 1.1955 v 1 v step voltage reference trim step 0.5 mv 1 v tdrift temperature drift (vmax -vmin across the full temperature range) 2 15 mv 1 i bg bandgap only current 60 80 a 1 i lp low-power buffer current 180 360 ua 1 i hp high-power buffer current 480 960 ma 1 v load load regulation ? current = 1.0 ma 200 v 1 , 2 t stup buffer startup time 100 s t chop_osc_st up internal bandgap start-up delay with chop oscillator enabled 35 ms v vdrift voltage drift (vmax -vmin across the full voltage range) 0.5 2 mv 1 1. see the chip's reference manual for the appropriate settings of the vref status and control register. 2. load regulation voltage is the difference between the vref_out voltage with no load vs. voltage with defined load. table 47. vref limited-range operating requirements symbol description min. max. unit notes t a temperature 0 50 c table 48. vref limited-range operating behaviors symbol description min. max. unit notes v out voltage reference output with factory trim 1.173 1.225 v 3.5 timers see general switching specifications . 3.6 communication interfaces peripheral operating requirements and behaviors 60 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 3.6.1 usb voltage regulator electrical specifications table 49. usb vreg electrical specifications symbol description min. typ. 1 max. unit notes vreg_in0 vreg_in1 regulator selectable input supply voltages 2.7 5.5 v 2 i ddon vreg_in0 vreg_in1 quiescent current run mode, load current equal zero, input supply (vreg_in*) > 3.6 v 157 157 a i ddstby vreg_in0 vreg_in1 quiescent current standby mode, load current equal zero 2 2 a i ddoff vreg_in0 vreg_in1 quiescent current shutdown mode ? vreg_in*= 5.0 v and temperature=25 c 680 920 na i loadrun maximum load current run mode 150 ma 3 i loadstby maximum load current standby mode 1 ma v dropout regulator drop-out voltage run mode at maximum load current with inrush current limit disabled 300 mv vreg_out regulator programmable output target voltage selected input supply > programmed output target voltage + v dropout ? run mode ? standby mode 3 2.1 3.3 2.8 3.6 3.6 v v 4 c out external output capacitor 1.76 2.2 8.16 f esr external output capacitor equivalent series resistance 1 100 m i lim short circuit current 350 ma 5 i inrush inrush current limit 40 100 ma 6 , 7 , 8 , 9 1. typical values assume the selected input supply is 5.0 v, temp = 25 c unless otherwise stated. 2. operation range is 2.7 v to 5.5 v; tolerance voltage is up to 6 v. 3. 150ma is inclusive of the run mode current of the on-chip usb modules. available load outside of the chip depends on usb operation and device power dissipation limits. 4. the target voltage for the regulator is programmable, accounting for the range of the max and min values. 5. current limit disabled. 6. current limit should be disabled after the powers have stabilized to allow full functionality of the regulator. 7. limited characterization 8. i inrush with vreginx=4.0 v to 5.5 v 9. total current load on startup should be less than i inrush min over full input voltage range of the regulator. peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 61 nxp semiconductors 3.6.2 usb full speed transceiver and high speed phy specifications this section describes the usb0 port full speed/low speed transceiver and usb1 port usb-phy high speed phy parameters. the high speed phy is capable of full and low speed as well. the usb0 (fs/ls transceiver) and usb1 ((usb hs/fs/ls) meet the electrical compliance requirements defined in the universal serial bus revision 2.0 specification with the amendments below. ? usb engineering change notice ? title: 5v short circuit withstand requirement change ? applies to: universal serial bus specification, revision 2.0 ? errata for usb revision 2.0 april 27, 2000 as of 12/7/2000 ? usb engineering change notice ? title: pull-up/pull-down resistors ? applies to: universal serial bus specification, revision 2.0 ? usb engineering change notice ? title: suspend current limit changes ? applies to: universal serial bus specification, revision 2.0 ? on-the-go and embedded host supplement to the usb revision 2.0 specification ? revision 2.0 version 1.1a july 27, 2012 ? battery charging specification (available from usb-if) ? revision 1.2 (including errata and ecns through march 15, 2012), march 15, 2012 usb1_vbus pin is a detector function which is 5v tolerant and complies with the above specifications without needing any external voltage division components. 3.6.3 usb dcd electrical specifications table 50. usb dcd electrical specifications symbol description min. typ. max. unit v dp_src , v dm_src usb_dp and usb_dm source voltages (up to 250 a) 0.5 0.7 v v lgc threshold voltage for logic high 0.8 2.0 v i dp_src usb_dp source current 7 10 13 a table continues on the next page... peripheral operating requirements and behaviors 62 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors table 50. usb dcd electrical specifications (continued) symbol description min. typ. max. unit i dm_sink , i dp_sink usb_dm and usb_dp sink currents 50 100 150 a r dm_dwn d- pulldown resistance for data pin contact detect 14.25 24.8 k v dat_ref data detect voltage 0.25 0.33 0.4 v 3.6.4 dspi switching specifications (limited voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 51. master mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 30 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 2 ns 1 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 2 ns 2 ds5 dspi_sck to dspi_sout valid 15.0 ns ds6 dspi_sck to dspi_sout invalid 1.0 ns ds7 dspi_sin to dspi_sck input setup 15.8 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 2. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 63 nxp semiconductors ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 27. dspi classic spi timing master mode table 52. slave mode dspi timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 15 1 mhz ds9 dspi_sck input cycle time 4 x t bus ns ds10 dspi_sck input high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid 23.0 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2.7 ns ds14 dspi_sck to dspi_sin input hold 7.0 ns ds15 dspi_ss active to dspi_sout driven 13 ns ds16 dspi_ss inactive to dspi_sout not driven 13 ns 1. the maximum operating frequency is measured with non-continuous cs and sck. when dspi is configured with continuous cs and sck, there is a constraint that spi clock should not be greater than 1/6 of bus clock, for example, when bus clock is 60mhz, spi clock should not be greater than 10mhz. peripheral operating requirements and behaviors 64 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 28. dspi classic spi timing slave mode table 53. master mode dspi3 timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 60 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 2 ns 1 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 2 ns 2 ds5 dspi_sck to dspi_sout valid 9.1 ns ds6 dspi_sck to dspi_sout invalid 1.0 ns ds7 dspi_sin to dspi_sck input setup 7.8 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 2. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. table 54. slave mode dspi3 timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 30 1 mhz ds9 dspi_sck input cycle time 4 x t bus ns ds10 dspi_sck input high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid 16.0 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2.7 ns ds14 dspi_sck to dspi_sin input hold 7.0 ns table continues on the next page... peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 65 nxp semiconductors table 54. slave mode dspi3 timing (limited voltage range) (continued) num description min. max. unit ds15 dspi_ss active to dspi_sout driven 13 ns ds16 dspi_ss inactive to dspi_sout not driven 13 ns 1. the maximum operating frequency is measured with non-continuous cs and sck. when dspi is configured with continuous cs and sck, there is a constraint that spi clock should not be greater than 1/6 of bus clock, for example, when bus clock is 60mhz, spi clock should not be greater than 10mhz. 3.6.5 dspi switching specifications (full voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 55. master mode dspi timing (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 15 mhz ds1 dspi_sck output cycle time 4 x t bus ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 4 ns 2 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 4 ns 3 ds5 dspi_sck to dspi_sout valid 16 ns ds6 dspi_sck to dspi_sout invalid 1.0 ns ds7 dspi_sin to dspi_sck input setup 19.1 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 3. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. peripheral operating requirements and behaviors 66 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 29. dspi classic spi timing master mode table 56. slave mode dspi timing (full voltage range) num description min. max. unit operating voltage 1.71 3.6 v frequency of operation 7.5 mhz ds9 dspi_sck input cycle time 8 x t bus ns ds10 dspi_sck input high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds11 dspi_sck to dspi_sout valid 23.1 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2.6 ns ds14 dspi_sck to dspi_sin input hold 7.0 ns ds15 dspi_ss active to dspi_sout driven 13.0 ns ds16 dspi_ss inactive to dspi_sout not driven 13.0 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 30. dspi classic spi timing slave mode peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 67 nxp semiconductors table 57. master mode dspi3 timing (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v frequency of operation 40 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) - 2 (t sck/2) + 2 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 2 ns 1 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 2 ns 2 ds5 dspi_sck to dspi_sout valid 9.5 ns ds6 dspi_sck to dspi_sout invalid 1.0 ns ds7 dspi_sin to dspi_sck input setup 10.5 ns ds8 dspi_sck to dspi_sin input hold 0.0 ns 1. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 2. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. table 58. slave mode dspi3 timing (full voltage range) num description min. max. unit notes> operating voltage 1.71 3.6 v frequency of operation 20 mhz 1 ds9 dspi_sck input cycle time 4 x t bus ns ds10 dspi_sck input high/low time (t sck /2) - 2 (t sck/2) + 2 ns ds11 dspi_sck to dspi_sout valid 18.2 ns ds12 dspi_sck to dspi_sout invalid 0.0 ns ds13 dspi_sin to dspi_sck input setup 2.7 ns ds14 dspi_sck to dspi_sin input hold 7.0 ns ds15 dspi_ss active to dspi_sout driven 13.0 ns ds16 dspi_ss inactive to dspi_sout not driven 13.0 ns 1. the maximum operating frequency is measured with non-continuous cs and sck. when dspi is configured with continuous cs and sck, there is a constraint that spi clock should not be greater than 1/6 of bus clock, for example,when bus clock is 60mhz, spi clock should not be greater than 10mhz. 3.6.6 inter-integrated circuit interface (i 2 c) timing table 59. i 2 c timing characteristic symbol standard mode fast mode unit minimum maximum minimum maximum scl clock frequency f scl 0 100 0 400 khz table continues on the next page... peripheral operating requirements and behaviors 68 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors table 59. i 2 c timing (continued) characteristic symbol standard mode fast mode unit minimum maximum minimum maximum hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 4 0.6 s low period of the scl clock t low 4.7 1.25 s high period of the scl clock t high 4 0.6 s set-up time for a repeated start condition t su ; sta 4.7 0.6 s data hold time for i 2 c bus devices t hd ; dat 0 1 3.45 2 0 3 0.9 1 s data set-up time t su ; dat 250 4 100 2 , 5 ns rise time of sda and scl signals t r 1000 20 +0.1c b 6 300 ns fall time of sda and scl signals t f 300 20 +0.1c b 5 300 ns set-up time for stop condition t su ; sto 4 0.6 s bus free time between stop and start condition t buf 4.7 1.3 s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a 0 50 ns 1. the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the sda and scl lines. 2. the maximum thd; dat must be met only if the device does not stretch the low period (tlow) of the scl signal. 3. input signal slew = 10 ns and output load = 50 pf 4. set-up time in slave-transmitter mode is 1 ipbus clock period, if the tx fifo is empty. 5. a fast mode i 2 c bus device can be used in a standard mode i2c bus system, but the requirement t su; dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, then it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 6. c b = total capacitance of the one bus line in pf. table 60. i 2 c 1 mbps timing characteristic symbol minimum maximum unit scl clock frequency f scl 0 1 1 mhz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 0.26 s low period of the scl clock t low 0.5 s high period of the scl clock t high 0.26 s set-up time for a repeated start condition t su ; sta 0.26 s data hold time for i 2 c bus devices t hd ; dat 0 s data set-up time t su ; dat 50 ns rise time of sda and scl signals t r 20 +0.1c b , 2 120 ns fall time of sda and scl signals t f 20 +0.1c b 2 120 ns table continues on the next page... peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 69 nxp semiconductors table 60. i 2 c 1 mbps timing (continued) characteristic symbol minimum maximum unit set-up time for stop condition t su ; sto 0.26 s bus free time between stop and start condition t buf 0.5 s pulse width of spikes that must be suppressed by the input filter t sp 0 50 ns 1. the maximum scl clock frequency of 1 mbps can support maximum bus loading when using the high drive pins across the full voltage range. 2. c b = total capacitance of the one bus line in pf. ? ? sda hd; sta t hd; dat t low t su; dat t high t su; sta sr p s s t hd; sta t sp t su; sto t buf t f t r t f t r scl figure 31. timing definition for devices on the i 2 c bus 3.6.7 lpuart switching specifications see general switching specifications . 3.6.8 sdhc specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. table 61. sdhc full voltage range switching specifications num symbol description min. max. unit operating voltage 1.71 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed\high speed) 0 25/45 mhz fpp clock frequency (mmc full speed\high speed) 0 25/45 mhz f od clock frequency (identification mode) 0 400 khz table continues on the next page... peripheral operating requirements and behaviors 70 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors table 61. sdhc full voltage range switching specifications (continued) num symbol description min. max. unit sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) 0 8.1 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t isu sdhc input setup time 5 ns sd8 t ih sdhc input hold time 0 ns table 62. sdhc limited voltage range switching specifications num symbol description min. max. unit operating voltage 2.7 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed\high speed) 0 25\50 mhz fpp clock frequency (mmc full speed\high speed) 0 20\50 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) 0 7 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t isu sdhc input setup time 5 ns sd8 t ih sdhc input hold time 0 ns peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 71 nxp semiconductors sd2sd3 sd1 sd6 sd8 sd7 sdhc_clk output sdhc_cmd output sdhc_dat[3:0] input sdhc_cmd input sdhc_dat[3:0] figure 32. sdhc timing 3.6.9 i 2 s switching specifications this section provides the ac timings for the i 2 s in master (clocks driven) and slave modes (clocks input). all timings are given for non-inverted serial clock polarity (tcr[tsckp] = 0, rcr[rsckp] = 0) and a non-inverted frame sync (tcr[tfsi] = 0, rcr[rfsi] = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (i2s_bclk) and/or the frame sync (i2s_fs) shown in the figures below. table 63. i2s master mode timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_bclk cycle time 80 ns s4 i2s_bclk pulse width high/low 45% 55% bclk period s5 i2s_bclk to i2s_fs output valid 15 ns s6 i2s_bclk to i2s_fs output invalid 0 ns s7 i2s_bclk to i2s_txd valid 15 ns s8 i2s_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_fs input setup before i2s_bclk 15 ns s10 i2s_rxd/i2s_fs input hold after i2s_bclk 0 ns peripheral operating requirements and behaviors 72 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_bclk (output) i2s_fs (output) i2s_fs (input) i2s_txd i2s_rxd figure 33. i 2 s timing master mode table 64. i2s slave mode timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v s11 i2s_bclk cycle time (input) 80 ns s12 i2s_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_fs input setup before i2s_bclk 4.5 ns s14 i2s_fs input hold after i2s_bclk 2 ns s15 i2s_bclk to i2s_txd/i2s_fs output valid 20 ns s16 i2s_bclk to i2s_txd/i2s_fs output invalid 0 ns s17 i2s_rxd setup before i2s_bclk 4.5 ns s18 i2s_rxd hold after i2s_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 73 nxp semiconductors s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_bclk (input) i2s_fs (output) i2s_fs (input) i2s_txd i2s_rxd s19 figure 34. i 2 s timing slave modes 3.6.9.1 normal run, wait and stop mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in normal run, wait and stop modes. table 65. i2s/sai master mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk (as an input) pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 15 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors 74 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 35. i2s/sai timing master modes table 66. i2s/sai slave mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 4.5 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 23.1 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 4.5 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 75 nxp semiconductors s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 36. i2s/sai timing slave modes 3.6.9.2 vlpr, vlpw, and vlps mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in vlpr, vlpw, and vlps modes. table 67. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 62.5 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 250 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 45 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 45 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 45 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors 76 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 37. i2s/sai timing master modes table 68. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 250 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 30 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 5 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 56.5 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 30 ns s18 i2s_rxd hold after i2s_rx_bclk 5 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 72 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors kinetis k28f mcu sub-family, rev. 4, 03/2017 77 nxp semiconductors s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 38. i2s/sai timing slave modes 4 dimensions 4.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to nxp.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 169-pin mapbga 98asa00628d 210-pin wlcsp 98asa01002d for additional packaging assembly information on mapbga, refer to applications note an4982. for additional packaging assembly information on wlcsp, refer to applications note an3846. 5 pinout dimensions 78 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 5.1 k28f signal multiplexing and pin assignments the signal multiplexing and pin assignments are provided in an excel file attached to this document: 1. click the paperclip symbol on the left side of the pdf window. 2. double-click on the excel file to open it. 3. select the pinout tab. the port control module is responsible for selecting which alt functionality is available on each pin. 5.2 recommended connection for unused analog and digital pins table 69 shows the recommended connections for analog interface pins if those analog interfaces are not used in the customer's application table 69. recommended connection for unused analog interfaces pin type k28f short recommendation detailed recommendation analog/non gpio adcx/cmpx float analog input - float analog/non gpio vref_out float analog output - float analog/non gpio dac0_out, dac1_out float analog output - float analog/non gpio rtc_wakeup_b float analog output - float analog/non gpio xtal32 float analog output - float analog/non gpio extal32 float analog input - float gpio/analog pta18/extal0 float analog input - float gpio/analog pta19/xtal0 float analog output - float gpio/analog ptx/adcx float float (default is analog input) gpio/analog ptx/cmpx float float (default is analog input) gpio/digital pta0/jtag_tclk float float (default is jtag with pulldown) gpio/digital pta1/jtag_tdi float float (default is jtag with pullup) gpio/digital pta2/jtag_tdo float float (default is jtag with pullup) gpio/digital pta3/jtag_tms float float (default is jtag with pullup) gpio/digital pta4/nmi_b 10k? pullup or disable and float pull high or disable in pcr & fopt and float gpio/digital ptx float float (default is disabled) usb usb0_dp float float table continues on the next page... pinout kinetis k28f mcu sub-family, rev. 4, 03/2017 79 nxp semiconductors table 69. recommended connection for unused analog interfaces (continued) pin type k28f short recommendation detailed recommendation usb usb0_dm float float usb vreg_out tie to input and ground through 10 k? tie to input and ground through 10 k? usb vreg_in0 tie to output and ground through 10 k? tie to output and ground through 10 k? usb vreg_in1 tie to output and ground through 10 k? tie to output and ground through 10 k? usb usb1vss always connect to vss always connect to vss usb usb1_dp float float usb usb1_dm float float usb usb_vbus float float v bat v bat float float vdda vdda always connect to vdd potential always connect to vdd potential vrefh vrefh always connect to vdd potential always connect to vdd potential vrefl vrefl always connect to vss potential always connect to vss potential vssa vssa always connect to vss potential always connect to vss potential 5.3 k28f pinouts the pinout diagrams are provided in an excel file attached to this document: 1. click the paperclip symbol on the left side of the pdf window. 2. double-click on the excel file to open it. 3. select the respective package tab. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. 6 ordering parts ordering parts 80 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 6.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: mk28. 7 part identification 7.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 7.2 format part numbers for this device have the following format: q k## a m fff r t pp cc n 7.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification k## kinetis family ? k28 a key attribute ? d = cortex-m4 w/ dsp ? f = cortex-m4 w/ dsp and fpu m flash memory type ? n = program flash only ? x = program flash and flexmemory fff program flash memory size ? 32 = 32 kb ? 64 = 64 kb ? 128 = 128 kb ? 256 = 256 kb ? 512 = 512 kb ? 1m0 = 1 mb ? 2m0 = 2 mb table continues on the next page... part identification kinetis k28f mcu sub-family, rev. 4, 03/2017 81 nxp semiconductors field description values r silicon revision ? z = initial ? (blank) = main ? a = revision after main t temperature range (c) ? v = C40 to 105 ? c = C40 to 85 pp package identifier ? fm = 32 qfn (5 mm x 5 mm) ? ft = 48 qfn (7 mm x 7 mm) ? lf = 48 lqfp (7 mm x 7 mm) ? lh = 64 lqfp (10 mm x 10 mm) ? mp = 64 mapbga (5 mm x 5 mm) ? lk = 80 lqfp (12 mm x 12 mm) ? ll = 100 lqfp (14 mm x 14 mm) ? mc = 121 mapbga (8 mm x 8 mm) ? lq = 144 lqfp (20 mm x 20 mm) ? md = 144 mapbga (13 mm x 13 mm) ? mi = 169 mapbga (9 mm x 9 mm) ? au = 210 wlcsp (6.9 mm x 6.9 mm) cc maximum cpu frequency (mhz) ? 5 = 50 mhz ? 7 = 72 mhz ? 10 = 100 mhz ? 12 = 120 mhz ? 15 = 150 mhz ? 18 = 180 mhz n packaging type ? r = tape and reel ? (blank) = trays 7.4 example this is an example part number: mk28fn2m0vmi15 8 terminology and guidelines 8.1 definitions key terms are defined in the following table: term definition rating a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: table continues on the next page... terminology and guidelines 82 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors term definition ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. note: the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. operating requirement a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip operating behavior a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions typical value a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions note: typical values are provided as design guidelines and are neither tested nor guaranteed. 8.2 examples operating rating : operating requirement : operating behavior that includes a typical value : example example example example terminology and guidelines kinetis k28f mcu sub-family, rev. 4, 03/2017 83 nxp semiconductors 8.3 typical-value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd supply voltage 3.3 v 8.4 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation 8.5 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. terminology and guidelines 84 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors 9 revision history the following table provides a revision history for this document. table 70. revision history rev. no. date substantial changes 0 05/2016 initial internal release 1 09/2016 ? updated the number of gpio for 210 wlcsp ? updated the operating characteristics and communication interfaces in front matter ? updated device mask set number in device revision number ? updated the v dd_core /v dd powering sequence figure ? added thermal attribute values of 169bga and 210wlcsp ? segregated power consumption operating behaviors table for vdd_core and vdd ? updated flash electrical specifications section ? added the drawing number for 210-pin wlcsp package ? updated fb4 value in flexbus limited voltage range switching specifications table ? updated d5 value in sdram timing (limited voltage range) table ? added dspi3 timing specifications ? added thermal operating requirements table for c-temp range ? updated v dd_core entry in voltage and current operating requirements ? updated i2c section ? removed "at 3.0 v" from power consumption operating behaviors (through vdd_core) table ? duplicated i dd_vlpw value for peripherals enabled and disabled in power consumption operating behaviors (through vdd) table 2 12/2016 ? updated the operating characteristics and communication interfaces section in front matter ? updated device mask set number in device revision number ? modified the title from "voltage and current operating ratings" to voltage and current maximum ratings ? updated voltage and current maximum ratings table ? removed the cases v dd =v ddio_e , v dd > v ddio_e , v dd < v ddio_e and associated figures in recommended power-on-reset (por) sequencing section ? updated voltage and current operating requirements table ? updated the values of power mode transition operating behaviors table ? updated the power consumption operating behaviors (through vdd_core) table and power consumption operating behaviors (through vdd) table in power consumption operating behaviors section ? added a new footnote and updated the existing footnote in thermal operating requirements (for v-temp range) table and thermal operating requirements (for c- temp range) table in thermal operating requirements section ? deleted one footnote for i inrush in usb voltage regulator electrical specifications 3 02/2017 ? editorial updates in front matter ? removed tsi block from k28f block diagram and tsi section ? updated maximum value of v bat from 4.25 v to 3.8v in voltage and current maximum ratings section ? updated note in hvd, lvd and por operating requirements section table continues on the next page... revision history kinetis k28f mcu sub-family, rev. 4, 03/2017 85 nxp semiconductors table 70. revision history (continued) rev. no. date substantial changes ? updated the symbol of digital supply voltage for port e to v ddio_e and maximum value of v bat to 3.6 in voltage and current operating requirements table ? updated the values of power mode transition operating behaviors table ? updated the values of power consumption operating behaviors (through vdd_core) table and power consumption operating behaviors (through vdd) table in power consumption operating behaviors section ? added power supplies figure and updated the verbiage in power consumption operating behaviors section ? removed the footnote associated with die junction temperature in thermal operating requirements (for v-temp range) table and thermal operating requirements (for c-temp range) table in thermal operating requirements section ? updated the values of table 8 ? removed low voltage detect of v dd_core supply table ? removed the row that had entry of tsi0x in recommended connection for unused analog interfaces table ? removed uart switching specifications section ? added statement about the package assembly information in obtaining package dimensions section 4 03/2017 ? updated ram array retained column by adding size in lls2/vlls2 additional typical iddc current consumption adders table in power consumption operating behaviors ? removed f flexcan_erclk entry from device clock specifications ? updated pinout excel sheet revision history 86 kinetis k28f mcu sub-family, rev. 4, 03/2017 nxp semiconductors how to reach us: home page: nxp.com web support: nxp.com/support information in this document is provided solely to enable system and software implementers to use nxp products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in nxp data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer's technical experts. nxp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions . nxp, the nxp logo, nxp secure connections for a smarter world, freescale, the freescale logo, and kinetis are trademarks of nxp b.v. all other product or service names are the property of their respective owners. arm, the arm powered logo, thumb, and cortex are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. all rights reserved. ? 2016C2017 nxp b.v. document number K28P210M150SF5 revision 4, 03/2017 |
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