pcie rtd3 slg7nt4129 silego technology, inc. rev 1.01 slg7nt4129_ds_r101 revised june 11, 2013 slg7nt4129_gp_r004 general description silego slg7nt4129 is a low power and small form device. the soc is housed in a 2.5mm x 2.5mm tdfn package which is optimal for using with small devices. features ? low power consumption ? dynamic supply voltage ? rohs compliant / halogen-free ? pb-free tdfn-12 package pin configuration 1 2 3 4 12 11 10 9 vdd pwr_cntrl_gpio # plt_rst # device_wake # pcie_wake# device_reset# nc wake_gpio tdfn-12 top view thermal pad connected to gnd slg7nt4129 5 6 8 7 rst _ cntrl _ gpio # nc nc gnd output summary ? 2 outputs ? open drain ? 2 outputs ? 3-state block diagram
pcie rtd3 slg7nt4129 slg7nt4129_ds_r101 page 2 pin configuration pin # pin name type pin description 1 vdd pwr supply voltage 2 pwr_cntrl_gpio# input digital input 3 plt_rst# input digital input 4 device_wake# input/output 3-state 5 rst_cntrl_gpio# input digital input 6 nc -- keep floating or connect to gnd 7 gnd gnd ground 8 nc -- keep floating or connect to gnd 9 wake_gpio output open drain 10 nc -- keep floating or connect to gnd 11 pcie_wake# input/output 3-state 12 device_reset# output open drain exposed bottom pad exposed bottom pad gnd ground ordering information part number package type SLG7NT4129V v = tdfn-12 SLG7NT4129Vtr vtr = tdfn-12 - tape and reel (3k units)
pcie rtd3 slg7nt4129 slg7nt4129_ds_r101 page 3 absolute maximum conditions parameter min. max. unit v high to gnd -0.3 7 v voltage at input pins -0.3 7 v current at input pin -1.0 1.0 ma storage temperature range -65 150 c junction temperature -- 150 c electrical characteristics (@ 25c, unless otherwise stated) symbol parameter condition/note min. typ. max. unit v dd supply voltage 1.71 -- 3.6 v i q quiescent current static inputs and outputs -- 1 -- a t a operating temperature -40 25 85 c i l input leakage current leakage current for digital inputs or outputs in high impedance state -100 -- 100 na v ih high-level input voltage logic input, at vdd= 1.8v 1.1 -- -- v logic input, at vdd=3.3v 1.8 v il low-level input voltage logic input, at vdd=1. 8v -- -- 0.65 v logic input, at vdd=3.3v 1.1 i ih high-level input curr ent logic input pins; v in =vdd -1 1 a i il low-level input current logic input pins; v in =0v -1 1 a t dly0 delay0 time 2.1 3 3.9 ms v oh output voltage high 3-state, oe=1, i oh = 100a at vdd=1.8v 1.66 -- -- v 3-state, oe=1, i oh = 3ma at vdd=3.3v 2.1 -- -- v ol output voltage low 3-state, oe=1, i ol = 100a at vdd=1.8v -- -- 0.04 v 3-state, oe=1, i ol = 3ma at vdd=3.3v -- -- 0.81 open drain, i ol = 5ma, at vdd=1.8v -- -- 0.340 open drain, i ol = 20ma at vdd=3.3v -- -- 0.605 v o maximal voltage applied to any pin in high-impedance state -- -- vdd v i ol low-level output current 3-state, oe=1, v ol =0.15v, at vdd=1.8v 0.34 -- -- ma 3-state, oe=1, v ol = 0.4v, at vdd=3. 3v 1.836 -- -- open drain, v ol =0.15v, at vdd= 1.8v 2.7 -- -- open drain, v ol = 0.4v, at vdd=3.3v 14.6 -- -- t su start up time after vdd reaches 1.6v level -- 7 -- ms
pcie rtd3 slg7nt4129 slg7nt4129_ds_r101 page 4 timing diagram
pcie rtd3 slg7nt4129 slg7nt4129_ds_r101 page 5 package top marking datasheet revision programming code number part code revision date 1.0 04 4129v aa 01/23/2013
pcie rtd3 slg7nt4129 slg7nt4129_ds_r101 page 6 package drawing and dimensions 12 lead tdfn package jedec mo-252, variation 2525e
pcie rtd3 slg7nt4129 slg7nt4129_ds_r101 page 7 tape and reel specification package type # of pins nominal package size (mm) max units reel & hub size (mm) trailer a leader b pocket (mm) per reel per box pockets length (mm) pockets length (mm) width pitch tdfn 12l 2.5x2.5mm 0.4p green 12 2.5x2.5x0.75 3000 3000 178/60 42 168 42 168 8 4 carrier tape drawing and dimensions package type pocket btm length (mm) pocket btm width (mm) pocket depth (mm) index hole pitch (mm) pocket pitch (mm) index hole diameter (mm) index hole to tape edge (mm) index hole to pocket center (mm) tape width (mm) a0 b0 k0 p0 p1 d0 e f w tdfn 12l 2.5x2.5mm 0.4p green 2.75 2.75 1.05 4 4 1.55 1.75 3.5 8 refer to eia-481 specifications recommended reflow soldering profile please see ipc/jedec j-std-020: latest revision fo r reflow profile based on package volume of 4.6875 mm 3 (nominal). more information can be found at www.jedec.org .
pcie rtd3 slg7nt4129 slg7nt4129_ds_r101 page 8 datasheet revision history date version change 11/08/2012 0.1 new design 11/22/2012 0.11 changed pin12 type to open drain 11/26/2012 0.20 cha nged device_wake# and pcie_wake# f unctionality to bi-directional 01/18/2013 0.21 some typos in pin out table are fixed 01/23/2013 1.0 production release 06/11/2013 1.01 housekeeping (fixed block diagram)
pcie rtd3 slg7nt4129 slg7nt4129_ds_r101 page 9 silego website & support silego technology website silego technology provides online support via our website at http://www.silego.com/ .this website is used as a means to make files and information easily available to customers. for more information regarding silego green products, please visit: http://greenpak.silego.com/ http://greenpak2.silego.com/ http://greenfet.silego.com/ http://greenfet2.silego.com/ http://greenclk.silego.com/ products are also available for purchase direct ly from silego at the silego online store at http://store.silego.com/ . silego technical support datasheets and errata, application notes and example desig ns, user guides, and hardware support documents and the latest software releases are available at the silego website or can be requested directly at info@silego.com . for specific greenpak design or applications ques tions and support please send email requests to greenpak@silego.com users of silego products can receive assistance through several channels: online live support silego technology has live video technical assistance and sales support available at http://www.silego.com/ . please ask our live web receptionist to schedule a 1 on 1 tr aining session with one of our application engineers. contact your local sales representative customers can contact their local sales r epresentative or field application engineer (fae) for support. local sales offices are also available to help customers. more information rega rding your local representative is available at the silego website or send a request to info@silego.com contact silego directly silego can be contacted directly via e-mail at info@silego.com or user submission form, located at the following url: http://support.silego.com/ other information the latest silego technology press releases, listing of semi nars and events, listings of world wide silego technology offices and representatives are all available at http://www.silego.com/ this product has been designed and qualified for the consum er market. applications or uses as critical components in life support devices or syst ems are not authorized. silego technology does not assume any liability aris ing out of such applications or uses of its products. silego technology r eserves the right to improve pr oduct design, functions and reliability without notice.
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