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| S34ML01G1 s34ml02g1 s34ml04g1 1 gb/2 gb/4 gb, 3 v, slc nand flash for embedded cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00676 rev. *v revised march 20, 2018 distinctive characteristics density ? 1 gb/ 2 gb / 4 gb architecture ? input / output bus width: 8-bits / 16-bits ? page size: ? x8 = 2112 (2048 + 64) byte s; 64 bytes is spare area ? x16 = 1056 (1024 + 32) wor ds; 32 words is spare area ? block size: 64 pages ? x8 = 128 kb + 4 kb ? x16 = 64k + 2k words ? plane size: ?1 gb / 2 gb : 1024 blocks per plane x8 = 128 mb + 4 mb x16 = 64m + 2m words ?4 gb : 2048 blocks per plane x8 = 256 mb+ 8 mb x16 = 128m + 4m words ? device size: ?1 gb : 1 plane per device or 128 mb ?2 gb : 2 planes per device or 256 mb ?4 gb : 2 planes per device or 512 mb nand flash interface ? open nand flash interfac e (onfi) 1.0 compliant ? address, data and commands multiplexed supply voltage ? 3.3-v device: vcc = 2.7 v ~ 3.6 v security ? one time programmable (otp) area ? hardware program/erase disabled during power transition additional features ? 2 gb and 4 gb parts support multiplane program and erase commands ? supports copy back program ? 2 gb and 4 gb parts support multiplane copy back program ? supports read cache electronic signature ? manufacturer id: 01h operating temperature ? industrial: -40 c to 85 c ? automotive: -40 c to 105 c performance page read / program ? random access: 25 s (max) ? sequential access: 25 ns (min) ? program time / multiplane program time: 200 s (typ) block erase (S34ML01G1) ? block erase time : 2.0 ms (typ) block erase / multiplane er ase (s34ml02g1, s34ml04g1) ? block erase time : 3.5 ms (typ) reliability ? 100,000 program / era se cycles (typ) (with 1 bit ecc per 528 byte s (x8) or 264 words (x16)) ? 10 year data retention (typ) ? for one plane structure (1-gb density) ? block zero is valid and will be valid for at least 1,000 program-erase cycles with ecc ? for two plane structures (2-gb and 4-gb densities) ? blocks zero and one are valid and will be valid for at least 1,000 program-erase cycles with ecc package options ? lead free and low halogen ? 48-pin tsop 12 ? 20 ? 1.2 mm ? 63-ball bga 9 ? 11 ? 1 mm
document number: 002-00676 rev. *v page 2 of 71 S34ML01G1 s34ml02g1 s34ml04g1 contents 1. general description ..................................................... 4 1.1 logic diagram............................................... ................. 5 1.2 connection diagram .......................................... ............ 6 1.3 pin description............................................. .................. 7 1.4 block diagram............................................... ................. 8 1.5 array organization .......................................... ............... 9 1.6 addressing .................................................. ................. 10 1.7 mode selection .............................................. .............. 12 2. bus operation ............................................................ 13 2.1 command input ............................................... ............ 13 2.2 address input............................................... ................ 13 2.3 data input .................................................. .................. 13 2.4 data output................................................. ................. 13 2.5 write protect ............................................... ................. 13 2.6 standby..................................................... ................... 13 3. command set ............................................................. 1 4 3.1 page read ................................................... ................ 15 3.2 page program................................................ .............. 15 3.3 multiplane program s34ml02g1 and s34ml04g1 ................................ 16 3.4 page reprogram s34ml02g1 and s34ml04g1 ................................ 16 3.5 block erase................................................. ................. 18 3.6 multiplane block erase s34ml02g1 and s34ml04g1 ................................ 18 3.7 copy back program........................................... .......... 18 3.8 edc operation s34ml 02g1 and s34ml04g1....... 19 3.9 read status register........................................ ........... 21 3.10 read status enhanced s34ml02g1 and s34ml04g1 ................................ 22 3.11 read status register field definition ...................... .... 22 3.12 reset...................................................... ...................... 22 3.13 read cache ................................................. ................ 23 3.14 cache program.............................................. .............. 24 3.15 multiplane cache program s34ml02g1 and s34ml04g1 ................................ 25 3.16 read id.................................................... .................... 26 3.17 read id2................................................... ................... 29 3.18 read onfi signature ....... ........... ........... ........... .......... 29 3.19 read parameter page ........................................ ......... 29 3.20 one-time programmable (otp) entry ........................ 3 1 4. signal descriptions ................................................... 32 4.1 data protection and power on / off sequence ........... 32 4.2 ready/busy.................................................. ................ 32 4.3 write protect operation . .................................... .......... 33 5. electrical characteristics .......................................... 34 5.1 valid blocks ................................................ ................. 34 5.2 absolute maximum ratings .................................... ..... 34 5.3 recommended operating conditions.......................... 3 4 5.4 ac test conditions .......................................... ............ 34 5.5 ac characteristics .......................................... ............. 35 5.6 dc characteristics .......................................... ............. 36 5.7 pin capacitance............. ........... ........... .......... .............. 36 5.8 thermal resistance .......................................... ............ 37 5.9 program / erase characteri stics ............................. ...... 37 6. timing diagrams ......................................................... 38 6.1 command latch cycle......................................... ......... 38 6.2 address latch c ycle ......................................... ............ 38 6.3 data input cycle timing.. ................................... ........... 39 6.4 data output cycle timing (cle=l, we#=h, ale=l, wp#=h)............................... 39 6.5 data output cycle timing (edo type, cle=l, we#=h, ale =l) .......................... 40 6.6 page read operation ......................................... .......... 40 6.7 page read operation (interrupted by ce#).................. 4 1 6.8 page read operation timing with ce# dont care...... 41 6.9 page program operation ...................................... ........ 42 6.10 page program operation timing with ce# dont care .......... .................................. ......... 42 6.11 page program operation with random data input ...... 43 6.12 random data output in a page ......... ........... ........... .... 43 6.13 multiplane page program operation s34ml02g1 and s34ml04g1 .... ........... ........... ....... 44 6.14 block erase operation ...................................... ............ 45 6.15 multiplane block erase s34ml02g1 and s34ml04g1 .... ........... ........... ....... 45 6.16 copy back read with optiona l data readout .. ............ 46 6.17 copy back program operation with random data input....... .................................. ...... 46 6.18 multiplane copy back program s34ml02g1 and s34ml04g1 .... ........... ........... ....... 47 6.19 read status register timin g ........... ........... .......... ........ 48 6.20 read status enhanced timi ng ........... ........... .......... ..... 48 6.21 reset operation timing ..................................... ........... 48 6.22 read cache ................. ........... ............ ......... ................. 49 6.23 cache program.............................................. ............... 50 6.24 multiplane cache program s34ml02g1 and s34ml04g1 .... ........... ........... ....... 51 6.25 read id operation timing ................................... ......... 53 6.26 read id2 operation timing .................................. ........ 53 6.27 read onfi signature timing................................. ....... 54 6.28 read parameter page timin g ............ ........... .......... ..... 54 6.29 otp entry timing ........................................... .............. 54 6.30 power on and data protecti on timing ........................ . 55 6.31 wp# handling............................................... ................ 55 7. physical interface ....................................................... 56 7.1 physical diagram ............................................ .............. 56 8. system interface ......................................................... 58 9. error management ...................................................... 59 9.1 system bad block replacement................................ ... 59 9.2 bad block management........ ........... ........... .......... ........ 60 10. ordering information .................................................. 61 11. document history page ............................................. 62 document number: 002-00676 rev. *v page 3 of 71 S34ML01G1 s34ml02g1 s34ml04g1 sales, solutions, and legal i nformation ....................... ... 71 worldwide sales and design s upport ........... ........... ..... 7 1 products ...................................................... .................. 71 psoc? solutions ............................................... ............ 71 cypress developer community ................................... .. 71 technical support ............................................. ............ 71 document number: 002-00676 rev. *v page 4 of 71 S34ML01G1 s34ml02g1 s34ml04g1 1. general description the cypress S34ML01G1, s34ml02g1, and s34ml04g1 series is offer ed with a 3.3-v v cc power supply, and with 8 or 16 i/o interface. its nand cell provides the most cost-effective solut ion for the solid state mass storage market. the memory is divi ded into blocks that can be erased independently so it is possible to pr eserve valid data while old dat a is erased. the page size for 8 is (2048 + 64 spare) bytes; f or 16 (1024 + 32) words. each block can be programmed and erased up to 100,000 cycles wi th ecc (error correction code) on. to extend t he lifetime of nand flash devices, the implem entation of an ecc is mandatory. the chip supports ce# don't care function. this function allows the direct download of the code from the nand flash memory dev ice by a microcontroller, since the ce# transitions do not stop the read operation. the devices have a read cache f eature that improves the read th roughput for large files. during cache reading, the devices loa d the data in a cache r egister while the previous data is transfe rred to the i/o buffers to be read. like all other 2-kb page nand flash devices, a program operatio n typically writes 2112 bytes (8), or 1056 words (16) in 200 s and an erase operatio n can typically be performed in 2 ms (s34m l01g1) on a 128-kb block (8) or 64-kword block (16). in addition, thanks to multiplane ar chitecture, it is possible to program two pages at a time (one per plane) or to erase two blo cks at a time (again, one per plane). the multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by 50%. in multiplane operations, data in the page can be read out at 2 5 ns cycle time per byte. the i /o pins serve as the ports for c ommand and address input as well as data input/output. this interface allows a reduced pin count and ea sy migration towards different densities, without any rearra ngement of the footprint. commands, data, and addresses are asynchronously introduced usi ng ce#, we#, ale, and cle control pins. the on-chip program/erase contro ller automates all read, progra m, and erase functions including pulse repetition, where requir ed, and internal verificat ion and margining of d ata. a wp# pin is a vailable to provide hardware pr otection against p rogram and era se operations. the output pin r/b# (open drain buffer) signals the status of t he device during each operation. i t identifies if the program/e rase/read controller is currently active. the use of an open-drain output allows the ready/busy pins from several memories to connect to a single pull-up resisto r. in a system w ith multiple m emories the r/b# pins can be connected all t ogether to provide a global sta tus signal. the reprogram function allows the optimization of defective blo ck management when a page progr am operation fails the data can be directly programmed in another page inside the same arra y section without the time consu ming serial data insertion phas e. the copy back operation automatically executes embedded error d etection operation: 1-bit error out of every 528 bytes (8) or 256 words (16) can be detected. wit h this feature it is no longer necessary to use an external mechanism to detect copy back operation errors. multiplane copy back is also suppo rted. data read out after cop y back read (both for single and multiplane cases) is allowed. in addition, cache program and multiplane cache program operati ons improve the pr ograming throughput b y programing data using the cache register. the devices provide two innovative features: page reprogram and multiplane page reprogram. the page reprogram re-programs one page. normally, this operation is performed after a failed page program operation. similarly , the multiplane page reprogra m re-programs two pages in paralle l, one per plane. the first pag e must be in the first plane whi le the second page must be in t he second plane. the multiplane page reprogram operation is perfor med after a failed multiplane page program operation. the page reprogram and multiplane page rep rogram guarantee improved perf ormance, since data insertion can be omitted during re-program operations. note : the S34ML01G1 device does not support edc. document number: 002-00676 rev. *v page 5 of 71 S34ML01G1 s34ml02g1 s34ml04g1 the devices come with an otp (on e time programmable) area, whic h is a restricted access area w here sensitive da ta/code can be stored permanently. this securi ty feature is subect to an nda (non-disclosure agreem ent) and is, therefore , not described in the data sheet. for more details, con tact your nearest cypress sale s office. 1.1 logic diagram figure 1. logic diagram table 1. product list device density (bits) number of planes number of blocks per plane edc support main spare S34ML01G1 128m x 8 64m x 16 4m x 8 2m x 16 1 1024 no s34ml02g1 256m x 8 128m x 16 8m x 8 4m x 16 2 1024 yes s34ml04g1 512m x 8 256m x 16 16m x 8 8m x 16 2 2048 yes table 2. signal names signal description i/o7 - i/o0 (8) data input / outputs i/o8 - i/o15 (16) cle command latch enable ale address latch enable ce# chip enable re# read enable we# write enable wp# write protect r/b# read/busy vcc power supply vss ground nc not connected vcc vss wp# cle ale re# we# ce# i/o0~i/o7 r/b# document number: 002-00676 rev. *v page 6 of 71 S34ML01G1 s34ml02g1 s34ml04g1 1.2 connection diagram figure 2. 48-pin tsop1 co ntact 8, 16 devices note 1. these pins should be connected to power supply or ground (as designated) following the onfi s pecification, however they migh t not be bonded internally. figure 3. 63-bga contact, 8 device (balls down, top view) note: 1. these pins should be c onnected to power supply or ground (as designated) following the onfi specification, however they might not be bonded internally. nc nc nc nc nc nc r/b# re# ce# nc nc vcc vss nc nc cle ale we# wp# nc nc nc nc nc vss nc nc nc i/o7 i/o6 i/o5 i/o4 nc vcc nc vcc vss nc vcc nc i/o3 i/o2 i/o1 i/o0 nc nc nc vss 12 13 37 36 25 48 1 24 nand flash tsop1 x8 x8 nc nc nc nc nc nc r/b# re# ce# nc nc vcc vss nc nc cle ale we# wp# nc nc nc nc nc x16 x16 vss i/o15 i/o14 i/o13 i/o7 i/o6 i/o5 i/o4 i/o12 vcc nc vcc vss nc vcc i/011 i/o3 i/o2 i/o1 i/o0 i/o10 i/o9 i/o8 vss [1] [1] [1] [1] f3 f4 f5 f6 f7 f8 e3 e4 e5 e6 e7 e8 d3 d4 d5 d6 d7 d8 c3 c4 c5 c6 c7 c8 rb# we# ce# vss ale wp# nc nc nc cle re# vcc (1) nc nc nc nc nc nc g3 g4 g5 g6 g7 g8 nc vss (1) nc nc nc nc h3 h4 h5 h6 h7 h8 v cc nc nc nc i/o0 nc b9 a9 nc nc a2 nc nc nc nc nc vcc (1) nc b10 a10 nc nc b1 a1 nc nc j3 j4 j5 j6 j7 j8 i/o7 i/o5 v cc nc i/o1 nc k3 k4 k5 k6 k7 k8 v ss i/o6 i/o4 i/o3 i/o2 v ss l9 nc l2 nc l10 nc l1 nc m9 nc m2 nc m10 nc m1 nc document number: 002-00676 rev. *v page 7 of 71 S34ML01G1 s34ml02g1 s34ml04g1 figure 4. 63-bga contact, 16 device (balls down, top view) 1.3 pin description notes 2. a 0.1 f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power suppl y. the pcb track widths must be sufficient to carry the currents required during program and erase operations. 3. an internal voltage detector disables all functions whenever v cc is below 1.8v to protect the device from any involuntary progr am/erase during power transitions. table 3. pin description pin name description i/o0 - i/o7 (8) inputs/outputs . the i/o pins are used for command input, address input, data input, and data output. the i/o pins float to high-z when the device is deselected or the outputs are disa bled. i/o8 - i/o15 (16) cle command latch enable. this input activates the latching of the i/o inputs inside the command register on the rising edge of write enable (we#). ale address latch enable. this input activates the latching of the i/o inputs inside the address register on the rising edge of write enable (we#). ce# chip enable. this input controls the selecti on of the device. when the devic e is not busy ce# low selects the memory. we# write enable. this input latches command, address and data. the i/o inputs ar e latched on the rising edge of we#. re# read enable. the re# input is the serial data-out control, and when active d rives the data onto the i/o bus. data is valid t rea after the falling edge of re# which also increments the intern al column address counter by one. wp# write protect. the wp# pin, when low, provides hardware protection against und esired data modification (program / erase). r/b# ready busy . the ready/busy output is an open drain pin that signals the s tate of the memory. vcc supply voltage . the v cc supplies the power for all the operations (read, program, eras e). an internal lock circuit prevents the insertion of commands when v cc is less than v lko . vss ground. nc not connected. f3 f4 f5 f6 f7 f8 e3 e4 e5 e6 e7 e8 d3 d4 d5 d6 d7 d8 c3 c4 c5 c6 c7 c8 rb# we# ce# vss ale wp# nc nc nc cle re# vcc nc nc nc nc nc nc g3 g4 g5 g6 g7 g8 nc vss nc nc nc nc h3 h4 h5 h6 h7 h8 v cc i/o14 i/o12 i/o10 i/o0 i/o8 b9 a9 nc nc a2 nc nc i/o15 i/o13 nc vcc nc b10 a10 nc nc b1 a1 nc nc j3 j4 j5 j6 j7 j8 i/o7 i/o5 v cc i/o11 i/o1 i/o9 k3 k4 k5 k6 k7 k8 v ss i/o6 i/o4 i/o3 i/o2 v ss l9 nc l2 nc l10 nc l1 nc m9 nc m2 nc m10 nc m1 nc document number: 002-00676 rev. *v page 8 of 71 S34ML01G1 s34ml02g1 s34ml04g1 1.4 block diagram figure 5. functional block diagram address register/ counter controller command interface logic command register data register re# i/o buffer y decoder page buffer x d e c o d e r nand flash memory array wp# ce# we# cle ale i/o0~i/o7 (x8) i/o0~i/o15 (x16) 1024 mbit + 32 mbit (1 gb device) program erase hv generation 2048 mbit + 64 mbit (2 gb device) 4096 mbit + 128 mbit (4 gb device) document number: 002-00676 rev. *v page 9 of 71 S34ML01G1 s34ml02g1 s34ml04g1 1.5 array organization figure 6. array organization 8 figure 7. array organization 16 plane(s) 2048 bytes 64 bytes i/o [7:0] 1 page = (2k + 64) bytes 1 block = (2k + 64) bytes x 64 pages = (128k + 4k) bytes 1 plane = (128k + 4k) bytes x 1024 blocks page buffer 1024 blocks per plane 1022 1023 1 0 2 array organization (x8) for 1 gb and 2 gb devices there are 1024 blocks per plane for 4 gb device there are 2048 blocks per plane note : 2 gb and 4 gb devices have two planes plane(s) 1024 words i/o0~i/o15 1 page = (1k + 32) words 1 block = (1k + 32) words x 64 pages = (64k + 2k) words 1 plane = (64k + 2k) words x 1024 blocks page buffer 1024 blocks per plane 1022 1023 1 0 2 array organization (x16) for 1 gb and 2 gb devices there are 1024 blocks per plane for 4 gb device there are 2048 blocks per plane note : 2 gb and 4 gb devices have two planes 32 words document number: 002-00676 rev. *v page 10 of 71 S34ML01G1 s34ml02g1 s34ml04g1 1.6 addressing 1.6.1 S34ML01G1 notes 4. cax = column address bit. 5. pax = page address bit. 6. bax = block address bit. 7. block address concatenated with page address = actual page ad dress, also known as the row address. 8. i/o[15:8] are not used during the addressing sequence and sho uld be driven low. for the 8 address bits, t he following rules apply: ? a0 - a11: column address in the page ? a12 - a17: page address in the block ? a18 - a27: block address for the 16 address bits, the following rules apply: ? a0 - a10: column address in the page ? a11 - a16: page address in the block ? a17 - a26: block address 1.6.2 s34ml02g1 table 4. address cyc le map 1 gb device bus cycle i/o [15:8] [8] i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 8 1st / col. add. 1 a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (c a5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 a8 (ca8) a9 (ca9) a10 (ca10) a11 (ca11) low low low low 3rd / row add. 1 a12 (pa0) a13 (pa1) a14 (pa2) a15 (pa3) a16 (pa4) a 17 (pa5) a18 (ba0) a19 (ba1) 4th / row add. 2 a20 (ba2) a21 (ba3) a22 (ba4) a23 (ba5) a24 (ba6) a 25 (ba7) a26 (ba8) a27 (ba9) 16 1st / col. add. 1 low a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 low a8 (ca8) a9 (ca9) a10 (ca10) low low low low low 3rd / row add. 1 low a11 (pa0) a12 (pa1) a13 (pa2) a14 (pa3) a15 (pa4 ) a16 (pa5) a17 (ba0) a18 (ba1) 4th / row add. 2 low a19 (ba2) a20 (ba3) a21 (ba4) a22 (ba5) a23 (ba6 ) a24 (ba7) a25 (ba8) a26 (ba9) table 5. address cyc le map 2 gb device bus cycle i/o [15:8] [14] i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 8 1st / col. add. 1 a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (c a5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 a8 (ca8) a9 (ca9) a10 (ca10) a11 (ca11) low low low low 3rd / row add. 1 a12 (pa0) a13 (pa1) a14 (pa2) a15 (pa3) a16 (pa4) a 17 (pa5) a18 (pla0) a19 (ba0) 4th / row add. 2 a20 (ba1) a21 (ba2) a22 (ba3) a23 (ba4) a24 (ba5) a 25 (ba6) a26 (ba7) a27 (ba8) 5th / row add. 3 a28 (ba9) low low low low low low low 16 1st / col. add. 1 low a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 low a8 (ca8) a9 (ca9) a10 (ca10) low low low low low 3rd / row add. 1 low a11 (pa0) a12 (pa1) a13 (pa2) a14 (pa3) a15 (pa4 ) a16 (pa5) a17 (pla0) a18 (ba0) 4th / row add. 2 low a19 (ba1) a20 (ba2) a21 (ba3) a22 (ba4) a23 (ba5 ) a24 (ba6) a25 (ba7) a26 (ba8) 5th / row add. 3 low a27 (ba9) low low low low low low low document number: 002-00676 rev. *v page 11 of 71 S34ML01G1 s34ml02g1 s34ml04g1 notes 9. cax = column address bit. 10. pax = page address bit. 11. pla0 = plane address bit zero. 12. bax = block address bit. 13. block address concatenated with page address and plane addre ss = actual page address, also known as the row address. 14. i/o[15:8] are not used during the addressing sequence and sh ould be driven low. for the 8 address bits, t he following rules apply: ? a0 - a11: column address in the page ? a12 - a17: page address in the block ? a18: plane address (for multipl ane operations) / block address (for normal operations) ? a19 - a28: block address for the 16 address bits, the following rules apply: ? a0 - a10: column address in the page ? a11 - a16: page address in the block ? a17: plane address (for multipl ane operations) / block address (for normal operations) ? a18 - a27: block address 1.6.3 s34ml04g1 notes 15. cax = column address bit. 16. pax = page address bit. 17. pla0 = plane address bit zero. 18. bax = block address bit. 19. block address concatenated with page address and plane addre ss = actual page address, also known as the row address. 20. i/o[15:8] are not used during the addressing sequence and sh ould be driven low. for the 8 address bits, t he following rules apply: ? a0 - a11: column address in the page ? a12 - a17: page address in the block ? a18: plane address (for multipl ane operations) / block address (for normal operations) ? a19 - a29: block address table 6. address cyc le map 4 gb device bus cycle i/o [15:8] [20] i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 8 1st / col. add. 1 a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (c a5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 a8 (ca8) a9 (ca9) a10 (ca10) a11 (ca11) low low low low 3rd / row add. 1 a12 (pa0) a13 (pa1) a14 (pa2) a15 (pa3) a16 (pa4) a 17 (pa5) a18 (pla0) a19 (ba0) 4th / row add. 2 a20 (ba1) a21 (ba2) a22 (ba3) a23 (ba4) a24 (ba5) a 25 (ba6) a26 (ba7) a27 (ba8) 5th / row add. 3 a28 (ba9) a29 (ba10) low low low low low low 16 1st / col. add. 1 low a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 low a8 (ca8) a9 (ca9) a10 (ca10) low low low low low 3rd / row add. 1 low a11 (pa0) a12 (pa1) a13 (pa2) a14 (pa3) a15 (pa4 ) a16 (pa5) a17 (pla0) a18 (ba0) 4th / row add. 2 low a19 (ba1) a20 (ba2) a21 (ba3) a22 (ba4) a23 (ba5 ) a24 (ba6) a25 (ba7) a26 (ba8) 5th / row add. 3 low a27 (ba9) a28 (ba10) low low low low low low document number: 002-00676 rev. *v page 12 of 71 S34ML01G1 s34ml02g1 s34ml04g1 for the 16 address bits, the following rules apply: ? a0 - a10: column address in the page ? a11 - a16: page address in the block ? a17: plane address (for multipl ane operations) / block address (for normal operations) ? a18 - a28: block address 1.7 mode selection notes 21. x can be v il or v ih . high= logic level high . low = logic level low. 22. wp# should be biased to cmos high or cmos low for stand-by m ode. 23. during busy time in read, re# must be held high to prevent u nintended data out. table 7. mode selection mode cle ale ce# we# re# wp# read mode command input high low low rising high x address input low high low rising high x program or erase mode command input high low low rising high high address input low high low rising high high data input low low low rising high high data output (on going) low low low high falling x data output (suspended) x x x high high x busy time in read x x x high high [23] x busy time in program x x x x x high busy time in erase x x x x x high write protect x x x x x low stand by x x high x x 0v / v cc [22] document number: 002-00676 rev. *v page 13 of 71 S34ML01G1 s34ml02g1 s34ml04g1 2. bus operation there are six standard bus operations that control the device: command input, address input, d ata input, data output, write protect, and standby. (see table 7 .) typically glitches less than 5 ns on chip enable, write enable, and read enable are ignored by t he memory and do not affect bu s operations. 2.1 command input the command input bus operation is used to give a command to th e memory device. commands ar e accepted with chip enable low, command latch enable high, address latch enable low, and r ead enable high and latched on the rising edge of write enable. moreover, for commands that start a modify operation (program/e rase) the write protect p in must be high. see figure 12 on page 38 and table 20 on page 35 for details of the timing requirements. command codes are alwa ys applied on i/o7:0 regardless of the bus configuration (8 or 16). 2.2 address input the address input bus operation a llows the insert ion of the mem ory address. for the s34ml02g1 and s34ml04g1 devices, five write cycles are needed to input t he addresses. for the s34ml01 g1, four write cycles are need ed to input the addresses. if necessary, a 5th dummy address cycle can be issu ed to S34ML01G1 , which will be ignored by t he nand device without causing problems. addresses ar e accepted with chip enable low, address latch enable high, command latch enable low, and read enable high and latched on the rising edge of write enable. mor eover, for commands that start a m odify operation (program/eras e) the write protect pi n must be high. see figure 13 on page 38 and table 20 on page 35 for details of the timing requirements. addresses are always applied on i/o7:0 regardless of the bus co nfiguration (8 or 16). refer to table 4 through table 6 on page 11 for more detail ed information. 2.3 data input the data input bus operation allo ws the data to be programmed t o be sent to the device. the dat a insertion is serial and timed by the write enable cycles. data is accepted only with chip enable low, address latch enable low, c ommand latch enable low, read enable high, and write protect h igh and latched on the rising e dge of write enable. see figure 14 on page 39 and table 20 on page 35 for details of the timing requirements. 2.4 data output the data output bus operation a llows data to be read from the m emory array and to check the st atus register content, the edc register content, and the id dat a. data can be serially shifted out by toggling the read enable pin with chip enable low, writ e enable high, address latch enab le low, and command latch enable low. see figure 15 on page 39 and table 20 on page 35 for details of the timi ngs requirements. 2.5 write protect the hardware write protection is activated when the write prote ct pin is low. in this conditi on, modify operations do not star t and the content of the memory is not alt ered. the write protect pin is not latched by write enable to ensure the protection even durin g power up. 2.6 standby in standby, the device is desel ected, outputs ar e disabled, and power consumption is reduced. document number: 002-00676 rev. *v page 14 of 71 S34ML01G1 s34ml02g1 s34ml04g1 3. command set table 8. command set command 1st cycle 2nd cycle 3rd cycle 4th cycle acceptable command during busy supported on S34ML01G1 page read 00h 30h no yes page program 80h 10h no yes random data input 85h no yes random data output 05h e0h no yes multiplane program 80h 11h 81h 10h no no onfi multiplane program 80h 11h 80h 10h no no page reprogram 8bh 10h no no multiplane page reprogram 8bh 11h 8bh 10h no no block erase 60h d0h no yes multiplane block erase 60h 60h d0h no no onfi multiplane block erase 60h d1h 60h d0h no no copy back read 00h 35h no yes copy back program 85h 10h no yes multiplane copy back program 85h 11h 81h 10h no no onfi multiplane copy back program 85h 11h 85h 10h no no special read for copy back 00h 36h no no read edc status register 7bh yes no read status register 70h yes yes read status enhanced 78h yes no reset ffh yes yes read cache 31h no yes read cache enhanced 00h 31h no no read cache end 3fh no yes cache program (end) 80h 10h no yes cache program (start) / (continue) 80h 15h no yes multiplane cache program (start/continue) 80h 11h 81h 15h no no onfi multiplane cache program (start/continue) 80h 11h 80h 15h no no multiplane cache program (end) 80h 11h 81h 10h no no onfi multiplane cache program (end) 80h 11h 80h 10h no no read id 90h no yes read id2 30h-65h-00h 30h no yes read onfi signature 90h no yes read parameter page ech no yes one-time programmable (otp) area entry 29h-17h-04h-19h no yes document number: 002-00676 rev. *v page 15 of 71 S34ML01G1 s34ml02g1 s34ml04g1 3.1 page read page read is initiated by writi ng 00h and 30h to t he command re gister along with five address cycles (four or fi ve cycles for S34ML01G1). two types of operatio ns are available: random read and serial page read. random re ad mode is enabled when the page address is changed. all dat a within the selected page are transferred to the data register s. the system controller may de tect the completion of thi s data transfer (t r ) by analyzing the output of the r/b pin. once the data in a pa ge is loaded into the data registers, they may be read out i n 25 ns cycle ti me by sequenti ally pulsing re#. the repetitive high to low transitions of the re# signal makes the devic e output the data, s tarting from the sele cted column address up to the last column address. the device may output random data in a page instead of the sequ ential data by writing random data output command. the column address of next data, which is going to be out, may be changed to the address that follows ra ndom data output command. random data output can be performe d as many times as needed. after power up, the device is i n read mode, so 00h command cycl e is not necessary to start a re ad operation. any operation oth er than read or random data outpu t causes the device to exit read mode. see figure 6.1 on page 40 and figure 21 on page 43 as references. 3.2 page program a page program cycle consists of a serial data loading period i n which up to 2112 byte s (8) or 1056 words (16) of d ata may b e loaded into the data register, fo llowed by a non-volatile progr amming period where the loaded data is programmed into the appropriate cell. the serial data loading period b egins by inputting the serial d ata input command (80h), followed by the five cycle address inp uts (four cycles for S34ML01G1) and t hen serial data. the words oth er than those to be programmed do not need to be loaded. the device supports random data input within a page. the column add ress of next data, wh ich will be entered, m ay be changed to the address that follows the random data input command (85h). rando m data input may be performed as many times as needed. the page program confirm command (10h) initiates the programmin g process. the internal write s tate controller automatically executes the algorithms and controls timings necessary for prog ram and verify, thereby freeing the system contr oller for other tasks. once the program process starts, the read status register comma nds (70h or 78h) may be issued to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/b# output, or the status bit (i/o6) of the status register. o nly the read status commands (7 0h or 78h) or reset command are valid while programming is in progress. when the page program i s complete, the write status bit (i/o0) may be checked. the internal write verify detects on ly errors for 1s that are not successfully programmed to 0s. the command register remains in read status command mode un til another valid command is written to t he command register. figure6.2 onpage42 and figure 20 on page 43 detail the sequence. the device is programmable by page, but it also allows multiple partial page programming of a word or consecutive bytes up to 2112 bytes (8) or 1056 wo rds (16) in a singl e page program cycle. the number of consec utive partial page pr ogramming operations ( nop) within the same page must not exceed the number indicated in table 23 on page 37 . pages may be programmed in any order within a block. users who use edc check (for s34ml02g1 and s34ml04g1 only) in copy back must comply with some limitations related to data handling during one page pr ogram sequence. refer to section 3.8 on page 19 for details. if a page program operation is i nterrupted by hardware reset, p ower failure or other means, the host must ensure that the interrupted page is not used for further read ing or programming operations until the next uninterrupted bl ock erase is complet e. document number: 002-00676 rev. *v page 16 of 71 S34ML01G1 s34ml02g1 s34ml04g1 3.3 multiplane program s 34ml02g1 and s34ml04g1 the s34ml02g1 and s34m l04g1 devices support multiplane program, making it possible to program two pages in parallel, one page per plane. a multiplane program cycle consis ts of a double serial data loa ding period in which up to 4224 bytes (8) or 2112 words (16) of data may be loaded into the data register, followed by a non-vo latile programming period where the loaded data is programmed i nto the appropriate cell. the serial data loading period begins wit h inputting the serial data inpu t command (80h), followed by th e five cycle address inputs and serial data for the 1s t page. t he addr ess for this page mus t be in the 1st plane (pla0 = 0). the devi ce supports random data input exactl y the same as in the case of p age program operation. the dummy page program confirm command (11h) stops 1st page dat a input and the device becomes busy for a short time (t dbsy ). once it has beco me ready again, the 81h command mus t be issued, followed by 2nd page address (5 cycles) and its serial data input. the address for this page must be in the 2nd plane (pla0 = 1). the program confirm comman d (10h) starts parallel pr ogramming of both pages. figure 22 on page 44 describes the sequences using the legacy protocol. in this cas e, the block address bits for the first plane are all zero and the second address issued selects the block for bo th planes. figure 23 on page 44 describes the sequences using the onfi protocol. for both addresse s issued in this protocol, the block address bits must be the s ame except for the bit(s) that select the plane. the user can check operation status by monitoring r/b# pin or r eading the status register (comm and 70h or 78h). the read statu s register command is also availa ble during dummy busy time (t dbsy ). in case of failure in either page program, the fail bit of t he status register will be set. refer to section 3.9 on page 21 for further info. the number of consec utive partial page pr ogramming operations ( nop) within the same page must not exceed the number indicated in table 23 on page 37 . pages may be programmed in any order within a block. if a multiplane program operatio n is interrupted by hardware re set, power failure or other means, the host must ensure that th e interrupted pages are not used for further reading or programmi ng operations until the next uninterrupted block erases are com plete for the applicable blocks. 3.4 page reprogram s34ml02g1 and s34ml04g1 page program may result in a fail, which can be detected by rea d status register. in this event, the host may call page reprog ram. this command allows the reprogramm ing of the same pattern of th e last (failed) page in to another memory location. the command sequence initiates with reprog ram setup (8bh), followed by the five cycle address inputs of the target page. if the target pat tern for the destination page is not changed compared to the last page, the program confirm c an be issued (10h) wi thout any data input cycle, as described in figure 8 . figure 8. page reprogram sr[6] i/ox cycle type as defined for page program a a c1 i/ox sr[6] cycle type cmd addr addr addr 00h c2 r1 r3 page n din din din din cmd d0 d1 . . . dn 10h cmd dout 70h e1 fail ! page m cmd 10h tadl twb tprog twb tprog addr r2 addr cmd addr addr addr addr addr 8bh c1 c2 r1 r3 r2 document number: 002-00676 rev. *v page 17 of 71 S34ML01G1 s34ml02g1 s34ml04g1 on the other hand, if the patte rn bound for the target page is different from that of the previ ous page, data in cycles can be issued before program confirm 10h, as described in figure 9 . figure 9. page reprogram with data manipulation the device supports random data input within a page. the column address of next data, which will be entered, may be changed to the address which follows the random data input command (85h). random data input may be operat ed multiple times regardless of how many times it is done in a page. the program confirm command (10 h) initiates the re-programming process. the internal write sta te controller automatically executes the algorithms and contro ls timings necessary for prog ram and verify, thereby freeing the system controller for other tasks. once the program process starts , the read status register comma nd may be issued to read the status register. the system controller can detect the comple tion of a program cycle by moni toring the r/b# output, or the status bit (i/o6) of the status register. only the read status command an d reset command are valid when p rogramming is in progress. when the page program is complete, the write status bit ( i/o0) may be checked. the inter nal write verify detects only err ors for 1s that are not succe ssfully programmed to 0s. the command reg ister remains in read status command mode until anoth er valid command i s written to the command register. the page reprogram must be issued in the same plane as the page program that failed. in order to program the data to a differe nt plane, use the page program oper ation instead. the multiplane p age reprogram can re-program two pages in parallel, one per plane. the multiplane page reprogram operation is performed aft er a failed multiplane page pr ogram operation. the command sequence is very similar to figure 22 on page 44 , except that it requir es the page reprogram command (8bh) inst ead of 80h and 81h. if a page reprogram operation is interrupted by hardware reset, power failure or other means, t he host must ensure that the interrupted page is not used for further read ing or programming operations until the next uninterrupted bl ock erase is complet e. c1 iox sr[6] sr[6] cycle type i/ox cycle type as defined for page program a a cmd addr addr addr addr 80h c2 r1 r3 page n din din din din cmd d0 d1 . . . dn 10h cmd addr addr addr addr 8bh c1 c2 r1 r3 fail ! page m cmd 10h tadl twb tprog twb tprog cmd dout 70h e1 din din din din d0 d1 . . . dn tadl addr r2 addr r2 document number: 002-00676 rev. *v page 18 of 71 S34ML01G1 s34ml02g1 s34ml04g1 3.5 block erase the block erase opera tion is done on a bloc k basis. block addre ss loading is accomplished in thr ee cycles (two cycles for S34ML01G1) initiated by an erase setup command (60h). only the block address bits are valid wh ile the page address bits are ignored. the erase confirm command (d0h) following the block address loa ding initiates the internal e rasing process. this two-step sequence of setup followed by t he execution comm and ensures tha t memory contents are not acci dentally erased due to external noise conditions. at the rising edge of we# after the erase confirm command input , the internal write controller handles erase and erase verify. once the erase process star ts, the read status re gister commands (70 h or 78h) may be i ssued to read the s tatus register. the system controller can detect the comple tion of an erase by monitoring the r/b# output, or t he status bit (i/ o6) of the sta tus register. only the read status commands (70h or 78h) and reset command are valid while erasing is in progress. when the erase operation is completed, the write status bit (i/o0) may be chec ked. figure 24 on page 45 details the sequence. if a block erase operation is int errupted by hardware reset, po wer failure or other means, the host must ensure that the inter rupted block is erased under continuous power conditions before that b lock can be trusted for further programming and reading operati ons. 3.6 multiplane block erase s34ml02g1 and s34ml04g1 multiplane block erase allows the erase of two blocks in parall el, one block per memory plane. the block erase setup command ( 60h) must be repeated two times, followed by 1st and 2nd block address resp ectively (3 cycles each). as for block erase, d0h command makes embedded operation start. in this case, multip lane erase does not need any dummy busy time between 1st and 2nd block insertion. see table 23 on page 37 for performance information. for the multiplane block erase operation, the address of the fi rst block must be within the firs t plane (pla0 = 0) and the add ress of the second block in the second plane (pla0 = 1). see figure 25 on page 45 for a description of the legacy protocol. in this case, the block address bits for the first plane are all zero and the sec ond address issued selects t he block for both planes. figure 26 on page 46 describes the sequences using t he onfi protocol. for both addr esses issued in this protocol, the block address bits must be the same exc ept for the bit(s) that select the plane. the user can check operation status by monitoring r/b# pin or r eading the status register (comm and 70h or 78h). the read statu s register command is also availa ble during dummy busy time (t dbsy ). in case of failure i n either erase, the fail bit of the stat us register will be set. refer to section 3.9 on page 21 for further information. if a multiplane block erase oper ation is interru pted by hardwar e reset, power failure or other means, the host must ensure tha t the interrupted blocks are erased und er continuous power conditions before thos e blocks can be trusted fo r further programming and reading operations. 3.7 copy back program the copy back featur e is intended to quickl y and efficiently re write data stored in one page without utilizing an external mem ory. since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is greatly improved . the benefit is especially obvious when a portion of a block nee ds to be updated and the rest of the block also needs to be cop ied to the newly assigned free block. the operation for performing a c opy back is a sequential execut ion of page-read (without mandat ory serial access) and copy back progr am with the add ress of destin ation page. a read operation with the 35h command and the address of the source page moves the whole page of data into th e internal data register. as soon as the device returns to the ready state, optional data read-out is allowed by toggling re# (see figure 27 on page 46 ), or the copy back program command (85h) with the address cycles o f the destination page may be written. the program confirm command (10h) is required to actually begin programming. the source and the destination pages in the copy back program s equence must belong to the same device plane (same pla0 for s34ml02g1 and s34ml04g1). copy back read and copy back program for a given plane must be between odd address pages or between even address pages for the device to meet the program t ime (t prog ) specification. copy back program may not meet this specification when c opying from an odd address page (source pag e) to an even address page (t arget page) or from an even address page (source page) to an odd address pa ge (target page) . the data input cycle for modifyin g a portion or multiple distin ct portions of the source page is allowed as shown in figure 28 on page 46 . as noted in section 1. on page 4 the device may include an automa tic edc (for s34ml02g1 and s34 ml04g1) check during the copy back operation, to detect single bit errors in edc units contained within the so urce page. more details on edc operation and limitat ions related to data input handling during one copy back program sequence are available in section 3.8 on page 19 . document number: 002-00676 rev. *v page 19 of 71 S34ML01G1 s34ml02g1 s34ml04g1 if a copy back program operation is interrupted by hardware res et, power failure or other means , the host must ensure that the interrupted page is not used for further read ing or programming operations until the next uninterrupted bl ock erase is complet e. 3.7.1 multiplane copy back progr am s34ml02g1 and s34ml04g1 the device supports multiplane co py back program with exactly t he same sequence and limitati ons as the page program. multiplane copy back program mu st be preceded by two single pag e copy back read command se quences (1st page must be read from the 1st plane and 2nd page from the 2nd plane). multiplane copy back cannot cross plane boundaries the conten ts of the source page of one devi ce plane can be copied only to a destination page of the same plane. edc check is available al so for multiplane copy back pr ogram only for s34ml02g1 and s34ml04g1. when edc check is used in cop y back, it must comply with some limitations related to data h andling during one multiplane cop y back program sequence. please refer to section 3.8 on page 19 for details on edc operation. the multiplane copy back program sequence represented in figure 29 on page 47 shows the legacy protocol. in thi s case, the blo ck address bit s for the first plane are all zero and the second address issued selects the block for bo th planes. figure 30 on page 47 describes the s equence using the onfi protocol. for both addresse s issued in this protocol, the block address bits must be the s ame except for the bit(s) that select the plane. if a multiplane copy back progra m operation is interrupted by h ardware reset, power failure or other means, the host must ensu re that the interrupted pages are n ot used for further reading or programming operations until the next uninterrupted block erase s are complete for the applicable blocks. 3.7.2 special read for copy b ack s34ml02g1 and s34ml04g1 the s34ml02g1 and s34m l04g1 devices support special read for co py back. if copy back read (described in section 3.7 and section 3.7.1 on page 19 ) is triggered with conf irm command 36h instead 35h, copy b ack read from target page(s) will be executed with an incr eased internal (v pass ) voltage. this special feature is used in order to minimize the number of read errors due to over-program o r read disturb it shall be used only if ecc read errors have o ccurred in the sour ce page using page read or copy back read sequences. excluding the copy back read c onfirm command, all other feature s described in section 3.7 and section 3.7.1 for standard copy back remain valid (including the figures referred to in those s ections). 3.8 edc operation s34ml02g1 and s34ml04g1 error detection code check is a f eature that can be used during the copy back operation (both single and multiplane) to detect single bit errors occurring in the source page(s). note : the S34ML01G1 device does not support edc. ? edc check allows detec tion of up to 1 single bit error every 52 8 bytes, where each 528 byte group is composed of 512 bytes of main arra y and 16 bytes of spare area (see table 10 and table 11 on page 21 ). the described 528-byte area is called an edc unit. ? in the 16 device, edc allows det ection of up to 1 single bit e rror every 264 words, wher e each 264 word group is composed by 256 words of main arra y and 8 words of spare area s ee table 10 and table 11 on page 21 ). the described 264-word area is called edc unit. edc results can be checked through a specific read edc register command, available only after issuing a copy back program or a multiplane copy back program. the edc regi ster can be queried d uring the copy back program busy time (t prog ). for the edc check feature to operate correctly, specific cond itions on data input handling apply for program operations. document number: 002-00676 rev. *v page 20 of 71 S34ML01G1 s34ml02g1 s34ml04g1 for the case of page program, mu ltiplane page program, page rep rogram, multiplane page re program, cache program, and multiplane cache program operations: ? in section3.2 onpage15 it was explained that a number of consecutive partial program operations (nop) is allowed within the same page. in case this feature is used, the number of part ial program operations occurring in the same edc unit must not exceed 1. in other words, page program opera tions must be p erformed on the whole page, or on whole e dc unit at a time. ? random data input in a given e dc unit can be ex ecuted several times during one page pro gram sequence, but data cannot be written to a ny column address mor e than once before t he program is initiated. for the case of copy back progr am or multiplane copy back progr am operations: ? if random data input is applied in a given edc unit, the entire edc unit must be written to the page buffer. in other words, the edc check is possi ble only if the whole edc unit is modifie d during one copy back program sequence. ? random data input in a given e dc unit can be ex ecuted several times during one copy back program sequence, but data insertion in each column a ddress of the edc unit must not exceed 1. if you use copy back without edc check, none of the limitations described above apply. after a copy back pr ogram operation, the host can use read edc status register to check the status of both the program operation and the copy back r ead. if the edc wa s valid and an e rror was reported in the edc (see table 9 on page 20 ), the host may perform special read for copy back on the source page and a ttempt the copy back program a gain. if this also fails, the hos t can execute a page re ad operation in order to correct a single bit error with external e cc software or hardware. 3.8.1 read edc status register s34ml02g1 and s34ml04g1 this operation is available only after issuing a copy back prog ram and it allows the detection of errors during copy back read . in the case of multiplane copy back , it is not possi ble to know wh ich of the two read operations caused the error. after writing the r ead edc status register command (7bh) to the command register, a read cycle outputs the content of the edc register to the i/o pins on the falling edge of ce# or re#, whi chever occurs last. the operation is the same as th e read status regi ster command. refer to table 9 for specific edc regi ster definitions: table 9. edc register coding id copy back program coding 0 pass / fail pass: 0; fail: 1 1 edc status no error: 0; error: 1 2 edc validity invalid: 0; valid: 1 3na 4na 5 ready / busy busy: 0; ready: 1 6 ready / busy busy: 0; ready: 1 7 write protect protect ed: 0; not protected: 1 document number: 002-00676 rev. *v page 21 of 71 S34ML01G1 s34ml02g1 s34ml04g1 3.9 read status register the status register is used to r etrieve the status value for th e last operation issued. after w riting 70h command to the comma nd register, a read cycle outputs the c ontent of the st atus regist er to the i/o pins on the falling edge of ce# or re#, whichever occurs last. this two-line control allo ws the system to p oll the progr ess of each device in multiple memory connections even when r/b # pins are common-wired. refer to section 13 on page 22 for specific status regi ster definition, and to figure 31 on page 48 for timings. if the read status register comm and is issued during multiplane operations then status regist er polling will return the combin ed status value related to the outcome of t he operation in the two planes according to the following table. in other words, the s tatus register is dynamic; the user is not required to toggle re# / ce# to update it. the command register remains in status read mode until further commands are issued. therefore, i f the status register is read during a random read cycle, the read comma nd (00h) must be issu ed before starti ng read cycles. note: the read status register command shall not be used for co ncurrent operations in multi-die stack configurations (single c e#). read status enhanced shall be used instead. table 10. page organization in edc units main field (2048 byte) spare field (64 byte) a area (1st sector) b area (2nd sector) c area (3rd sector) d area (4th sector) e area (1st sector) f area (2nd sector) g area (3rd sector) h area (4th sector) 8 512 byte 512 byte 512 byte 512 byte 16 byte 16 byte 16 byte 16 byte 16 256 words 256 words 256 words 256 words 8 words 8 words 8 words 8 word s table 11. page organization in edc units by address sector main field (column 0-2047) spare field (column 2048-2111) area name column address area name column address 8 1st 528-byte sector a 0-511 e 2048-2063 2nd 528-byte sector b 512-1023 f 2064-2079 3rd 528-byte sector c 1024-1535 g 2080-2095 4th 528-byte sector d 1536-2047 h 2096-2111 16 1st 256-word sector a 0-255 e 1024-1031 2nd 256-word sector b 256-511 f 1032-1039 3rd 256-word sector c 512-767 g 1040-1047 4th 256-word sector d 768-1023 h 1048-1055 table 12. read status definition status register bit composite status value bit 0, pass/fail or bit 1, cache pass/fail or document number: 002-00676 rev. *v page 22 of 71 S34ML01G1 s34ml02g1 s34ml04g1 3.10 read status enhanced s34ml02g1 and s34ml04g1 read status enhanced is used to retrieve the status value for a previous operation in the specified plane. figure 32 on page 48 defines the read status enhanced behavior and timings. the pla ne and die address must be specified in the command sequence in order to retr ieve the status of the die and the plane of interest. refer to table 13 for specific status register definitions . the command register remains in status rea d mode until further commands are issued. the status register is dynamic; the user is not required to tog gle re# / ce# to update it. 3.11 read status register field definition table 13 below lists the meani ng of each bit of the read status registe r and read status enh anced (s34ml02g1 and s34ml04g1). 3.12 reset the reset feature is executed by writing ffh to the command reg ister. if the device is in the busy state during random read, program, or erase mode, the reset operation will abort these op erations. the contents of memor y cells being altered are no lon ger valid, as the data may be partially programmed or erased. the c ommand register is cleared to wa it for the next command, and th e status register is cleared to value e0h when wp# is high or val ue 60h when wp# is low. if the device is already in reset state a new reset command will not be accept ed by the command register. the r/b# pin transitions to low for t rst after the reset command is written. refer to figure 33 on page 48 for further details. the status register ca n also be read to d etermine the status of a reset operation. table 13. status register coding id page program / page reprogram block erase read read cache cache program / cache reprogram coding 0 pass / fail pass / fail na na pass / fail n page pass: 0 fail: 1 1 na na na na pass / fail n - 1 page pass: 0 fail: 1 2na nanana na 3na nanana na 4na nanana na 5 ready / busy ready / busy ready / busy ready / busy ready / busy internal data operation active: 0 idle: 1 6 ready / busy ready / busy ready / busy ready / busy ready / busy ready / busy busy: 0 ready: 1 7 write protect write protect na na write protect protected: 0 not protected: 1 document number: 002-00676 rev. *v page 23 of 71 S34ML01G1 s34ml02g1 s34ml04g1 3.13 read cache read cache can be used to increase the re ad operation speed, as defined in section 3.1 on page 15 , and it cannot cross a block boundary. as soon as the user st arts to read one page, the devi ce automatically load s the next page into the cache register. s erial data output may be executed whil e data in the memory is read in to the cache register. read cache is initiated b y the page read sequence (00-30h) on a page m. after random access to the first page is complete (r/b# returne d to high, or read status regi ster i/o6 switches to high), two command sequences can be us ed to continue read cache: ? read cache (command 31h only): once the command is latched in to the command register (see figure 35 on page 49 ), device goes busy for a short time (t cbsyr ), during which data of the first page is t ransferred from the data register to the cache register. at the end of th is phase, the cache register da ta can be output by toggling re # while the next page (page address m+1) is read from the me mory array into the data regist er. ? read cache enhanced (sequence 00h document number: 002-00676 rev. *v page 24 of 71 S34ML01G1 s34ml02g1 s34ml04g1 3.14 cache program cache program can impr ove the program thro ughput by using the c ache register. the cache progr am operation cannot cross a block boundary. the cache register allows new dat a to be input while the previous d ata that was transferred to the data regist er is programmed into the memory array. after the serial data input command (80h) is loaded to the comm and register, followed by five cycles of address, a full or par tial page of data is latched int o the cache register. once the cache write command (15h) is loade d to the command reg ister, the data in the cache register is tr ansferred into the d ata register for cell programming. at this time the device remains in the busy state fo r a short time (t cbsyw ). after all data of the cache register is transferred into the data register, the device retu rns to the ready state and allows loading the next data into th e cache register through another cache program command sequence (80h-15 h). the busy time following the first sequence 80h - 15h equals the time needed to transfer the data from the cache register to th e data register. cell programming the d ata of the data r egister and lo ading of the next data into the cache register is consequently processed through a pipeline model. in case of any subsequent sequenc e 80h - 15h, transfer from the cache register to the data register is held off until cell pro gramming of current data regist er contents is comple te; till this moment the device will stay in a busy state (t cbsyw ). read status commands (70h or 78h) may be issued t o check the st atus of the different registers, and the pass/fail status of th e cached program operations. ? the cache-busy status bit i/o6 i ndicates when the cache registe r is ready to accept new data. ? the status bit i/o5 can be used to determine when the cell prog ramming of the current data r egister contents is complete. ? the cache program erro r bit i/o1 can be used to identify if the previous page (page n-1) has been successfully programmed or not in a cache prog ram operation. the status bit is valid upon i/o6 stat us bit changing to 1. ? the error bit i/o0 is used to identify if any error has been de tected by the program/erase controller while programming page n. the status bit is valid upon i/o5 status bit changing to 1. i/o1 may be read t ogether with i/o0. if the system monitors the progress of the operation onl y with r/b#, the last page of the target prog ram sequence must be programmed with page program confirm command (10h). if the cach e program command (15h) is used instead, the status bit i/o5 must be polled to find out if the last programming is finished before starting any other operation. see table 13 on page 22 and figure 38 on page 50 for more details. if a cache program operation is i nterrupted by hardware reset, power failure or othe r means, the host must ensure that the interrupted pages are not used for further reading or programmi ng operations until the next uninterrupted block erases are com plete for the applicable blocks. document number: 002-00676 rev. *v page 25 of 71 S34ML01G1 s34ml02g1 s34ml04g1 3.15 multiplane cache program s34ml02g1 and s34ml04g1 the multiplane cache program enables high program throughput by programming two pages in paral lel, while exploiting the data and cache registers of both planes to implement cache. the command sequence can be summarized as follows: ? serial data input com mand (80h), fo llowed by the five cycle add ress inputs and then serial d ata for the 1st page. address for this page must be within 1st plane (pla0 = 0). the data of 1st page other than those to b e programmed do not need to be loaded. the device supports r andom data input exactly like p age program operation. ? the dummy page program confirm command (11h) stops 1st page dat a input and the device bec omes busy for a short time (t dbsy ). ? once device returns to ready agai n, 81h command must be issued, followed by 2nd page address (5 cycles) and its se rial data input. addr ess for this page mus t be within 2nd plane (pla0 = 1) . the data of 2nd page other than those to be programm ed do not need to be loaded. ? cache program confirm command (15h). once the cache write comma nd (15h) is loaded to the command register, the data in the cache registers is transferred into the data registers f or cell programming. at this time the device remains in the bus y state for a short time (t cbsyw ). after all data from the cac he registers are transferred into the data registers, the device returns to the ready state, an d allows loading the next data in to the cache register thr ough another cache program command sequence. the sequence 80h-...- 11h...-... 81h...-...15h can be iterated, and each time the device will be busy for the t cbsyw time needed to complete programming the current data register contents, and tr ansferring the new data from t he cache registers. the sequence to end multiplane cache program is 80h-...- 11h...-...81h...-...10 h. the multiplane cache program is available only within two paire d blocks in separate planes. figure 39 on page 51 shows the legacy protocol for the multiplane cac he program operation. in this ca se, the block address bi ts for the first plane are all zero and the second address issued selects the block for both planes. figure 40 on page 52 shows the onfi protocol for the multiplane cache program operation. for both addr esses issued in this protocol, the block address bits must be the same except for the bit(s) t hat select the plane. the user can check oper ation status by r/b# pin or read status register commands (70h or 78h). if the user opts for 70h, read status register will provide g lobal informati on about the ope ration in the two planes. ? i/o6 indicates when both cache r egisters are ready to accept ne w data. ? i/o5 indicates when the cell pr ogramming of the current data re gisters is complete. ? i/o1 identifies if t he previous pages in both planes (pages n-1 ) have been successfully progra mmed or not. this status bit is valid upon i/o6 stat us bit changing to 1. ? i/o0 identifies if any error has been detected by the program/e rase controller while programming the two pages n. this status bit is vali d upon i/o5 status bit changing to 1. see table 13 on page 22 for more details. if the system monitors the progress of the operation onl y with r/b#, the last pages of the ta rget program sequence must be programmed with page program confirm command (10h). if the cach e program command (15h) is used instead, the status bit i/o5 must be polled to find out if the last programming is finished before starting any oth er operation. refer to section 3.9 on page 21 for further information. if a multiplane cache program ope ration is interru pted by hardw are reset, power failure or othe r means, the host must ensure t hat the interrupted pages are not used for further reading or progr amming operations until the next uninterrupt ed block erases are complete for the applicable blocks. document number: 002-00676 rev. *v page 26 of 71 S34ML01G1 s34ml02g1 s34ml04g1 3.16 read id the device contains a product id entification mode , initiated by writing 90h to the command reg ister, followed by an address in put of 00h. note : if you want to execute read st atus command (0x70) after read id sequence, you should input dummy command (0x00) before read status command (0x70). for the s34ml02g1 and s34ml04g1 devices, five read cycles seque ntially output the ma nufacturer code (01h) , and the device code and 3rd, 4th, and 5th cycle id, respectively. for the s34m l01g1 device, four read cycles s equentially output the manufact urer code (01h), device id (f1h), 3rd cycle (00h), and 4th cycle id of 1dh respectively. the command register remains in read id mo de until further commands are issued to it. figure 41 on page 53 shows the operation sequence, while table 14 to table 3.3 explain the byte meaning. table 14. read id for supported configurations density org v cc 1st 2nd 3rd 4th 5th 1 gb 8 3.3v 01h f1h 00h 1dh 2 gb 01h dah 90h 95h 44h 4 gb 01h dch 90h 95h 54h 1 gb 16 01h c1h 00h 5dh 2 gb 01h cah 90h d5h 44h 4 gb 01h cch 90h d5h 54h table 15. read id bytes device identifier byte description 1st manufacturer code 2nd device identifier 3rd internal chip number, cell type, etc. 4th page size, block size, spare size, serial acce ss time, organ ization 5th (s34ml02g1, s34ml04g1) ecc, multiplane information document number: 002-00676 rev. *v page 27 of 71 S34ML01G1 s34ml02g1 s34ml04g1 3 rd id data 4 th id data table 16. read id byte 3 description description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2-level cell 4-level cell 8-level cell 16-level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 11 interleave program between multiple chips not supported supported 0 1 cache program not supported supported 0 1 table 3.1 read id byte 4 description S34ML01G1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (without spare area) 1 kb 2 kb 4 kb 8 kb 0 0 0 1 1 0 1 1 block size (without spare area) 64 kb 128 kb 256 kb 512 kb 0 0 0 1 1 0 1 1 spare area size (byte / 512 byte) 8 16 0 1 serial access time 45 ns 25 ns reserved reserved 0 0 1 1 0 1 0 1 organization 8 0 16 1 document number: 002-00676 rev. *v page 28 of 71 S34ML01G1 s34ml02g1 s34ml04g1 5 th id data table 3.2 read id byte 4 descripti on s34ml02g1 and s34ml04g1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (without spare area) 1 kb 2 kb 4 kb 8 kb 0 0 0 1 1 0 1 1 block size (without spare area) 64 kb 128 kb 256 kb 512 kb 0 0 0 1 1 0 1 1 spare area size (byte / 512 byte) 8 16 0 1 serial access time 50 ns / 30 ns 25 ns reserved reserved 0 1 0 1 0 0 1 1 organization 8 0 16 1 table 3.3 read id byte 5 descripti on s34ml02g1 and s34ml04g1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 plane number 1 2 4 8 0 0 0 1 1 0 1 1 plane size (without spare area) 64 mb 128 mb 256 mb 512 mb 1 gb 2 gb 4 gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 reserved 0 0 0 document number: 002-00676 rev. *v page 29 of 71 S34ML01G1 s34ml02g1 s34ml04g1 3.17 read id2 the device contains an alternate identification mode, initiated by writing 30h-65h-00h to the command register, followed by ad dress inputs, followed by command 30h . the address for S34ML01G1 will be 00h-02h-02h-00h. the address for s34ml02g1 and s34ml04g1 will b e 00h-02h-02h-00h-00h. the id2 data can then be read from the device by pulsing re#. the command register remains in read id2 mode until further co mmands are issued to it. figure 42 on page 53 shows the read id2 command sequence. read id2 values are all 0 xfs, unless specific v alues are requested when ordering from cypress. 3.18 read onfi signature to retrieve the onfi s ignature, the command 90h together with a n address of 20h shall be entered (i.e. it i s not valid to ente r an address of 00h and re ad 36 bytes to get the onfi signature). th e onfi signature is the ascii encoding of ' onfi' where 'o' = 4f h, 'n' = 4eh, 'f' = 46h, and 'i' = 4 9h. reading beyond four bytes yields indeterminate values. figure 43 on page 54 shows the operation sequence. 3.19 read parameter page the device supports the onfi rea d parameter page operation, ini tiated by writing ech to the com mand register, followed by an address input of 00h. the host ma y monitor the r/b# pin or wait for the maximum data transfer time (t r ) before reading the parameter page data. the command register remains in parameter page mode until further commands are issued to it. if the statu s register is read to determine wh en the data is ready, the read command (00h) must be issued befor e starting read cycles. figure 44 on page 54 shows the operation sequence, while table 3.4 explains the parameter fields. for 16 devices, the upper eight i/os are not us ed and are 0xff . note: for 41nm 2gb/4gb cypr ess nand, for a parti cular condition, the read parameter page command does not give the correct values. to overcome th is issue, the host must issue a reset com mand before the read paramete r page command. issuance of reset before the read parameter page command will provide the c orrect values and will not outpu t 00h values. this does not app ly to 48nm 1gb. table 3.4 parameter page description byte o/m description values revision information and features block 0-3 m parameter page signature byte 0: 4fh, o byte 1: 4eh, n byte 2: 46h, f byte 3: 49h, i 4fh, 4eh, 46h, 49h 4-5 m revision number 2-15 reserved (0) 1 1 = supports onfi version 1.0 0 reserved (0) 02h, 00h 6-7 m features supported 5-15 reserved (0) 4 1 = supports odd to even page copyback 3 1 = supports interleaved operations 2 1 = supports non-sequential page programming 1 1 = supports multiple lun operations 0 1 = supports 16-bit data bus width S34ML01G100 (8) : 14h, 00h s34ml02g100 (8) : 1ch, 00h s34ml04g100 (8) : 1ch, 00h S34ML01G104 (16) : 15h, 00h s34ml02g104 (16) : 1dh, 00h s34ml04g104 (16) : 1dh, 00h 8-9 m optional commands supported 6-15 reserved (0) 5 1 = supports read unique id 4 1 = supports copyback 3 1 = supports read status enhanced 2 1 = supports get features and set features 1 1 = supports read cache commands 0 1 = supports page cache program command S34ML01G1: 13h, 00h s34ml02g1: 1bh, 00h s34ml04g1: 1bh, 00h 10-31 reserved (0) 00h manufacturer information block document number: 002-00676 rev. *v page 30 of 71 S34ML01G1 s34ml02g1 s34ml04g1 32-43 m device manufacturer (12 ascii characters) 53h, 50h, 41h, 4eh, 53h, 49h, 4fh, 4eh, 20h, 20h, 20h, 20h 44-63 m device model (20 ascii characters) S34ML01G1: 53h, 33h, 34h, 4dh, 4ch, 30h, 31h, 47h, 31h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h s34ml02g1: 53h, 33h, 34h, 4dh, 4ch, 30h, 32h, 47h, 31h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h s34ml04g1: 53h, 33h, 34h, 4dh, 4ch, 30h, 34h, 47h, 31h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h 64 m edec manufacturer id 01h 65-66 o date code 00h 67-79 reserved (0) 00h memory organization block 80-83 m number of data bytes per page 00h, 08h, 00h, 00h 84-85 m number of spare bytes per page 40h, 00h 86-89 m number of data bytes per partial page 00h, 02h, 00h, 00 h 90-91 m number of spare bytes per partial page 10h, 00h 92-95 m number of pages per block 40h, 00h, 00h, 00h 96-99 m number of blocks per logical unit (lun) S34ML01G1: 00h, 04h, 00h, 00h s34ml02g1: 00h, 08h, 00h, 00h s34ml04g1: 00h, 10h, 00h, 00h 100 m number of logical units (luns) 01h 101 m number of address cycles 4-7 column address cycles 0-3 row address cycles S34ML01G1: 22h s34ml02g1: 23h s34ml04g1: 23h 102 m number of bits per cell 01h 103-104 m bad blocks maximum per lun S34ML01G1: 14h, 00h s34ml02g1: 28h, 00h s34ml04g1: 50h, 00h 105-106 m block endurance 01h, 05h 107 m guaranteed valid blocks at beginning of target 01h 108-109 m block endurance for guaranteed valid blocks 01h, 03h 110 m number of programs per page 04h 111 m partial programming attributes 5-7 reserved 4 1 = partial page layout is partial page data followed by partial page spare 1-3 reserved 0 1 = partial page programming has constraints 00h 112 m number of bits ecc correctability 01h 113 m number of interleaved address bits 4-7 reserved (0) 0-3 number of interleaved address bits S34ML01G1: 00h s34ml02g1: 01h s34ml04g1: 01h 114 o interleaved operation attributes 4-7 reserved (0) 3 address restrictions for program cache 2 1 = program cache supported 1 1 = no block address restrictions 0 overlapped / concurrent interleaving support S34ML01G1: 00h s34ml02g1: 04h s34ml04g1: 04h 115-127 reserved (0) 00h electrical parameters block table 3.4 parameter page descr iption (continued) byte o/m description values document number: 002-00676 rev. *v page 31 of 71 S34ML01G1 s34ml02g1 s34ml04g1 note 24. o stands for optional, m for mandatory. 3.20 one-time program mable (otp) entry the device contains a one-time programmable (otp) area, which i s accessed by writing 29h-17h-04h-19h to the command register. the device is then ready to accep t page read and page program c ommands (refer to page read and page program on page 15 ). the otp area is of a single erase block size (64 pages), and he nce only row addresses between 00h and 3fh are allowed. the hos t must issue the reset command (refer to reset on page 22 ) to exit the otp area and access the normal flash array. the b lock erase command is not allowed in the otp area. refer to figure 45 on page 54 for more detail on the o tp entry command sequence. note: the otp feature in t he S34ML01G1 does not have non-volatile pr otection. 128 m i/o pin capacitance 0ah 129-130 m timing mode support 6-15 reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0, shall be 1 1fh, 00h 131-132 o program cache timing mode support 6-15 reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0 1fh, 00h 133-134 m t prog maximum page program time (s) bch, 02h 135-136 m t bers maximum block erase time (s) S34ML01G1: b8h, 0bh s34ml02g1: 10h, 27h s34ml04g1: 10h, 27h 137-138 m t r maximum page read time (s) 19h, 00h 139-140 m t ccs minimum change column setup time (ns) 64h, 00h 141-163 reserved (0) 00h vendor block 164-165 m vendor specific revision number 00h 166-253 vendor specific 00h 254-255 m integrity crc S34ML01G100 (8) : ffh, 63h s34ml02g100 (8) : 3bh, c5h s34ml04g100 (8) : 45h, 8eh S34ML01G104 (16) : 8dh, 15h s34ml02g104 (16) : 49h, b3h s34ml04g104 (16) : 37h, f8h redundant parameter pages 256-511 m value of bytes 0-255 repeat value of bytes 0-255 512-767 m value of bytes 0-255 repeat value of bytes 0-255 768+ o additional redundant parameter pages ffh table 3.4 parameter page descr iption (continued) byte o/m description values document number: 002-00676 rev. *v page 32 of 71 S34ML01G1 s34ml02g1 s34ml04g1 4. signal descriptions 4.1 data protection and power on / off sequence the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage de tector disables all functions whenever v cc is below about 1.8v. the power-up and power-dow n sequence is shown in figure 46 on page 55 . the ready/busy signal shall be va lid within 100 s after the po wer supplies have reached the mi nimum values (as specified on), and shall return to one within 5 ms (max). during this busy time, the device executes the initialization p rocess (cam reading), and dissipates a current i cc0 (30 ma max), in addition, it disrega rds all commands excluding read status regi ster (70h). at the end of this busy time, the device defaults into read se tup, thus if the user decides to issue a page read command, th e 00h command may be skipped. the wp# pin provides hardware pr otection and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 100 s is required before the internal circuit gets ready for any command sequences as shown in figure 46 on page 55 . the two-step command sequence for program/erase provides addi tional software protection. 4.2 ready/busy the ready/busy output provides a method of indicating the compl etion of a page program, erase, c opyback, or read completion. the r/b# pin is normally high and goes to low when the device i s busy (after a reset, read, program, or erase operation). it r eturns to high when the internal controlle r has finished the operation. t he pin is an open-drain driver the reby allowing two or more r/b # outputs to be or-tied. because t he pull-up resistor value is re lated to t r (r/b#) and the current drain dur ing busy (ibusy), and output load capacitance is related to t f an appropriate value can be obtained with the reference chart shown in figure 10 . for example, for a particular system with 20 pf of output load, t f from v cc to v ol at 10% to 90% will be 10 ns, whereas for a particular load of 50 pf, cypre ss measured it to be 20 ns as sh own in figure 10 . document number: 002-00676 rev. *v page 33 of 71 S34ML01G1 s34ml02g1 s34ml04g1 figure 10. ready/busy pin electrical application 4.3 write protect operation erase and program operations are aborted if wp# is driven low d uring busy time, and kept low for about 100 ns. switching wp# l ow during this time is equivalent to issuing a reset command (ffh) . the contents of memory cells being altered are no longer vali d, as the data will be partially programmed or erased. the r/b# pin w ill stay low for t rst (similarly to figure 33 on page 48 ). at the end of this time, the command register is ready to process the next co mmand, and the status r egister bit i/o6 will be cleared to 1, w hile i/o7 value will be related to the wp# value. refer to table 13 on page 22 for more information on device status. erase and program operations ar e enabled or disabled by setting wp# to high or low respective ly, prior to issu ing the setup commands (80h or 60h). the le vel of wp# shall be set t ww ns prior to raising the we# pin for the set up command, as exp lained in figure 47 and figure 48 on page 55 . figure 11. wp# low timing requirements during program/erase comm and sequence rp vs. t r , t f and rp vs. ibusy rp ibusy busy ready v cc v oh v ol v ol : 0.4v, v oh : 2.4v vcc gnd device open drain output r/b# c l 300n 200n 100n = t f (ns) 20 20 20 20 50 = t r (ns) 3m 2m 1m ibusy [a] t r ,t f [s] 1k 2k 3k 4k = ibusy ( ma ) 1.2 2.4 100 150 200 0.8 0.6 rp (ohm) @ vcc = 3.3v, ta = 25c, c l =50 pf rp value guidence rp (min.) = = vcc (max.) - v ol (max.) 3.2v 8ma + i l i ol + i l rp(max) is determined by maximum permissible limit of tr. where is the sum of the input currents of all devices tied to the r/b# pin. l i t f t r legend we# i/o[7:0] wp# valid > 100 ns sequence aborted document number: 002-00676 rev. *v page 34 of 71 S34ML01G1 s34ml02g1 s34ml04g1 5. electrical c haracteristics 5.1 valid blocks 5.2 absolute maximum ratings notes 25. except for the rating operating temperature range, stresse s above those listed in the table absolute maximum ratings absolute maximum ratings may cause permanent damage to the device. these are stress ratings only a nd operation of the device at these or any other conditions abo ve those indicated in the operating sections of this specification is not implied. exposure to abso lute maximum rating conditions for extended periods may affect device reliability. 26. minimum voltage may undershoot to -2v during transition and for less than 20 ns during transitions. 27. maximum voltage may overshoot to vcc+2.0v during transition and for less than 20 ns during transitions. 5.3 recommended operating conditions 5.4 ac test conditions table 17. valid blocks device symbol min typ max unit S34ML01G1 n vb 1004 1024 blocks s34ml02g1 n vb 2008 2048 blocks s34ml04g1 n vb 4016 4096 blocks table 5.1 absolute maximum ratings parameter symbol value unit ambient operating temperature (i ndustrial temperature range) t a -40 to +85 c temperature under bias t bias -50 to +125 c storage temperature t stg -65 to +150 c input or output voltage v io [26] -0.6 to +4.6 v supply voltage v cc -0.6 to +4.6 v table 18. recommended operating conditions parameter symbol min typ max units vcc supply voltage vcc 2.7 3.3 3.6 v ground supply voltage vss 0 0 0 v table 19. ac test conditions parameter value input pulse levels 0.0v to v cc input rise and fall times 5 ns input and output timing levels v cc / 2 output load (2.7v - 3.6v ) 1 ttl gate and cl = 50 pf document number: 002-00676 rev. *v page 35 of 71 S34ML01G1 s34ml02g1 s34ml04g1 5.5 ac characteristics notes 28. the time to ready depends on the value of the pull-up resist or tied to r/b# pin. 29. if reset command (ffh) is written at ready state, the device goes into busy for maximum 5 s. 30. ce# low to high or re# low to high can be at different times and produce three cases. depending on which signal comes high first, either t coh or t rhoh will be met. 31. during data output, t cea depends partly on t cr (ce# low to re# low). if t cr exceeds the minimum value specified, then the maximum time for t cea may also be exceeded (t cea = t cr + t rea ). table 20. ac characteristics parameter symbol min max unit ale to re# delay t ar 10 ns ale hold time t alh 5ns ale setup time t als 10 ns address to data loading time t adl 70 ns ce# low to re# low t cr 10 ns ce# hold time t ch 5ns ce# high to output high-z t chz 30ns cle hold time t clh 5ns cle to re# delay t clr 10 ns cle setup time t cls 10 ns ce# access time t cea [31] 25ns ce# high to output hold t coh [30] 15 ns ce# high to ale or cle don't care t csd 10 ns ce# setup time t cs 20 ns data hold time t dh 5ns data setup time t ds 10 ns data transfer from cell to register t r 25s output high-z to re# low t ir 0ns read cycle time t rc 25 ns re# access time t rea 20ns re# high hold time t reh 10 ns re# high to output hold t rhoh [30] 15 ns re# high to we# low t rhw 100 ns re# high to output high-z t rhz 100ns re# low to output hold t rloh 5ns re# pulse width t rp 12 ns ready to re# low t rr 20 ns device resetting time (read/program/erase) t rst 5/10/500 s we# high to busy t wb 100ns write cycle time t wc 25 ns we# high hold time t wh 10 ns we# high to re# low t whr 60 ns we# pulse width t wp 12 ns write protect time t ww 100 ns document number: 002-00676 rev. *v page 36 of 71 S34ML01G1 s34ml02g1 s34ml04g1 5.6 dc characteristics notes 32. all v cc pins, and v ss pins respectively, are shorted together. 33. values listed in this table refer to the complete voltage ra nge for v cc and to a single device in case of device stacking. 34. all current measurements are performed with a 0.1 f capacit or connected between the v cc supply voltage pin and the v ss ground pin. 35. standby current measurement can be performed after the devic e has completed the initialization process at power up. refer t o section 4.1 for more details. 5.7 pin capacitance note 36. for the stacked devices version the input is 10 pf x [number of stacked chips] and the input/output is 10 pf x [number of s tacked chips]. table 5.2 dc characteristics and operating conditions parameter symbol test conditions min typ max units power-on current (s34ml02g1, s34ml04g1) i cc0 power-up current (refer to section 4.1 ) 1530ma operating current sequential read i cc1 t rc = see table 20 ce#=v il , i out = 0 ma 1530ma program i cc2 normal ( S34ML01G1) 1530ma normal (s34ml02g1) 1530ma normal (s34ml04g1) 30ma cache (s34ml02g1) 2040ma cache (s34ml04g1) 40ma erase i cc3 (S34ML01G1) 1530ma (s34ml02g1) 30ma (s34ml04g1) 1530ma standby current, (ttl) i cc4 ce# = v ih , wp# = 0v/vcc 1ma standby current, (cmos) i cc5 ce# = v cc C0.2, wp# = 0/v cc 1050a input leakage current i li v in = 0 to 3.6v 10 a output leakage current i lo v out = 0 to 3.6v 10 a input high voltage v ih v cc x 0.8 v cc + 0.3 v input low voltage v il -0.3v cc x 0.2 v output high voltage v oh i oh = C400 a 2.4 v output low voltage v ol i ol = 2.1 ma 0.4 v output low current (r/b#) i ol(r/b#) v ol = 0.4v 8 10 ma erase and program lockout voltage v lko 1.8v table 21. pin capacitance (ta = 25c, f=1.0 mhz) parameter symbol test condition min max unit input c in v in = 0v 10 pf input / output c io v il = 0v 10 pf document number: 002-00676 rev. *v page 37 of 71 S34ML01G1 s34ml02g1 s34ml04g1 5.8 thermal resistance note 37. test conditions follow standard methods and procedures for m easuring thermal impedance in accordance with eia/jesd51. 5.9 program / erase characteristics notes 38. typical program time is defined as the time within which mor e than 50% of the whole pages are programmed (v cc = 3.3v, 25c). 39. copy back read and copy back program for a given plane must be between odd address pages or between even address pages for the device to meet the program time (t prog ) specification. copy back progr am may not meet this specificat ion when copying from an odd address page (source page) to an e ven address page (target page) or from an even address page (source page) to an odd addr ess page (target page). table 22. thermal resistance parameter symbol ts048 vbm063 vbt067 unit theta ja thermal resistance (junction to ambient) 40 39 39 c/w table 23. program / erase characteristics parameter description min typ max unit program time / multiplane program time [39] t prog 200 700 s dummy busy time for multiplane program ( s34ml02g1, s34ml04g1) t dbsy 0.5 1 s cache program short busy time ( s34ml02g1, s34ml04g1) t cbsyw 5t prog s number of partial program cycles i n the same page main + spare n op 4 cycle block erase time / multiplane erase time ( s34ml02g1, s34ml04g1) t bers 3.510ms block erase time ( S34ML01G1) t bers 2 3ms read cache busy time t cbsyr 3t r s document number: 002-00676 rev. *v page 38 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6. timing diagrams 6.1 command latch cycle command input bus ope ration is used to giv e a command to the me mory device. commands are accepted with chip enable low, command latch enable high, addre ss latch enable low, and read e nable high and latch ed on the rising edge of write enable. moreover for commands that start s a modify operation (write/ er ase) the write protec t pin must be high. figure 12. command latch cycle 6.2 address latch cycle address input bus operation allo ws the insertion of the memory address. to insert the 27 (8 d evice) addresses needed to acces s the 1 gb, four write cycles are needed. addresses are accepted with chip enable low, address latch enable high, command latch enable low, and read enable hi gh and latched on the rising edge of write enable. moreover, for c ommands that start a modify operation (write/ er ase) the write protec t pin must be high. figure 13. address latch cycle tcl s tcs twp command cle ce# we# ale i/ox tdh tds tals talh tclh tch = don?t care tcls tcs twc tals tals tals tals tals talh talh talh talh twc twc twc twp twp twh twp twp twh twh twh tds col. add1 cle ce# we# ale i/ox tds tds tds tds tdh tdh tdh tdh tdh col. add2 row. add2 row. add1 row. add3 talh = don?t care document number: 002-00676 rev. *v page 39 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6.3 data input cycle timing data input bus operation allows the data to be programmed to be sent to the device. the data i nsertion is serially, and timed by the write enable cycles. dat a is accepted on ly with chip enable low , address latch enable low, command latch enable low, read enable high, and write protect high and latched on the rising e dge of write enable. figure 14. input data latch cycle 6.4 data output cycle timing (c le=l, we#=h, ale=l, wp#=h) figure 15. data output cycle timing notes 40. transition is measured at 200 mv from steady state voltage with load. 41. this parameter is sampled and not 100% tested. 42. t rhoh starts to be valid when frequency is lower than 33 mhz. twc tclh tch twp twh din twh tdh tdh tdh tds tds tds twp twp cle ale ce# i/ox we# tals din 0 din final = don?t care trc ce# re# i/ox r/b# trea trr t u o d t u o d t u o d trea trhz trea tchz tcoh trhoh treh trhz document number: 002-00676 rev. *v page 40 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6.5 data output cycle timing (ed o type, cle=l, we#=h, ale=l) figure 16. data output cycle timing (edo) notes 43. transition is measured at 200 mv from steady state voltage with load. 44. this parameter is sampled and not 100% tested. 45. t rloh is valid when frequency is higher than 33 mhz. 46. t rhoh starts to be valid when frequency is lower than 33 mhz. 6.6 page read operation figure 6.1 page read operatio n (read one page) note 47. if status register polling is used to determine completion o f the read operation, the read command (00h) must be issued bef ore data can be read from the page buffer. trc trp treh trea tcr trloh trr trea tchz tcoh trhz trhoh dout dout ce# re# i/ox r/b# = don?t care ce# we# i/ox cle re# r/b# ale 00h col. add. 1 col. add. 2 row add. 1 row add. 2 row add. 3 30h dout n dout n +1 column address row address tcsd twb tclr tr trc trr busy tar dout m trhz twc = don?t care document number: 002-00676 rev. *v page 41 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6.7 page read operation (interrupted by ce#) figure 17. page read operation interrupted by ce# 6.8 page read operation timing with ce# dont care figure 18. page read operation timing with ce# dont care ce# we# i/ox cle re# r/b# ale 00h col. add. 1 col. add. 2 row add. 1 row add. 2 row add. 3 30h dout n dout n +1 column address row address tcsd twb tclr tr trc trr busy tar tchz tcoh dout n +2 = don?t care 00h col. add. 1 col. add. 2 row add. 1 row add. 2 dout n dout n + 1 : don?t care (v ih or v il ) ce# re# trea tcr ce# don?t care ce# cle ale we# re# i/ox 30h dout n + 2 dout n + 3 dout n + 4 dout n + 5 dout m dout m + 1 dout m + 2 r/b# tr trr trc i/ox dout row add. 3 document number: 002-00676 rev. *v page 42 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6.9 page program operation figure 6.2 page program operation note 48. t adl is the time from the we# rising edge of final address cycle to the we# rising edge of first data cycle. 6.10 page program operation timing with ce# dont care figure 19. page program operation timing with ce# dont care cle ale ce# re# r/b# i/ox we# twc serial data input command column address row address read status command program command i/o0=0 successful program i/o0=1 error in program 1 up to m byte serial input din n din m twc twb tprog twhr twc tadl 80h col. add1 col. add2 row. add1 row. add2 h 0 7 h 0 1 i/o0 row. add3 = don?t care 80h col. add. 1 col. add. 2 row add. 1 row add. 2 din n din n + 1 din m din p din p + 1 din r 10h : don?t care ce# we# twp tcs tch ce# don?t care ce# cle ale we# re# i/ox row add. 3 document number: 002-00676 rev. *v page 43 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6.11 page program operat ion with random data input figure 20. random data input notes 49. t adl is the time from the we# rising edge of final address cycle to the we# rising edge of first data cycle. 50. for edc operation only one random data input is allowed at e ach edc unit. 6.12 random data output in a page figure 21. random data output cle ale ce# re# r/b# i/ox we# 80h din n din m din j din k 85h 10h 70h serial data input command random data input command column address column address serial input program command read status command tprog io0 twb col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 tadl row address twc twc tadl twc twhr = don?t care ce# we# i/ox cle re# r/b# ale 00h col. add. 1 col. add. 2 row add. 1 row add. 2 row add. 3 30h dout n dout n +1 05h col. add. 1 col. add. 2 dout m dout m +1 e0h column address row address column address tclr twhr trea twb tar trhw tr trc trr busy = don?t care document number: 002-00676 rev. *v page 44 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6.13 multiplane page program opera tion s34ml02g1 and s34ml04g1 figure 22. multiplane page program notes 51. any command between 11h and 81h is prohibited except 70h, 78 h, and ffh. 52. a18 is the plane address bit for 8 devices. a17 is the plan e address bit for 16 devices. figure 23. multiplane page program (onfi 1.0 protocol) notes 53. c1a-c2a column address for page a. c1a is the least signific ant byte. 54. r1a-r3a row address for page a. r1a is the least significant byte. 55. d0a-dna data to program for page a. 56. c1b-c2b column address for page b. c1b is the least signific ant byte. 57. r1b-r3b row address for page b. r1b is the least significant byte. 58. d0b-dnb data to program for page b. 59. the block address bits must be the same except for the bit(s ) that select the plane. cle ale ce# re# r/b# i/ox we# r/b# i/o0~7 ex.) address restriction for multiplane page p rogram 81h 70h io program confirm command (true) tdbsy col add 1,2 and row add 1,2,3 (2112 byte data) a0 ~ a11: valid a12 ~ a17: fixed ?low? a18: fixed ?low? a19 ~ a28: fixed ?low? serial data input command column address page row address 1 up to 2112 byte data serial input program command (dummy) 11h 10h din n din m din n din m col. add1 80h col. add2 row add1 row add2 row add3 twb tprog twb tdbsy col. add1 col. add2 row add1 row add2 row add3 twc read staus command twhr tprog 80h address & data input 11h col add 1,2 and row add 1,2,3 (2112 byte data) a0 ~ a11: valid a12 ~ a17: valid a18: fixed ?high? a19 ~ a28: valid tadl tadl 81h address & data input 10h 70h (note 51) cmd addr addr addr addr addr cmd addr addr addr addr addr din din din din din din din din cmd cmd 80h c1 a c2 a d0 a r3 a r2 a r1 a d1 a ... dn a 11h 80h c1 b c2 b d0 b r3 b r2 b r1 b d1 b ... dn b 10h cycle type dqx sr[6] cycle type dqx sr[6] a tadl tadl tadl tipbsy tadl tprog document number: 002-00676 rev. *v page 45 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6.14 block erase operation figure 24. block erase operation (erase one block) 6.15 multiplane block erase s34ml02g1 and s34ml04g1 figure 25. multiplane block erase note 60. a18 is the plane address bit for 8 devices. a17 is the plan e address bit for 16 devices. twc cle ce# we# ale re# i/ox r/b# twb tbers busy auto block erase setup command i/o0=0 successful erase i/o0=1 error in erase row address d0h 60h 70h i/o0 erase command read status command row add1 row add2 row add3 twhr = don?t care row address block erase setup command1 block erase setup command2 erase confirm command read status command busy row address ex.) address restriction for multiplane block erase operation ale cle ce# re# r/b# i/ox we# r/b# i/o0~7 twc 60h 60h row add1,2,3 row add1,2,3 a12 ~ a17 : fixed low a18 : fixed low a19 ~ a28 : fixed low a12 ~ a17 : fixed low a18 : fixed high a19 ~ a28 : valid address address h 0 7 h 0 6 d0h h 0 d h 0 6 70h i/o0 row add1 row add1 row add2 row add2 3 d d a w o r 3 d d a w o r twc twb tbers tbers twhr i/o 1 = 0 successful erase i/o 1 = 1 error in plane document number: 002-00676 rev. *v page 46 of 71 S34ML01G1 s34ml02g1 s34ml04g1 figure 26. multiplane block erase (onfi 1.0 protocol) notes 61. r1a-r3a row address for block on plane 0. r1a is the least s ignificant byte. 62. r1b-r3b row address for block on plane 1. r1b is the least s ignificant byte. 63. the block address bits must be the same except for the bit(s ) that select the plane. 6.16 copy back read with optional data readout figure 27. copy back read with optional data readout 6.17 copy back program operat ion with random data input figure 28. copy back progra m with random data input 60h cle we# ale re# iox r1 a r2 a r3 a d1h 60h r1 b r2 b sr[6] t iebsy r3 b d0h t bers i/o r/b# busy tr (read busy time) busy tprog (program busy time) 00h source add inputs 35h data outputs 85h target add inputs 10h 70h/ 7bh sr0/ edc reg read status register/ edc register i/o r/b# busy tr (read busy time) busy tprog (program busy time) 00h source add inputs 35h 85h 2 cycle add inputs 10h unlimited number of repetitions 70h sr0 read status register 85h target add inputs data data document number: 002-00676 rev. *v page 47 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6.18 multiplane copy back progr am s34ml02g1 and s34ml04g1 figure 29. multiplane copy back program notes 64. copy back program operation is allowed only within the same memory plane. 65. any command between 11h and 81h is prohibited except 70h, 78 h, and ffh. 66. a18 is the plane address bit for 8 devices. a17 is the plan e address bit for 16 devices. figure 30. multiplane copy back program (onfi 1.0 protocol) note 67. c1a-c2a column address for page a. c1a is the least signific ant byte. 68. r1a-r3a row address for page a. r1a is the least significant byte. 69. c1b-c2b column address for page b. c1b is the least signific ant byte. 70. r1b-r3b row address for page b. r1b is the least significant byte. 71. the block address bits must be the same except for the bit(s ) that select the plane. i/ox r/b# r/b# i/ox tr tr tdbsy tprog 1 1 00h add. (5 cycles) 35h col. add. 1, 2 and row add. 1, 2, 3 source address on plane 0 00h add. (5 cycles) 35h col. add. 1, 2 and row add. 1, 2, 3 source address on plane 1 85h add. (5 cycles) 11h col. add. 1, 2 and row add. 1, 2, 3 destination address a0 ~ a11 : fixed ?low? a12 ~ a17 : fixed ?low? a18 : fixed ?low? a19 ~ a28 : fixed ?low? 81h add. (5 cycles) col. add. 1, 2 and row add. 1, 2, 3 destination address a0 ~ a11 : fixed ?low? a12 ~ a17 : valid a18 : fixed ?high? a19 ~ a28 : valid 10h 70h plane 0 (1) (3) data field spare field plane 1 (2) (3) data field spare field source page source page target page target page (1) : copy back read on plane 0 (2) : copy back read on plane 1 (3) : multiplane copy back program 1 r w h 85h cle we# ale re# iox c1 a c2 a r1 a r2 a r3 a 11h 85h c1 b c2 b sr[6] a t ipbsy r1 b r2 b r3 b 10h t prog document number: 002-00676 rev. *v page 48 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6.19 read status register timing figure 31. status / edc read cycle 6.20 read status enhanced timing figure 32. read status enhanced timing 6.21 reset operation timing figure 33. reset operation timing tcls t clr t clh t cs t ch t wp t whr t cea t ds t rea t chz t coh t rhz t rhoh 70h or 7bh status output t dh t ir ce# we# i/ox cle re# = don?t care cle ale we# i/o0-7 re# 78h r1 r2 sr r3 twhr tar ff t rst we# ale cle re# i/o7:0 r/b# document number: 002-00676 rev. *v page 49 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6.22 read cache figure 34. read cache operation timing figure 35. sequential read cache timing, start (and continuati on) of cache operation page n page n page n + 1 page n + 2 page n + 1 page n + 3 page n + 2 page n + 3 data cache page buffer cell array page n page n + 1 page n + 2 page n + 3 1 1 2 3 3 4 5 5 6 7 7 8 9 ce# cle ale we# re# i/ox r/b# ce# cle ale we# re# i/ox r/b# a a 1 2 3 7 8 9 6 00h col. add 1 col. add 2 column address 00h row add 1 row add 2 page address n 30h 31h dout 0 dout 1 dout 31h dout 0 dout 1 col. add. 0 page n + 2 3fh dout 0 dout 1 dout 31h dout 0 dout dout 1 dout twc twb tr tcbsyr twb trr twb col. add. 0 page n col. add. 0 page n + 1 trc trc trr tcbsyr tcbsyr twb trr trc tcbsyr twb trr trc col. add. 0 page n + 3 = don?t care row add 3 4 5 5 cmd cmd dout dout dout cmd dout 0 d h 0 3 31h ... dn 31h d0 cycle type i/ox sr[6] trr as defined for read trr twb tr twb tcbsyr twb tcbsyr document number: 002-00676 rev. *v page 50 of 71 S34ML01G1 s34ml02g1 s34ml04g1 figure 36. random read cache timing, start (and continuation) of cache operation figure 37. read cache timing, end of cache operation 6.23 cache program figure 38. cache program cycle type i/ox sr[6] cycle type i/ox sr[6] as defined for read a cmd addr addr addr addr twb tr a addr cmd 00h c1 c2 r1 r2 r3 31h cmd 30h dout dout dout d0 . . . dn page n page r cmd addr addr addr addr addr cmd 00h c1 c2 r1 r2 r3 31h dout d0 trr twb tcbsyr trr twb tcbsyr trr cycle type i/ox sr[6] as defined for read cache (sequential or random) dout dout dout cmd twb tcbsyr d0 . . . dn 3fh cmd 31h dout dout dout d0 . . . dn trr twb tcbsyr trr column address row address twb column address row address tcbsyw 1 1 cle ale ce# re# r/b# i/ox we# tcbsyw din n din m din n din m column address row address 10h din n din m 70h tprog 80h col. add1 col. add2 row. add1 row. add2 row. add3 15h 80h 15h 80h col. add1 col. add2 row. add1 row. add2 row. add3 tadl status twc col. add1 col. add2 row. add1 row. add2 row. add3 twc twc cle ale ce# re# r/b# i/ox we# document number: 002-00676 rev. *v page 51 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6.24 multiplane cache program s34ml02g1 and s34ml04g1 figure 39. multiplane cache program notes 72. read status register (70h) is used in the figure. read statu s enhanced (78h) can be also used. 73. a18 is the plane address bit for 8 devices. a17 is the plan e address bit for 16 devices. cle ale ce# re# r/b# i/ox we# column address row address twb twc column address row address tcbsyw 1 1 tdbsy 80h col. add1 col. add2 row add1 row add2 row add3 81h col. add1 col. add2 row add1 row add2 row add3 15h din n din m 11h din n din m column address row address twc column address row address tprog tdbsy 11h din n din m 80h 81h col. add1 col. add2 row add1 row add2 row add3 10h din n din m twb tadl tadl twb status 70h 80h address input data input 11h 81h address input data input 15h command input t dbsy return to 1 repeat a max of 63 times 80h address input data input 11h 81h address input data input 10h command input t dbsy t prog t cbsyw ry/by# ry/by# 1 1 cle ale ce# re# r/b# i/ox we# col. add1 col. add2 row add1 row add2 row add3 a0~a11: valid a12~a17: fixed ?low? a19~a28: fixed ?low? a18: fixed ?low? a0~a11: valid a18: fixed ?high? a19~a28: valid a12~a17: valid a0~a11: valid a18: fixed ?high? a19~a28: valid a12~a17: valid a0~a11: valid a18: fixed ?low? a19~a28: fixed ?low? a12~a17: fixed ?low? document number: 002-00676 rev. *v page 52 of 71 S34ML01G1 s34ml02g1 s34ml04g1 figure 40. multiplane cache program (onfi 1.0 protocol) notes 74. the block address bits must be the same except for the bit(s ) that select the plane. 75. read status register (70h) is used in the figure. read statu s enhanced (78h) can be also used. cle ale ce# re# r/b# iox we# column address row address twb twc column address row address tcbsyw 1 1 cle ale ce# re# r/b# iox we# tdbsy 11h din n din m 80h col. add1 col. add2 row add1 row add2 row add3 80h col. add1 col. add2 row add1 row add2 row add3 15h din n din m column address row address twc column address row address tprog tdbsy 11h din n din m 80h col. add1 col. add2 row add1 row add2 row add3 80h col. add1 col. add2 row add1 row add2 row add3 10h din n din m twb tadl tadl twb status 70h 80h address input data input 11h 80h address input data input 15h command input t dbsy return to 1 repeat a max of 63 times 80h address input data input 11h 80h address input data input 10h command input t dbsy t prog t cbsyw ry/by# ry/by# 1 1 document number: 002-00676 rev. *v page 53 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6.25 read id operation timing figure 41. read id operation timing 6.26 read id2 operation timing figure 42. read id2 operation timing notes 76. 4-cycle address is shown for the S34ML01G1. for s34ml02g1 an d s34ml04g1, insert an additional address cycle of 00h. 77. if status register polling is used to determine completion o f the read id2 operation, the read command (00h) must be issued before id2 data can be read from the flash. ce# we# cle re# ale twhr tar trea i/ox 01h f1h 00h 1dh 1 gb device i/ox 01h dah 90h 95h 2 gb device 44h i/ox 01h dch 90h 95h 4 gb device 54h read id command address 1 cycle maker code device code 3rd cycle 4th cycle 5th cycle 90h 90h 09h 00h 00h 00h ce# we# cle re# ale tr read id2 commands 4 cycle address 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle i/ox read id2 confirm command 30h 65h 00h 00h 02h 02h 00h 30h id2 data id2 data id2 data id2 data id2 data r/b# busy (note 76) document number: 002-00676 rev. *v page 54 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6.27 read onfi signature timing figure 43. onfi signature timing 6.28 read parameter page timing figure 44. read parameter page timing note 78. if status register polling is used to determine completion o f the read operation, the read command (00h) must be issued bef ore data can be read from the page buffer. 6.29 otp entry timing figure 45. otp entry timing 90h cle we# ale re# io0~7 20h 4fh t 4eh 46h whr 49h trea 00h cle we# ale re# io0-7 p1 r/b# ... ... t r 1 p0 1 p1 0 p0 0 ech cle ale we# i/o0-7 29h 17h 19h 04h document number: 002-00676 rev. *v page 55 of 71 S34ML01G1 s34ml02g1 s34ml04g1 6.30 power on and data protection timing figure 46. power on and data protection timing note 79. v th = 1.8 volts. 6.31 wp# handling figure 47. program enabling / disabling through wp# handling figure 48. erase enabling / dis abling through wp# handling vcc v vcc(min) 100 s max invalid 0v ce v il v operation 5 ms max ih v il wp ready/busy dont care dont care dont care vcc(min) v th th t 80h 10h ww we# i/ox wp# r/b# t 80h 10h ww we# i/ox wp# r/b# t 60h d0h ww t 60h d0h ww we# i/ox wp# r/b# we# wp# r/b# i/ox document number: 002-00676 rev. *v page 56 of 71 S34ML01G1 s34ml02g1 s34ml04g1 7. physical interface 7.1 physical diagram 7.1.1 48-pin thin small outline package (tsop1) figure 49. ts/tsr 48 48-lead pl astic thin small outline, 12 x 20 mm, package outline 5006 \ f16-038 \ 6.5.13 package ts/tsr 48 jedec mo-142 (d) dd symbol min nom max a --- --- 1.20 a1 0.05 --- 0.15 a2 0.95 1.00 1.05 b1 0.17 0.20 0.23 b 0.17 0.22 0.27 c1 0.10 --- 0.16 c 0.10 --- 0.21 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 e 11.90 12.00 12.10 e 0.50 basic l 0.50 0.60 0.70 o 0? --- 8 r 0.08 --- 0.20 n48 notes: 1. dimensions are in millimeters (mm). (dimensioning and tolerancing conform to ansi y14.5m-1994). 2. pin 1 identifier for standard pin out (die up). 3. pin 1 identifier for reverse pin out (die down): ink or laser mark. 4. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 5. dimensions d1 and e do not include mold protrusion. allowable mold protrusion on e is 0.15mm per side and on d1 is 0.25mm per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of b dimension at max. material condition. dambar cannot be located on lower radius or the foot. minimum space between protrusion and an adjacent lead to be 0.07mm. 7. these dimensions apply to the flat section of the lead between 0.10mm and 0.25mm from the lead tip. 8. lead coplanarity shall be within 0.10mm as measured from the seating plane. 9. dimension "e" is measured at the centerline of the leads. document number: 002-00676 rev. *v page 57 of 71 S34ML01G1 s34ml02g1 s34ml04g1 7.1.2 63-pin ball grid array (bga) figure 50. vbm063 63-pin bga, 11 mm x 9 mm package g5011\ 16-038.25 \ 6.5.13 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 3, spp-020. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the total number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0. when there is an even number of solder balls in the outer row, sd = ed/2 and se = ee/2. 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbm 063 jedec m0-207(m) 11.00 mm x 9.00 mm nom package symbol min nom max note a --- --- 1.00 profile a1 0.25 --- --- ball height d 11.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 63 ball count b 0.40 0.45 0.50 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc. ball pitch sd 0.40 bsc. solder ball placement se 0.40 bsc. solder ball placement a3-a8,b2-b8,c1,c2,c9,c10 depopulated solder balls d1,d2,d9,d10,e1,e2,e9,e10 f1,f2,f9,f10,g1,g2,g9,g10 h1,h2,h9,h10,j1,j2,j9,j10 k1,k2,k9,k10 l3-l8,m3-m8 document number: 002-00676 rev. *v page 58 of 71 S34ML01G1 s34ml02g1 s34ml04g1 8. system interface to simplify system interface, ce# may be unasse rted during data loading or sequential data reading as shown in figure 51 . by operating in this way, it is po ssible to connect nand flash to a microprocessor. figure 51. program operat ion with ce# don't care figure 52. read operation with ce# don't care figure 53. page programming within a block ce# don?t care h 0 1 t u p n i a t a d (5 cycle) . d d a t r a t s h 0 8 data input cle ce# we# ale i/ox ce# don?t care h 0 3 h 0 0 cle ce# re# ale r/b# we# i/ox ) l a i t n e u q e s ( t u p t u o a t a d (5 cycle) . d d a t r a t s tr page 63 page 31 page 2 page 1 page 0 page 63 page 31 page 2 page 1 page 0 (64) (32) (3) (2) (1) (64) (1) (3) (32) (1) data register data register from the lsb page to msb page data in : data (1) data (64) ex.) random page program (optional) data in : data (1) data (64) document number: 002-00676 rev. *v page 59 of 71 S34ML01G1 s34ml02g1 s34ml04g1 9. error management 9.1 system bad block replacement over the lifetime of the device, additiona l bad blocks may deve lop. in this case, eac h bad block has to be replaced by copying any valid data to a new block. these additional bad blocks can be i dentified whenever a program or erase operation reports fail in the status register. the failure of a page program operation does not affect the dat a in other pages in the same block, thus the block can be repla ced by re-programming the current data an d copying the rest of the rep laced block to an available valid block. refer to table 24 and figure 54 for the recommended procedure to follow if an error occurs dur ing an operation. figure 54. bad block replacement notes 80. an error occurs on the nth page of block a during a program operation. 81. data in block a is copied to the same location in block b, w hich is a valid block. 82. the nth page of block a, which is in controller buffer memor y, is copied into the nth page of block b. 83. bad block table should be updated to prevent from erasing or programming block a. table 24. block failure operation recommended procedure erase block replacement program block replacement read ecc (1 bit / 512+16 byte) data buffer memory of the controller n page ffh data ffh failure th n page th block a block b [80 [81 [82 document number: 002-00676 rev. *v page 60 of 71 S34ML01G1 s34ml02g1 s34ml04g1 9.2 bad block management devices with bad blo cks have the same qualit y level and the sam e ac and dc characteristics as d evices where all the blocks are valid. a bad block does not aff ect the performance of valid blo cks because it is isolated from the bit line and common source line by a select transistor. the devices are supplied with all the loca tions inside valid blocks erased (ffh). the bad block informati on is written prior to shipping. any block where the 1st byte in the spare area of the 1st or 2nd or last page does not contain ffh is a bad block. that is, if the first pa ge has an ff value and should ha ve been a non-ff value, then the non-ff value in the second pag e or the last page will ind icate a bad block.th e bad block informati on must be read before any erase i s attempted, as the bad block information may be erased. for the system t o be able to recogni ze the bad blocks based on the original info rmation, it is recommended to create a bad block table following the flowchart shown in figure 55 . the host is responsible to detect and track bad blocks, both factory bad b locks and blocks that may go bad during operation. once a block is found to be bad , data should not be written to that block.the 1s t block, which is placed on 00h block address is guaranteed to be a valid block. figure 55. bad block management flowchart note 84. check for ffh at the 1st byte in the spare area of the 1st, 2nd, and last pages. yes yes no no start block address= block 0 data =ffh? last block? end increment block address update bad block table [84] document number: 002-00676 rev. *v page 61 of 71 S34ML01G1 s34ml02g1 s34ml04g1 10. ordering information the ordering part number is form ed by a valid combination of th e following: valid combinations valid combinations list configur ations planned to be supported in volume for th is device. consult your l ocal sales office to c onfirm availability of specific valid c ombinations and to check on new ly released combinations. notes 85. bga package marking omits the leading s34 and the packing type designator from the ordering part number. 86. a, v, b: 4g 16 (04 in bus width) available, but for other 16 versions contact factory. s34ml 04g 1 00 t f i 00 0 packing type 0 = tray 3 = 13 tape and reel model number 00 = standard interface / onfi (8) 00 = standard interface (16) 01 = onfi (16) temperature range i = industrial (C40c to + 85c) a = industrial with aecq-100 and gt grade (-40?c to +85?c) v = industrial plus (C40c to + 105c) b = industrial plus with aecq-100 and gt grade (-40?c to +105?c ) materials set f = lead (pb)-free h = lead (pb)-free and low halogen package b = bga t = tsop bus width 00 = 8 nand, single die 04 = 16 nand, single die technology 1 = cypress nand revision 1 (4x nm) density 01g = 1 gb 02g = 2 gb 04g = 4 gb device family s34ml - 3v cypress slc nand flash memory for embedded valid combinations device family density technology bus width package type temperature range additional ordering options packing type package description s34ml 01g 1 00, 04 tf, bh i a, v, b [86] 00, 01 0, 3 tsop, bga [85] 02g 04g document number: 002-00676 rev. *v page 62 of 71 S34ML01G1 s34ml02g1 s34ml04g1 11. document history page document title: S34ML01G1/s34ml 02g1/s34ml04g1, 1 gb/2 gb/4 gb, 3 v, slc nand flash for embedded document number: 002-00676 rev. ecn no. orig. of change submission date description of change ** C xila 04/16/2012 initial release *a C xila 05/04/2012 global: removed spansion confidential designation read status enhanced: updated text command set: updated table: command set read id: updated table: read id for supported configurations legacy read id: removed section heading: legacy read id valid blocks: updated table: valid blocks *b C xila 05/23/2012 global: changed cache read to read cache general description: updated text block diagram: combined three block diagrams into one addressing: updated address cycle map tables mode selection: updated table: busy ti me in read; updated note command set: updated table added supported in S34ML01G1 column copy back program: updated text multiplane copy back program: updated text special read for copy back: updated text read edc status register: updated text read id: read id byte 4 description s3 4ml01g1 table: changed number of i/o to spare area size (byte / 512 byte) absolute maximum ratings: updated input or output vol tage and supply voltage rows program / erase characteristics: updated table *c C xila 05/24/2012 performance: updated performance section read id: updated read id for suppor ted configurations table modified tables: read id byte 3 description, read id byte 4 des cription C S34ML01G1, read id byte 4 descr iption C s34ml02g1 and s34ml04g1 , read id byte 5 description C s34ml02g1 a nd s34ml04g1 ac test conditions: updated table document number: 002-00676 rev. *v page 63 of 71 S34ML01G1 s34ml02g1 s34ml04g1 d ila 05/31/2012 global: data sheet designation updated fr om advance information to prel iminary distinctive characteristics/performance: updated distinctive characteristics and performance section pin description: updated pin description table addressing: updated address cycle ma p 1 gb device table updated address cycle ma p 2 gb device table updated address cycle ma p 4 gb device table command set: updated command set table e ila 07/13/2012 performance: corrected page read/program - sequential access: from 25ns (max ) to 25 ns (min) connection diagram: corrected figure: 48-pin tsop1 contact x8 device mode selection: mode selection table: corrected busy time in read, we# from hig h to corrected notes command set: command set table: added onfi, ex tended read status, and read i d2 commands note that all onfi information is in the advanced information d esignation copy back program: updated section multiplane copy back program s34ml02g1 and s34ml04g1: updated section read id2: added section read onfi signature: added section note that all onfi information is in the advanced information d esignation read parameter page: added section note that all onfi information is in the advanced information d esignation one-time programmable (otp) entry: added section note that all onfi information is in the advanced information d esignation program/erase characteristics: added note to table timing diagrams: rearranged section added timing diagrams: multiplane block erase (onfi 1.0 protoco l), multiplane cache program (onfi 1 .0 protocol), read id2 operation timing, o nfi signature timing, read parameter page timing, read id2 operatio n timing, otp entry timing updated timing diagrams: page read operation (read one page), p age read operation intercepted by ce#, p age read operatio n timing with c e# dont care, page program operation, page program operation timing wit h ce# dont care, random d ata input, random data output, multiplane p age program, block erase operation (erase one block), reset operati on timing, read cache operation timing, ca che program, multiplane cache pr ogram, read id operation timing note that all onfi information is in the advanced information d esignation 11. document history page (continued) document title: S34ML01G1/s34ml 02g1/s34ml04g1, 1 gb/2 gb/4 gb, 3 v, slc nand flash for embedded document number: 002-00676 rev. ecn no. orig. of change submission date description of change document number: 002-00676 rev. *v page 64 of 71 S34ML01G1 s34ml02g1 s34ml04g1 f ila 07/23/2012 command set: command set table: changed read onfi signature to es for sup ported on S34ML01G1 read parameter page: parameter page description ta ble: changed byte 254-255 values valid blocks: valid blocks table: remov ed note 1 and note 3 dc characteristics: dc characteristics and oper ating conditions table: corrected output low voltage test conditions corrected output low current (r/b#) typ and max values g ila 08/02/2012 global: note that all onfi information is now in the preliminary design ation read parameter page: parameter page description table: updated values for bytes 6-7, 108-109, 254- 255 physical interface: added tsop (2 ce 8 gb) diagram added bga diagram ordering information: updated data appendix a: added errata h ila 08/29/2012 global: removed 8 gb data added x16 i/o bus width data i ila 09/06/2012 connection diagram: 48-pin tsop1 contact x8, x16 de vices figure: corrected pinouts 63-vfbga contact, x16 device (ba lls down, top view) figure: cor rected pinouts, removed note command set: reorganized section ac characteristics: corrected tals min and tds min 11. document history page (continued) document title: S34ML01G1/s34ml 02g1/s34ml04g1, 1 gb/2 gb/4 gb, 3 v, slc nand flash for embedded document number: 002-00676 rev. ecn no. orig. of change submission date description of change document number: 002-00676 rev. *v page 65 of 71 S34ML01G1 s34ml02g1 s34ml04g1 ila 10/01/2012 addressing address cycle map -1 gb device: corr ected data address cycle map -2 gb device: corr ected data address cycle map -4 gb device: corr ected data multiplane program -s34m l02g1 and s34ml04g: added text block erase added text multiplane block erase -s 34ml02g1 and s34ml04g1: added text copy back program: added text multiplane copy back program s34ml02g1 and s34ml04g: added text multiplane cache program s34ml02g1 and s34ml04g1: added text read parameter page: parameter page description table: corrected electrical parameters block values for bytes 129-130 and bytes 131- 132 corrected vendor block va lues for bytes 254-255 multiplane page program opera tion s34ml02g1 and s34ml04g1: added note to multiplane page program figure added note to multiplane page program (onfi 1.0 protocol) figur e multiplane block erase s34ml02g1 and s34ml04g1: added note to multiplane block erase figure updated note to multiplane block erase (onfi 1.0 protocol) figu re multiplane copy back program s34ml02g1 and s34ml04g1: added note to multiplane copy back program figure multiplane copy back program (onf i 1.0 protocol) figure: correc ted iox values updated note multiplane cache program s34ml02g1 and s34ml04g1: added note to multiplane cache program figure multiplane cache program (o nfi 1.0 protoc ol) figure: removed address values from r/b# changed iox value from f1h to 70h updated note ac characteristics: ac characteristics table: added ce# access time ila 11/02/2012 global: data sheet designation updated fr om preliminary to full product ion absolute maximum ratings: added note ordering information: valid combinations table: added to additional ordering options 11. document history page (continued) document title: S34ML01G1/s34ml 02g1/s34ml04g1, 1 gb/2 gb/4 gb, 3 v, slc nand flash for embedded document number: 002-00676 rev. ecn no. orig. of change submission date description of change document number: 002-00676 rev. *v page 66 of 71 S34ML01G1 s34ml02g1 s34ml04g1 l ila 12/19/2012 command set: added page reprogram command changed readid2 to be s upported on S34ML01G1 page reprogram: moved section added paragraph copy back program: added paragraph reset: updated paragraph readid2: updated paragraph read parameter page: parameter page description table: fixed values of by tes 6-7 and 254-255 fixed description of by tes 129-130 and 131-132 dc characteristics: dc characteristics and oper ating conditions table: power-on reset current ( S34ML01G1): removed row operating current: removed icc1 : trc = trc (min) icc2: removed cache (S34ML01G1) input leakage current: removed vin = 0 to vcc (max) output leakage current: re moved vout = 0 to vcc (max) output high voltage: removed ioh = -100 a, ioh = 100 a, and i oh = 400 a rows output low voltage: rem oved iol = -100 a row output low current (r/b# ): removed vol = 0.1v row ac characteristics: ac characteristics table: added note page read operation: page read operation (read one page) figur e: added note read id2 operation timing: read id2 operation timing figure: replaced twhr with tr and added r/b# timing signal added note bad block management: added text bad block management flowchart: updated note 11. document history page (continued) document title: S34ML01G1/s34ml 02g1/s34ml04g1, 1 gb/2 gb/4 gb, 3 v, slc nand flash for embedded document number: 002-00676 rev. ecn no. orig. of change submission date description of change document number: 002-00676 rev. *v page 67 of 71 S34ML01G1 s34ml02g1 s34ml04g1 m ila 02/28/2013 command set: command set table: removed nth page entries page program: added paragraph multiplane program s34ml02g1 and s34ml04g1: added paragraph page reprogram s34ml02g1 a nd s34ml04g1: added paragraph block erase: added paragraph multiplane block erase s34ml02g1 and s34ml04g1: added paragraph copy back program: added paragraph multiplane copy back program s34ml02g1 and s34ml04g1: added paragraph cache program s34ml02g1 a nd s34ml04g: added paragraph multiplane cache program s34ml02g1 and s34ml04g1 added paragraph read parameter page: added paragraph electrical characteristics: valid blocks table: updated table ac characteristics: ac characteristics table: corrected min value for tcls and max value for tcea read status cycle timing: status / edc read cycle figure: removed note n ila 03/07/2013 ready/busy: updated section corrected ready/busy pin electrical application figure 11. document history page (continued) document title: S34ML01G1/s34ml 02g1/s34ml04g1, 1 gb/2 gb/4 gb, 3 v, slc nand flash for embedded document number: 002-00676 rev. ecn no. orig. of change submission date description of change document number: 002-00676 rev. *v page 68 of 71 S34ML01G1 s34ml02g1 s34ml04g1 o ila 08/09/2013 distinctive characteristics: security -removed serial number (unique id) operating temperature: removed commercial and extended temperat ures performance: updated reliability general description: updated section removed bullet: serial number (unique identifier) addressing: appended note in all address cycle map tables added text to bus cycl e column in all addr ess cycle map tables mode selection: updated mode selection table command set: command set table: updated acceptable command during busy column changed status of cache program ( end) and cache pr ogram (start) / (continue) to suppo rted on S34ML01G1 page read: updated section page program: changed sentence in addition, pa ges must be sequentially progr ammed within a block. to pages may be progra mmed in any order within a blo ck. multiplane program s34ml02g1 and s34ml04g1: changed sentence in addition, pages must be programmed sequent ially within a block. to pages may be progra mmed in any order within a blo ck. page reprogram s34ml02g1 and s34ml04g1: corrected page reprogram figure corrected page reprogram with data manipulation figure copy back program: updated section read status enhanced s34ml02g1 and s34ml04g1: updated section read status register field definition: updated status register coding table cache program: removed s34ml02g1 and s34ml04g1 from heading read id: read id bytes: updated description read parameter page: parameter page description table: corrected values for bytes 8- 9 and 254-255 absolute maximum ratings: updated absolute maximum ratings table multiplane page program opera tion s34ml02g1 and s34ml04g1: updated multiplane p age program figure updated multiplane page pro gram (onfi 1.0 protocol) copy back read with optional data readout: corrected copy back read with optional data readout figure copy back program operati on with random data input: updated copy back program operat ion with random data input figu re read status register timing: removed read status enhanced cycle figure read status enhanced timing: removed read status timing figure 11. document history page (continued) document title: S34ML01G1/s34ml 02g1/s34ml04g1, 1 gb/2 gb/4 gb, 3 v, slc nand flash for embedded document number: 002-00676 rev. ecn no. orig. of change submission date description of change document number: 002-00676 rev. *v page 69 of 71 S34ML01G1 s34ml02g1 s34ml04g1 o (contd) ila 08/09/2013 read cache: updated read cache operation timing figure removed cache timing heading cache program: updated cache program figure multiplane cache program s34ml02g1 and s34ml04g1: updated multiplane cache program figure updated multiplane cache progra m (onfi 1.0 protocol) figure read parameter page timing: added note to read par ameter page timing figure one-time programmable (otp) entry: added note stating that the otp feature in the S34ML01G1 does n ot have non- volatile protection electrical characteristics: absolute maximum ratings table: removed ambient operating tempe rature (commercial temperature range) and ambient operating temperatur e (extended temperature range) physical interface: updated figures: ts/tsr 48 48-lead plastic thin small outline, 12 x 20 mm, pac kage outline vbm063 63-pin bga, 11 mm x 9 mm package system interface: updated read operation wit h ce# don't care figure ordering information: updated materials set: h = low halogen to h = lead (pb)-free an d low halogen added note to valid combinations table p ila 02/10/2014 distinctive characteristics: operating temperature: added automotive read id: updated section ordering information: temperature range: added a, v, b valid combinations: temperature range: added a, v, b 4963050 ila 11/02/2015 updated to cypress template. r 5160512 ila 04/25/2016 updated command set : updated read parameter page : updated description. updated electrical characteristics : added recommended operating conditions . updated dc characteristics : replaced vcc supply voltage (erase and program lockout) with erase and program lockout voltage in para meter column co rresponding to v lo . updated ordering information : updated details under temperature range. updated to new template. s 5409174 ila 08/30/2016 updated performance : updated details under reliability. t 5738855 gn 05/16/2017 updated the cypress logo a nd copyright information. 11. document history page (continued) document title: S34ML01G1/s34ml 02g1/s34ml04g1, 1 gb/2 gb/4 gb, 3 v, slc nand flash for embedded document number: 002-00676 rev. ecn no. orig. of change submission date description of change document number: 002-00676 rev. *v page 70 of 71 S34ML01G1 s34ml02g1 s34ml04g1 u 5995650 mnad 12/21/2017 updated electrical characteristics : added thermal resistance . updated timing diagrams : updated multiplane cache program s34ml02g1 and s34ml04g1 : updated figure 39 on page 51 . updated to new template. v 6104589 mnad 03/20/2018 no technical updates. completing sunset review. 11. document history page (continued) document title: S34ML01G1/s34ml 02g1/s34ml04g1, 1 gb/2 gb/4 gb, 3 v, slc nand flash for embedded document number: 002-00676 rev. ecn no. orig. of change submission date description of change document number: 002-00676 rev. * v revised march 20, 2018 page 7 1 of 71 ? cypress semiconductor corporation, 2012-2018. this document i s the property of cypress semiconductor corporation and its sub sidiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in th is document ("software"), is owned by cypress under the intelle ctual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and trea ties and does not, except as spec ifically stated in this paragr aph, grant any license under its patents, copyrights, trademark s, or other intellectual property rights. if the software is not accompani ed by a license agreement and you do not otherwise have a writt en agreement with cypress governing the use of the software, th en cypress hereby grants you a personal, non-exclusive, nontransferable li cense (without the right to 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and test the functionality and safety of any application ma de of this information and any resulting product. cypress products are not designed, intended, or authorized for use as critical componen ts in systems designed or intended for the operation of weapons , weapons systems, nuclear installations, life-support devices or systems , other medical devices or system s (including resuscitation equ ipment and surgical implants), pollution control or hazardous s ubstances management, or other uses where the failure of the device or sy stem could cause personal injury, death, or property damage ("u nintended uses"). a critical component is any component of a de vice or system whose failure to perform can be reasonably expected t o cause the failure of the device or system, or to affect its s afety or effectiveness. cypress is not liable, in whole or in p art, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended 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