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thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 1 / 19 thine electronics, inc. security e thc63lvd 827- q low power / small package / 24bit color lvds transmitter general description the thc63lvd827 - q transmitter is designed to support pixel data transmission between host and flat panel display and dual link transmission between host and flat pa nel display up to 1080p/1920x1 20 0 resolutions. the thc63lvd827 - q converts 27bits (rgb 8 bits + hsync, vsync, de) of cmos/ttl data into lvds (low voltage differential signaling) data stream. the transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. for dual lvds out, lvds clock frequency of 87mhz, 51bits of rgb data are transmitted at an effective rate of 609mbps per lvds channel. for single lvds out, lvds clock frequency of 174mhz, 27bits of rgb data are transmitted at an effective rate of 1218mbps per lvds chann el. 21bits (rgb 6 bits + hsync, vsync, de) mode is also selectable for 6bit color transmission with lower power. features ? low power 1.8v cmos design ? 7mm x 7mm/72pin/0.65mm pitch/tfbga package applicable to non - hdi pcb. ? wide dot clock range, 10 - 1 74mhz, suited for tv signal: up to 1080p(74.25mhz dual) pc signal: up to 1920x1 200( 77 mhz dual) ? supports 1.8v single power supply ? 1.8v/2.5v/3.3v ttl/cmos inputs are supported by setting iovcc=1.8v/2.5v/3.3v ? lvds swing reducible by rs - pin to reduce both emi and power consumption ? pll requires no external components ? flexible input / output mode 1. single in / dual lvds out 2. single in / single lvds out 3. double edge single in / dual lvds out ? 2 lvds data m apping to simplify pcb layout ? power down mode ? input clock triggering edge selectable by r/f pin ? 6bit / 8bit modes selectable by 6b/8b pin ? aec - q100 grade 2 ( - 40 to 105degc ) block diagram figure 1. r17~r10 g17~g10 b17~b10 clkin
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 2 / 19 thine electronics, inc. security e pin diagram (top view) figure 2.
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 3 / 19 thine electronics, inc. security e pin description table 1 . pin description pin name pin # type description ta1 + ,ta1 - a1,b1 lvds out the 1st link. the 1st pixel output data when dual out. output data when single out. tb1 + ,tb1 - a2,b2 tc1 + ,tc1 - a3,b3 td1 + , td1 - a5,b5 tclk1+, tclk1 - a4,b4 lvds clock out for 1st link. ta2 + ,ta2 - a6,b6 the 2nd link. the 2nd pixel output data when dual out. tb2 + ,tb2 - a7,b7 tc2 + ,tc2 - a8,b8 td2 + , td2 - c9,c8 tclk2+, tclk2 - a9,b9 lvds clock out for 2nd link. r17~r10 g1,g2,f1,f2 e1,e2,d1,d2 in pixel data inputs. g17~g10 j4,h4,j3,h3 j2,h2,j1,h1 b17~b10 j8,h8,j7,h7 j6,h6,j5,h5 de g9 in data enable input. vsync h9 in vsync input. hsync j9 in hsync input. clkin f9 in clock input. r/f g8 in i nput clock triggering edge select. h: rising edge, l: falling edge rs f8 in lvds swing mode select . rs lvds swing(v od , see fig .7 and fig .8 ) h 350mv l 200mv map e8 in lvds mapping table select. see fig .12 and fig. 13. map mapping mode h mapping mode1 l mapping mode2 mode e7 in pixel data mode. see fig .10 and fig. 11. mode modes h single out (single - in / single - out) l dual out (single - in / dual - out) o / e d9 in output enable h: output enable. l: output disable (all outputs are hi - z). /pdwn d8 in power down enable h: normal operation. l: power down (all outputs are hi - z and all circuits are stand - by mode with minimum current (i tccs )). prbs (*a) c1 in must be tied to gnd.
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 4 / 19 thine electronics, inc. security e pin d e scription (continued) pin name pin # type description reserved1 c3 in must be tied to gnd. 6b/8b f7 in 6bit / 8bit mode select. h: 6bit mode (21bit mode), l: 8bit mode (27bit mode). ddrn e9 in ddr function is active when mode=l (dual - out mode) h: ddr (double edge input) function disable (fig .7 ). l: ddr (double edge input) function enable (fig .8 ). n/c c2 - must be open. vcc g3,g5 power power supply pins for digital circuitry. iovcc g7 power supply pins for io inputs circuitry. lvdsvcc c5,d3 power supply pins for lvds outputs. pllvcc c7 power supply pins for pll circuitry. gnd f3,g4,g6,c4, e3,c6,d7 ground ground p ins . (* a ) : setting the prbs pin high enables the internal test pattern generator. it generates pseudo - random bit sequence of 2 23 - 1. the generated prbs is fed into input data latches, encoded and serialized into lvds out. this function is normally to be used for anal yzing the signal integrity of the transmission channel including pcb traces, connectors, and cables.
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 5 / 19 thine electronics, inc. security e absolute maximum ratings table 2 . absolute maximum rating parameter min max unit power supply voltage (iovcc) - 0.3 +4.0 v power supply voltage (vcc,pllvcc,lvdsvcc) - 0.3 +2.1 v cmos/ttl input voltage - 0.3 iovcc+0.3 v lv d s transmitter out put voltage - 0.3 lvdsvcc+0.3 v output current - 50 +50 ma junction temperature - + 125 c storage temperature range - 55 + 125 c reflow peak temperature / time - + 260 / 10sec c maximum power dissipation @+25 c - 1.3 w recommended operating conditions table 3 . operating condition symbol parameter min typ max unit ta operating ambient temperature - 40 25 + 105 c iovcc power supply voltage 1.62 1.8 2.5 3.3 3.6 v pllvcc lvdsvcc vcc power supply voltage 1.62 1.8 1.98 v f clk clock frequency mode = l dual - out single edge input (ddrn=h) input 20 - 174 mhz lvds output 10 - 87 double edge input (ddrn=l) input 10 - 174 lvds output 10 - 174 mode=h single - out input 10 - 174 lvds output 10 - 174
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 6 / 19 thine electronics, inc. security e electrical characteristics cmos/ttl (pin type ? in ? ) dc specifications over recommended operating supply and temperature ranges unless otherwise specified. table 4 . cmos/ttl dc specifications symbol parameter conditions min typ max unit v ih18 high level data input voltage iovcc=1.62v~1.98v 0.65*iovcc - iovcc v v i l 18 low level data input voltage gnd - 0.35*iovcc v v ih25 high level data input voltage iovcc= 2.3 v~ 2.7 v 1.7 - iovcc v v il25 low level data input voltage gnd - 0.7 v v ih33 high level data input voltage iovcc= 3.0 v~ 3.6 v 2.0 - iovcc v v il33 low level data input voltage gnd - 0.8 v i in c input current vin=gnd~iovcc -10 - +10 a lvds transmitter (pin type ? lvds out ?) dc specifications over recommended operating supply and temperature ranges unless otherwise specified. table 5 . lvds transmitter dc specifications symbol parameter conditions min typ max unit v od differential out put voltage r l = 100 ? normal swing rs=h 250 350 450 m v reduced swing rs=l 140 200 300 ? v od change in v od between complementary output states r l = 100 ? - - 35 v oc common mode voltage 1.125 1.25 1.375 v ? v oc change in v o c between complementary output states - - 35 mv i os output short circuit current v out =gnd, r l = 100 ? - - 100 ma i oz output tri - state current /pdwn=l , v out = gnd ~ lvdsvcc -2 0 - + 2 0 a
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 7 / 19 thine electronics, inc. security e electrical characteristics (continued) power supply current over recommended operating supply and temperature ranges unless otherwise specified. table 6. power supply current symbol parameter conditions typ. max unit i tccw operating current r l =100 ? cl=5pf rs= h (rs=l) mode = h single - out clkin= 37 mhz 24 (18) 33 (26) ma clkin=65mhz 29 (23) 43 (37) clkin= 72 mhz 30 (24) 46 (40) mode = l dual - out ddrn = h ddr input off clkin= 89 mhz 48 (36) 65 (53) clkin= 119 mhz 53 (41) 75 (63) clkin= 139 mhz 56 (44) 82 (70) clkin= 154 mhz 58 (46) 88 (76) mode = l dual - out ddrn = l ddr input on clkin= 44.5 mhz 47 (35) 64 (52) clkin= 59 .5mhz 51 (39) 74 (62) clkin= 69 mhz 54 (42) 80 (68) clkin=77mhz 56 (44) 85 (73) i tc cs power down current /pdwn = l, all inputs = fixed l or h 1 140 a (a) all typ. values are at v cc =1.8v, ta=25 c . the 256 grayscale test pattern inputs test for a typical display pattern. (b) all max. values are at v cc =1.98v, ta= 105c . worst case test pattern produces maximum switching frequency for all the lvds outputs (fig. 3 ). figure 3 . test pattern (lvds output full toggle pattern)
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 8 / 19 thine electronics, inc. security e switching characteristics over recommended operating supply and temperature ranges unless otherwise specified. table 7 . switching characteristics symbol parameter min typ max unit t tcip clkin period (fig.7,8) 5.75 - 100 ns t tch clkin high time (fig.7,8) 0.35t tc ip 0.5t tc ip 0.65t tc ip ns t tcl clkin low time (fig.7,8) 0.35t tc ip 0.5t tc ip 0.65t tc ip ns t ts ttl data setup to clk in (fig.7,8) 0.8 - - ns t th ttl data hold to clk in (fig.7,8) 0.8 - - ns t tcd clkin to tclk+/ - delay (fig7,8) mode=l,ddr n =h 9t tc ip +3.1 - 9t tc ip +8 . 0 ns others 5t tc ip +3.1 - 5t tc ip +8 . 0 ns t t cop tclk1,2 period (fig.6) 5.75 - 100 ns t lvt lvds transition t i me (fig.4) - 0.6 1.5 ns t t op1 output data position0 (fig.9) t tcop =5.75ns~15ns - 0.15 0.0 +0.15 ns t t op0 output data position1 (fig.9) t tcop 7 - 0.15 t tcop 7 t tcop 7 +0.15 ns t t op6 output data position2 (fig.9) 2 t tcop 7 2 t tcop 7 2 t tcop 7 +0.15 ns t t op5 output data position3 (fig.9) 3 t tcop 7 - 0.15 3 t tcop 7 3 t tcop 7 +0.15 ns t t op4 output data position4 (fig.9) 4 t tcop 7 - 0.15 4 t tcop 7 4 t tcop 7 +0.15 ns t t op3 output data position5 (fig.9) 5 t tcop 7 - 0.15 5 t tcop 7 5 t tcop 7 +0.15 ns t t op2 output data position6 (fig.9) 6 t tcop 7 - 0.15 6 t tcop 7 6 t tcop 7 +0.15 ns t t pll phase lock time (fig.5) - - 10.0 ms t deint de input period (fig.6) dual out mode only(mode=l) 4 t tc ip t tc ip * (2n) (a) - n s t deh de input period (fig.6) dual out mode only(mode=l) 2t tc ip t tci p * (2m) (a) - ns t del de input period (fig.6) dual out mode only(mode=l) 2t tc ip - - ns (a) refer to fig .6 for details.
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 9 / 19 thine electronics, inc. security e ac timing diagrams fig ure 4. lvds output load and transition time figure 5. pll lock time note: d ual - out mode(mode=l) t he period between rising edges of de (t deint ), high time of de (t deh ) should always satisfy following equations. t deh = t tcip * (2m) t deint = t tcip * (2n) m, n = integer figure 6. dual - out mode de input timing
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 10 / 19 thine electronics, inc. security e ac timing diagrams (continued) fig ure 7. clkin period, high/low time, setup/hold timing for single edge input mode mode = h or ddr n = h fig ure 8. clkin period, high/low time, setup/hold timing for double edge input mode(ddr) mode = l, ddr n = l
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 11 / 19 thine electronics, inc. security e ac timing diagrams(continued) figure 9. lvds output data position
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 12 / 19 thine electronics, inc. security e single - in / dual - out mode (mode = l) fig ure 10. single - in / dual - out mode (mode = l)
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 13 / 19 thine electronics, inc. security e single - in / single - out mode (mode = h) fig ure 1 1. single - in / single - out mode (mode = h)
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 14 / 19 thine electronics, inc. security e lvds data mapping for 8 bit mode (6b/8b = l) figure 12 . lvds data mapping for 8 bit mode (6b/8b = l) r12 g12 r17 r16 r15 r14 r13 r13 r12 g13 b13 b12 g17 g16 g15 g14 g14 g13 tclkn+/- tan+/- b14 de vsync hsync b17 b16 b15 b15 b14 r10 0 b11 b10 g11 g10 r11 r11 r10 tbn+/- tcn+/- tdn+/- current cycle previous cycle n=1,2 (a) lvds data mapping when map = h (mapping mode 1) r10 g10 r15 r14 r13 r12 r11 r11 r10 g11 b11 b10 g15 g14 g13 g12 g12 g11 tclkn+/- tan+/- b12 de vsync hsync b15 b14 b13 b13 b12 r16 0 b17 b16 g17 g16 r17 r17 r16 tbn+/- tcn+/- tdn+/- current cycle previous cycle n=1,2 (b) lvds data mapping when map = l (mapping mode 2)
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 15 / 19 thine electronics, inc. security e lvds data mapping for 6 bit mode (6b/8b = h) figure 13. lvds data mapping for 6 bit mode (6b/8b = h) note: input pins which are not used in 6 bit mode (r10 - 11,g10 - 11,b10 - 11 on mapping mode 1, r16 - 17,g16- 17,b16 - 17 on mapping mode 2) can be h, l, or open. hiz r12 g12 r17 r16 r15 r14 r13 r13 r12 g13 b13 b12 g17 g16 g15 g14 g14 g13 tclkn+/- tan+/- b14 de vsync hsync b17 b16 b15 b15 b14 tbn+/- tcn+/- tdn+/- current cycle previous cycle n=1,2 (a) lvds data mapping when map = h (mapping mode 1) r10 g10 r15 r14 r13 r12 r11 r11 r10 g11 b11 b10 g15 g14 g13 g12 g12 g11 tclkn+/- tan+/- b12 de vsync hsync b15 b14 b13 b13 b12 tbn+/- tcn+/- tdn+/- current cycle previous cycle n=1,2 (b) lvds data mapping when map = l (mapping mode 2) hiz
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 16 / 19 thine electronics, inc. security e note 1) cable connection and disconnection don ? t connect and disconnect the lvds cable, when the power is supplied to the system. 2) gnd connection connect the each gnd of the pcb which thc63lvd827- q and lvds - rx on it. it is better for emi reduction to place gnd cable as close to lvds cable as pos sible. 3) multi drop connection multi drop connection is not recommended. figure 14. multi drop connection 4) asynchronous use asynchronous use such as following systems are not recommended. figure 15. asynchronous use thc63lvd827-q thc63lvd827-q ic clkout clkout data data lvds-rx lvds-rx ic tclk+ tclk- tclk+ tclk- clkout data data thc63lvd827-q thc63lvd827-q ic tclk+ tclk- tclk+ tclk- clkout clkout data data ic lvds - rx thc63lvd827-q lvds-rx tclk+ tclk-
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 17 / 19 thine electronics, inc. security e package tfbga figure 16. package d iagram
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 18 / 19 thine electronics, inc. security e identification code if a product has ? - ? in its product name, the product may have multiple product name s and the figure/character after ? - ? is called ? identification code ? . the identification code is b/d/f/g/h/l/q or other figure/ character (s) and it is used for thine internal product identification . for example, the product ? thc63lvd827 - q ? ma y have other product name , like ? thc63lvd827 - b ? .
thc63lvd827 - q _rev.1. 20 _e copyright?201 5 thine electronics, inc. 19 / 19 thine electronics, inc. security e notices and requests 1. the product specifications described in this material are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer?s design. we are not responsible for possible errors and omissions in this material. please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. this material contains our copyright, know - how or other proprietary . copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsi bility unless it directly relates to the production process or functions of the product. 5. product application 5.1 application of this product is intended for and limited to the following applications: audio - video device, office automation device, communication device, consumer electronics, smartphone, feature phone , and amusement machine device. this product must not be used for applications that require extremely high - reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 this product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of iso/ts16949 ("the specified product") in this data sheet. thine electronics, inc. (?thine?) accept s no liability whatsoever for any product other than the specified product for it not conforming to the aforementioned demands and specifications. 5.3 thine accepts liability for demands and specifications of the specified product only to the extent that the user and thine have been previously and explicitly agreed to each other. 6. despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi - conductor produ ct. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. please note that this product is not designed to be radiation - pro of. 8. testing and other quality control techniques are used to this product to the extent thine deems necessary to support warranty for performance of this product. except where mandated by applicable law or deemed necessary by thine based on the user?s requ est, testing of all functions and performance of the product is not necessarily performed. 9. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign exchange and foreign trade co ntrol law. 10. the product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. the damages may cause a smoking and ignition. therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. thine electronics, inc. sales@thine.co.jp

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