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innovative power tm - 1 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. act8847 advanced pmu for multi - core application processors features integrated power supplies ? four dc/dc step - down (buck) regulators ? 2 x 2.8a, 2 x 1.5a ? five low - noise ldos ? 2 x 150ma, 3 x 350ma ? three low - input voltage ldos ? 1 x 150ma, 2 x 350ma ? one low iq keep - alive ldo ? backup battery charger system control and interface ? six general purpose i/o with pwm drivers ? i 2 c serial interface ? interrupt controller system management ? reset interface and sequencing controller ? power on reset ? soft / hard reset ? watchdog supervision ? multiple sleep modes ? thermal management subsystem applications ? tablet pc ? mobile internet devices (mid) ? ebooks ? personal navigation devices general description the act8847 is a complete, cost effective, and highly - efficient activepmu tm power management solution optimized for the power, voltage sequencing and control requirements of samsung exynos 4210 (s5pc210/s5pv310) and other application processors. (please see ordering information section and its appendix.) the act8847 features four fixed - frequency, current - mode, synchronous pwm step - down converters that achieve peak efficiencies of up to 97%. these regulators operate with a fixed frequency of 2.25mhz, minimizing noise in sensitive applications and allowing the use of small external components. these buck regulators supply up to 2.8a of output current and can fully satisfy the power and control requirements of the multi - core application processor. dynamic voltage scaling (dvs) is supported either by dedicated control pins, or through i2c interface to optimize the energy - per - task performance for the processor. this device also include eight low - noise ldos (up to 350ma per ldo), one always - on ldo and an integrated backup battery charger to provide a complete power system for the processor. the power sequence and reset controller provides power - on reset, sw - initiated reset, and power cycle reset for the processor. it also features the watchdog supervisory function. multiple sleep modes with autonomous sleep and wake - up sequence control are supported. the thermal management and protection subsystem allows the host processor to manage the power dissipation of the pmu and the overall system dynamically. the pmu provides a thermal warning to the host processor when the temperature reaches a certain threshold such that the system can turn off some of the non - essential functions, reduce the clock frequency and etc to manage the system temperature. the act8847 is available in a compact, pb - free and rohs - compliant tqfn66 - 48 package. rev 9, 27 - june - 17
act8847 rev 9, 27 - june - 17 innovative power tm - 2 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. functional block dia gram s d a r e g 2 v p 2 g p 2 s w 2 o u t 2 o u t 2 r e g 1 v p 1 g p 1 4 s w 1 o u t 1 o u t 1 t o b a t t e r y n i r q r e g 5 l d o o u t 5 o u t 5 i n l 1 r e f b p r e f e r e n c e r e g 3 v p 3 g p 3 s w 3 o u t 3 o u t 3 g a e p n p b s t a t p w r h l d p w r e n s c l n r s t o v s e l r 2 v i o n p b i n p u s h b u t t o n i n l 2 r e g 6 l d o o u t 6 o u t 6 r e g 7 l d o o u t 7 o u t 7 r e g 1 0 l d o o u t 1 0 o u t 1 0 t o b a t t e r y t o b a t t e r y r e g 4 v p 4 g p 1 4 s w 4 o u t 4 o u t 4 t o b a t t e r y r e g 1 1 l d o o u t 1 1 o u t 1 1 i n l 3 r e g 1 2 l d o o u t 1 2 o u t 1 2 g p i o 1 v i o v i o r e g 1 3 r t c l d o o u t 1 3 g p i o 2 g p i o 4 g p i o 3 g p i o 5 g p i o 6 s y s t e m c o n t r o l i n l 2 r e g 8 l d o o u t 8 o u t 8 r e g 9 l d o o u t 9 o u t 9 o u t 1 3 a c t 8 8 4 7 t o b a t t e r y t o b a t t e r y t o b a t t e r y
act8847 rev 9, 27 - june - 17 innovative power tm - 3 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. ordering information ? ? : all active - semi components are rohs compliant and with pb - free plating unless specified differently. the term pb - free means semiconductor products that are in compliance with current rohs (restriction of hazardous substances) standards. ? : the package code designator q represents qfn. ? : the pin count designator m represents 48 pins. ? : xxx represents the cmi (code matrix index) option. the cmi identifies the ic s default register settings. ? : act8847qm174 - t is dedicated to s5pv310 application. ? : act8847 data sheet is described according to act8847qm171 - t application; please see the appendix of act8847qm211 - t for its specification. ? : act8847qm600 - t and act8849qm614 - t is the association application for samsung exynos 4412/ 4212 platforms; please see the appendix of app_act8847 act8849_rev0_16jun14_p for its specification. ? : act8847qm502 - t is dedicated to freescale i.mx6 application. ? : act8847qm102 - t is dedicated to freescale i.mx6ul/i.mx6ull with custom startup and system level considerations part number v out1 v out2 v out3 v out4 v out5 v out6 v out7 v out8 v out9 v out10 v out11 v out12 v out13 act8847qm102 - t 1.35v 3.3v 3.8v 1.3v 3.3v off 3.3v off off off off off 3.3v act8847qm171 - t 1.2v 1.2v 1.1v 1.1v 1.1v 1.1v 3.3v 1.8v 3.3v 1.2v 1.1v 1.8v 1.8v act8847qm174 - t 1.5v 1.2v 1.1v 1.1v 1.1v 1.1v 3.3v 1.8v 3.3v 1.5v 1.1v 1.8v 1.8v act8847qm211 - t 1.3v 1.1v 1.5v off off off 3.3v 1.8v 2.5v off 2.8v off 3.3v act8847qm600 - t 1.0v 1.3v 1.0v 1.125v 1.8v 3.0v 1.8v 3.3v 3.3v 1.1v 1.8v 1.0v 1.8v act8849qm614 - t 2.8v 1.2v 2.0v 2.8v 1.8v 1.8v 2.8v 1.8v 1.8v 1.0v 1.2v 1.0v 1.8v act8847qm502 - t 1.4v 1.4v 1.5v 3.3v off off 2.8v 1.8v 3.0v 2.5v off off 3.2v act8847qm503 - t off 1.4v 3.3/3.1v 1.5/1.35v 2.5v off 3.3v 1.8v off off 1.2v 0.75v 3.3v package pins temperature range tqfn66 - 48 48 - 40 c to +85 c act 8847 qm _ _ _ - t cmi option pin count package code product number active - semi tape and reel
act8847 rev 9, 27 - june - 17 innovative power tm - 4 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. pin configuration top view thin - qfn (tqfn66 - 48) a c t 8 8 4 7 e p o u t 1 3 o u t 7 g p i o 4 o u t 6 i n l 1 o u t 5 g p i o 3 g p i o 2 g p i o 1 o u t 3 g p i o 6 n i r q n r s t o p w r h l d n p b i n v p 1 o u t 1 s w 1 s w 3 s w 3 g p 3 o u t 1 0 o u t 1 1 i n l 3 o u t 1 2 v s e l r 2 n p b s t a t g p 2 s c l s d a o u t 4 g a o u t 9 i n l 2 r e f b p p w r e n o u t 2 o u t 8 v p 3 v p 3 s w 2 s w 2 v p 2 v p 2 s w 4 g p 1 4 v p 4 g p i o 5
act8847 rev 9, 27 - june - 17 innovative power tm - 5 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. pin descriptions pin name description 1, 2 sw3 switch node for reg3. 3 gp3 power ground for reg3. connect gp14, gp2, gp3, and ga together at a single point as close to the ic as possible. 4 out10 reg10 output. bypass it to ground with a 2.2f capacitor. 5 out11 reg11 output. bypass it to ground with a 2.2f capacitor. 6 inl3 power input for reg10, reg11 and reg12. 7 out12 reg12 output. bypass it to ground with a 2.2f capacitor. 8 vselr2 output voltage selection for reg2. drive to logic low to select default output voltage. drive to logic high to select secondary output voltage. 9 npbstat active - low open - drain push - button status output. npbstat is asserted low whenever the npbin is pushed, and is high - z otherwise. 10 gp2 power ground for reg2. connect gp14, gp2, gp3, and ga together at a single point as close to the ic as possible. 11, 12 sw2 switch node for reg2. 13, 14 vp2 power input for reg2. bypass to gp2 with a high quality ceramic capacitor placed as close to the ic as possible. 15 out2 output voltage sense for reg2. 16 pwren power enable input. 17 refbp reference bypass. connect a 0.047 f ceramic capacitor from refbp to ga. this pin is discharged to ga in shutdown. 18 inl2 power input for reg8, reg9. 19 out9 reg9 output. bypass it to ground with a 2.2f capacitor. 20 ga analog ground. 21 out4 output voltage sense for reg4. 22 out8 reg8 output. bypass it to ground with a 2.2f capacitor. 23 sda data input for i 2 c serial interface. data is read on the rising edge of scl. 24 scl clock input for i 2 c serial interface. 25 vp4 power input for reg4. bypass to gp14 with a high quality ceramic capacitor placed as close to the ic as possible.
act8847 rev 9, 27 - june - 17 innovative power tm - 6 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. pin descriptions cont d pin name description 26 sw4 switch node for reg4. 27 gp14 power ground for reg1 and reg4. connect gp14, gp2, gp3, and ga together at a single point as close to the ic as possible. 28 sw1 switch node for reg1. 29 out1 output voltage sense for reg1. 30 vp1 power input for reg1. bypass to gp14 with a high quality ceramic capacitor placed as close to the ic as possible. 31 npbin master enable input. drive npbin to ga through a 50k resistor to enable the ic, drive npbin directly to ga to assert a manual - reset condition. 32 pwrhld power hold input. pwrhld is internally pulled down to ga through a 900k resistor. 33 nrsto open - drain reset output. 34 nirq open - drain interrupt output. 35 gpio6 general purpose i/o #6. configured as pwm led driver output for up to 6ma current with programmable frequency and duty cycle. see the pwm led drive section for more information. 36 gpio5 general purpose i/o #5. configured as pwm led driver output for up to 6ma current with programmable frequency and duty cycle. see the pwm led driver section for more information. 37 out13 reg13 output. bypass it to ground with a 2.2f capacitor. 38 out7 reg7 output. bypass it to ground with a 2.2f capacitor. 39 gpio4 general purpose i/o #4. configured as pwm led driver output for up to 6ma current with programmable frequency and duty cycle. see the pwm led driver section for more information. 40 out6 reg6 output. bypass it to ground with a 2.2f capacitor. 41 inl1 power input for reg5, reg6, reg7. 42 out5 reg5 output. bypass it to ground with a 2.2f capacitor. 43 gpio3 general purpose i/o #3. configured as pwm led driver output for up to 6ma current with programmable frequency and duty cycle. see the pwm led drier section for more information. 44 gpio2 general purpose i/o #2. configured as vselr4 for voltage selection of reg4. drive to logic low to select default output voltage. drive to logic high to select secondary output voltage. 45 gpio1 general purpose i/o #1. configured as vselr3 for voltage selection of reg3. drive to logic low to select default output voltage. drive to logic high to select secondary output voltage. 46 out3 output voltage sense for reg3. 47,48 vp3 power input for reg3. bypass to gp3 with a high quality ceramic capacitor placed as close to the ic as possible. ep ep exposed pad. must be soldered to ground on pcb.
act8847 rev 9, 27 - june - 17 innovative power tm - 7 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. absolute maximum rat ings ? parameter value unit inl1, inl2, inl3 to ga; vp1, sw1, out1 to gp14; vp2, sw2, out2 to gp2; vp3, sw3, out3 to gp3; vp4, sw4, out4 to gp14 - 0.3 to 6 v gp14, gp2, gp3 to ga - 0.3 to + 0.3 v out5, out6, out7, out13 to ga - 0.3 to inl1 + 0.3 v out8, out9, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, vselr2, npbin, nrsto, nirq, npbstat, pwren, pwrhld, refbp, scl, sda to ga - 0.3 to inl2 + 0.3 v out10, out11, out12 to ga - 0.3 to inl3 + 0.3 v junction to ambient thermal resistance 21 c/w operating ambient temperature range - 40 to 85 c operating junction temperature - 40 to 125 c storage temperature - 55 to 150 c lead temperature (soldering, 10 sec) 300 c ? : do not exceed these limits to prevent damage to the device. exposure to absolute maximum rating conditions for long periods ma y affect device reliability.
act8847 rev 9, 27 - june - 17 innovative power tm - 8 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. figure 1: i 2 c compatible serial bus timing (v inl2 = 3.6v, t a = 25c, unless otherwise specified.) i 2 c interface electric al characteristics parameter test conditions min typ max unit scl, sda input low v inl2 = 3.1v to 5.5v, t a = - 40oc to 85oc 0.35 v scl, sda input high v inl2 = 3.1v to 5.5v, t a = - 40oc to 85oc 1. 55 v sda leakage current 1 a scl leakage current 1 a sda output low i ol = 5ma 0.3 5 v scl clock period, t scl 1.5 s sda data setup time, t su 100 ns sda data hold time, t hd 300 ns start setup time, t st for start condition 100 ns stop setup time, t sp for stop condition 100 ns sda scl t st t su t hd t sp t scl start condition stop condition
act8847 rev 9, 27 - june - 17 innovative power tm - 9 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. block address bits d7 d6 d5 d4 d3 d2 d1 d0 sys 0x00 name nbatlevmsk nbatstat vbatdat reserved batlev[3] batlev[2] batlev[1] batlev[0] default ? 0 r r 0 0 0 0 0 sys 0x01 name ntmsk tstat reserved reserved reserved reserved reserved reserved default ? 0 r 0 0 0 0 0 0 reg1 0x10 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default ? 0 0 0 1 1 0 0 0 reg1 0x12 name on reserved reserved reserved reserved phase nfltmsk ok default ? 1 1 0 0 0 0 0 r reg2 0x20 name reserved reserved vset0[5] vset0[4] vset0[3] vset0[2] vset0[1] vset0[0] default ? 0 0 0 1 1 0 0 0 reg2 0x21 name reserved reserved vset1[5] vset1[4] vset1[3] vset1[2] vset1[1] vset1[0] default ? 0 0 0 1 1 0 0 0 reg2 0x22 name on reserved reserved reserved reserved phase nfltmsk ok default ? 1 1 0 1 0 0 0 r reg3 0x30 name reserved reserved vset0[5] vset0[4] vset0[3] vset0[2] vset0[1] vset0[0] default ? 0 0 0 1 0 1 0 0 reg3 0x31 name reserved reserved vset1[5] vset1[4] vset1[3] vset1[2] vset1[1] vset1[0] default ? 0 0 0 1 0 1 0 0 reg3 0x32 name on reserved reserved reserved reserved phase nfltmsk ok default ? 1 1 0 1 0 1 0 r reg4 0x40 name reserved reserved vset0[5] vset0[4] vset0[3] vset0[2] vset0[1] vset0[0] default ? 0 0 0 1 0 1 0 0 reg4 0x41 name reserved reserved vset1[5] vset1[4] vset1[3] vset1[2] vset1[1] vset1[0] default ? 0 0 0 1 0 1 0 0 reg4 0x42 name on reserved reserved reserved reserved phase nfltmsk ok default ? 1 1 0 1 0 1 0 r reg5 0x50 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default ? 0 0 0 1 0 1 0 0 reg5 0x51 name on reserved reserved reserved reserved dis nfltmsk ok default ? 1 1 0 1 0 1 0 r reg6 0x58 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default ? 0 0 0 1 0 1 0 0 reg6 0x59 name on reserved reserved reserved reserved dis nfltmsk ok default ? 1 1 0 0 0 1 0 r reg7 0x60 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default ? 0 1 1 1 1 0 0 1 reg7 0x61 name on reserved reserved reserved reserved dis nfltmsk ok default ? 1 1 0 0 0 1 0 r reg8 0x68 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default ? 0 0 1 0 0 1 0 0 reg8 0x69 name on reserved reserved reserved reserved dis nfltmsk ok default ? 1 1 0 1 0 1 0 r global register map ? : default values of act8847qm171 - t.
act8847 rev 9, 27 - june - 17 innovative power tm - 10 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. block address bits d7 d6 d5 d4 d3 d2 d1 d0 reg9 0x70 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default ? 0 0 1 1 1 0 0 1 reg9 0x71 name on reserved reserved reserved reserved dis nfltmsk ok default ? 1 1 0 1 0 1 0 r reg10 0x80 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default ? 0 0 0 1 1 0 0 0 reg10 0x81 name on reserved reserved reserved reserved dis nfltmsk ok default ? 1 1 0 1 0 1 0 r reg11 0x90 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default ? 0 0 0 1 0 1 0 0 reg11 0x91 name on reserved reserved reserved reserved dis nfltmsk ok default ? 1 1 0 1 0 1 0 r reg12 0xa0 name reserved reserved vset[5] vset[4] vset[3] vset[2] vset[1] vset[0] default ? 0 1 1 0 0 1 0 0 reg12 0xa1 name on reserved reserved reserved reserved dis nfltmsk ok default ? 1 1 0 0 0 1 0 r reg13 0xb1 name on reserved reserved reserved reserved reserved reserved reserved default ? 1 0 0 0 0 0 0 0 pb 0xc0 name pbamsk pbdmsk reserved reserved reserved reserved wdsren wdpcen default ? 0 0 0 0 0 0 0 0 pb 0xc1 name intadr [7] intadr [6] intadr [5] intadr [4] intadr [3] intadr [2] intadr [1] intadr [0] default ? r r r r r r r r pb 0xc2 name pbastat pbdstat pbdat reserved reserved reserved reserved reserved default ? r r r r r r r r pb 0xc3 name reserved reserved reserved reserved reserved reserved reserved sipc default ? 0 0 0 0 0 0 0 0 pb 0xc5 name reserved reserved reserved reserved reserved reserved pcstat srstat default ? 0 0 0 0 0 0 r r gpio6 0xe3 name pwm6en fre6[2] fre6[1] fre6[0] duty6[3] duty6[2] duty6[1] duty6[0] default ? 0 0 0 0 0 0 0 0 gpio5 0xe4 name pwm5en fre5[2] fre5[1] fre5[0] duty5[3] duty5[2] duty5[1] duty5[0] default ? 0 0 0 0 0 0 0 0 gpio3 0xf4 name pwm3en fre3[2] fre3[1] fre3[0] duty3[3] duty3[2] duty3[1] duty3[0] default ? 0 0 0 0 0 0 0 0 gpio4 name pwm4en fre4[2] fre4[1] fre4[0] duty4[3] duty4[2] duty4[1] duty4[0] 0xf5 default ? 0 0 0 0 0 0 0 0 global register map cont d ? : default values of act8847qm171 - t.
act8847 rev 9, 27 - june - 17 innovative power tm - 11 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. register and bit descriptions block address bit name access description sys 0x00 [7] nbatlevmsk r/w battery voltage level interrupt mask. set this bit to 1 to unmask the interrupt. see the programmable battery voltage monitor section for more information sys 0x00 [6] nbatstat r battery voltage status. value is 1 when batlev interrupt is generated, value is 0 otherwise. sys 0x00 [5] vbatdat r battery voltage monitor real time status. value is 1 when vbat < batlev, value is 0 otherwise. sys 0x00 [4] - r/w reserved. sys 0x00 [3:0] batlev r/w battery voltage detect threshold. defines the batlev voltage threshold. see the programmable battary voltage monitor section for more information. sys 0x01 [7] ntmsk r/w thermal interrupt mask. set this bit to 1 to unmask the interrupt. sys 0x01 [6] tstat r thermal interrupt status. value is 1 when a thermal interrupt is generated, value is 0 otherwise. sys 0x01 [5:0] - r/w reserved. reg1 0x10 [7:6] - r reserved. reg1 0x10 [5:0] vset0 r/w primary output voltage selection. see the output voltage programming section for more information reg1 0x12 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg1 0x12 [6:3] - r reserved. reg1 0x12 [2] phase r/w regulator phase control. set bit to 1 for the regulator to operate 180 out of phase with the oscillator, clear bit to 0 for the regulator to operate in phase with the oscillator. reg1 0x12 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault - interrupts, clear bit to 0 to disable fault - interrupts. reg1 0x12 [0] ok r regulator power - ok status. value is 1 when output voltage exceeds the power - ok threshold, value is 0 otherwise. reg2 0x20 [7:6] - r reserved. reg2 0x20 [5:0] vset0 r/w primary output voltage selection. valid when vsel is driven low. see the output voltage programming section for more information reg2 0x21 [7:6] - r reserved. reg2 0x21 [5:0] vset1 r/w secondary output voltage selection. valid when vsel is driven high. see the output voltage programming section for more information. reg2 0x22 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg2 0x22 [6:3] - r reserved. reg2 0x22 [2] phase r/w regulator phase control. set bit to 1 for the regulator to operate 180 out of phase with the oscillator, clear bit to 0 for the regulator to operate in phase with the oscillator. reg2 0x22 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault - interrupts, clear bit to 0 to disable fault - interrupts. reg2 0x22 [0] ok r regulator power - ok status. value is 1 when output voltage exceeds the power - ok threshold, value is 0 otherwise. reg3 0x30 [7:6] - r reserved. reg3 0x30 [5:0] vset0 r/w primary output voltage selection. valid when vsel is driven low. see the output voltage programming section for more information
act8847 rev 9, 27 - june - 17 innovative power tm - 12 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. register and bit descriptions cont d block address bit name access description reg3 0x31 [7:6] - r reserved. reg3 0x31 [5:0] vset1 r/w secondary output voltage selection. valid when vsel is driven high. see the output voltage programming section for more information. reg3 0x32 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg3 0x32 [6:3] - r reserved. reg3 0x32 [2] phase r/w regulator phase control. set bit to 1 for the regulator to operate 180 out of phase with the oscillator, clear bit to 0 for the regulator to operate in phase with the oscillator. reg3 0x32 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault - interrupts, clear bit to 0 to disable fault - interrupts. reg3 0x32 [0] ok r regulator power - ok status. value is 1 when output voltage exceeds the power - ok threshold, value is 0 otherwise. reg4 0x40 [7:6] - r reserved. reg4 0x40 [5:0] vset0 r/w primary output voltage selection. valid when vsel is driven low. see the output voltage programming section for more information reg4 0x41 [7:6] - r reserved. reg4 0x41 [5:0] vset1 r/w secondary output voltage selection. valid when vsel is driven high. see the output voltage programming section for more information. reg4 0x42 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg4 0x42 [6:3] - r reserved. reg4 0x42 [2] phase r/w regulator phase control. set bit to 1 for the regulator to operate 180 out of phase with the oscillator, clear bit to 0 for the regulator to operate in phase with the oscillator. reg4 0x42 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault - interrupts, clear bit to 0 to disable fault - interrupts. reg4 0x42 [0] ok r regulator power - ok status. value is 1 when output voltage exceeds the power - ok threshold, value is 0 otherwise. reg5 0x50 [7:6] - r reserved. reg5 0x50 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg5 0x51 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg5 0x51 [6:3] - r reserved. reg5 0x51 [2] dis r/w output discharge control. when activated, ldo output is discharged to ga through 1.5k resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg5 0x51 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault - interrupts, clear bit to 0 to disable fault - interrupts. reg5 0x51 [0] ok r regulator power - ok status. value is 1 when output voltage exceeds the power - ok threshold, value is 0 otherwise. reg6 0x58 [7:6] - r reserved. reg6 0x58 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg6 0x59 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator.
act8847 rev 9, 27 - june - 17 innovative power tm - 13 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. register and bit descriptions cont d block address bit name access description reg6 0x59 [6:3] - r reserved. reg6 0x59 [2] dis r/w output discharge control. when activated, ldo output is discharged to ga through 1.5k resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg6 0x59 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault - interrupts, clear bit to 0 to disable fault - interrupts. reg6 0x59 [0] ok r regulator power - ok status. value is 1 when output voltage exceeds the power - ok threshold, value is 0 otherwise. reg7 0x60 [7:6] - r reserved. reg7 0x60 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg7 0x61 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg7 0x61 [6:3] - r reserved. reg7 0x61 [2] dis r/w output discharge control. when activated, ldo output is discharged to ga through 1.5k resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg7 0x61 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault - interrupts, clear bit to 0 to disable fault - interrupts. reg7 0x61 [0] ok r regulator power - ok status. value is 1 when output voltage exceeds the power - ok threshold, value is 0 otherwise. reg8 0x68 [7:6] - r reserved. reg8 0x68 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg8 0x69 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg8 0x69 [6:3] - r reserved. reg8 0x69 [2] dis r/w output discharge control. when activated, ldo output is discharged to ga through 1.5k resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg8 0x69 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault - interrupts, clear bit to 0 to disable fault - interrupts. reg8 0x69 [0] ok r regulator power - ok status. value is 1 when output voltage exceeds the power - ok threshold, value is 0 otherwise. reg9 0x70 [7:6] - r reserved. reg9 0x70 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg9 0x71 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg9 0x71 [6:3] - r reserved. reg9 0x71 [2] dis r/w output discharge control. when activated, ldo output is discharged to ga through 1.5k resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg9 0x71 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault - interrupts, clear bit to 0 to disable fault - interrupts. reg9 0x71 [0] ok r regulator power - ok status. value is 1 when output voltage exceeds the power - ok threshold, value is 0 otherwise. reg10 0x80 [7:6] - r reserved.
act8847 rev 9, 27 - june - 17 innovative power tm - 14 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. register and bit descriptions cont d block address bit name access description reg10 0x80 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg10 0x81 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg10 0x81 [6:3] - r reserved. reg10 0x81 [2] dis r/w output discharge control. when activated, ldo output is discharged to ga through 1.5k resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg10 0x81 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault - interrupts, clear bit to 0 to disable fault - interrupts. reg10 0x81 [0] ok r regulator power - ok status. value is 1 when output voltage exceeds the power - ok threshold, value is 0 otherwise. reg11 0x90 [7:6] - r reserved. reg11 0x90 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg11 0x91 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg11 0x91 [6:3] - r reserved. reg11 0x91 [2] dis r/w output discharge control. when activated, ldo output is discharged to ga through 1.5k resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg11 0x91 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault - interrupts, clear bit to 0 to disable fault - interrupts. reg11 0x91 [0] ok r regulator power - ok status. value is 1 when output voltage exceeds the power - ok threshold, value is 0 otherwise. reg12 0xa0 [7:6] - r reserved. reg12 0xa0 [5:0] vset r/w output voltage selection. see the output voltage programming section for more information. reg12 0xa1 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg12 0xa1 [6:3] - r reserved. reg12 0xa1 [2] dis r/w output discharge control. when activated, ldo output is discharged to ga through 1.5k resistor when in shutdown. set bit to 1 to enable output voltage discharge in shutdown, clear bit to 0 to disable this function. reg12 0xa1 [1] nfltmsk r/w regulator fault mask control. set bit to 1 enable fault - interrupts, clear bit to 0 to disable fault - interrupts. reg12 0xa1 [0] ok r regulator power - ok status. value is 1 when output voltage exceeds the power - ok threshold, value is 0 otherwise. reg13 0xb1 [7] on r/w regulator enable bit. set bit to 1 to enable the regulator, clear bit to 0 to disable the regulator. reg13 0xb1 [6:0] - r reserved. pb 0xc0 7 npbamsk r/w npbin assertion interrupt control. set this bit to 1 to generate an interrupt when npbin is asserted. pb 0xc0 6 npbdmsk r/w npbin de - assertion interrupt control. set this bit to 1 to generate an interrupt when npbin is de - asserted. pb 0xc0 [5:2] - r reserved. pb 0xc0 1 wdsren r/w watchdog soft - reset enable. set this bit to 1 to enable watchdog function. when the watchdog timer expires, the pmu commences a soft - reset routine. this bit is automatically reset to 0 when entering sleep mode.
act8847 rev 9, 27 - june - 17 innovative power tm - 15 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. register and bit descriptions cont d block address bit name access description pb 0xc0 [5:2] - r reserved. pb 0xc0 1 wdsren r/w watchdog soft - reset enable. set this bit to 1 to enable watchdog function. when the watchdog timer expires, the pmu commences a soft - reset routine. this bit is automatically reset to 0 when entering sleep mode. pb 0xc0 0 wdpcen r/w watchdog power - cycle enable. set this bit to 1 to enable watchdog function. when watchdog timer expires, the pmu commence a power cycle. this bit is automatically reset to 0 when entering sleep mode. pb 0xc1 [7:0] intadr r interrupt address. it holds the address of the block that triggers the interrupt. this byte defaults to 0xff and is automatically set to 0xff after being read. bit 7 is the msb while bit 0 is the lsb. pb 0xc2 7 pbastat r npbin assertion interrupt status. the value of this bit is 1 if the npbin assertion interrupt is triggered. pb 0xc2 6 pbdstat r npbin de - assertion interrupt status. the value of this bit is 1 if the npbin de - assertion interrupt is triggered. pb 0xc2 5 pbastat r npbin status bit. this bit contains the real - time status of the npbin pin. the value of this bit is 1 if npbin is asserted, and is 0 if npbin is de - asserted. pb 0xc2 [4:0] - r reserved. pb 0xc3 [7:1] - r reserved. pb 0xc3 0 sipc r/w software initiated power cycle. when this bit is set, the pmu commences a power cycle after 8ms delay. pb 0xc5 [7:2] - r reserved. pb 0xc5 1 pcstat r/w power - cycle flag. the value of this bit is 1 after a power cycle. this bit is automatically cleared to 0 after read. pb 0xc5 0 srstat r/w soft - reset flag. the value of this bit is 1 after a soft - reset. this bit is automatically cleared to 0 after read. gpio6 0xe3 [7] pwm6en r/w pwm function enable. set 1 to enable pwm function of gpio6. gpio6 0xe3 [6:4] fre6 r/w pwm frequency selection bits for gpio6. see the table 6 for code to frequency cross. gpio6 0xe3 [3:0] duty6 r/w duty cycle selection bits for gpio6. see the table 7 for code to duty cross. gpio5 0xe4 [7] pwm5en r/w pwm function enable. set 1 to enable pwm function of gpio5. gpio5 0xe4 [6:4] fre5 r/w pwm frequency selection bits for gpio5. see the table 6 for code to frequency cross. gpio5 0xe4 [3:0] duty5 r/w duty cycle selection bits for gpio5. see the table 7 for code to duty cross. gpio3 0xf4 [7] pwm3en r/w pwm function enable. set 1 to enable pwm function of gpio3. gpio3 0xf4 [6:4] fre3 r/w pwm frequency selection bits for gpio3. see the table 6 for code to frequency cross. gpio3 0xf4 [3:0] duty3 r/w duty cycle selection bits for gpio3. see the table 7 for code to duty cross. gpio4 0xf5 [7] pwm4en r/w pwm function enable. set 1 to enable pwm function of gpio4. gpio4 0xf5 [6:4] fre4 r/w pwm frequency selection bits for gpio4. see the table 6 for code to frequency cross. gpio4 0xf5 [3:0] duty4 r/w duty cycle selection bits for gpio4. see the table 7 for code to duty cross.
act8847 rev 9, 27 - june - 17 innovative power tm - 16 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. system control elect rical characteristics (v inl2 = 3.6v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit input voltage range 3.0 5.5 v uvlo threshold voltage v inl2 rising 2.6 2.8 3.0 v uvlo hysteresis v inl2 hysteresis 200 mv operating supply current all regulators enabled but no load 0.6 1.2 ma shutdown supply current all regulators disabled except reg13 10 20 a oscillator frequency 2.0 2.25 2.5 mhz logic high input voltage 1.4 v logic low input voltage 0. 4 v leakage current v[nirq] = v[nrsto] = 4.2v 1 a low level output voltage nirq, nrsto, isink = 5ma 0.3 v thermal shutdown temperature temperature rising 160 c thermal shutdown hysteresis 20 c
act8847 rev 9, 27 - june - 17 innovative power tm - 17 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. step - down dc/dc elec trical characteristics (v vp1 = v vp2 = v vp3 = v vp4 = 3.6v, t a = 25c, unless otherwise specified.) parameter conditions min typ max unit operating voltage range 2.7 5.5 v uvlo threshold input voltage rising 2.5 2.6 2.7 v uvlo hysteresis input voltage falling 100 mv standby supply current v out = 103%, regulator enabled 72 100 a shutdown current v vp = 5.5v, regulator disabled 0 2 a v out 1.0v, i out = 10ma - 1% v nom ? 1% v output voltage accuracy v out < 1.0v, i out = 10ma - 10 10 mv line regulation v vp = max (v nom ? +1v, 3.2v) to 5.5v 0.15 %/v load regulation reg1/4 i out = 10ma to imax ? 1.70 %/a load regulation reg2/3 i out = 10ma to imax ? 1.00 %/a power good threshold v out rising 93 %v nom power good hysteresis v out falling 2 %v nom switching frequency v out 20% of v nom 2 2.25 2.5 mhz v out = 0v 550 khz soft - start period 400 s minimum on - time 75 ns reg1 and reg4 maximum output current 1.5 a current limit 1.8 2.2 2.7 a pmos on - resistance i sw = - 100ma 0.11 ? nmos on - resistance i sw = 100ma 0.08 ? sw leakage current v vp = 5.5v, v sw = 0 or 5.5v 0 2 a input capacitor 4.7 f output capacitor 33 f power inductor 1.0 2.2 3.3 h reg2 and reg3 maximum output current 2.8 a current limit 3.5 4.2 a pmos on - resistance i sw = - 100ma 0.07 ? nmos on - resistance i sw = 100ma 0.08 ? sw leakage current v vp = 5.5v, v sw = 0 or 5.5v 0 2 a input capacitor 10 f output capacitor 44 f power inductor 0.5 1 2.2 h ? : v nom refers to the nominal output voltage level for v out as defined by the ordering information section. ? : imax maximum output current.
act8847 rev 9, 27 - june - 17 innovative power tm - 18 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. low - noise ldo electr ical characteristics (v inl1 = v inl2 = 3.6v, c out5 = c out6 = c out7 = c out8 = c out9 = 2.2f, t a = 25c, unless otherwise specified.) ? : v nom refers to the nominal output voltage level for v out as defined by the ordering information section. ? : imax maximum output current. ? : dropout voltage is defined as the differential voltage between input and output when the output voltage drops 100mv below t he regulation voltage (for 3.1v output voltage or higher). ? : ldo current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation vo lta ge. under heavy overload conditions the output current limit folds back by 50% (typ.) parameter test conditions min typ max unit operating voltage range 2. 5 5.5 v v out 1.0v, i out = 10ma - 1 v nom ? 1 % output voltage accuracy v out < 1.0v, i out = 10ma - 10 10 mv line regulation v inl = max (v out + 0.5v, 3.6v) to 5.5v 0.5 mv load regulation i out = 1ma to imax ? 0.1 v/a power supply rejection ratio f = 1khz, i out = 20ma, v out = 1.2v 75 db f = 10khz, i out = 20ma, v out = 1.2v 65 supply current per output regulator enabled 25 a regulator disabled 0 2 soft - start period v out = 3.0v 140 s power good threshold v out rising 92 % power good hysteresis v out falling 3.5 % output noise i out = 20ma, f = 10hz to 100khz, v out = 1.2v 30 v rms discharge resistance ldo disabled, dis[ ] = 1 1.5 k ? ldo rated at 150ma (reg5 & reg6) dropout voltage ? i out = 80ma, v out > 3.1v 140 280 mv maximum output current 150 ma current limit ? v out = 95% of regulation voltage 180 ma recommend output capacitor 2.2 f ldo rated at 350ma (reg7, reg8 & reg9) dropout voltage ? i out = 160ma, v out > 3.1v 140 280 mv maximum output current 350 ma current limit ? v out = 95% of regulation voltage 400 ma recommend output capacitor 2.2 f
act8847 rev 9, 27 - june - 17 innovative power tm - 19 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. low - input voltage ldo electrical charact eristics (v inl3 = 3.6v, c out10 = c out11 = c out12 = 2.2f, t a = 25c, unless otherwise specified.) ? : v nom refers to the nominal output voltage level for v out as defined by the ordering information section. ? : imax maximum output current. ? : dropout voltage is defined as the differential voltage between input and output when the output voltage drops 100mv below t he regulation voltage (for 3.1v output voltage or higher). ? : ldo current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation vo lta ge. under heavy overload conditions the output current limit folds back by 50% (typ) parameter test conditions min typ max unit operating voltage range 1.7 5.5 v v out 1.0v, i out = 10ma - 1 v nom ? 1 % output voltage accuracy v out < 1.0v, i out = 10ma - 10 10 mv line regulation v inl = max (v out + 0.5v, 3.6v) to 5.5v 0.5 mv load regulation i out = 1ma to imax ? 0.1 v/a power supply rejection ratio f = 1khz, i out = 20ma, v out = 1.2v 50 db f = 10khz, i out = 20ma, v out = 1.2v 40 supply current per output regulator enabled 22 a regulator disabled 0 2 soft - start period v out = 3.0v 100 s power good threshold v out rising 92 % power good hysteresis v out falling 3.5 % output noise i out = 20ma, f = 10hz to 100khz, v out = 1.2v 30 v rms discharge resistance ldo disabled, dis[ ] = 1 1.5 k ? ldo rated at 150ma (reg10) dropout voltage ? i out = 80ma, v out > 3.1v 100 200 mv maximum output current 150 ma current limit ? v out = 95% of regulation voltage 180 ma recommend output capacitor 2.2 f ldo rated at 350ma (reg11 & reg12) dropout voltage ? i out = 160ma, v out > 3.1v 100 200 mv maximum output current 350 ma current limit ? v out = 95% of regulation voltage 400 ma recommend output capacitor 2.2 f
act8847 rev 9, 27 - june - 17 innovative power tm - 20 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. low - power(always - on) ldo electrical char acteristics (v inl1 = 3.6v, c out13 = 1f, t a = 25c, unless otherwise specified.) ? : v nom refers to the nominal output voltage level for v out as defined by the ordering information section. parameter test conditions min typ max unit reg13 v nom = 1.8v operating voltage range 2.5 5.5 v output voltage accuracy - 3 v nom ? 3 % line regulation v inl1 = max (v out + 0.2v, 2.5v) to 5.5v 13 mv supply current from v inl1 5 a maximum output current 50 ma recommend output capacitor 0.47 f pwm led driver electrical characteristics (v inl2 = 3.6v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit output current 100% duty cycle 6 10 16 ma output low voltage feed in with 6ma 0.35 v leakage current sinking from 5.5v source 1 a pwm frequency fre[2:0] = 000 0.25 hz pwm duty adjustment duty[3:0] = 0000 to 1111 6.26 100 %
act8847 rev 9, 27 - june - 17 innovative power tm - 21 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. typical performance characteristics (t a = 25c, unless otherwise specified.) startup of out6/4/2/3 startup of out5/7/1/12 startup of out3/5/7/12 startup of out11/10/8/9 temperature (c) - 40 - 20 0 20 40 60 80 100 120 140 act8847 - 001 v ref vs. temperature v ref (v) 1.204 1.200 1.196 1.192 1.188 1.184 act8847 - 002 frequency vs. temperature frequency (mhz) 2.360 2.340 2.320 2.300 2.280 2.260 2.240 2.220 2.200 2.180 temperature (c) - 40 - 20 0 20 40 60 80 100 120 140 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch4 act8847 - 003 act8847 - 004 act8847 - 005 act8847 - 006 ch1: v out5 , 1v/div ch2: v out7 , 2v/div ch3: v out1 , 1v/div ch4: v out12, 2v/div time: 400s/div ch1: v out6 , 1v/div ch2: v out4 , 1v/div ch3: v out2 , 1v/div ch4: v out3, 1v/div time: 400s/div ch1: v out3 , 1v/div ch2: v out5 , 1v/div ch3: v out7 , 2v/div ch4: v out12, 1v/div time: 200s/div ch1: v out11 , 1v/div ch2: v out10, 1v/div ch3: v out8 , 500mv/div ch4: v out9, 2v/div time: 400s/div
act8847 rev 9, 27 - june - 17 innovative power tm - 22 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. typical performance characteristics cont d (t a = 25c, unless otherwise specified.) startup of npbin, out6/4/2 startup of npbin, out6, nrsto sleep of pwren, out3/5/11 sleep of pwren, out4/2/3 npbin and npbstat sleep of pwren, out10/8/9 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch4 ch1 ch2 act8847 - 008 act8847 - 007 act8847 - 009 act8847 - 010 act8847 - 012 act8847 - 011 ch1: v npbin , 2v/div ch2: v out6 , 1v/div ch3: v out4 , 1v/div ch4: v out2, 1v/div time: 10ms/div ch1: v npbin , 2v/div ch2: v out6 , 1v/div ch3: v nrsto , 2v/div time: 20ms/div ch1: v pwren , 2v/div ch2: v out3 , 1v/div ch3: v out5 , 1v/div ch3: v out11 , 1v/div time: 1ms/div ch1: v pwren , 2v/div ch2: v out4 , 1v/div ch3: v out2 , 1v/div ch3: v out3 , 1v/div time: 1ms/div ch1: v pwren , 2v/div ch2: v out10 , 1v/div ch3: v out8 , 1v/div ch3: v out9 , 2v/div time: 1ms/div ch1: v npbin , 2v/div ch2: v npbstat , 2v/div time: 10ms/div
act8847 rev 9, 27 - june - 17 innovative power tm - 23 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. typical performance characteristics cont d (t a = 25c, unless otherwise specified.) shutdown of pwrhold and nrsto shutdown of pwrhold and out11/10/8 shutdown of pwrhold and out9/7/12 shutdown of pwrhold and out3/5/6 shutdown of pwrhold and out1/4/2 reg1 efficiency vs. output current ch1 ch2 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch4 ch1 ch2 ch3 ch4 v in = 3. 6v v in = 4.0v v in = 5.0v v out = 1.2v 100 80 60 40 20 0 efficiency (%) output current (ma) 0 1 10 100 1000 10000 act8847 - 013 act8847 - 014 act8847 - 016 act8847 - 015 act8847 - 017 act8847 - 018 ch1: v pwrhold , 2v/div ch2: v nrsto , 2v/div time: 2ms/div ch1: v pwrhold , 2v/div ch2: v out11 , 1v/div ch3: v out10 , 1v/div ch3: v out8 , 2v/div time: 400s/div ch1: v pwrhold , 2v/div ch2: v out9 , 2v/div ch3: v out7 , 2v/div ch3: v out12 , 2v/div time: 400s/div ch1: v pwrhold , 2v/div ch2: v out3 , 1v/div ch3: v out5 , 1v/div ch3: v out6 , 1v/div time: 2ms/div ch1: v pwrhold , 2v/div ch2: v out1 , 1v/div ch3: v out4 , 1v/div ch3: v out2 , 1v/div time: 1ms/div
act8847 rev 9, 27 - june - 17 innovative power tm - 24 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. typical performance characteristics cont d (t a = 25c, unless otherwise specified.) reg2 efficiency vs. output current reg3 efficiency vs. output current reg4 efficiency vs. output current reg10 @ 10ma vs. temperature v out10 @ 150ma vs. temperature reg5/6 dropout voltage vs. i out output current (ma) 0 1 10 100 1000 10000 100 80 60 40 20 0 efficiency (%) v out = 1.1v v in = 3. 6v v in = 4.0v v in = 5.0v 100 80 60 40 20 0 efficiency (%) output current (ma) 0 1 10 100 1000 10000 v out = 1.1v v in = 3. 6v v in = 4.0v v in = 5.0v temperature (c) - 40 - 20 0 20 40 60 80 100 120 140 1.205 1.200 1.195 1.190 1.185 1.180 v out (v) temperature (c) - 40 - 20 0 20 40 60 80 100 120 140 1.186 1.182 1.178 1.174 1.170 v out (v) output current (ma) 0 50 100 150 200 250 dropout voltage (mv) 400 350 300 250 200 150 100 50 0 act8847 - 020 act8847 - 021 act8847 - 022 act8847 - 024 act8847 - 023 output current (ma) 0 1 10 100 1000 10000 efficiency (%) v out = 1.2v v in = 3. 6v v in = 4.0v v in = 5.0v act8847 - 019 100 80 60 40 20 0
act8847 rev 9, 27 - june - 17 innovative power tm - 25 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. typical performance characteristics cont d (t a = 25c, unless otherwise specified.) reg5 v out vs. i out reg6 v out vs. i out reg7/8/9 dropout voltage vs. i out reg7 v out vs. i out reg8 v out vs. i out reg9 v out vs. i out dropout voltage (v) 1.200 1.160 1.120 1.080 1.040 1.000 output current (ma) 0 40 80 120 160 200 output current (ma) 0 40 80 120 160 200 dropout voltage (v) 1.200 1.160 1.120 1.080 1.040 1.000 dropout voltage (mv) 400 300 200 100 0 output current (ma) 0 50 100 150 200 250 300 350 400 output current (ma) 0 50 100 150 200 250 300 350 output voltage (v) 3.400 3.360 3.320 3.280 3.240 3.200 output current (ma) 0 50 100 150 200 250 300 350 output voltage (v) 1.900 1.860 1.820 1.780 1.740 1.700 output current (ma) 0 50 100 150 200 250 300 350 400 output voltage (v) 3.310 3.300 3.290 3.280 3.270 3.260 3.250 act8847 - 026 act8847 - 025 act8847 - 027 act8847 - 028 act8847 - 029 act8847 - 030
act8847 rev 9, 27 - june - 17 innovative power tm - 26 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. typical performance characteristics cont d (t a = 25c, unless otherwise specified.) reg10 dropout voltage vs. i out reg10 v out vs. i out reg11 dropout voltage vs. i out reg11 v out vs. i out reg12 v out vs. i out reg12 dropout voltage vs. i out output current (ma) 0 50 100 150 200 dropout voltage (mv) 250 200 150 100 50 0 output voltage (v) 1.300 1.260 1.220 1.180 1.140 1.000 output current (ma) 0 40 80 120 160 200 dropout voltage (mv) 250 200 150 100 50 0 output current (ma) 0 100 200 300 400 output current (ma) 0 100 200 300 400 dropout voltage (mv) 250 200 150 100 50 0 output voltage (v) 1.200 1.160 1.120 1.080 1.040 1.000 output current (ma) 0 50 100 150 200 250 300 350 output current (ma) 0 50 100 150 200 250 300 350 output voltage (v) 1.900 1.860 1.820 1.780 1.740 1.700 act8847 - 031 act8847 - 032 act8847 - 033 act8847 - 034 act8847 - 035 act8847 - 036
act8847 rev 9, 27 - june - 17 innovative power tm - 27 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. the act8847 is optimized for the samsung s5pc210/s5pv310 and other application processors, supporting both the power domains as well as the signal interface. the following paragraphs describe how to design act8847 with the s5pc210/s5pv310 processors. while the act8847 supports many possible configurations for powering these processors, one of the most common configurations is detailed in this datasheet. in general, this document refers to the act8847 pin names and functions. however, in cases where the description of interconnections between these devices benefits by doing so, both the act8847 pin names and the s5pc210/s5pv310 processors pin names are provided. when this is done, the s5pc210/s5pv310 pin names are located after the act8847 pin names, and are italicized and located inside parentheses. for example, pwren ( xpwrrgton ) refers to the logic signal applied to the act8847's pwren input, identifying that it is driven from the s5pc210's xpwrrgton output. system control information interfacing with the samsung s5pc210/s5pv310 processors table 1: act8847 and samsung s5pc210 power domains table 2: act8847 and samsung s5pc210 power mode act8847 re g- ulator power domain default voltage max cu r r e n t power up order on/off @ sleep type reg1 vdd_mem, vdd12_slp_on 1.2v 1.5a 7 on dc/dc step down reg2 vdd_arm 1.2v 2.8a 3 off dc/dc step down reg3 vdd_g3d 1.1v 2.8a 4 off dc/dc step down reg4 vdd_int 1.1v 1.5a 2 off dc/dc step down reg5 vdd_pll 1.1v 150ma 5 off low - noise ldo reg6 vdd_alive 1.1v 150ma 1 on low - noise ldo reg7 vdd33_slp_on 3.3v 350ma 6 on low - noise ldo reg8 vdd18_slp_off 1.8v 350ma 11 off low - noise ldo reg9 vdd33_slp_off 3.3v 350ma 12 off low - noise ldo reg10 vdd12_slp_off 1.2v 150ma 10 off low input - voltage ldo reg11 vdd11_slp_off 1.1v 350ma 9 off low input - voltage ldo reg12 vdd18_slp_on 1.8v 350ma 8 on low input - voltage ldo reg13 vdd_rtc 1.8v 50ma 0 on always - on ldo power mode control state power domain state quiescent current all on pwrhld is asserted, pwren is asserted all regulators on 0.6ma sleep pwrhld is asserted, pwren is de - asserted reg1/6/7/12/13 are on, all other regulators are off. 200 a shutdown pwrhld is de - asserted, pwren is de - asserted, vinl2 > 2.6v reg13 is on, all other regula- tors are off. 10 a all off pwrhld is de - asserted, pwren is de - asserted, vinl2 < 2.2v all regulators off. 5 a
act8847 rev 9, 27 - june - 17 innovative power tm - 28 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. table 3: act8847 and s5pc210 signal interface ? act8847 direction samsung s5pc210 pwren xpwrrgton scl xi2cscl[0] sda xi2csda[0] vselr2 dvs_gpio1 gpio1/vselr3 dvs_gpio2 gpio2/vselr4 dvs_gpio3 nrsto xnreset nirq xeint0 npbstat xeint1 pwrhld xpshold ? : typical connections shown, actual connections may vary. control signals enable inputs the act8847 features a variety of control inputs, which are used to enable and disable outputs depending upon the desired mode of operation. pwren, pwrhld are logic inputs, while npbin is a unique, multi - function input. npbin multi - function input the act8847 features the npbin multi - function pin, which combines system enable/disable control with a hardware reset function. select either of the two pin functions by asserting this pin, either through a direct connection to ga, or through a 50k resistor to ga, as shown in figure 2. manual reset function the second major function of the npbin input is to provide a manual - reset input for the processor. to manually - reset the processor, drive npbin directly to ga through a low impedance (less than 2.5k ). an internal timer detects the duration of the mr event: short press / soft - reset: if the mr is asserted for less than 4s, act8847 commences a soft - reset operation where nrsto immediately asserts low, then remains asserted low until the npbin input is de - asserted and the reset time - out period expires. a status bit, srstat[ ] , is set after a soft - reset event. the srstat[ ] bit is automatically cleared to 0 after read. after short press, set wdsren[ ] to 1 about 1s after nrsto de - assert then clear wdsren[ ] for properly shutdown sequence. long press / power - cycle: if the mr is asserted for more than 4s, act8847 commences a power cycle routine in which case all regulators are turned off and then turned back on. a status bit, pcstat[ ], is set after the power cycle. the pcstat[ ] bit is automatically cleared to 0 after read. npbstat output npbstat is an open - drain output that reflects the state of the npbin input; npbstat is asserted low whenever npbin is asserted, and is high - z otherwise. this output is typically used as an interrupt signal to the processor, to initiate a software - programmable routine such as operating mode selection or to open a menu. connect npbstat to an appropriate supply voltage through a 10k or greater resistor. figure 2: npbin input n p b i n a c t 8 8 4 7 m a n u a l r e s e t p u s h - b u t t o n n p b s t a t m a n u a l r e s e t d e t e c t p u s h - b u t t o n d e t e c t t o c p u i n l 2 v i o 5 0 k
act8847 rev 9, 27 - june - 17 innovative power tm - 29 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. nrsto output nrsto is an open - drain output which asserts low upon startup or when manual reset is asserted via the npbin input. when asserted on startup, nrsto remains low until reset time - out period expires. when asserted due to manual - reset, nrsto immediately asserts low, then remains asserted low until the npbin input is de - asserted and the reset time - out period expires. connect a 10k or greater pull - up resistor from nrsto to an appropriate voltage supply. nirq output nirq is an open - drain output that asserts low any time an interrupt is generated. connect a 10k or greater pull - up resistor from nirq to an appropriate voltage supply. nirq is typically used to drive the interrupt input of the system processor. many of the act8847's functions support interrupt - generation as a result of various conditions. these are typically masked by default, but may be unmasked via the i 2 c interface. for more information about the available fault conditions, refer to the appropriate sections of this datasheet. push - button control the act8847 is designed to initiate a system enable sequence when the npbin multi - function input is asserted. once this occurs, a power - on sequence commences, as described below. the power - on sequence must complete and the microprocessor must take control (by asserting pwrhld) before npbin is de - asserted. if the microprocessor is unable to complete its power - up routine successfully before the user releases the push - button, the act8847 automatically shuts the system down. this provides protection against accidental or momentary assertions of the push - button. if desired, longer push - and - hold times can be implemented by simply adding an additional time delay before asserting pwren or pwrhld. control sequences the act8847 features a variety of control sequences that are optimized for supporting system enable and disable, as well as sleep mode of the samsung s5pc210 / s5pv310 processors. enabling/disabling sequence a typical enable sequence is initiated whenever the npbin is asserted low via 50k resistance. the power control diagram is shown in figure 3. during the boot sequence, the microprocessor must assert pwrhld ( xpshold) , and pwren (xpwrrgton) , to ensure that the system remains powered after npbin is released. once the power - up routine is completed, the system remains enabled after the push - button is released as long as pwrhld is asserted high. if the processor does not assert pwrhld before the user releases the push - button, the boot - up sequence is terminated and all regulators are disabled. this provides protection against "false - enable", when the push - button is accidentally depressed, and also ensures that the system remains enabled only if the processor successfully completes the boot - up sequence. as with the enable sequence, a typical disable sequence is initiated when the user presses the push - button, which interrupts the processor via the npbstat output. the actual disable sequence is completely software - controlled, but typically involved initiating various clean - up processes before the processor finally de - asserts pwrhld. sleep mode sequence the act8847 supports s5pc210 / s5pv310 processors sleep mode operation. once a successful power - up routine has been completed, sleep mode may be initiated through a variety of software - controlled mechanisms. sleep mode is typically initiated when the user presses the push - button during normal operation. pressing the push - button asserts the npbin input, which asserts the npbstat output, which interrupts the processor. in response to this interrupt the processor should de - assert pwren (xpwrrgton) , disabling reg2/3/4/5/8/9/10/11. pwrhld should remain asserted during sleep mode so that reg1/6/7/12 remain enabled. the act8847 wakes up from sleep mode when either the push - button and/or pwren (xpwrrgton) is asserted. in either case, reg2/3/4/5/8/9/10/11 are enable which allow the system to resume normal operation.
act8847 rev 9, 27 - june - 17 innovative power tm - 30 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. watch - dog supervision the act8847 features a watchdog supervisory function. an internal watchdog timer of 4s is unmasked by setting either wdsren[ ] or wdpcen [ ] bit to one. once enabled, the watchdog timer is reset whenever there is i2c activity for the pmu. in the case where the system software stops responding and that there is no i2c transactions for 4s, the watchdog timer expires. as a result, the pmu either perform a soft - reset or power cycle, depending on whether wdsren [ ] or wdpcen [ ] is set. software - initiated power cycle act8847 supports software - initiated power cycle. once the sipc[ ] bit is set, the pmu waits for 8ms and then initiate a power cycle to restart the entire system. figure 3: power control sequence 6 0 m s s l e e p / w a k e u p s e q u e n c e e n a b l e s e q u e n c e n p b i n n r s t o p w r e n ( v d d a l i v e ) o u t 6 o u t 2 / 3 / 5 2 m s p w r h l d u v l o m a i n b a t t e r y o u t 1 3 s h u t d o w n s e q u e n c e 2 m s 4 m s 8 m s o u t 4 0 . 5 m s 9 3 % o f v o u t 6 9 3 % o f v o u t 2 o u t 7 o u t 1 o u t 1 2 o u t 1 1 o u t 1 0 9 3 % o f v o u t 1 1 o u t 8 0 . 5 m s o u t 9 1 m s 0 . 5 m s 1 m s 2 m s 2 m s 9 3 % o f v o u t 1 1 2 m s 2 m s 0 . 5 m s 1 m s 9 3 % o f v o u t 2 2 m s
act8847 rev 9, 27 - june - 17 innovative power tm - 31 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. figure 4: act8847qm502 - t power control sequence for freescale i.mx6 platform. a c t 8 8 4 7 q m 5 0 2 - t 4 0 m s e n a b l e s e q u e n c e n p b i n n r s t o p w r h l d o u t 9 o u t 1 u v l o m a i n p o w e r o u t 1 3 s h u t d o w n s e q u e n c e 2 m s 1 m s 9 3 % o f v o u t 9 9 3 % o f v o u t 1 o u t 8 o u t 1 0 o u t 7 1 m s o u t 2 o u t 4 o u t 3 0 . 5 m s 9 3 % o f v o u t 2 1 m s 0 . 5 m s 0 . 5 m s 0 . 5 m s 9 3 % o f v o u t 8 9 3 % o f v o u t 1 0 9 3 % o f v o u t 7 9 3 % o f v o u t 4 p w r e n k e e p d i s a b l e f o r r e g 5 , r e g 6 , r e g 1 1 a n d r e g 1 2 , a p c a n t u r n o n t h e m t h r o u g h i 2 c i f n e e d .
act8847 rev 9, 27 - june - 17 innovative power tm - 32 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. i 2 c interface the act8847 features an i 2 c interface that allows advanced programming capability to enhance overall system performance. to ensure compatibility with a wide range of system processors, the i 2 c interface supports clock speeds of up to 400khz ( fast - mode operation) and uses standard i 2 c commands. i 2 c write - byte commands are used to program the act8847, and i 2 c read - byte commands are used to read the act8847 s internal registers. the act8847 always operates as a slave device, and is addressed using a 7 - bit slave address followed by an eighth bit, which indicates whether the transaction is a read - operation or a write - operation, [1011010x]. sda is a bi - directional data line and scl is a clock input. the master device initiates a transaction by issuing a start condition, defined by sda transitioning from high to low while scl is high. data is transferred in 8 - bit packets, beginning with the msb, and is clocked - in on the rising edge of scl. each packet of data is followed by an acknowledge (ack) bit, used to confirm that the data was transmitted successfully. for more information regarding the i 2 c 2 - wire serial interface, go to the nxp website: http://www.nxp.com. housekeeping functions programmable battery voltage monitor the act8847 features a programmable battery - voltage monitor, which monitors the voltage at inl2 (which should be connected directly to the battery) and compares it to a programmable threshold voltage. the vbatmon comparator is designed to be immune to noise resulting from switching, load transients, etc. the batmon comparator is disable by default; to enable it, set the batlev[3:0] register to one of the value in table 4. note that there is a 200mv hysteresis between the rising and falling threshold for the comparator. the vbatdat [ - ] bit reflects the output of the batmon comparator. the value of vbatdat[ ] is 1 when v inl2 < batlev; value is 0 otherwise. the vbatmon comparator can generate an interrupt when v inl2 is lower than batlev[ ] voltage. the interrupt is masked by default by can be unmasked by setting vbatmsk[ ] = 1. table 4: batlev falling threshold thermal protection the act8847 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. thermal interrupt if the thermal interrupt is unmasked (by setting ntmsk[ ] to 1), act8847 can generate an interrupt when the die temperature reaches 1 20c (typ). thermal protection if the act8847 die temperature exceeds 160c, the thermal protection circuitry disables all regulators and prevents the regulators from being enabled until the ic temperature drops by 20c (typ). functional descripti on batlev[3:0] batlev falling threshold 0000 2.5 0001 2.6 0010 2.7 0011 2.8 0100 2.9 0101 3.0 0110 3.1 0111 3.2 1000 3.3 1001 3.4 1010 3.5 1011 3.6 1100 3.7 1101 3.8 1110 3.9 1111 4.0
act8847 rev 9, 27 - june - 17 innovative power tm - 33 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. general description reg1, reg2, reg3, and reg4 are fixed - frequency, current - mode, synchronous pwm step - down converters that achieves peak efficiencies of up to 97%. these regulators operate with a fixed frequency of 2.25mhz, minimizing noise in sensitive applications and allowing the use of small external components. additionally, reg1, reg2, reg3, and reg4 are available with a variety of standard and custom output voltages, and may be software - controlled via the i 2 c interface for systems that require advanced power management functions. 100% duty cycle operation reg1, reg2, reg3, and reg4 are capable of operating at up to 100% duty cycle. during 100% duty cycle operation, the high - side power mosfets are held on continuously, providing a direct connection from the input to the output (through the inductor), ensuring the lowest possible dropout voltage in battery powered applications. operating mode by default, reg1, reg2, reg3, and reg4 operate in fixed - frequency pwm mode at medium to heavy loads, then transition to a proprietary power - saving mode at light loads in order to save power. synchronous rectification reg1, reg2, reg3, and reg4 each feature integrated synchronous rectifiers, maximizing efficiency and minimizing the total solution size and cost by eliminating the need for external rectifiers. soft - start reg1, reg2, reg3, and reg4 include internal 400 us soft - start ramps which limit the rate of change of the output voltage, minimizing input inrush current and ensuring that the output powers up in a monotonic manner that is independent of loading on the outputs. this circuitry is effective any time the regulator is enabled, as well as after responding to a short - circuit or other fault condition. compensation reg1, reg2, reg3, and reg4 utilize current - mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. no compensation design is required; simply follow a few simple guide lines described below when choosing external components. input capacitor selection the input capacitor reduces peak currents and noise induced upon the voltage source. a 10 f ceramic capacitor is recommended for each regulator in most applications. output capacitor selection reg1, reg2, reg3, and reg4 were designed to take advantage of the benefits of ceramic capacitors, namely small size and very - low esr. reg1, reg2, reg3 and reg4 are designed to operate with 33uf or 44uf output capacitor over most of their output voltage ranges, although more capacitance may be desired depending on the duty cycle and load step requirements. two of the most common dielectrics are y5v and x5r. whereas y5v dielectrics are inexpensive and can provide high capacitance in small packages, their capacitance varies greatly over their voltage and temperature ranges and are not recommended for dc/dc applications. x5r and x7r dielectrics are more suitable for output capacitor applications, as their characteristics are more stable over their operating ranges, and are highly recommended. inductor selection reg1, reg2, reg3, and reg4 utilize current - mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. these devices were optimized for operation with 2.2 h or 1 h inductors. choose an inductor with a low dc - resistance, and avoid inductor saturation by choosing inductors with dc ratings that exceed the maximum output current by at least 30%. configuration options output voltage programming by default, each regulator powers up and regulates to its default output voltage. for reg2, reg3 and reg4, the output voltage is selectable by setting corresponding vsel pin that when vsel is low, output voltage is programmed by vset0[ - ] bits, and when vsel is high, output voltage is programmed by vset1[ - ] bits. also, once the system is enabled, each regulator's output voltage may be independently programmed to a different value. program the output voltages via the i 2 c serial interface by writing to the regulator's vset0[ - ] register if vsel is low or vset1[ - ] register if vsel is high as shown in table 5. step - down dc/dc regu lators
act8847 rev 9, 27 - june - 17 innovative power tm - 34 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. enable / disable control during normal operation, each buck may be enabled or disabled via the i 2 c interface by writing to that regulator's on[ ] bit. ok[ ] and output fault interrupt each dc/dc features a power - ok status bit that can be read by the system microprocessor via the i 2 c interface. if an output voltage is lower than the power - ok threshold, typically 7% below the programmed regulation voltage, that regulator's ok[ ] bit will be 0. if a dc/dc's nfltmsk[ - ] bit is set to 1, the act8847 will interrupt the processor if that dc/dc's output voltage falls below the power - ok threshold. in this case, nirq will assert low and remain asserted until either the regulator is turned off or back in regulation, and the ok[ ] bit has been read via i 2 c. pcb layout considerations high switching frequencies and large peak currents make pc board layout an important part of step - down dc/dc converter design. a good design minimizes excessive emi on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. step - down dc/dcs exhibit discontinuous input current, so the input capacitors should be placed as close as possible to the ic, and avoiding the use of via if possible. the inductor, input filter capacitor, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. the ground nodes for each regulator's power loop should be connected at a single point in a star - ground configuration, and this point should be connected to the backside ground plane with multiple via. the output node for each regulator should be connected to its corresponding outx pin through the shortest possible route, while keeping sufficient distance from switching nodes to prevent noise injection. finally, the exposed pad should be directly connected to the backside ground plane using multiple via to achieve low electrical and thermal resistance. regx /vset [2:0] regx/vset[5:3] 000 001 010 011 100 101 110 111 000 0.600 0.800 1.000 1.200 1.600 2.000 2.400 3.200 001 0.625 0.825 1.025 1.250 1.650 2.050 2.500 3.300 010 0.650 0.850 1.050 1.300 1.700 2.100 2.600 3.400 011 0.675 0.875 1.075 1.350 1.750 2.150 2.700 3.500 100 0.700 0.900 1.100 1.400 1.800 2.200 2.800 3.600 101 0.725 0.925 1.125 1.450 1.850 2.250 2.900 3.700 110 0.750 0.950 1.150 1.500 1.900 2.300 3.000 3.800 111 0.775 0.975 1.175 1.550 1.950 2.350 3.100 3.900 table 5 : regx /vset[ ] output voltage setting
act8847 rev 9, 27 - june - 17 innovative power tm - 35 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. low - noise, low - dropo ut linear regulators general description act8847 features eight low - noise, low - dropout linear regulators (ldos) that supply up to 350ma . three of these ldos (reg10, reg11, and reg12) supports extended input voltage range down to 1.7v. each ldo has been optimized to achieve low noise and high - psrr. output current limit each ldo contains current - limit circuitry featuring a current - limit fold - back function. during normal and moderate overload conditions, the regulators can support more than their rated output currents. during extreme overload conditions, however, the current limit is reduced by approximately 30%, reducing power dissipation within the ic. compensation the ldos are internally compensated and require very little design effort, simply select input and output capacitors according to the guidelines below. input capacitor selection each ldo requires a small ceramic input capacitor to supply current to support fast transients at the input of the ldo. bypassing each inl pin to ga with 1 f. high quality ceramic capacitors such as x7r and x5r dielectric types are strongly recommended. output capacitor selection each ldo requires a small 2.2 f ceramic output capacitor for stability . for best performance, each output capacitor should be connected directly between the output and ga pins, as close to the output as possible, and with a short, direct connection. high quality ceramic capacitors such as x7r and x5r dielectric types are strongly recommended. configuration options output voltage programming by default, each ldo powers up and regulates to its default output voltage. once the system is enabled, each output voltage may be independently programmed to a different value by writing to the regulator's vset[ - ] register via the i 2 c serial interface as shown in table 5. enable / disable control during normal operation, each ldo may be enabled or disabled via the i 2 c interface by writing to that ldo's on[ ] bit. output discharge each of the ldos features an optional output discharge function, which discharges the output to ground through a 1.5k resistance when the ldo is disabled. this feature may be enabled or disabled by setting dis[ - ]; set dis[ - ] to 1 to enable this function, clear dis[ - ] to 0 to disable it. ok[ ] and output fault interrupt each ldo features a power - ok status bit that can be read by the system microprocessor via the interface. if an output voltage is lower than the power - ok threshold, typically 11% below the programmed regulation voltage, the value of that regulator's ok[ - ] bit will be 0. if a ldo's nfltmsk[ - ] bit is set to 1, the act8847 will interrupt the processor if that ldo's output voltage falls below the power - ok threshold. in this case, nirq will assert low and remain asserted until either the regulator is turned off or back in regulation, and the ok[ - ] bit has been read via i 2 c. pcb layout considerations the act8847 s ldos provide good dc, ac, and noise performance over a wide range of operating conditions, and are relatively insensitive to layout considerations. when designing a pcb, however, careful layout is necessary to prevent other circuitry from degrading ldo performance. a good design places input and output capacitors as close to the ldo inputs and output as possible, and utilizes a star - ground configuration for all regulators to prevent noise - coupling through ground. output traces should be routed to avoid close proximity to noisy nodes, particularly the sw nodes of the dc/dcs. refbp is a noise - filtered reference, and internally has a direct connection to the linear regulator controller. any noise injected onto refbp will directly affect the outputs of the linear regulators, and therefore special care should be taken to ensure that no noise is injected to the outputs via refbp. as with the ldo output capacitors, the refbp bypass capacitor should be placed as close to the ic as possible, with short, direct connections to the star - ground. avoid the use of via whenever possible. noisy nodes, such as from the dc/dcs, should be routed as far away from refbp as possible.
act8847 rev 9, 27 - june - 17 innovative power tm - 36 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. general description reg13 is an always - on, low - dropout linear regulator (ldo) that is optimized for rtc and backup - battery applications. reg13 features low - quiescent supply current, current - limit protection, and reverse - current protection, and is ideally suited for always - on power supply applications, such as for a real - time clock, or as a backup - battery or super - cap charger. reverse - current protection reg13 features internal circuitry that limits the reverse supply current to less than 1a when the input voltage falls below the output voltage, as can be encountered in backup - battery charging applications. reg13's internal circuitry monitors the input and the output, and disconnects internal circuitry and parasitic diodes when the input voltage falls below the output voltage, greatly minimizing backup battery discharge. typical application voltage regulators reg13 is ideally suited for always - on voltage - regulation applications, such as for real - time clock and memory keep - alive applications. this regulator requires only a small ceramic capacitor with a minimum capacitance of 0.47 f for stability. for best performance, the output capacitor should be connected directly between the output and ga, with a short and direct connection. figure 5: typical application of rtc ldo backup battery charging reg13 features a constant current - limit, which protects the ic under output short - circuit conditions as well as provides a constant charge current, when operating as a backup battery charger. always - on ldo (reg13) a c t 8 8 4 7 r t c s u p p e r c a p o r b a c k - u p b a t t e r y o u t 1 3
act8847 rev 9, 27 - june - 17 innovative power tm - 37 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. the gpio3, the gpio4, the gpio5, and the gpio6 are configured as pwm led drivers, which could support up to 6ma current with programmable frequency and duty cycle. set pwmxen[ ] bit to 1 to enable pwm function of gpiox. pwm frequence selection each led driver may be independently programmed to a different frequency by writing to the gpio s fre[2:0] register via the i 2 c serial interface as shown in table 6. table 6: gpiox/fre[ ] pwm frequency setting pwm duty cycle selection each led driver may be independently programmed to a different duty cycle by writing to the gpio s duty[3:0] register via the i 2 c serial interface as shown in table 7. table 7: gpiox/duty[ ] pwm frequency setting pwm led drivers gpiox/fre[2:0] pwm frequency [hz] 000 0.25 001 0.5 010 1 011 2 100 128 101 256 gpiox/duty[3:0] pwm duty cycle [%] 0000 6.25 0001 12.5 0010 18.75 0011 25 0100 31.25 0101 37.5 0110 43.75 0111 50 1000 56.25 1001 62.5 1010 68.75 1011 75 1100 81.25 1101 87.5 1110 93.75 1111 100
act8847 rev 9, 27 - june - 17 innovative power tm - 38 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. cmi options this section provides the basic default configuration settings for the act8847 cmi options. refer to each option s application note for the comprehensive list of default settings. cmi 102: act8847qm102 - t cmi 102 is optimized for imx6ul/imx6ull processors. reg6, reg8, reg9, reg10, reg11, and reg12 are not enabled by default with this cmi, but can be enabled via i2c. typical connections to the imx6ul are shown below. sequencing act8846 regulator voltage imx6ul function imx6ul pins reg1 1.35v ddr3l supply nvcc_dram reg2 3.3v gpio supplies nvcc_xxxx reg3 3.8v system supply n/a reg4 1.3v core supply vdd_soc_in reg5 3.3v system supply for startup sequencing n/a reg7 3.3v vdd high supply vdd_high_in reg13 3.3v secure nvm storage sup- ply vdd_snvs_in rail vset0 voltage (v) vset1 voltage (v) sequencing input trigger startup delay (us) soft - start (us) vin 5 5 n/a n/a n/a reg13 3.3 3.3 vin_uvlo 400 400 reg7 3.3 3.3 gpio1 32000 100 reg1 1.35 1.35 out7 2000 400 reg4 1.3 1.3 out1 2000 400 reg2 3.3 3.3 out4 2000 400 reg5 3.3 3.3 out2 0 100 reg3 3.8 3.8 pwren and pwrhld 2000 400 reg6 off off n/a n/a n/a reg8 off off n/a n/a n/a reg9 off off n/a n/a n/a reg10 off off n/a n/a n/a reg11 off off n/a n/a n/a reg12 off off n/a n/a n/a
act8847 rev 9, 27 - june - 17 innovative power tm - 39 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. hardware configuration the following hardware connections are required to achieve the specified startup sequencing. connect a 2.2uf capacitor between gpio1 and gpio2 connect a 1mohm resistor from gpio2 to ga. connect a 51kohm resistor between gpio3 and npbin. connect a 10kohm resistor between reg7 and pwrhld. startup the act8847qm102 - t has three startup sequences. reg13. when power is applied to the ic. reg13 automatically turns on when input power is applied and the input voltage is above uvlo. reg7/1/4/2/5. reg7/1/4/2/5 turn on when gpio1 is pulled high. reg7/1/4/2/5 are latched on after reg7 goes into regulation and pulls pwrhld high. gpio1 may remain high or return to a logic low after this time. reg7/1/4/2/5 stay on in either case. reg3. the enable input for reg3 is the and of pwrhld and pwren. note that pwrhld should be connected to reg7. reg3 is intended to be turned on after reg7/1/4/2/5 are in regulation. once reg7/1/4/2/5 are in regulation and pwrhld is high, reg3 can be independently enabled and disabled with pwren.
act8847 rev 9, 27 - june - 17 innovative power tm - 40 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. shutdown reg3 shuts down when either pwren or pwrhld go low. reg7/1/4/2/5 shut down by pressing npbin for longer than 4s or by pulling pwrhld low while gpio1 is low. npbin npbin retains the short and long press functionality described earlier in the datasheet. a short press pulls nrsto low to reset the processor. a long press powers down all outputs. the outputs restart per the defined sequencing when npbin is released after a long press nrsto nrsto is gated by reg5 and should be pulled up to reg5. nrsto has a 40ms delay after reg5 goes into regulation.
act8847 rev 9, 27 - june - 17 innovative power tm - 41 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. tqfn66 - 48 package outline and dimensions active - semi, inc. reserves the right to modify the circuitry or specifications without notice. users should evaluate each product to make sure that it is suitable for their applications. active - semi products are not intended or authorized for use as critical components in life - support devices or systems. active - semi, inc. does not assume any liability arising out of the use of any product or circuit described in this datasheet, nor does it convey any patent license. active - semi and its logo are trademarks of active - semi, inc. for more information on this and other products, contact sales@active - semi.com or visit http://www.active - semi.com . is a registered trademark of active - semi. symbol dimension in millimeters dimension in inches min max min max a 0.700 0.800 0.032 0.036 a1 0.200 ref 0.008 ref a2 0.000 0.000 0.050 0.002 b 0.150 0.250 0.006 0.010 d 6.00 0.24 e 6.00 0.24 d2 4.15 4.40 0.166 0.176 e2 4.15 4.40 0.166 0.176 e 0.400 bsc 0.016 bsc l 0.300 0.500 0.012 0.020 r 0.300 0.012 e d d / 2 e / 2 a a 2 d 2 e 2 e b r l a 1
act8847 rev 9, 27 - june - 17 innovative power tm - 42 - www.active - semi.com copyright ? 2015 - 2017 active - semi, inc. activepmu tm is a trademark of active - semi. i 2 c tm is a trademark of nxp. revision history revision date description 8 17 - jan - 17 1. added opn act8847qm503 9 27 - june - 17 1. added opn act8847qm102

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