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n 567 hp33 0 otp data sheet publication release date: jan . 20 1 3 - 1 - revision a 2 table of contents 1. general description ................................ ................................ ................................ .......... 2 2. features ................................ ................................ ................................ ................................ . 2 3. pin descripti on ................................ ................................ ................................ ..................... 4 4. block diagram ................................ ................................ ................................ ...................... 5 5. electrical character istics ................................ ................................ ........................... 5 5.1 abso lute maximum ratings ................................ ................................ ............................... 5 5.2 d . c . c haracteristics ................................ ................................ ................................ ........... 6 5.3 a . c . characteristics ................................ ................................ ................................ ........... 7 6. typical application circuits ................................ ................................ .......................... 8 7. revision history ................................ ................................ ................................ ................ 12
n 567 hp33 0 otp data sheet publication release date: jan . 20 1 3 - 2 - revision a 2 1. general description the n567hp 33 0 is an advanced 8 - ch melody ic with 8mbit embedded otp. it combines with the technology of 8 - bit 65c02 core and new 4 - bit or 5 - bit mdpcm synthesizer to implement sophisticated applications in high level of sound quality. the n567hp 33 0 provides 32 i/o pins , 384 bytes ram , ir carrier , and serial interface manag ement (sim) for various interactive toys or cartridge applications . it contains 6 led output pins with 64 - level control for the application of motor control or led fading . in addition, n567hp 33 0 provides high quality pwm mode audio output to save power dur ing playback . it also built in internal oscillation to save component cost and control the system frequency in a precise range. furthermore, n567hp 33 0 provides watch dog timer and low voltage reset to prevent latch - up situation occurring as power bouncing or vibration . the n567hp 33 0 build in 8mbit otp to cover the families of n567g (4 - ch), n567k (6 - ch) and n567h (8 - ch). 2. features ? wide range of operating voltage: ? 8 mhz @ 3. 0 volt ~ 5.5 volt ? 6 mhz @ 2.4 volt ~ 5.5 volt oscillator ? internal oscillator (trim) ? s ystem clock setting: 4 096k hz, 6 144k hz, and 8 192k hz ? x tal o scillator ? e xternal cry s tal : 8mhz~16mhz for system clock 4m~8mhz ? power management: ? stop mode for stopping all ic operations ? status changes of the ip0 and bp0~bp2 pins can wake up the chip ? prov ides up to 8 inputs and 24 i/o pins ? audio output : 1 speaker output ? dac mode: typical c urrent output 3ma or 5ma , resolution 1 0+3 bit s , without nois e shaping ? pwm : d irect driv e speaker with 12 - bit resolution. support noise shaping . ? f/w s peech synthesis: ? mu ltiple formats ? new 4 - bit mdpcm (nm4), 5 - bit mdpcm (mdm) , 4 - bit mdpcm (md4), 4 - bit adpcm (apm), 8 - bit log pcm (lp8) ? pitch shi ft adpcm for voice changer application ? dual sample rate in voice synthesis ? f/w melody synthesis: ? 8 melody channels that can emula te characteristics of musical instruments ? multi - midi files simultaneous
n 567 hp33 0 otp data sheet publication release date: jan . 20 1 3 - 3 - revision a 2 ? multi - midi channels dynamic control ? more midi events are supported for colorful melody playback, such as modulation wheel, pitch - bending, pedal, pitch - shift, and vibrato etc. ? speech and melody c an be playing at the same time ? 2 channels speech + 6 channel s wavetable melody ? 1 channel speech + 7 channels wavetable melody ? 8 channels wavetable melody ? built - in ir carrier ge neration circuit to simplify firmware ir application ? built - in ti merg 1 for general purpose applications ? harmonized synchronization among midi, speech, led, and motor ? build - in 6 led outputs (3 pairs) with 64 - level control of brightness ? buil d - in watch - dog timer (wdt) and low voltage reset (lv r ) ? provide serial inte rface management (sim) to access the external memory ? w551cxx x ? spi flash /rom ? support powerscript tm for developing codes in easy way ? full - fledged development system ? source - level ice debugger (assembly & powerscript tm format) ? ultra_ i/o tm tool for e vent sy nchronization mechanism ? ice system with usb port ? user - friendly gui environment ? available package form: ? cob is essential
n 567 hp33 0 otp data sheet publication release date: jan . 20 1 3 - 4 - revision a 2 3. pin description pin name i/o function reset b in ic reset input with an internal pull - up resistor , low active . osc i n i main - clock oscillation input for x tal mode . build - in r osc by mask option . oscout o main - clock oscillation out put for x tal mode . ip0 0~ip07 in general input port with pull - high selection. each input pin can be programmed to generate interrupt reques t and used to release ic from stop mode. bp0 0~bp07 i/o general input/output pins. when used as output pin, it can be open C dra in or cmos type and with high sink capability . when set as input pin, there may have a pull - high option and generate interrupt req uest to release ic from stop mode. when bp0 7 is used as output pin, it can be the ir transmis sion carrier . bp00~bp05 are used as 6 led outputs with 64 - level control (by pair) . bp0 0~bp03 sh are pins to program otp bp1 0~bp17 i/o general input/output pins. wh en used as output pin, it can be open C drain or cmos type. when used as input pin, there may have a pull - high option and generate interrupt request to release ic from stop mode. when serial interface management (sim) is enabled , and set memory type as w551c , bp 10~bp12 are used to be an interface with the external memory, w551cxxx . if set memory to spi f lash, bp 1 0~bp13 are used to be an interface with the external memory, spi flash . bp2 0~bp27 i/o general input/output pins. when used as output pin, it can be open C drain or cmos type. when used as input pin, there may have a pull - high option and generate interrupt request to release ic from stop mode. pwm + /dac o pwm driver positive output or current type dac output pwm - o pwm driver negative output v dd power positive power supply for up and peripherals vss power negative power supply for up and peripherals vdd _ spk power positive power supply for speaker driver vss _ spk power negative power supply for speaker driver vdd _sim power positive power supply for s erial i nterface management (sim) bp10~bp13 for non - sim application, it should be connect ed to v dd to keep normal standby current. v33o o for 3 battery (3.3v~5.5v) application, add capacito r 0.1uf to shunt between v33o and gnd as power stability for regula tor output. for 2 battery (2.4 v~3.6v) application, v33o will connect to vdd directly . vpp power high power to program otp v33osc i power for oscillator . no connect. test b i test pad . no connect. note: as program otp, the bp 0 0 ~ bp 0 3, vdd, vss, r esetb and vpp pin will be used
n 567 hp33 0 otp data sheet publication release date: jan . 20 1 3 - 5 - revision a 2 4. block diagram 5. electrical character istics 5.1 absolute maximum ratings parameter rating unit supply voltage to ground potential - 0.3 to +7.0 v d.c. voltage on any pin to ground potential - 0.3 to v dd +0.3 v operating temperature 0 to +70 ? c storage temperature - 55 to +150 ? c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. timing generator 8 bits up data ram program rom speaker driver interrupt controller timers & hq generator i/o wdt lvr mixer address/data bus bp10~17 pwm+ /dac resetb pwm- ip00~07 oscout oscin serial interface bp10~13 bp20~27 bp00~07
n 567 hp33 0 otp data sheet publication release date: jan . 20 1 3 - 6 - revision a 2 5.2 d . c . c haracteristics (v dd ? v ss = 4.5 v, f m = 8 mhz, ta = 25 ? parameter sym . test conditions spec. unit m in . t yp . m ax . operating voltage v dd f sys = 6 mhz 2.4 - 5.5 v f sys = 8 mhz 3. 0 - 5.5 v operating current i op f sys = 8mhz , n ormal operation - 8 12 ma standby current i sb stop mode - - 10 ? a input low voltage v il all input pins v ss - 0.3 v dd v input high voltage v ih all input pins 0.7 v dd - v dd v input current i/o pins i in 1 v in = 0v , pulled - high resistor = 500k ohm - 5 - 9 - 14 ? a input current i/o pins i in 2 v in = 0v , pulled - high resistor = 150k ohm - 15 - 30 - 45 ? a output current (bp0) i ol v dd = 3v, v out = 0.4v 8 12 - ma i oh v dd = 3v, v out = 2.6v - 4 - 8 - ma output current (bp1, bp2) i ol v dd = 3v, v out = 0.4v 4 6 - ma i oh v dd = 3v, v out = 2.6v - 4 - 8 - ma dac full scale current i dac v dd = 4.5v, rl = 100 ? - 2.4 - 4.0 - 3.0 - 5.0 - 3.6 - 6.0 ma output current pwm+ / pwm - i ol1 rl= 8 ohm, [pwm+] --- [rl] --- [pwm - ] +200 - - ma ioh1 - 200 - - ma
n 567 hp33 0 otp data sheet publication release date: jan . 20 1 3 - 7 - revision a 2 5.3 a . c . c haracteristics (v dd - v ss = 4.5 v, f m = 8 mhz, ta = 25 ? parameter sym . test conditions spec. unit m in . t yp . m ax . main - clock f m rosc build - in, @3.0~5.5v 3973 4096 4218 k hz rosc build - in, @3.0~5.5v 5959 6144 6328 rosc build - in, @3.0~5.5v 7946 8 192 8437 main - clock f m rosc build - in, @2.4~3.6v 3973 4096 4218 khz rosc build - in, @2.4~3.6v 5959 6144 6328 main - clock wake - up stable time t wsm 2^16 clock cycle 8 - 16 ms
n 567 hp33 0 otp data sheet publication release date: jan . 20 1 3 - 8 - revision a 2 6. typical application circuit s (a) 3 - battery applic ation with internal o scillator (trim) notes: 1. for three batteries application, v33o should shunt a 0.1 uf capacitor to gnd and can t connect to vdd. 2. rosc is built in n567h chip internally. user needn t connect rosc resistor to os cin pin. 3. the 4.7uf is necessary for power stability. 4. the rs value is suggested in 270 ? ~ 1k ? to limit too large dac output current flowing into transistor. 5. the vdd_sim pad must be connected to vdd for non - sim application. 6. the above application circuits ar e for reference only. no warranty for mass production. n 5 6 7 h p 3 3 0 o s c i n v d d _ s p k v s s r e s e t b p w m + / d a c v d d p w m - v d d _ s p k 4 . 5 v b p 0 0 | b p 0 7 b p 1 0 | b p 1 7 b p 2 0 | b p 2 7 r s v d d _ s i m i p 0 0 | i p 0 7 v s s _ s p k o s c o u t p w m + s p k / d a c : d a c c i r c u i t 4 . 7 u f v p p v 3 3 o s c t e s t b v 3 3 o 0 . 1 u f
n 567 hp33 0 otp data sheet publication release date: jan . 20 1 3 - 9 - revision a 2 (b) 2 - battery application with internal oscillator (trim) notes: 1. for two batteries application, v33o connect to vdd directly 2. rosc is built in n567h chip internally. user need n t connect rosc resistor to oscin pin. 3. the 4.7uf is necessary for power stability. 4. the rs value is suggested in 270 ? ~ 1k ? to limit too large dac output current flowing into transistor. 5. the vdd_sim pad must be connected to vdd for non - sim application. 6. th e above application circuits are for reference only. no warranty for mass production. n 5 6 7 h p 3 3 0 o s c i n v d d _ s p k v s s r e s e t b p w m + / d a c v d d p w m - v d d _ s p k 3 . 0 v b p 0 0 | b p 0 7 b p 1 0 | b p 1 7 b p 2 0 | b p 2 7 r s v d d _ s i m i p 0 0 | i p 0 7 v s s _ s p k o s c o u t p w m + s p k / d a c : d a c c i r c u i t 4 . 7 u f v p p v 3 3 o s c t e s t b v 3 3 o
n 567 hp33 0 otp data sheet publication release date: jan . 20 1 3 - 10 - revision a 2 (c) 3 - battery a pplication with crystal mode notes: 1. the crystal value must be double of system clock (fsys) . for e xample , as connect x tal 1 2mhz, the fsys will be 6m hz. t he crystal had better placed as close to ic in pcb layout for stability concern. 2. the 4.7uf is necessary for power stability . 3. the rs value is suggested in 270 ? ~ 1k ? to limit too large dac output current flowing into transistor . 4. the vdd_sim pad must be connected to vdd for non - sim application. 5. the above application circuits are for reference only. no warranty for mass production. 6. for more a pplication circuits , please refer to n567hxxx design guide. n 5 6 7 h p 3 3 0 v d d _ s p k v s s r e s e t b p w m + / d a c v d d p w m - v d d _ s p k 4 . 5 v b p 0 0 | b p 0 7 b p 1 0 | b p 1 7 b p 2 0 | b p 2 7 r s v d d _ s i m i p 0 0 | i p 0 7 v s s _ s p k o s c o u t p w m + s p k / d a c : d a c c i r c u i t 4 . 7 u f v p p v 3 3 o s c t e s t b v 3 3 o o s c i n c p 1 c p 2 2 0 p f 2 0 p f : c o m p o n e n t i s o p t i o n 0 . 1 u f
n 567 hp33 0 otp data sheet publication release date: jan . 20 1 3 - 11 - revision a 2 (d) 2 - battery a pplication with crystal mode notes: 1. the crystal value must be double of system clock (fsys) . for example, as connect x tal 12mhz, the fsys will be 6m hz. the crystal had better placed as close to ic in pcb layout for stability concern. 2. the 4.7 uf is necessary for power stability. 3. the rs value is suggested in 270 ? ~ 1k ? to limit too large dac output current flowing into transistor. 4. the vdd_sim pad must be connected to vdd for non - sim application. 5. the above application circuits are for reference o nly. no warranty for mass production. 6. for more application circuits, please refer to n567hxxx design guide. n 5 6 7 h p 3 3 0 v d d _ s p k v s s r e s e t b p w m + / d a c v d d p w m - v d d _ s p k 3 . 0 v b p 0 0 | b p 0 7 b p 1 0 | b p 1 7 b p 2 0 | b p 2 7 r s v d d _ s i m i p 0 0 | i p 0 7 v s s _ s p k o s c o u t p w m + s p k / d a c : d a c c i r c u i t 4 . 7 u f v p p v 3 3 o s c t e s t b v 3 3 o o s c i n c p 1 c p 2 2 0 p f 2 0 p f : c o m p o n e n t i s o p t i o n
n 567 hp33 0 otp data sheet publication release date: jan . 20 1 3 - 12 - revision a 2 (e) write interface 1. writer interface pins are bp00~bp03, reset b , vpp, vss and vdd. 2. detail application circuit, please refer to nhs - n567hp80 v1_0 user s guide a0. (f) pcb layout guide 1. the ic substrate should be connected to vss in pcb layout , bu t vss_spk can t connect with ic substrate directly. both vss and vss_spk tie together in battery negative power. 2. each vdd , vdd_sim and vdd_ spk pad must connect to positive power to support stable voltage for individual function work successfully. (don t let them be floating . ) 7. revision history v ersion date reasons for change page a 0 .0 jul. 2012 preliminary release a1 .0 sep. 2012 rename to N567HP330 1, 10~1 3 a2 .0 jan. 2013 remove vss_sim and vdd2 pad description vss_sim rename to vss , connect to vss directly. vdd2 rename to vdd , connect to vdd directly 4, 8~11
n 567 hp33 0 otp data sheet publication release date: jan . 20 1 3 - 13 - revision a 2 important notice nuvoton products are neither intended nor warranted for usa ge in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, insecure usage. insecure usage includes, but is not limited to: equipment for surgical i mplementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications in tended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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