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silego technology, inc. rev 1.09 SLG46531_ds_109 revised october 21, 2016 greenpak programmable mixed -signal matrix with asynchronous state machine SLG46531 block diagram features ? logic & mixed signal circuits ? highly versatile macro cells ? read back protection (read lock) ? 1.8 v (5%) to 5 v (10%) supply ? operating temperature range: -40c to 85c ? rohs compliant / halogen-free ? 20-pin stqfn: 2 x 3 x 0.55 mm, 0.4 mm pitch applications ? personal computers and servers ? pc peripherals ? consumer electronics ? data communications equipment ? handheld and portable electronics pin configuration gpio gpio gpio gpio gpio gpio 2 3 414 15 16 17 gpi vdd 1 stqfn-20 (top view) gpio gpio 5 6 gpio gpio 12 13 gpio 7 gnd 11 sda/gpio scl/gpio 8 9 gpio 10 gpio gpio 18 19 gpio 20 3-bit lut3_2 or dff5 pin 6 gpio programmable delay rc oscillator pin 7 gpio pin 1 vdd pin 2 gpi pin3 gpio pin 4 gpio pin 5 gpio pin 20 gpio pin 19 gpio pin 18 gpio pin 8 scl or gpio pin 9 sda or gpio pin 10 gpio pin 12 gpio pin 11 gnd pin 17 gpio pin 16 gpio pin 15 gpio pin 14 gpio pin 13 gpio acmp0 acmp1 acmp2 acmp 3 additional logic functions combination function macrocells 2-bit lut2_0 or dff0 2-bit lut2_2 or dff2 2-bit lut2_1 or dff1 2-bit lut2_3 or pgen 3-bit lut3_1 or dff4 3bit lut3_0 or dff3 3-bit lut3_4 or dff7 3-bit lut3_3 or dff6 filter_1 with edge detect por i 2 c serial communication asm 8 states 3-bit lut3_5 or cnt/dly2 3-bit lut3_6 or cnt/dly3 3-bit lut3_7 or cnt/dly4 3-bit lut3_8 or cnt/dly5 3-bit lut3_9 or cnt/dly6 4-bit lut4_0 or cnt/dly0 4-bit lut4_1 or cnt/dly1 3-bit lut3_10 or pipe de- fil- ter_0with edge detect 8 byte ram + otp memory vref crystal oscillator 25m oscillator
SLG46531_ds_109 page 1 of 169 SLG46531 1.0 overview the SLG46531 provides a small, low power component for commonly used mixed-signal functions. the user creates their circuit design by programming the one time non-volatile memory (nvm) to configure the interconnect logic, the i/o pins and the macro cells of the SLG46531. this highly versatile device allows a wi de variety of mixed-signal functions to be designed within a ve ry small, low power single integrat ed circuit. the macro cells in the device include the following: ? four analog comparators (acmp) ? two voltage references (vref) ? seventeen combination function macrocells ? three selectable dff/latch or 2-bit luts ? one selectable continuous dff/latch or 3-bit lut ? four selectable dff/latch or 3-bit luts ? one selectable pipe delay or 3-bit lut ? one selectable programmable pattern generator or 2-bit lut ? five 8-bit delays/co unters or 3-bit luts ? two 16-bit delays/co unters or 4-bit luts ? asynchronous state machine ? eight states ? flexible input logic from state transitions ? serial communications ?i 2 c protocol compliant ? pipe delay C 16 sta ge/3 output (part of c ombination function m acrocell) ? programmable delay ? additional logic functions C 2 deg litch filters with edge dete ctors ? two oscillators (osc) ? configurable 25 khz/2 mhz ? 25 mhz rc oscillator ? crystal oscillator ? power-on-reset (por) ? eight byte ram + otp user memory ? ram memory space that is readable and writeable via i 2 c ? user defined initial valu es transferred from otp
SLG46531_ds_109 page 2 of 169 SLG46531 2.0 pin description 2.1 functional pin description pin # pin name function 1 vdd power supply 2 gpi general purpose input 3 gpio general purpose i/o with oe 4 gpio general purpose i/o 5 gpio general purpose i/o with oe 6 gpio general purpose i/o o r analog comparator 0 (+) 7 gpio general purpose i/o with oe or external vref (acmp0 in-) 8 scl/gpio general purpose i/o scl or gpiod (nmos open drain only ) 9 sda/gpio general purpose i/o sda or gpiod (nmos open drain only ) 10 gpio general purpose i/o with oe or analog comparator 1 (+) 11 gnd ground 12 gpio general purpose i/o o r external vre f (acmp1 in-) 13 gpio general purpose i/o with oe or analog comparator 2 (+) 14 gpio general purpose i/o with oe or external vref (acmp2 in-) 15 gpio general purpose i/o o r analog comparator 3 (+) 16 gpio general pu rpose i/o with oe 17 gpio general purpose i/o 18 gpio general purpose i/o wit h oe and vref output (vref1) 19 gpio general purpose i/o wit h oe and vref output (vref0) 20 gpio general purpose i/o or external clock input
SLG46531_ds_109 page 3 of 169 SLG46531 3.0 user programmability the SLG46531 is a user programmable device with one-time-programmable (otp) memory elements that are able to construct combinatorial logic elements. three of the i/o pins provide a c onnection for the bit patterns into the otp on board memory. a programming development kit allows the user the ability to crea te initial devices. once the design is finalized, the programmi ng code (.gpx file) is forwarded to silego to integrate into a pro duction process. figure 1. steps to create a cu stom silego greenpak device 3urgxfw 'hilqlwlrq &xvwrphu&uhdwhvwkhlurzqghvljqlq *uhhq3$.'hvljqhu 3urjudp(qjlqhhulqj6dpsohvzlwk *uhhq3$.3urjudpphu &xvwrphuyhulilhv*uhhq3$. lqv\vwhpghvljq (pdlojs[ilohwr *uhhq3$.#vlohjrfrp (pdlo3urgxfw,ghd'hilqlwlrq'udzlqjru 6fkhpdwlfwr*uhhq3$.#vlohjrfrp 6lohjr$ssolfdwlrqv(qjlqhhuvzloouhylhzghvljq vshflilfdwlrqvzlwkfxvwrphu 6dpsohvdqg'hvljq &kdudfwhul]dwlrq 5hsruwvhqwwrfxvwrphu &xvwrphuyhulilhv*uhhq3$.ghvljq &xvwrp*uhhq3$.sduw hqwhuvsurgxfwlrq *uhhq3$.'hvljq dssuryhglqv\vwhpwhvw *uhhq3$.'hvljq dssuryhg *uhhq3$.'hvljq dssuryhg
SLG46531_ds_109 page 4 of 169 SLG46531 4.0 ordering information part number type SLG46531v 20-pin stqfn SLG46531vtr 20-pin stqfn - tape and reel (3k units)
SLG46531_ds_109 page 5 of 169 SLG46531 5.0 electrical specifications 5.1 absolute maximum conditions 5.2 electrical charac teristics (1.8 v 5% v dd ) parameter min. max. unit supply voltage on vdd relative to gnd -0.5 7 v dc input voltage g nd - 0.5 vdd + 0.5 v current at input pin -1.0 1.0 ma storage temperature range -65 150 c junction temperature -- 150 c esd protection (human body model) 2000 -- v esd protection (charged device model) 1300 -- v moisture sensitivity level 1 symbol parameter condition/note min. typ. max. unit v dd supply voltage 1.71 1.80 1.89 v t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v acmp acmp input voltage range positive input 0 -- v dd v negative input 0 -- 1.0 v v ih high-level input voltage logic input 1.06 -- v dd v logic input with schm itt trigger 1.28 -- v dd v low-level logic input 0.94 -- v dd v v il low-level input voltage logic input 0 -- 0.76 v logic input with schm itt trigger 0 -- 0.49 v low-level logic input 0 -- 0.52 v v hys schmitt trigger hysteresis voltage logic input with schmit t trigger 0.10 0.41 0.66 v i lkg input leakage (absolute value) -- 1 1000 na v oh high-level output voltage push-pull, i oh = 100 ? a, 1x driver 1.69 1.79 -- v pmos od, i oh = 100 ? a, 1x driver 1.69 1.79 -- v push-pull, i oh = 100 ? a, 2x driver 1.70 1.79 -- v pmos od, i oh = 100 ? a, 2x driver 1.70 1.79 -- v v ol low-level output voltage push-pull, i ol = 100 ? a, 1x driver -- 0.009 0.013 v push-pull, i ol = 100 ? a, 2x driver -- 0.004 0.006 v open drain, i ol = 100 ? a, 1x driver -- 0.006 0.009 v open drain, i ol = 100 ? a, 2x driver -- 0.003 0.004 v open drain nmos 4x, i ol = 100 ? a -- 0.001 0.002 v
SLG46531_ds_109 page 6 of 169 SLG46531 i oh high-level output current push-pull, v oh = v dd - 0.2, 1x driver 1.07 1.70 -- ma pmos od, v oh = v dd - 0.2, 1x driver 1.07 1.70 -- ma push-pull, v oh = v dd - 0.2, 2x driver 2.22 3.41 -- ma pmos od, v oh = v dd - 0.2, 2x driver 2.22 3.41 -- ma i ol low-level output current push-pull, v ol = 0.15 v, 1x driver 0.92 1.69 -- ma push-pull, v ol = 0.15 v, 2x driver 1.83 3.38 -- ma open drain, v ol = 0.15 v, 1x driver 1.38 2.53 -- ma open drain, v ol = 0.15 v, 2x driver 2.75 5.07 -- ma open drain nmos 4x, v ol = 0.15 v 7.21 9.00 -- ma v o maximal voltage applied to any pin in high-impedance state -- -- v dd v i o maximal average or dc current total current on pin 2 C pin 10 or on pin 12 C pin 20 -- -- 90 ma t su startup time from vdd rising past pon thr 0.63 1.36 1.87 ms pon thr power on threshold v dd level required to start up the chip 1.41 1.54 1.66 v poff thr power off threshold v dd level required to switch off the chip 1.00 1.15 1.31 v r pup pull up resistance 1 m pull up 859.8 1097.1 1358.9 k ? 100 k pull up 86.47 110.13 136.18 k ? 10 k pull up 10.82 12.86 15.36 k ? r pdwn pull down resistance 1 m pull down 873.9 1097.0 1359.0 k ? 100 k pull down 88.89 110.53 136.55 k ? 10 k pull down 9.65 12.75 15.76 k ? symbol parameter condition/note min. typ. max. unit
SLG46531_ds_109 page 7 of 169 SLG46531 5.3 electrical charac teristics (3.3 v 10% v dd ) symbol parameter condition/note min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v acmp acmp input voltage range positive input 0 -- v dd v negative input 0 -- 1.0 v v ih high-level input voltage logic input 1.81 -- v dd v logic input with schm itt trigger 2.14 -- v dd v low-level logic input 1.06 -- v dd v v il low-level input voltage logic input 0 -- 1.31 v logic input with schm itt trigger 0 -- 0.97 v low-level logic input 0 -- 0.67 v v hys schmitt trigger hysteresis voltage logic input with schmit t trigger 0.29 0.62 0.94 v i lgk input leakage (absolute value) -- 1 1000 na v oh high-level output voltage push-pull, i oh = 3 ma, 1x driver 2.70 3.12 -- v pmos od, i oh = 3 ma, 1x driver 2.70 3.12 -- v push-pull, i oh = 3 ma, 2x driver 2.85 3.21 -- v pmos od, i oh = 3 ma, 2x driver 2.86 3.21 -- v v ol low-level output voltage push-pull, i ol = 3 ma, 1x driver -- 0.13 0.23 v push-pull, i ol = 3 ma, 2x driver -- 0.06 0.11 v open drain, i ol = 3 ma, 1x driver -- 0.08 0.15 v open drain, i ol = 3 ma, 2x driver -- 0.04 0.08 v open drain nmos 4x, i ol = 3 ? ma -- 0.02 0.04 v i oh high-level output current push-pull, v oh = 2.4 v, 1x driver 6.05 12.08 -- ma pmos od, v oh = 2.4 v, 1x driver 6.05 12.08 -- ma push-pull, v oh = 2.4 v, 2x driver 11.54 24.16 -- ma pmos od, v oh = 2.4 v, 2x driver 11.52 24.16 -- ma i ol low-level output current push-pull, v ol = 0.4 v, 1x driver 4.88 8.24 -- ma push-pull, v ol = 0.4 v, 2x driver 9.75 16.49 -- ma open drain, v ol = 0.4 v, 1x driver 7.31 12.37 -- ma open drain, v ol = 0.4 v, 2x driver 14.54 24.74 -- ma open drain nmos 4x, v ol = 0.4 v 31.32 41.06 -- ma i o maximum average or dc current per each chip side -- -- 90 ma v o maximal voltage applied to any pin in high-impedance state -- -- v dd v i o maximal average or dc current total current on pin 2 C pin 10 or on pin 12 C pin 20 -- -- 90 ma
SLG46531_ds_109 page 8 of 169 SLG46531 t su startup time from vdd rising past pon thr 0.61 1.24 1.65 ms pon thr power on threshold v dd level required to start up the chip 1.41 1.54 1.66 v poff thr power off threshold v dd level required to switch off the chip 1.00 1.15 1.31 v r pup pull up resistance 1 m pull up 873.2 1094.7 1364.3 k ? 100 k pull up 85.17 109.30 135.52 k ? 10 k pull up 9.61 11.86 14.73 k ? r pdwn pull down resistance 1 m pull down 862.5 1096.3 1357.4 k ? 100 k pull down 87.95 109.76 136.06 k ? 10 k pull down 8.66 11.81 15.05 k ? symbol parameter condition/note min. typ. max. unit
SLG46531_ds_109 page 9 of 169 SLG46531 5.4 electrical charac teristics (5 v 10% v dd ) symbol parameter condition/note min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v t a operating temperature -40 25 85 c v pp programming volt age 7.25 7.50 7.75 v v acmp acmp input voltage range positive input 0 -- v dd v negative input 0 -- 1.0 v v ih high-level i nput voltage logic input 2.68 -- v dd v logic input with schmitt trigger 3.34 -- v dd v low-level logic input 1.15 -- v dd v v il low-level input voltage logic input 0 -- 1.96 v logic input with schmitt trigger 0 -- 1.41 v low-level logic input 0 -- 0.77 v v hys schmitt trigger hysteresis voltage logic input with schmitt trigger 0.44 0.90 1.38 v i lgk input leakage (absolute value) -- 1 1000 na v oh high-level output voltage push-pull, i oh = 5 ma, 1x driver 4.15 4.76 -- v pmos od, i oh = 5 ma, 1x driver 4.16 4.76 -- v push-pull, i oh = 5 ma, 2x driver 4.32 4.89 -- v pmos od, i oh = 5 ma, 2x driver 4.33 4.89 -- v v ol low-level output voltage push-pull, i ol = 5 ma, 1x driver -- 0.19 0.24 v push-pull, i ol =5 ma, 2x driver -- 0.09 0.12 v open drain, i ol = 5 ma, 1x driver -- 0.12 0.16 v open drain, i ol = 5 ma, 2x driver -- 0.07 0.08 v open drain nmos 4x, i ol = 5 ma -- 0.03 0.05 v i oh high-level output current push-pull, v oh = 2.4 v, 1x driver 22.08 34.04 -- ma pmos od, v oh = 2.4 v, 1x driver 22.08 34.04 -- ma push-pull, v oh = 2.4 v, 2x driver 41.76 68.08 -- ma pmos od, v oh = 2.4 v, 2x driver 41.69 68.08 -- ma i ol low-level output current push-pull, v ol = 0.4 v, 1x driver 7.22 11.58 -- ma push-pull, v ol = 0.4 v, 2x driver 13.83 23.16 -- ma open drain, v ol = 0.4 v, 1x driver 10.82 17.38 -- ma open drain, v ol = 0.4 v, 2x driver 17.34 34.76 -- ma open drain nmos 4x, v ol = 0.4 v 41.06 55.18 -- ma i o maximum average or dc current per each chip side -- -- 90 ma v o maximal voltage applied to any pin in high-impedance state -- -- v dd v i o maximal average or dc current total current on pin 2 C pin 10 or on pin 12 C pin 20 -- -- 90 ma
SLG46531_ds_109 page 10 of 169 SLG46531 5.5 i 2 c specifications 5.6 asynchronous state machine (asm) specifications t su startup time from v dd rising past pon thr 0.60 1.23 1.61 ms pon thr power on threshold v dd level required to start up the chip 1.41 1.54 1.66 v poff thr power off threshold v dd level required to switch off the chip 1.00 1.15 1.31 v r pup pull up resistance 1 m pull up 864.6 1093.4 1348.1 k ? 100 k pull up 84.32 108.97 135.24 k ? 10 k pull up 8.74 11.37 14.52 k ? r pdwn pull down resistance 1 m pull down 873.3 1096.1 1370.5 k ? 100 k pull down 87.57 109.48 135.89 k ? 10 k pull down 7.95 11.33 14.78 k ? symbol parameter condition/note min. typ. max. unit f scl clock frequency, scl v dd = (1.71...5.5) v -- -- 400 khz t low clock pulse width low v dd = (1.71...5.5) v 1300 ns t high clock pulse width high v dd = (1.71...5.5) v 600 -- -- ns t i input filter spike suppression (scl, sda) v dd = 1.8 v 5 % -- -- 168 ns v dd = 3.3 v 10% 157 v dd = 5.0 v 10 % 156 t aa clock low to data out valid v dd = (1.71...5.5) v -- -- 900 ns t buf bus free time between stop and start v dd = (1.71...5.5) v 1300 -- -- ns t hd_sta start hold time v dd = (1.71...5.5) v 600 -- -- ns t su_sta start set-up time v dd = (1.71...5.5) v 600 -- -- ns t hd_dat data hold time v dd = (1.71...5.5) v 0 -- -- ns t su_dat data set-up time v dd = (1.71...5.5) v 100 -- -- ns t r inputs rise time v dd = (1.71...5.5) v -- -- 300 ns t f inputs fall time v dd = (1.71...5.5) v -- -- 300 ns t su_std stop set-up time v dd = (1.71...5.5) v 600 -- -- ns t dh data out hold time v dd = (1.71...5.5) v 50 -- -- ns symbol parameter condition/note min. typ. max. unit t st_out_delay asynchronous state machine output delay time v dd = 1.8 v 5 % 225 -- 275 ns v dd = 3.3 v 10% 95 118 v dd = 5.0 v 10 % 67 -- 77 t st_out asynchronous state machine output transition time v dd = 1.8 v 5 % -- -- 165 ns v dd = 3.3 v 10% 70 v dd = 5.0 v 10 % -- 46 t st_pulse asynchronous state machine input pulse acceptance time v dd = 1.8 v 5 % 29 -- -- ns v dd = 3.3 v 10% 14 v dd = 5.0 v 10 % 9.2 -- symbol parameter condition/note min. typ. max. unit
SLG46531_ds_109 page 11 of 169 SLG46531 t st_comp asynchronous state machine input compete time v dd = 1.8 v 5 % -- -- 29 ns v dd = 3.3 v 10% 14 v dd = 5.0 v 10 % -- 10 symbol parameter condition/note min. typ. max. unit
SLG46531_ds_109 page 12 of 169 SLG46531 5.7 idd estimator 5.8 timing estimator table 1. typical current e stimated for each block symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit i current chip quiescent 0.45 0.75 1.12 ? a osc 2 mhz, predivide = 1 41.48 64.00 94.89 ? a osc 2 mhz, predivide = 8 25.68 32.41 43.22 ? a osc 25 khz, predivide = 1 7.16 7.94 9.25 ? a osc 25 khz, predivide = 8 6.97 7.60 8.68 ? a osc 25 mhz, predivide = 1 87.25 238.27 428.66 ? a osc 25 mhz, predivide = 1, force on 87.25 238.27 428.67 ? a osc 25 mhz, predivide = 8 78.01 212.45 390.17 ? a acmp (each) 54.96 52.64 60.81 ? a acmp with buffer (each) 75.06 72.74 81.25 ? a vref (each) 49.70 47.32 55.60 ? a vref with buffer (each) 71.93 71.27 79.62 ? a table 2. typical delay es timated for each block symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit rising falling rising falling rising falling tpd delay digital input without schmitt trigger 45 50 19 21 14 15 ns tpd delay digital input with schmitt trigger 44 49 19 21 14 15 ns tpd delay low voltage digital input 46 447 19 195 14 134 ns tpd delay digital input-- pmos 44 - 19 - 14 - ns tpd delay digital input-- nmos - 81 - 30 - 20 ns tpd delay output enable from pin, oe hi-z to 1 48 - 20 - 15 - ns tpd delay output enable from pin, oe hi-z to 0 - 46 - 20 - 24 ns tpd delay lut2bit(latch) 34 33 14 13 10 9 ns tpd delay latch(lut2bit) 30 34 14 13 10 9 ns tpd delay lut3bit(latch) 38 37 18 15 13 10 ns tpd delay latch+nreset(lut3bit) 45 42 21 17 15 12 ns tpd delay latch 33 5 14 14 ns tpd delay lut4bit 28 33 14 13 10 9 ns tpd delay lut2bit 31 31 14 13 10 9 ns tpd delay lut3bit 35 33 15 13 11 10 ns tpd delay cnt/dly 62 68 27 29 19 20 ns tpd delaydff 3228141211 9 ns tpd delayp_dly1c 626827291920ns tpd delay p_dly2c 667 656 303 297 225 221 ns tpd delay p_dly3c 968 956 440 434 327 322 ns tpd delay p_dly4c 1265 1252 576 570 428 423 ns tpd delay filter 213 210 84 83 55 55 ns tpd delay acmp (5mv across inputs) 1600 1900 1500 1800 1600 1800 ns tw width i/o with 1x push pull (min transmitted) 20 20 20 20 20 20 ns
SLG46531_ds_109 page 13 of 169 SLG46531 5.9 typical counter/de lay offset measurements 5.10 expected delays and widths 5.11 typical pulse width performance tw width filter (min transmitted) 150 150 55 55 35 35 ns table 3. typical counter/delay offset measurements parameter rc osc freq rc osc power v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit offset (start time) 25 khz auto 1.6 1.6 1.6 ? s offset (start time), fast s tart 25 khz auto 2.1 2.1 2.1 ? s offset (start time) 2 mhz auto 0.4 0.2 0.2 ? s offset (start time), fast start 2 mhz auto 0.7 0.5 0.4 ? s offset (start time) 25 mhz auto 0.01 0.05 0.04 ? s frequency settling time 25 khz auto 19 14 12 ? s frequency settling time 2 mhz auto 14 14 14 ? s variable (clk period) 25 khz forced 0-40 0-40 0-40 ? s variable (clk period) 2 mhz forced 0-0.5 0-0.5 0-0.5 ? s variable (clk period) 25 mhz 0-0.04 0-0.04 0-0.04 ? s tpd (non-delayed edge) 25 khz/ 2 mhz either 35 14 10 ns table 4. expected delays and widths (typical) symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit width width, 1 cell mode:(any)edge detect, edge detect output 296 1 35 101 ns width width, 2 cell mode:(any)edge detect, edge detect output 597 2 72 203 ns width width, 3 cell mode:(any)edge detect, edge detect output 898 4 10 305 ns width width, 4 cell mode:(any)edge detect, edge detect output 1195 546 407 ns time1 delay, 1 cell mode:(any)edge detect, edge detect output 55 24 18 ns time1 delay, 2 cell mode:(any)edge detect, edge detect output 55 24 18 ns time1 delay, 3 cell mode:(any)edge detect, edge detect output 55 24 18 ns time1 delay, 4 cell mode:(any)edge detect, edge detect output 55 24 18 ns time2 delay, 1 cell m ode: both edge delay, edg e detect output 367 165 106 ns time2 delay, 2 cell m ode: both edge delay, edg e detect output 667 300 193 ns time2 delay, 3 cell m ode: both edge delay, edg e detect output 968 440 279 ns time2 delay, 4 cell m ode: both edge delay, edg e detect output 126 5 575 365 ns table 5. typical pulse widt h performance at t=25c parameter v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit filtered pulse width for filter 0 < 114 < 47 < 30 ns filtered pulse width for filter 1 <75 <30 <19 ns table 2. typical delay es timated for each block symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit rising falling rising falling rising falling
SLG46531_ds_109 page 14 of 169 SLG46531 5.12 osc specifications table 6. 25 khz rc osc0 frequency limits power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c minimum value, khz maximum value, khz minimum value, khz maximum value, khz minimum value, khz maximum value, khz 1.8 v 5% 24.240 25.781 21.963 27.188 21.963 27.562 3.3 v 10% 24.447 25.556 21.905 27.221 21.905 27.263 5 v 10% 24.315 25.911 22.045 27.099 22.045 27.422 2.5 v ... 4.5 v 24.398 25.576 21.897 27.221 21.897 27.277 1.71 v 5.5 v 24.089 26.128 21.897 27.373 21.897 27.613 table 7. 25 khz rc osc0 frequen cy error (error cal culated relati ve to nominal value) power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) 1.8 v 5% -2.76% 3.42% -1 1.89% 9.07% -11.89% 10.57% 3.3 v 10% -2.01% 2.43% - 12.20% 9.11% -12.20% 9.28% 5 v 10% -2.51% 3.89% -11. 61% 8.65% -11.61% 9.95% 2.5 v ... 4.5 v -2.21% 2.52% -12.23% 9.11% -12.23% 9.33% 1.71 v 5.5 v -3.44% 4.73% -12.23% 9.72% -12.23% 10.68%
SLG46531_ds_109 page 15 of 169 SLG46531 5.12.1 2 mhz rc oscillator table 8. 2 mhz rc osc0 frequency limits power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c minimum value, mhz maximum value, mhz minimum value, mhz maximum value, mhz minimum value, mhz maximum value, mhz 1.8 v 5% 1.932 2.058 1.793 2.171 1.793 2.171 3.3 v 10% 1.932 2.099 1. 808 2.204 1.808 2.204 5 v 10% 1.981 2.194 1.759 2.316 1.759 2.316 2.5 v ... 4.5 v 1.920 2.120 1.800 2.214 1.800 2.214 1.71 v 5.5 v 1.811 2.288 1.710 2.337 1.710 2.361 table 9. 2 mhz rc osc0 f requency error (error calculated relativ e to nominal value) power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) 1.8 v 5% -3.23% 3.10% -10. 21% 8.73% -10.21% 8.73% 3.3 v 10% -3.40% 4.94% -9 .60% 10.19% -9.60% 10.19% 5 v 10% -5.44% 9.70% - 12.03% 2.32% -12.03% 15.81% 2.5 v ... 4.5 v -4.00% 5.98% -9.99% 10.68% -9.99% 10.68% 1.71 v 5.5 v -9.46% 14.4 2% -14.48% 16.85% -14.48% 18.05%
SLG46531_ds_109 page 16 of 169 SLG46531 5.12.2 25 mhz rc oscillator note: 25 mhz rc osc1 performance is not guaranteed at vdd < 2.5 v. table 10. 25 mhz rc os c1 frequency limits power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c minimum value, mhz maximum value, mhz minimum value, mhz maximum value, mhz minimum value, mhz maximum value, mhz 2.5 v 10% 22.344 27.023 21.687 27.777 21.687 27.706 3.3 v 10% 22.412 26.290 21.399 26.595 21.399 27.069 5 v 10% 23.049 26.646 21.900 27.220 21.900 27.647 2.5 v ... 4.5 v 21.511 26.29 0 20.738 26.685 20.738 27.123 1.71 v 5.5 v 13.290 26.290 12.770 26.685 11.908 27.123 table 11. 25 mhz rc osc1 frequency error (error calculated relat ive to nominal value) power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) 2.5 v 10% -10.37% 8.40% -13.00% 9.42% -13.00% 11.14% 3.3 v 10% -11.10% 4.28% - 15.12% 5.49% -15.12% 7.37% 5 v 10% -9.80% 4.27% -14. 30% 6.52% -14.30% 8.19% 2.5 v ... 4.5 v -14.68% 4.28% -17.74% 5.85% -17.74% 7.58% 1.71 v 5.5 v -47.29% 4.28% -49.35% 5.85% -52.77% 7.58%
SLG46531_ds_109 page 17 of 169 SLG46531 5.12.3 osc power on delay table 12. oscillators power on delay at room temperature, dly/cn t counter data = 100; rc osc power setting: "auto power on", rc osc clock to matrix input: "enable" power supply range (vdd) v rc osc0 2 mhz rc osc0 25 khz rc osc1 typical value, s maximum value, s typical value, ms maximum value, ms typical value, s maximum value, s 1.71 368.7 402.3 16.26 17.87 114.4 134.8 1.80 347.0 375.4 15.93 17.79 104.9 122.0 1.89 329.4 354.2 15.58 17.67 96.5 111.5 2.50 278.4 295.2 14.08 16.75 72.0 80.3 2.70 263.2 277.8 13.20 16.21 65.0 71.4 3.00 251.6 264.9 8.38 9.11 60.0 65.1 3.30 238.3 250.6 1.64 2.02 55.2 58.7 3.60 228.3 240.0 1.57 1.92 51.7 55.0 4.20 220.3 231.7 1.55 1.93 49.1 51.9 4.50 208.0 219.2 1.55 2.01 45.5 47.8 5.00 203.0 213.9 1.56 2.01 44.3 46.5 5.50 195.7 206.5 1.58 2.07 43.0 44.8 table 13. oscillators power on delay at room temperature, dly/cn t counter data = 100; rc osc power setting: "auto power on", rc osc clock to matrix input: "enable", fast start-u p time mode power supply range (vdd) v rc osc0 2 mhz rc osc1 25 khz typical value, s maximum value, s typical value, ms maximum value, ms 1.71 741.8 924.7 20.78 21.36 1.80 703.9 861.5 20.80 21.26 1.89 672.5 809.0 20.81 21.42 2.50 578.5 651.8 20.84 21.40 2.70 546.8 592.8 20.88 21.42 3.00 520.6 549.2 20.93 21.63 3.30 490.4 515.8 21.00 21.65 3.60 468.9 504.7 21.09 21.75 4.20 453.0 496.6 21.18 21.98 4.50 430.1 478.2 21.36 22.34 5.00 420.7 468.5 21.39 22.34 5.50 406.1 451.9 21.38 22.34
SLG46531_ds_109 page 18 of 169 SLG46531 5.13 acmp specifications table 14. acmp power on delay, mi nimal required acmp wake time for the wake and sleep function. bg=550 s. regulator and charge pump automatic on/off power supply range (vdd) v temperature range -40 ... +85 c +25c typical value, s maximum value, s typical value, s maximum value, s 1.71 651.8 975.1 602.2 835.7 1.80 657.9 985.4 603.2 840.3 1.89 670.4 1020.3 608.6 857.8 2.50 672.0 1023.4 608.9 860.0 2.70 673.8 1025.7 609.2 861.9 3.00 674.9 1028.8 609.7 862.0 3.30 675.0 1028.2 609.3 862.2 3.60 673.4 1026.8 607.7 860.0 4.20 671.4 1022.5 605.2 855.5 4.50 662.2 1004.3 597.0 841.7 5.00 645.2 972.9 581.5 816.5 5.50 651.8 975.1 602.2 835.7 table 15. acmp power on delay, minimal required acmp wake time f or the wake and sleep f unction. bg=100 s (can be used for vdd>2.7v). regulator and charge pump automatic on/o ff power supply range (vdd) v temperature range -40 ... +85 c +25c typical value, s maximum value, s typical value, s maximum value, s 2.70 149.4 212.7 132.4 176.2 3.00 149.3 212.7 131.8 176.1 3.30 149.2 213.5 131.3 176.1 3.60 149.0 212.5 130.9 175.8 4.20 148.6 211.9 130.2 174.9 4.50 148.0 211.1 129.4 173.9 5.00 146.1 208.8 127.7 171.5 5.50 142.7 203.2 124.7 167.1
SLG46531_ds_109 page 19 of 169 SLG46531 table 16. acmp power on delay, minimal required acmp wake time f or the wake and sleep function. bg=550 s. regulator auto on/off and charge pump always off (can be used f or vdd>3.0 v) power supply range (vdd) v temperature range -40 ... +85 c +25c typical value, s maximum value, s typical value, s maximum value, s 3.00 673.6 1024.8 609.1 861.5 3.30 674.4 1027.5 609.5 862.0 3.60 674.6 1027.2 609.1 862.0 4.20 673.0 1025.3 607.6 859.4 4.50 671.1 1021.3 605.1 855.3 5.00 662.4 1004.7 597.0 841.1 5.50 645.0 970.4 581.4 815.8 table 17. acmp power on delay, minimal required acmp wake time f or the wake and sleep function. bg=100 s. regulator auto on/off and charge pump always off (can be used f or vdd>3.0 v) power supply range (vdd) v temperature range -40 ... +85 c +25c typical value, s maximum value, s typical value, s maximum value, s 3.00 149.2 212.7 131.6 176.0 3.30 149.1 213.3 131.2 175.9 3.60 148.9 212.5 130.8 175.7 4.20 148.6 211.7 130.2 174.7 4.50 148.0 211.1 129.4 173.8 5.00 146.1 208.9 127.7 171.4 5.50 142.8 204.0 124.8 167.1
SLG46531_ds_109 page 20 of 169 SLG46531 5.14 analog temperature sensor (ts) specifications table 18. ts output vs temperature, without buffer t, c vdd = 1.8 v vdd = 3.3 v vdd = 5.0 v typical, v accuracy, % typical, v accuracy, % typical, v accuracy, % -40 0.69 0.85 0.70 1.13 0.70 1.09 -30 0.67 0.70 0.68 1.12 0.68 1.02 -20 0.66 0.78 0.66 1.27 0.66 1.19 -10 0.64 0.70 0.64 1.03 0.64 1.05 0 0.62 0.66 0.62 1.13 0.62 1.10 10 0.60 0.54 0.60 1.16 0.60 1.15 20 0.58 0.50 0.58 0.74 0.58 0.76 30 0.56 0.91 0.56 1.29 0.56 1.22 40 0.54 0.48 0.54 0.53 0.54 0.53 50 0.51 0.89 0.51 1.33 0.51 1.25 60 0.49 0.95 0.49 1.14 0.49 1.18 70 0.47 0.77 0.47 0.98 0.47 1.01 80 0.45 0.63 0.45 0.70 0.45 0.70 90 0.43 1.12 0.43 1.22 0.43 1.22 100 0.41 2.33 0.41 2.42 0.41 2.36 110 0.39 1.41 0.39 1.49 0.39 1.58 120 0.37 3.28 0.37 3.25 0.37 3.31 130 0.35 3.48 0.35 3.57 0.35 3.53 140 0.33 1.38 0.33 1.54 0.33 1.53 150 0.31 1.42 0.31 1.61 0.31 1.58 160 0.28 5.40 0.28 5.55 0.28 5.33 170 0.26 2.41 0.26 2.60 0.26 2.41 180 0.24 6.04 0.24 5.84 0.24 6.16 table 19. ts output vs temperature, with buffer (output range 1) t, c vdd = 1.8 v vdd = 3.3 v vdd = 5.0 v typical, v accuracy, % typical, v accuracy, % typical, v accuracy, % -40 1.20 3.33 1.20 3.29 1.20 3.29 -30 1.16 3.35 1.16 3.32 1.16 3.29 -20 1.13 3.49 1.13 3.42 1.13 3.42 -10 1.10 3.42 1.10 3.33 1.10 3.38 0 1.06 3.51 1.06 3.46 1.06 3.45 10 1.03 3.63 1.03 3.60 1.03 3.60 20 0.99 3.72 0.99 3.61 0.99 3.58 30 0.96 4.00 0.96 3.92 0.96 3.87 40 0.92 3.73 0.92 3.64 0.92 3.64 50 0.88 4.01 0.88 3.90 0.88 3.92 60 0.85 4.11 0.85 4.03 0.85 3.97 70 0.81 4.18 0.81 4.12 0.81 4.06 80 0.78 4.43 0.78 4.36 0.78 4.26
SLG46531_ds_109 page 21 of 169 SLG46531 90 0.75 4.98 0.75 4.89 0.75 4.81 100 0.71 5.64 0.71 5.52 0.71 5.44 110 0.67 5.45 0.67 5.33 0.67 5.29 120 0.64 6.73 0.64 6.59 0.64 6.55 130 0.60 7.00 0.60 6.88 0.60 6.84 140 0.56 6.25 0.56 6.06 0.56 6.02 150 0.53 6.65 0.53 6.51 0.53 6.45 160 0.49 9.29 0.49 9.12 0.49 9.08 170 0.46 7.64 0.46 7.27 0.46 7.31 180 0.42 10.28 0.42 10.03 0.42 9.98 table 20. ts output vs temperature, with buffer (output range 2) t, c vdd = 1.8 v vdd = 3.3 v vdd = 5.0 v typical, v accuracy, % typical, v accuracy, % typical, v accuracy, % -40 0.99 3.29 0.99 3.28 0.99 3.28 -30 0.96 3.33 0.96 3.24 0.96 3.31 -20 0.93 3.37 0.93 3.30 0.93 3.34 -10 0.90 3.46 0.90 3.39 0.90 3.40 0 0.87 3.45 0.87 3.39 0.87 3.40 10 0.85 3.62 0.85 3.51 0.85 3.53 20 0.82 3.66 0.82 3.58 0.82 3.53 30 0.79 3.93 0.79 3.81 0.79 3.80 40 0.76 3.71 0.76 3.65 0.76 3.62 50 0.73 3.97 0.73 3.90 0.73 3.91 60 0.70 4.02 0.70 3.97 0.70 4.00 70 0.67 4.22 0.67 4.13 0.67 4.08 80 0.64 4.38 0.64 4.29 0.64 4.26 90 0.61 4.89 0.61 4.88 0.61 4.77 100 0.59 5.60 0.59 5.53 0.59 5.43 110 0.56 5.42 0.56 5.29 0.56 5.23 120 0.53 6.72 0.53 6.59 0.53 6.59 130 0.50 7.05 0.50 6.92 0.50 6.87 140 0.46 6.24 0.46 6.04 0.46 6.04 150 0.43 6.68 0.43 6.44 0.43 6.46 160 0.41 9.32 0.41 9.12 0.41 9.00 170 0.38 7.55 0.38 7.21 0.38 7.34 180 0.35 10.24 0.35 10.08 0.35 9.98 table 19. ts output vs temperature, with buffer (output range 1) t, c vdd = 1.8 v vdd = 3.3 v vdd = 5.0 v typical, v accuracy, % typical, v accuracy, % typical, v accuracy, %
SLG46531_ds_109 page 22 of 169 SLG46531 table 21. ts output error, without buffer vdd, v error at t -40c, % -20c, % 0c, % 20c, % 40c, % 60c, % 80c, % 100c, % 120c, % 140c, % 160c, % 180c, % 1.71 2.78 1.27 0.68 0.48 0.46 0.91 0.60 2.31 3.32 1.48 5.42 6.2 2 1.80 0.85 0.78 0.66 0.50 0.48 0.95 0.63 2.33 3.28 1.38 5.40 6.0 4 1.89 0.71 0.90 0.79 0.56 0.48 0.96 0.66 2.29 3.32 1.41 5.49 6.0 8 2.30 1.05 1.23 1.04 0.66 0.49 1.03 0.73 2.36 3.26 1.54 5.34 6.1 0 2.50 1.12 1.24 1.16 0.74 0.51 1.07 0.70 2.39 3.28 1.43 5.53 6.1 2 2.70 1.11 1.22 1.12 0.71 0.52 1.10 0.67 2.34 3.31 1.52 5.55 6.1 6 3.00 1.14 1.25 1.11 0.74 0.53 1.03 0.66 2.40 3.25 1.55 5.53 6.1 8 3.30 1.13 1.27 1.13 0.74 0.53 1.14 0.70 2.42 3.25 1.54 5.55 5.8 4 3.60 1.07 1.24 1.17 0.79 0.54 1.13 0.77 2.44 3.28 1.47 5.41 6.0 1 4.20 1.10 1.19 1.11 0.73 0.56 1.23 0.72 2.35 3.33 1.50 5.52 6.2 4 4.50 1.04 1.23 1.14 0.75 0.53 1.19 0.68 2.44 3.26 1.58 5.51 6.1 1 5.00 1.09 1.19 1.10 0.76 0.53 1.18 0.70 2.36 3.31 1.53 5.33 6.1 6 5.50 1.05 1.14 1.06 0.77 0.57 1.17 0.69 2.45 3.26 1.53 5.50 6.0 1 table 22. ts output error, with buffer (output range 1) vdd, v error at t -40c, % -20c, % 0c, % 20c, % 40c, % 60c, % 80c, % 100c, % 120c, % 140c, % 160c, % 180c, % 1.71 3.28 3.38 3.43 3.67 3.72 4.13 4.42 5.66 6.69 6.24 9.27 10. 26 1.80 3.29 3.37 3.45 3.66 3.71 4.02 4.38 5.60 6.72 6.24 9.32 10. 24 1.89 3.21 3.38 3.44 3.63 3.72 4.06 4.39 5.58 6.75 6.17 9.18 10. 29 2.30 3.23 3.34 3.46 3.56 3.66 4.03 4.32 5.55 6.66 6.15 9.14 10. 17 2.50 3.27 3.37 3.44 3.59 3.68 4.03 4.26 5.56 6.68 6.15 9.15 10. 07 2.70 3.24 3.31 3.39 3.59 3.65 4.04 4.29 5.54 6.66 6.12 9.15 9.9 7 3.00 3.27 3.33 3.39 3.57 3.65 4.02 4.26 5.52 6.57 6.12 9.17 10. 16 3.30 3.28 3.30 3.39 3.58 3.65 3.97 4.29 5.53 6.59 6.04 9.12 10. 08 3.60 3.28 3.28 3.34 3.58 3.64 3.96 4.30 5.45 6.63 6.06 9.07 9.9 9 4.20 3.23 3.36 3.34 3.58 3.62 4.04 4.28 5.48 6.59 6.04 9.12 9.9 1 4.50 3.27 3.31 3.38 3.56 3.61 4.03 4.26 5.44 6.59 6.00 9.10 10. 03 5.00 3.28 3.34 3.40 3.53 3.62 4.00 4.26 5.43 6.59 6.04 9.00 9.9 8 5.50 3.26 3.37 3.44 3.57 3.61 4.01 4.22 5.42 6.54 6.05 9.08 10. 00
SLG46531_ds_109 page 23 of 169 SLG46531 table 23. ts output error, with buffer (output range 2) vdd, v error at t -40c, % -20c, % 0c, % 20c, % 40c, % 60c, % 80c, % 100c, % 120c, % 140c, % 160c, % 180c, % 1.71 3.34 3.50 3.56 3.69 3.73 4.09 4.43 5.61 6.75 6.23 9.24 10. 17 1.80 3.33 3.49 3.51 3.72 3.73 4.11 4.43 5.64 6.73 6.25 9.29 10. 28 1.89 3.33 3.47 3.55 3.70 3.72 4.11 4.40 5.60 6.71 6.22 9.17 10. 22 2.30 3.31 3.46 3.50 3.69 3.66 4.05 4.38 5.59 6.60 6.22 9.15 10. 11 2.50 3.31 3.44 3.51 3.62 3.66 4.03 4.36 5.57 6.59 6.12 9.13 10. 10 2.70 3.30 3.46 3.46 3.64 3.65 3.97 4.31 5.53 6.62 6.13 9.15 10. 02 3.00 3.31 3.46 3.46 3.62 3.64 4.07 4.34 5.50 6.56 6.12 9.07 10. 08 3.30 3.29 3.42 3.46 3.61 3.64 4.03 4.36 5.52 6.59 6.06 9.12 10. 03 3.60 3.25 3.42 3.46 3.59 3.62 3.98 4.34 5.49 6.55 6.07 9.02 9.9 7 4.20 3.28 3.42 3.45 3.62 3.62 4.01 4.30 5.50 6.54 6.06 9.05 9.9 4 4.50 3.32 3.41 3.46 3.63 3.62 4.01 4.29 5.46 6.59 6.00 9.09 10. 04 5.00 3.29 3.42 3.45 3.58 3.64 3.97 4.26 5.44 6.55 6.02 9.08 9.9 8 5.50 3.30 3.47 3.50 3.61 3.64 4.02 4.31 5.50 6.54 6.03 9.04 9.9 1
SLG46531_ds_109 page 24 of 169 SLG46531 6.0 summary of macro cell function 6.1 i/o pins ? digital input (low voltage or normal voltage, with or without schmitt trigger) ? open drain outputs ? push pull outputs ? analog i/o ? 10 k ? /100 k ? /1 m ?? pull-up/pull-down resistors ? 40 ma open drain 4x drive output 6.2 connection matrix ? digital matrix for circuit co nnections based on user design 6.3 analog compa rators (4 total) ? selectable hysteresis 0 m v / 25 mv / 50 mv / 200 mv ? wake and sleep control (part of combination function macrocell ) 6.4 voltage reference ? used for references on analog comparators ? can also be driven to external pins 6.5 combination functi on macrocells (17 total) ? three selectable dff/latch or 2-bit luts ? five selectable dff/latch or 3-bit luts ? one selectable pipe delay or 3-bit lut ? one selectable programmable pattern generator or 4-bit lut ? five selectable 8-bit cnt/dly or 3-bit lut ? two selectable 16-bi t cnt/dly or 4-bit lut ? wake and sleep controller 6.6 asynchronous state machine ? eight states ? flexible input logic from state transitions 6.7 serial communications ?i 2 c protocol compliant 6.8 pipe delay (part of combination function macrocell) ? 16 stage / 3 output ? one 1 stage fixed output ? two 1-16 stage se lectable outputs.
SLG46531_ds_109 page 25 of 169 SLG46531 6.9 programmable delay ? 125 ns/250 ns/375 ns/500 ns @ 3.3 v ? includes edge detection function 6.10 additional logic functions (2 total) ? two deglitch filter macro cells ? includes edge detection function 6.11 rc oscillator ? 25 khz and 2 mhz s electable frequency ? 25 mhz rc oscillator ? first stage divider (4): osc /1, osc/2, osc/4, and osc/8 ? second stage divider for 25 khz and 2 mhz (5): output to matri x: osc/1, osc/2, osc/3, osc/4, osc/8, osc/12, osc/24, osc/64 6.12 crystal oscillator 6.13 eight byte ram + otp user memory ? ram memory space that is readable and writable via i 2 c 6.14 analog temperature sensor
SLG46531_ds_109 page 26 of 169 SLG46531 7.0 i/o pins the SLG46531 has a total of 18 mu lti-function i/o pins which ca n function as either a user defined input or output, as well as serving as a special function (s uch as outputting the voltage r eference), or serving as a signal for programming of the on-chi p non volatile memory (nvm). refer to section 2.0 pin descripti on for normal and programming modepin definitions. normal mode pin definitions are as follows: ? pin 1: v dd power supply ? pin 2: general purpose input ? pin 3: general purpose i nput or output with oe ? pin 4: general purpo se input or output ? pin 5: general purpose i nput or output with oe ? pin 6: general purpose input or output or analog comparator 0( +) ? pin 7: general purpose input or output with oe or analog compa rator 0(-) ? pin 8: general purpose i nput or od output scl ? pin 9: general purpose i nput or od output sda ? pin 10: general purpose input or output with oe or analog comp arator 1(+) ? pin 11: ground ? pin 12: general purpose input or output or analog comparator 1 (-) ? pin 13: general purpose input or output with oe or analog comp arator 2(+) ? pin 14: general purpose input or output with oe or analog comp arator 2(-) ? pin 15: general purpose input or output or analog comparator 3 (+) ? pin 16: general purpose input or output with oe ? pin 17: general purpose input or output ? pin 18: general purpose input or output with oe and vref outpu t (vref2) ? pin 19: general purpose input or output with oe and vref outpu t (vref1) ? pin 20: general purpose input or output or external clock inpu t programming mode pin definitions are as follows: ? pin 1: v dd power supply ? pin 2: v pp programming voltage ? pin 8: programming scl ? pin 9: programming sda ? pin 11: ground ? pin 16: programming mode control of the 18 user defined i/o pins on the SLG46531, all but one of the pins (pin 2) can serve as both digital input and digital o utput. pin 2 can only serve as a digital input pin. 7.1 input modes each i/o pin can be configured as a digital input pin with/with out buffered schmitt trigger, or can also be configured as a lo w voltage digital input. pins 6, 7, 10, 12, 13, 14, and 15 can al so be configured to serve as analog inputs to the on-chip compa rators. pins 18 and 19 can also be configured as analog reference volta ge inputs. 7.2 output modes pins 3, 4, 5, 6, 7, 8 , 9, 10, 12, 13, 14, 15, 16, 17, 18, 19, a nd 20 can all be configured as digital output pins. 7.3 pull up/down resistors all i/o pins have the option for user selectable resistors connected to the input structure. th e selectable values on these re sistors are 10 k ? , 100 k ? and 1 m ? . in the case of pin 2, the resistors are fixed to a pull-down configuration. in the case of all other i/o pins, the internal resistors can be configured as either pull-u p or pull-downs.
SLG46531_ds_109 page 27 of 169 SLG46531 7.4 i/o register settings 7.4.1 pin 2 re gister settings 7.4.2 pin 3 regi ster settings table 24. pin 2 register settings signal function register bit address register definition pin 2 pull down resistor value selection <1028:1029> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 2 mode control <1030:1031> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved table 25. pin 3 register settings signal function register bit address register definition pin 3 pull up/down resistor selection <1033> 0: pull down resistor 1: pull up resistor pin 3 pull up/down resistor value selection <1035:1034> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 3 mode control (sig_pin3_oe =0) <1037:1036> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved pin 3 mode control (sig_pin3_oe =1) <1039:1038> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x
SLG46531_ds_109 page 28 of 169 SLG46531 7.4.3 pin 4 re gister settings 7.4.4 pin 5 re gister settings table 26. pin 4 register settings signal function register bit address register definition pin 4 driver strength selection <1041> 0: 1x 1: 2x pin 4 pull up/down resistor selection <1042> 0: pull down resistor 1: pull up resistor pin 4 pull up/down resistor value selection <1044:1043> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 4 mode control <1047:1045> 000 : digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved table 27. pin 5 register settings signal function register bit address register definition pin 5 pull up/down resistor selection <1049> 0: pull down resistor 1: pull up resistor pin 5 pull up/down resistor value selection <1051:1050> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 5 mode control (sig_pin5_oe =0) <1053:1052> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved pin 5 mode control (sig_pin5_oe =1) <1055:1054> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x
SLG46531_ds_109 page 29 of 169 SLG46531 7.4.5 pin 6 re gister settings 7.4.6 pin 7 re gister settings table 28. pin 6 register settings signal function register bit address register definition pin 6 driver strength selection <1057> 0: 1x 1: 2x pin 6 pull up/down resistor selection <1058> 0: pull down resistor 1: pull up resistor pin 6 pull up/down resistor value selection <1060:1059> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 6 mode control <1063:1061> 000 : digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain table 29. pin 7 register settings signal function register bit address register definition pin 7 pull up/down resistor selection <1065> 0: pull down resistor 1: pull up resistor pin 7 pull up/down resistor value selection <1067:1066> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 7 mode control (sig_pin7_oe =0) <1069:1068> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output pin 7 mode control (sig_pin7_oe =1) <1071:1070> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x
SLG46531_ds_109 page 30 of 169 SLG46531 7.4.7 pin 8 re gister settings 7.4.8 pin 9 re gister settings table 30. pin 8 register settings signal function register bit address register definition pin 8 driver strength selection <1073> 0: 1x 1: 2x sele ct sc l & virt ua l input 0 or pin8 <1074> 0: scl & virtual input 0 1: pin8 pin 8 pull down resistor value selection <1076:1075> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 8 mode control <1079:1077> 000 : digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: reserved 101: open drain nmos 110: reserved 111: reserved table 31. pin 9 register settings signal function register bit address register definition pin9 (or sda) driver strength selection <1081> 0: 1x 1: 2x select sda & virtual input 1 or pin9 <1082> 0: sda & virtual input 1 1: pin9 pin9 pull down resistor value selection <1084:1083> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 9 (or sda) mode control <1087:1085> 000: digital i nput without sc hmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: reserved 101: open drain nmos 110: reserved 111: reserved
SLG46531_ds_109 page 31 of 169 SLG46531 7.4.9 pin 10 register settings 7.4.10 pin 12 register settings table 32. pin 10 register settings signal function register bit address register definition pin 10 4x drive (4x, nmos open drain) selection <1088> 0: 4x drive off 1: 4x drive on (if <884:882> = 101) pin 10 pull up/down resistor selection <1089> 0: pull down resistor 1: pull up resistor pin 10 pull up/down resistor value selection <1091:1090> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 10 mode control (sig_pin10_oe =0) <1093:1092> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output pin 10 mode control (sig_pin10_oe =1) <1095:1094> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x table 33. pin 12 register settings signal function register bit address register definition pin 12 4x drive (4x, nmos open drain) selection <1096> 0: 4x drive off 1: 4x drive on (if <892:890> = 101) pin 12 driver strength selection <1097> 0: 1x 1: 2x pin 12 pull up/down resistor selection <1098> 0: pull down resistor 1: pull up resistor pin 12 pull up/down resistor value selection <1100:1099> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 12 mode control <1103:1101> 000: digital i nput without sc hmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain
SLG46531_ds_109 page 32 of 169 SLG46531 7.4.11 pin 13 register settings 7.4.12 pin 14 register settings table 34. pin 13 register settings signal function register bit address register definition pin 13 pull up/down resistor selection <1105> 0: pull down resistor 1: pull up resistor pin 13 pull up/down resistor value selection <1107:1106> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 13 mode control (sig_pin13_oe =0) <1109:1108> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output pin 13 mode control (sig_pin13_oe =1) <1111:1110> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x table 35. pin 14 register settings signal function register bit address register definition pin 14 pull up/down resistor selection <1113> 0: pull down resistor 1: pull up resistor pin 14 pull up/down resistor value selection <1115:1114> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 14 mode control (sig_pin14_oe =0) <1117:1116> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output pin 14 mode control (sig_pin14_oe =1) <1119:1118> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x
SLG46531_ds_109 page 33 of 169 SLG46531 7.4.13 pin 15 register settings 7.4.14 pin 16 register settings table 36. pin 15 register settings signal function register bit address register definition pin 15 driver strength selection <1121> 0: 1x 1: 2x pin 15 pull up/down resistor selection <1122> 0: pull down resistor 1: pull up resistor pin 15 pull up/down resistor value selection <1124:1123> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 15 mode control <1127:1125> 000: digital i nput without sc hmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain table 37. pin 16 register settings signal function register bit address register definition pin 16 pull up/down resistor selection <1129> 0: pull down resistor 1: pull up resistor pin 16 pull up/down resistor value selection <1131:1130> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 16 mode control (sig_pin16_oe =1) <1135:1134> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x pin 16 mode control (sig_pin16_oe =0) <1133:1132> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved
SLG46531_ds_109 page 34 of 169 SLG46531 7.4.15 pin 17 register settings 7.4.16 pin 18 register settings table 38. pin 17 register settings signal function register bit address register definition pin 17 driver strength selection <1137> 0: 1x 1: 2x pin 17 pull up/down resistor selection <1138> 0: pull down resistor 1: pull up resistor pin 17 pull up/down resistor value selection <1140:1139> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 17 mode control <1143:1141> 000: digital i nput without sc hmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved table 39. pin 18 register settings signal function register bit address register definition pin 18 pull up/down resistor selection <1145> 0: pull down resistor 1: pull up resistor pin 18 pull up/down resistor value selection <1147:1146> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 18 mode control (sig_pin18_oe =0) <1149:1148> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output pin 18 mode control (sig_pin18_oe =1) <1151:1150> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x
SLG46531_ds_109 page 35 of 169 SLG46531 7.4.17 pin 19 register settings 7.4.18 pin 20 register settings table 40. pin 19 register settings signal function register bit address register definition pin 19 pull up/down resistor selection <1153> 0: pull down resistor 1: pull up resistor pin 19 pull up/down resistor value selection <1155:1154> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 19 mode control (sig_pin19_oe =0) <1157:1156> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output pin 19 mode control (sig_pin19_oe =1) <1159:1158> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x table 41. pin 20 register settings signal function register bit address register definition pin 20 driver strength selection <1161> 0: 1x 1: 2x pin 20 pull up/down resistor selection <1162> 0: pull down resistor 1: pull up resistor pin 20 pull up/down resistor value selection <1164:1163> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 20 mode control <1167:1165> 000: digital i nput without sc hmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved
SLG46531_ds_109 page 36 of 169 SLG46531 7.5 gpi structure 7.5.1 gpi structure (for pin 2) figure 2. pin 2 gpi s tructure diagram digital in low voltage input non-schmitt trigger input oe lv_en schmitt trigger input oe smt_en oe wosmt_en pad s0 s1 s2 s3 floating 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1, oe=0 01: digital in with schmit t trigger, smt_en=1, oe=0 10: low voltage digital in mode, lv_en = 1, oe=0 11: reserved note 1: oe cannot be selected by user note 2: oe is matrix output , digital in is matrix input
SLG46531_ds_109 page 37 of 169 SLG46531 7.6 matrix oe io structure 7.6.1 matrix oe io structure (fo r pins 3, 5, 7, 13, 14, 16, 1 8, 19) figure 3. matrix oe io structure diagram pad s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1 01: digital in with schm itt trigger, smt_en=1 10: low voltage digital in mode, lv_en = 1 11: analog io mode output mode [1:0] 00: 1x push-pull mode, pp1x_en=1 01: 2x push-pull mode, pp2x_en=1, pp1x_en=1 10: 1x nmos open drain mode, od1x_en=1 11: 2x nmos open drain mode, od2x_en=1, od1x_en=1 note: digital out and oe are matrix output, digital in is matri x input (for pins 7, 13, 14, 18 and 19 only) digital out digital out oe od2x_en oe od1x_en digital out oe pp2x_en digital out oe pp1x_en digital in low voltage input non-schmitt trigger input analog io oe lv_en schmitt trigger input oe smt_en oe wosmt_en
SLG46531_ds_109 page 38 of 169 SLG46531 7.6.2 matrix oe io struc ture (for pi ns 8 and 9) figure 4. matrix oe io structure diagram pad s0 s1 s2 s3 floating 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? pin 8, pin 9 mode [2:0] 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: reserved 101: open drain nmos 110: reserved 111: reserved note: digital out and oe are matrix output, digital in is matri x input digital out oe od1x_en digital in low voltage input non-schmitt trigger input analog io oe lv_en schmitt trigger input oe smt_en oe wosmt_en
SLG46531_ds_109 page 39 of 169 SLG46531 7.6.3 matrix oe 4x driv e structure (for pin 10) figure 5. matrix oe io 4x drive structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? low voltage input non-schmitt trigger input input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1 01: digital in with schmitt trigger, smt_en=1 10: low voltage digital in mode, lv_en = 1 11: analog io mode output mode [1:0] 00: 1x push-pull mode, pp1x_en=1 01: 2x push-pull mode, pp2x_en=1, pp1x_en=1 10: 1x nmos open drain mode, od1x_en=1, odn_en=1 11: 2x nmos open drain mode, od2x_en=1, od1x_en=1, odn_en=1 note: digital out and oe are matrix output, digital in is matri x input analog io digital out digital out oe oe digital out oe pp2x_en digital out oe pp1x_en oe lv_en schmitt trigger input oe smt_en oe wosmt_en odn_en od1x_en 4x_en oe digital out od2x_en 4x_en odn_en odn_en 4x_en digital out oe odn_en 4x_en
SLG46531_ds_109 page 40 of 169 SLG46531 7.7 io structure 7.7.1 io structure (for pins 4, 6, 15, 17, 20) figure 6. io structure diagram pad s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? mode [2:0] 000: digital in without schmitt trigger, wosmt_en=1, oe = 0 001: digital in with schmitt trigger, smt_en=1, oe = 0 010: low voltage digital in mode, lv_en = 1, oe = 0 011: analog io mode 100: push-pull mode, pp_en=1, oe = 1 101: nmos open drain mode, odn_en=1, oe = 1 110: pmos open drain mode, odp_en=1, oe = 1 111: analog io and nmos open-drain mode, odn_en=1 and aio_en=1 note 1: oe cannot be selected by user note 2: digital out and oe are matrix output, digital in is mat rix input digital out digital out oe odn_en oe odn_en digital out oe 2x_en pp_en 2x_en odp_en digital out oe pp_en 2x_en odp_en digital in low voltage input non-schmitt trigger input analog io oe lv_en schmitt trigger input oe smt_en oe wosmt_en
SLG46531_ds_109 page 41 of 169 SLG46531 7.7.2 4x drive str ucture (for pin 12) figure 7. io 4x drive structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? low voltage input non-schmitt trigger input analog io digital out digital out oe oe digital out oe pp2x_en digital out oe pp1x_en oe lv_en schmitt trigger input oe smt_en oe wosmt_en odn_en od1x_en 4x_en oe digital out od2x_en 4x_en odn_en odn_en 4x_en digital out oe odn_en 4x_en mode [2:0] 000: digital in without schmitt trigger, wosmt_en=1, oe = 0 001: digital in with schmitt trigger, smt_en=1, oe = 0 010: low voltage digital in mode, lv_en = 1, oe = 0 011: analog io mode 100: push-pull mode, pp_en=1, oe = 1 101: nmos open drain mode, odn_en=1, oe = 1 110: pmos open drain mode, odp_en=1, oe = 1 111: analog io and nmos open-drain mode, odn_en=1 and aio_en=1 note 1: oe cannot be selected by user note 2: digital out and oe are matrix output, digital in is mat rix input
SLG46531_ds_109 page 42 of 169 SLG46531 8.0 connection matrix the connection matrix in the SLG46531 is used to create the internal routing for internal functional macrocells of the device once it is programmed. the registers are programmed from the one-tim e nvm cell during test mode operation. the output of each functional macrocell within the SLG46531 has a specific digital bit code assigned to it that is either set to active high or inactive low based on the design that is created. once the 2048 register bits within the SLG46531 are programmed a fully custom circu it will be created. the connection matrix has 64 inputs and 110 outputs. each of th e 64 inputs to the connection matrix is hard-wired to the digit al output of a particular source macrocell, including i/o pins, lu ts, analog comparators, other digital resources and vdd and ground. the input to a digital macrocell uses a 6-bit register to select one of these 64 input lines. for a complete list of the slg 46531s register t able, see secti on 22.0 appendix a - slg465 31 register definition. figure 8. connection matrix figure 9. connection matrix example ground 0 pin 2 digital in 1 pin 3 digital in 2 pin 4 digital in 3 matrix input signal functions n resetb_core 62 vdd 63 n function registers 109 matrix out: pd of either temp out or xtal osc reg<877:872> 0 matrix out: asm-state0-en0 reg<5:0> 1 matrix out: asm-state0-en1 reg<13:8> 2 matrix out: asm-state0-en2 reg<21:16> matrix inputs matrix outputs pin 12 pin 13 pin 14 connection matrix lut pin 13 pin 12 lut pin 14 function
SLG46531_ds_109 page 43 of 169 SLG46531 8.1 matrix input table table 42. matrix input table matrix input number matrix input signal function matrix decode 5 4 3 2 1 0 0 ground 000000 1 pin2 digital input 0 0 0 0 0 1 2 pin3 digital input 0 0 0 0 1 0 3 pin4 digital input 0 0 0 0 1 1 4 pin5 digital input 0 0 0 1 0 0 5 pin6 digital input 0 0 0 1 0 1 6 pin7 digital input 0 0 0 1 1 0 7 pin10 digital input 0 0 0 1 1 1 8 lut2_0 / dff0 output 0 0 1 0 0 0 9 lut2_1 / dff1 output 0 0 1 0 0 1 10 lut2_2 / dff2 output 0 0 1 0 1 0 11 lut2_3 / pgen output 0 0 1 0 1 1 12 lut3_0 / dff3 output 0 0 1 1 0 0 13 lut3_1 / dff4 output 0 0 1 1 0 1 14 lut3_2 / dff5 output 0 0 1 1 1 0 15 lut3_3 / dff6 output 0 0 1 1 1 1 16 lut3_4 / dff7 output 0 1 0 0 0 0 17 lut3_5 / cnt_dly2(8bit) output 0 1 0 0 0 1 18 lut3_6 / cnt_dly3(8bit) output 0 1 0 0 1 0 19 lut3_7 / cnt_dly4(8bit) output 0 1 0 0 1 1 20 lut3_8 / cnt_dly5(8bit) output 0 1 0 1 0 0 21 lut3_9 / cnt_dly6(8bit) output 0 1 0 1 0 1 22 lut4_0 / cnt_dly0(16bit) output 0 1 0 1 1 0 23 lut4_1 / cnt_dly1(16bit) output 0 1 0 1 1 1 24 lut3_10 / pipe delay ( 1st stage) output 0 1 1 0 0 0 25 pipe delay output0 0 1 1 0 0 1 26 pipe delay output1 0 1 1 0 1 0 27 internal osc pre-divided by 1/2/4/8 output and post-divided by 1/2/3/4/8/12/ 24/64 output ( 25khz/2mhz) 011011 28 internal osc pre-divided by 1/2/4/8 output and post-divided by 1/2/3/4/8/12/ 24/64 output ( 25khz/2mhz) 011100 29 internal osc pre-divided by 1/2/4/8 output (25mhz) 011101 30 filter0 / edge det ect0 output 0 1 1 1 1 0 31 filter1 / edge det ect1 output 0 1 1 1 1 1 32 pin8 digital or i2c_virtual_0 input 1 0 0 0 0 0 33 pin9 digital or i2c_virtual_1 input 1 0 0 0 0 1 34 i2c_virtual_2 input 1 0 0 0 1 0 35 i2c_virtual_3 input 1 0 0 0 1 1
SLG46531_ds_109 page 44 of 169 SLG46531 36 i2c_virtual_4 input 1 0 0 1 0 0 37 i2c_virtual_5 input 1 0 0 1 0 1 38 i2c_virtual_6 input 1 0 0 1 1 0 39 i2c_virtual_7 input 1 0 0 1 1 1 40 asm-statex-dout0 1 0 1 0 0 0 41 asm-statex-dout1 1 0 1 0 0 1 42 asm-statex-dout2 1 0 1 0 1 0 43 asm-statex-dout3 1 0 1 0 1 1 44 asm-statex-dout4 1 0 1 1 0 0 45 asm-statex-dout5 1 0 1 1 0 1 46 asm-statex-dout6 1 0 1 1 1 0 47 asm-statex-dout7 1 0 1 1 1 1 48 pin12 digital input 1 1 0 0 0 0 49 pin13 digital input 1 1 0 0 0 1 50 pin14 digital input 1 1 0 0 1 0 51 pin15 digital input 1 1 0 0 1 1 52 pin16 digital input 1 1 0 1 0 0 53 pin17 digital input 1 1 0 1 0 1 54 pin18 digital input 1 1 0 1 1 0 55 pin19 digital input 1 1 0 1 1 1 56 pin20 digital input 1 1 1 0 0 0 57 acmp_0 output 1 1 1 0 0 1 58 acmp_1 output 1 1 1 0 1 0 59 acmp_2 output 1 1 1 0 1 1 60 acmp_3 output 1 1 1 1 0 0 61 programmable delay with e dge detector output 1 1 1 1 0 1 62 resetb_core (por) as matrix input 1 1 1 1 1 0 63 vdd 111111 table 42. matrix input table matrix input number matrix input signal function matrix decode 5 4 3 2 1 0
SLG46531_ds_109 page 45 of 169 SLG46531 8.2 matrix output table table 43. matrix output table register bit address matrix output signal function note: for each address, the two m ost significant bits are unuse d) matrix output number reg <7:0> matrix out: asm-state0-en0 0 reg <15:8> matrix out: asm-state0-en1 1 reg <23:16> matrix out: asm-state0-en2 2 reg <31:24> matrix out: asm-state1-en0 3 reg <39:32> matrix out: asm-state1-en1 4 reg <47:40> matrix out: asm-state1-en2 5 reg <55:48> matrix out: asm-state2-en0 6 reg <63:56> matrix out: asm-state2-en1 7 reg <71:64> matrix out: asm-state2-en2 8 reg <79:72> matrix out: asm-state3-en0 9 reg <87:80> matrix out: asm-state3-en1 10 reg <95:88> matrix out: asm-state3-en2 11 reg <103:96> matrix out: asm-state4-en0 12 reg <111:104> matrix out: asm-state4-en1 13 reg <119:112> matrix out: asm-state4-en2 14 reg <127:120> matrix out: asm-state5-en0 15 reg <135:128> matrix out: asm-state5-en1 16 reg <143:136> matrix out: asm-state5-en2 17 reg <151:144> matrix out: asm-state6-en0 18 reg <159:152> matrix out: asm-state6-en1 19 reg <167:160> matrix out: asm-state6-en2 20 reg <175:168> matrix out: asm-state7-en0 21 reg <183:176> matrix out: asm-state7-en1 22 reg <191:184> matrix out: asm-state7-en2 23 reg <199:192> matrix out: asm-state-nrst 24 reg <207:200> matrix out: pi n3 digital output source 25 reg <215:208> matrix out : pin3 output enable 26 reg <223:216> matrix out: pi n4 digital output source 27 reg <231:224> matrix out: pi n5 digital output source 28 reg <239:232> matrix out : pin5 output enable 29 reg <247:240> matrix out: pi n6 digital output source 30 reg <255:248> matrix out: pi n7 digital output source 31 reg <263:256> matrix out : pin7 output enable 32 reg <271:264> matrix out: pin8 dig ital output source (scl with v i/input & nmos open-drain) 33 reg <279:272> matrix out: pin9 dig ital output source (sda with vi/input & nmos open-drain) 34 reg <287:280> matrix out: pin1 0 digital output source 35 reg <295:288> matrix out: pin10 output enable 36 reg <303:296> matrix out: pin1 2 digital output source 37
SLG46531_ds_109 page 46 of 169 SLG46531 reg <311:304> matrix out: pin1 3 digital output source 38 reg <319:312> matrix out: pin13 output enable 39 reg <327:320> matrix out: pin1 4 digital output source 40 reg <335:328> matrix out: pin14 output enable 41 reg <343:336> matrix out: pin1 5 digital output source 42 reg <351:344> matrix out: pin1 6 digital output source 43 reg <359:352> matrix out: pin16 output enable 44 reg <367:360> matrix out: pin1 7 digital output source 45 reg <375:368> matrix out: pin1 8 digital output source 46 reg <383:376> matrix out: pin18 output enable 47 reg <391:384> matrix out: pin1 9 digital output source 48 reg <399:392> matrix out: pin19 output enable 49 reg <407:400> matrix out: pin2 0 digital output source 50 reg <415:408> matrix out: acmp0 pdb (power down) 51 reg <423:416> matrix out: acmp1 pdb (power down) 52 reg <431:424> matrix out: acmp2 pdb (power down) 53 reg <439:432> matrix out: acmp3 pdb (power down) 54 reg <447:440> matrix out: input of filter_0 with fixed time edge detector 55 reg <455:448> matrix out: input of filter_1 with fixed time edge detector 56 reg <463:456> matrix out: input of programmable delay & edge det ector 57 reg <471:464> matrix out: osc 25khz/2mhz pdb (power down) 58 reg <479:472> matrix out: os c 25mhz pdb (power down) 59 reg <487:480> matrix out: in0 o f lut2_0 or clock input of dff0 60 reg <495:488> matrix out: in1 o f lut2_0 or data input of dff0 61 reg <503:496> matrix out: in0 o f lut2_1 or clock input of dff1 62 reg <511:504> matrix out: in1 o f lut2_1 or data input of dff1 63 reg <519:512> matrix out: in0 o f lut2_2 or clock input of dff2 64 reg <527:520> matrix out: in1 o f lut2_2 or data input of dff2 65 reg <535:528> matrix out: in0 o f lut2_3 or clock input of pgen 66 reg <543:536> matrix out: in1 of lut2_3 or nrst of pgen 67 reg <551:544> matrix out: in0 o f lut3_0 or clock input of dff3 68 reg <559:552> matrix out: in1 o f lut3_0 or data input of dff3 69 reg <567:560> matrix out: in2 of l ut3_0 or nrst (nset) of dff3 70 reg <575:568> matrix out: in0 o f lut3_1 or clock input of dff4 71 reg <583:576> matrix out: in1 o f lut3_1 or data input of dff4 72 reg <591:584> matrix out: in2 of l ut3_1 or nrst (nset) of dff4 73 reg <599:592> matrix out: in0 o f lut3_2 or clock input of dff5 74 reg <607:600> matrix out: in1 o f lut3_2 or data input of dff5 75 reg <615:608> matrix out: in2 of l ut3_2 or nrst (nset) of dff5 76 table 43. matrix output table register bit address matrix output signal function note: for each address, the two m ost significant bits are unuse d) matrix output number
SLG46531_ds_109 page 47 of 169 SLG46531 reg <623:616> matrix out: in0 o f lut3_3 or clock input of dff6 77 reg <631:624> matrix out: in1 o f lut3_3 or data input of dff6 78 reg <639:632> matrix out: in2 of l ut3_3 or nrst (nset) of dff6 79 reg <647:640> matrix out: in0 o f lut3_4 or clock input of dff7 80 reg <655:648> matrix out: in1 o f lut3_4 or data input of dff7 81 reg <663:656> matrix out: in2 of l ut3_4 or nrst (nset) of dff7 82 reg <671:664> matrix out: in0 of lut3_5 or delay2 input (or coun ter2 rst input) 83 reg <679:672> matrix out: in1 o f lut3_5 or external clock input of delay2 (or counter2) 84 reg <687:680> matrix out: in2 of lut3_5 85 reg <695:688> matrix out: in0 of lut3_6 or delay3 input (or coun ter3 rst input) 86 reg <703:696> matrix out: in1 o f lut3_6 or external clock input of delay3 (or counter3) 87 reg <711:704> matrix out: in2 of lut3_6 88 reg <719:712> matrix out: in0 of lut3_7 or delay4 input (or coun ter4 rst input) 89 reg <727:720> matrix out: in1 o f lut3_7 or external clock input of delay4 (or counter4) 90 reg <735:728> matrix out: in2 of lut3_7 91 reg <743:736> matrix out: in0 of lut3_8 or delay5 input (or coun ter5 rst input) 92 reg <751:744> matrix out: in1 o f lut3_8 or external clock input of delay5 (or counter5) 93 reg <759:752> matrix out: in2 of lut3_8 94 reg <767:760> matrix out: in0 of lut3_9 or delay6 input (or coun ter6 rst input) 95 reg <775:768> matrix out: in1 o f lut3_9 or external clock input of delay6 (or counter6) 96 reg <783:776> matrix out: in2 of lut3_9 97 reg <791:784> matrix out: in0 of lut3_10 or input of pipe delay 9 8 reg <799:792> matrix out: in1 of l ut3_10 or nrst of pipe delay 99 reg <807:800> matrix out: in2 of lut3_10 or clock of pipe delay 1 00 reg <815:808> matrix out: in0 of lut4_0 or delay0 input (or coun ter0 rst/set input) 101 reg <823:816> matrix out: in1 o f lut4_0 or external clock input of delay0 (or counter0) 102 reg <831:824> matrix out: in2 o f lut4_0 or up input of fsm0 103 reg <839:832> matrix out: in3 o f lut4_0 or keep input of fsm0 104 reg <847:840> matrix out: in0 of lut4_1 or delay1 input (or coun ter1 rst/set input) 105 reg <855:848> matrix out: in1 o f lut4_1 or external clock input of delay1 (or counter1) 106 reg <863:856> matrix out: in2 o f lut4_1 or up input of fsm1 107 reg <871:864> matrix out: in3 o f lut4_1 or keep input of fsm1 108 reg <879:872> matrix out: pd of ei ther temp-output with bg and/o r crystal oscillator by reg<1268> 109 table 43. matrix output table register bit address matrix output signal function note: for each address, the two m ost significant bits are unuse d) matrix output number
SLG46531_ds_109 page 48 of 169 SLG46531 8.3 connection matrix virtual inputs as mentioned previously, the conn ection matrix inputs come from the outputs of various digital m acrocells on the device. eight of the connection matrix inputs have the special characteristic that the state of these signal lines comes from a correspondin g data bit written as a register value via i 2 c. this gives the user the ability to write data via the serial channel, and have this information translated into sig nals that can be driven into the connection matrix and from the connection matrix to the digita l inputs of other macrocell s on the device. the i 2 c address for reading and writing these regist er values is at b yte 0244. six of the eight connection matr ix virtual inputs are dedicated to this virtual input function. an i 2 c write command to these register bits will set the signal values going into the connection matrix to the desired state. a read command to these register bits w ill read either the original data values coming from the nvm memory bits (that were loaded during the initial device startup), or the v alues from a previous write command (if that has happened). two of the eight connection matrix virtual inputs are shared with pin digital inputs,(pin8 digital or i2c_virtual_0 input) and (pin9 digital or i2c_virtual_1 input). if the virtual input mode is s elected, an i 2 c write command to these register bits will set the signal values going into the connection matrix to the desired state. a read command to these register bits will read either the origi nal data values coming from the nvm memory bits (that were loaded d uring the initial device startup ), or the values from a previou s write command (if that has happen ed). two register bits select whether the connection matrix in put comes from the pin input or from the virtual register: ? reg <1074> select scl & v irtual input 0 or pin8 ? reg <1082> select sda & v irtual input 1 or pin9 see table below for connecti on matrix virtual inputs. 8.4 connection matrix virtual outputs the digital outputs of the various macrocells are routed to the connection matrix to enable interconnections to the inputs of other macrocells in the device. at the same time, it is possible to r ead the state of each of the macrocell outputs as a register va lue via i 2 c. this option, called connecti on matrix virtual outputs, allow s the user to remotely read the values of each macrocell output . the i 2 c addresses for reading these register values are at bytes 0240 to 0247. write commands to these same register values will be ignored (with the exception of the virtual input regist er bits at byte 0244). matrix input number matrix input signal function register bit addresses (d) 32 i2c_virtual_0 input reg<1952> 33 i2c_virtual_1 input reg<1953> 34 i2c_virtual_2 input reg<1954> 35 i2c_virtual_3 input reg<1955> 36 i2c_virtual_4 input reg<1956> 37 i2c_virtual_5 input reg<1957> 38 i2c_virtual_6 input reg<1958> 39 i2c_virtual_7 input reg<1959>
SLG46531_ds_109 page 49 of 169 SLG46531 9.0 combination function macro cells the SLG46531 has seventeen combination function macrocells that can serve more than one logic or timing function. in each case, they can serve as a look up table (lut), or as another lo gic or timing function. see the list below for the functions th at can be implemented in these macrocells: ? three macrocells that can serve as either 2-bit luts or as d f lip flops. ? five macrocells that can serve as either 3-bit luts or as d fl ip flops with se t/reset input ? one macrocell that can serve as either 3-bit lut or as pipe de lay ? one macrocell that can serve as either 2-bit lut or as program mable pattern generator (pgen) ? five macrocells that can serve as either 3-bit luts or as 8-bi t counter / delays ? two macrocells that can serve as either 4-bit luts or as 16-bi t counter / delays inputs/outputs for the 17 combi nation function macrocells are c onfigured from the connection matrix with specific logic functi ons being defined by the state of nvm bits. when used as a lut to implement combinatorial logic functions, the outputs of the luts can be configured to any user defined function, including th e following standard digital logic device s (and, nand, or, nor, xor, xnor). 9.1 2-bit lut or d flip flop macrocells there are three macrocells that c an serve as either 2-bit luts or as d flip flops. when used to implement lut functions, the 2-bit luts each take in two input signals from the connection m atrix and produce a single output, which goes back into the connection matrix. when used to implement d flip flop function, the two input signals from the connection matrix go to the dat a (d) and clock (clk) inputs for t he flip flop, with the output g oing back to the connection matrix. the operation of the d flip-flop and latch will follow the functional descriptions below: dff: clk is rising edge triggered, then q = d; otherwise q will not change latch: if clk = 0, then q = d figure 10. 2-bit lut0 or dff0 dff0 clk d 2-bit lut0 out in0 in1 to connection matrix input <8> 4-bits nvm from connection matrix output <61> 1-bit nvm reg <1207:1204> reg <1191> from connection matrix output <60> q/nq reg <1207> dff or latch select reg <1206> output select (q or nq) reg <1205> dff initial polarity select lut truth table dff registers s0 s1 s0 s1 s0 s1 0: 2-bit lut0 in0 1: dff0 clk 0: 2-bit lut0 in1 1: dff0 data 0: 2-bit lut0 out 1: dff0 out
SLG46531_ds_109 page 50 of 169 SLG46531 figure 11. 2-bit lut1 or dff1 figure 12. 2-bit lut2 or dff2 dff1 clk d 2-bit lut1 out in0 in1 to connection matrix input <9> 4-bits nvm from connection matrix output <63> 1-bit nvm reg <1203:1200> reg <1190> from connection matrix output <62> q/nq reg <1203> dff or latch select reg <1202> output select (q or nq) reg <1201> dff initial polarity select lut truth table dff registers s0 s1 s0 s1 s0 s1 0: 2-bit lut1 in0 1: dff1 clk 0: 2-bit lut1 in1 1: dff1 data 0: 2-bit lut1 out 1: dff1 out dff2 clk d 2-bit lut2 out in0 in1 to connection matrix input <10> 4-bits nvm from connection matrix output <65> 1-bit nvm reg <1215:1212> reg <1189> from connection matrix output <64> q/nq reg <1215> dff or latch select reg <1214> output select (q or nq) reg <1213> dff initial polarity select lut truth table dff registers s0 s1 s0 s1 s0 s1 0: 2-bit lut2 in0 1: dff2 clk 0: 2-bit lut2 in1 1: dff2 data 0: 2-bit lut2 out 1: dff2 out
SLG46531_ds_109 page 51 of 169 SLG46531 9.1.1 2-bit lut or d flip flop macrocells used as 2-bit luts each macrocell, when programmed for a lut function, uses a 4-bi t register to define their output function: 2-bit lut0 is defined by reg<1207:1204> 2-bit lut1 is defined by reg<1203:1200> 2-bit lut2 is defined by reg<1215:1212> the table below shows the regist er bits for the standard digita l logic devices (and, nand, or , nor, xor, xnor) that can be created within each of the t wo 2-bit lut logic cells. table 47. 2-bit lut stand ard digital functions function msb lsb and-2 1000 nand-2 0 1 1 1 or-2 1110 nor-2 0 0 0 1 xor-2 0110 xnor-2 1001 table 44. 2-bit lut0 truth table in1 in0 out 0 0 reg <1204> lsb 0 1 reg <1205> 1 0 reg <1206> 1 1 reg <1207> msb table 45. 2-bit lut1 truth table in1 in0 out 0 0 reg <1200> lsb 0 1 reg <1201> 1 0 reg <1202> 1 1 reg <1203> msb table 46. 2-bit lut2 truth table in1 in0 out 0 0 reg <1212> lsb 0 1 reg <1213> 1 0 reg <1214> 1 1 reg <1215> msb
SLG46531_ds_109 page 52 of 169 SLG46531 9.1.2 2-bit lut or d flip flop macrocells used as d flip flop register settings table 48. dff0 register settings signal function register bit address register definition lut2_0 or dff0 select <1191> 0: lut2_0 1: dff0 dff0 initial polarity select <1205> 0: low 1: high dff0 output select <1206> 0: q output 1: nq output dff0 or latch select <1207> 0: dff function 1: latch function table 49. dff1 register settings signal function register bit address register definition lut2_1 or dff1 select <1190> 0: lut2_1 1: dff1 dff1 initial polarity select <1201> 0: low 1: high dff1 output select <1202> 0: q output 1: nq output select or latch select <1203> 0: dff function 1: latch function table 50. dff2 register settings signal function register bit address register definition lut2_2 or dff2 select <1189> 0: lut2_2 1: dff2 dff2 initial polarity select <1213> 0: low 1: high dff2 output select <1214> 0: q output 1: nq output dff2 or latch select <1215> 0: dff function 1: latch function
SLG46531_ds_109 page 53 of 169 SLG46531 9.2 initial polarity operations figure 13. dff polarity operations
SLG46531_ds_109 page 54 of 169 SLG46531 9.3 2-bit lut or progr ammable pattern generator the SLG46531 has one combination function macrocell that can se rve as a logic or timing function. this macrocell can serve as a look up table (lut), or progra mmable pattern generator (pgen) . when used to implement lut functions, the 2-bit lut takes in tw o input signals from the connection matrix and produce a single output, which goes back into the connection matrix. when used a s a lut to implement combinatorial logic functions, the outputs of the luts can be configured to any user defined function, inc luding the following standard digital logic devices (and, nand, or, nor, xor, xnor). the user can also define the combinatorial relationship between inputs and outputs to be any selectable function. when operating as a programmable pattern generator, the output of the block with clock out a sequence of two to sixteen bits that are user selectable in their bit values, and user selectab le in the number of bits (up to sixteen) that are output before the pattern repeats. figure 14. 2-bit lut2 or pgen pgen out clk nrst 2-bit lut3 out to connection matrix input <11> from connection matrix output <66> reg <1211:1208> reg <1188> from connection matrix output <67> in0 in1 reg <1623:1616> lut truth table pgen pattern pgen counter data 0: 2-bit lut3 out 1: pgen out s0 s1
SLG46531_ds_109 page 55 of 169 SLG46531 9.4 3-bit lut or d flip flop with set/reset macrocells there are five macrocells that can serve as either 3-bit luts o r as d flip flops with set/reset inputs. when used to implement lut functions, the 3-bit luts each take in three input signals from the connection matrix and produce a single output, which g oes back into the connection matrix. when used to implement d flip flop function, the three input signals from the connection matr ix go to the data (d) and clock (clk) and set/reset (nrst/nset) in puts for the flip flop, with the output going back to the conne ction matrix. dff3 has a user selectable option to allow the macrocell output to either come from the q/nq output of one d flip flop, or two d flip flops in series, with the first d flip flop triggering o n the rising clock edge, and the second d flip flop triggering on the falling clock edge. figure 15. 3-bit lut0 or dff3 with rst/set dff3 clk d to connection matrix input <12> 8-bits nvm from connection matrix output <70> 1-bit nvm 3-bit lut0 out in1 in2 in0 nrst/nset from connection matrix output <69> from connection matrix output <68> reg <1223:1216> reg <1187> reg <1471> selects output from one or two dff q/nq ddq q reg <1222> reg <1471> lut truth tab l e reg <1223> dff or latch select reg <1222> output select (q or nq) reg <1221> dff nrst or nset select reg <1220> dff initial polarity select s0 s1 s0 s1 s0 s1 s0 s1 0: 3-bit lut0 in1 1: dff3 d 0: 3-bit lut0 in1 1: dff3 nrset/nset 0: 3-bit lut0 out 1: dff3 out 0: 3-bit lut0 in0 1: dff3 clk
SLG46531_ds_109 page 56 of 169 SLG46531 figure 16. 3-bit lut1 or dff4 figure 17. 3-bit lut2 or dff5 dff4 clk d 8-bits nvm 1-bit nvm 3-bit lut1 out in1 in2 in0 nrst/nset from connection matrix output <73> from connection matrix output <72> from connection matrix output <71> reg <1231:1224> reg <1186> to connection matrix< input 13> q/nq reg <1231> dff or latch select reg <1230> output select (q or nq) reg <1229> dff nrst or nset select reg <1228> dff initial polarity select lut truth tab l e dff registers s0 s1 s0 s1 s0 s1 s0 s1 0: 3-bit lut1 in1 1: dff4 d 0: 3-bit lut1 in1 1: dff4 nrset/nset 0: 3-bit lut1 out 1: dff4 out 0: 3-bit lut1 in0 1: dff4 clk dff5 clk d to connection matrix< input 14> 8-bits nvm from connection matrix output <76> 1-bit nvm 3-bit lut2 out in1 in2 in0 nrst/nset from connection matrix output <75> from connection matrix output <74> reg <1239:1232> reg <1185> q/nq reg <1239> dff or latch select reg <1238> output select (q or nq) reg <1237> dff nrst or nset select reg <1236> dff initial polarity select lut truth table dff registers s0 s1 s0 s1 s0 s1 s0 s1 0: 3-bit lut2 in1 1: dff5 d 0: 3-bit lut2 in1 1: dff5 nrset/nset 0: 3-bit lut2 out 1: dff5 out 0: 3-bit lut2 in0 1: dff5 clk
SLG46531_ds_109 page 57 of 169 SLG46531 figure 18. 3-bit lut3 or dff6 figure 19. 3-bit lut4 or dff7 dff6 clk d 8-bits nvm 1-bit nvm 3-bit lut3 out in1 in2 in0 nrst/nset from connection matrix output <79> from connection matrix output <78> from connection matrix output <77> reg <1247:1240> reg <1184> to connection matrix< input 15> q/nq reg <1247> dff or latch select reg <1246> output select (q or nq) reg <1245> dff nrst or nset select reg <1244> dff initial polarity select lut truth tab l e dff registers s0 s1 s0 s1 s0 s1 s0 s1 0: 3-bit lut3 in1 1: dff6 d 0: 3-bit lut3 in1 1: dff6 nrset/nset 0: 3-bit lut3 out 1: dff6 out 0: 3-bit lut3 in0 1: dff6 clk dff7 clk d to connection matrix< input 16> 8-bits nvm from connection matrix output <82> 1-bit nvm 3-bit lut4 out in1 in2 in0 nrst/nset from connection matrix output <81> from connection matrix output <80> reg <1255:1248> reg <1199> q/nq reg <1255> dff or latch select reg <1254> output select (q or nq) reg <1253> dff nrst or nset select reg <1252> dff initial polarity select lut truth table dff registers 0: 3-bit lut4 in1 1: dff7 d 0: 3-bit lut4 in1 1: dff7 nrset/nset 0: 3-bit lut4 out 1: dff7 out 0: 3-bit lut4 in0 1: dff7 clk s0 s1 s0 s1 s0 s1 s0 s1
SLG46531_ds_109 page 58 of 169 SLG46531 9.4.1 3-bit lut or d flip flop macrocells used as 3-bit luts each macrocell, when programmed for a lut function, uses a 8-bi t register to define their output function: 3-bit lut0 is defined by reg<1223:1216> 3-bit lut1 is defined by reg<1231:1324> 3-bit lut2 is defined by reg<1239:1232> 3-bit lut3 is defined by reg<1247:1240> 3-bit lut5 is defined by reg<1235:1248> table 51. 3-bit lut0 truth table in2 in1 in0 out 0 0 0 reg <1216> lsb 0 0 1 reg <1217> 0 1 0 reg <1218> 0 1 1 reg <1219> 1 0 0 reg <1220> 1 0 1 reg <1221> 1 1 0 reg <1222> 1 1 1 reg <1223> msb table 52. 3-bit lut1 truth table in2 in1 in0 out 0 0 0 reg <1224> lsb 0 0 1 reg <1225> 0 1 0 reg <1226> 0 1 1 reg <1227> 1 0 0 reg <1228> 1 0 1 reg <1229> 1 1 0 reg <1230> 1 1 1 reg <1231> msb table 53. 3-bit lut2 truth table in2 in1 in0 out 0 0 0 reg <1232> lsb 0 0 1 reg <1233> 0 1 0 reg <1234> 0 1 1 reg <1235> 1 0 0 reg <1236> 1 0 1 reg <1237> 1 1 0 reg <1238> 1 1 1 reg <1239> msb table 54. 3-bit lut3 truth table in2 in1 in0 out 0 0 0 reg <1240> lsb 0 0 1 reg <1241> 0 1 0 reg <1242> 0 1 1 reg <1243> 1 0 0 reg <1244> 1 0 1 reg <1245> 1 1 0 reg <1246> 1 1 1 reg <1247> msb table 55. 3-bit lut4 truth table in2 in1 in0 out 0 0 0 reg <1248> lsb 0 0 1 reg <1249> 0 1 0 reg <1250> 0 1 1 reg <1251> 1 0 0 reg <1252> 1 0 1 reg <1253> 1 1 0 reg <1254> 1 1 1 reg <1255> msb
SLG46531_ds_109 page 59 of 169 SLG46531 the table below shows the regist er bits for the standard digita l logic devices (and, nand, or , nor, xor, xnor) that can be created within each of the s ix 3-bit lut logic cells. 9.4.2 3-bit lut or d flip flop macrocells used as d flip flop register settings table 56. 3-bit lut stand ard digital functions function msb lsb and-3 10000000 nand-3 01111111 or-3 11111110 nor-3 00000001 xor-3 10010110 xnor-3 01101001 table 57. dff3 register settings signal function register bit address register definition lut3_0 or dff3 select reg<1187> 0: lut3_0 1: dff3 dff3 initial polarity select reg<1220> 0: low 1: high dff3 nrst/nset select reg<1221> 1: nset from matrix out 0: nrst from matrix out dff3 output select reg<1222> 0: q output 1: nq output dff3 or latch select reg<1223> 0: dff function 1: latch function table 58. dff4 register settings signal function register bit address register definition lut3_1 or dff4 select reg<1186> 0: lut3_1 1: dff4 dff4 initial polarity select reg<1128> 0: low 1: high dff4 nrst/nset select reg<1129> 1: nset from matrix out 0: nrst from matrix out dff4 output select reg<1130> 0: q output 1: nq output dff4 or latch select reg<1131> 0: dff function 1: latch function
SLG46531_ds_109 page 60 of 169 SLG46531 table 59. dff5 register settings signal function register bit address register definition lut3_2 or dff5 select reg<1185> 0: lut3_2 1: dff5 dff5 initial polarity select reg<1236> 0: low 1: high dff5 nrst/nset select reg<1237> 1: nset from matrix out 0: nrst from matrix out dff5 output select reg<1238> 0: q output 1: nq output dff5 or latch select reg<1239> 0: dff function 1: latch function table 60. dff6 register settings signal function register bit address register definition lut3_3 or dff6 select reg<1184> 0: lut3_3 1: dff6 dff6 initial polarity select reg<1244> 0: low 1: high dff6 nrst/nset select reg<1245> 1: nset from matrix out 0: nrst from matrix out dff6 output select reg<1246> 0: q output 1: nq output dff6 or latch select reg<1247> 0: dff function 1: latch function table 61. dff7 register settings signal function register bit address register definition lut3_4 or dff7 select reg<1199> 0: lut3_4 1: dff7 dff7 initial polarity select reg<1252> 0: low 1: high dff7 nrst/nset select reg<1253> 1: nset from matrix out 0: nrst from matrix out dff7 output select reg<1254> 0: q output 1: nq output dff7 or latch select reg<1255> 0: dff function 1: latch function
SLG46531_ds_109 page 61 of 169 SLG46531 9.5 initial polarity operations figure 20. dff polarity operations with nreset
SLG46531_ds_109 page 62 of 169 SLG46531 figure 21. dff polarity operations with nset
SLG46531_ds_109 page 63 of 169 SLG46531 9.6 3-bit lut or pipe delay macrocell there is one macrocell that can serve as either a 3-bit lut or as a pipe delay. when used to implement lut functions, the 3-bit lut take in thr ee input signals from the connection matrix and produces a sing le output, which goes back into the connection matrix. when used as a pipe delay, there are three inputs signals from the matrix, input (in), clock (clk) and reset (rst). the pipe delay cell is built from 16 d flip-flop logic cells that provide the three output opt ions, two of which ar e user selectable. t he dff cells are tied in series where the output (q) of each delay cel l goes to the next dff cell. the first delay option (out2) is f ixed at the output of the first flip-f lop stage. the other two outputs (out0 and out1) provide user selectable options for 1 C 16 stag es of delay there are delay output points for each set of the out0 and out1 outputs to a 16-input mux that is controlled by reg <1259:1256> for out0 and reg <1263 :1260> for out1. the 16-input mux is used to select the amount of delay. the overall time of the delay is based on the clock used in the SLG46531 design. each dff cell has a time delay of the inverse of the clock time (either extern al clock or the r c oscillator w ithin the SLG46531). th e sum of the number of dff cells used wi ll be the total time delay of the pipe delay logic cell. note: clk is rising edge triggered. figure 22. 3-bit lut10 or pipe delay 3-bit lut10 out in1 in0 from connection matrix output <98> from connection matrix output <99> in2 from connection matrix output <100> 16 flip flop block nrst in clk from connection matrix output <98> from connection matrix output <99> from connection matrix output <100> reg <1263:1260> reg <1259:1256> to connection matrix input<26> to connection matrix input <25> out1 out0 reg <1271> to connection matrix input <24> out2 s0 s1 s0 s1 lut truth ta bl e reg <1263:1256> reg <1270>
SLG46531_ds_109 page 64 of 169 SLG46531 9.6.1 3-bit lut or pipe delay macrocells used as 3-bit luts each macrocell, when programmed for a lut function, uses a 8-bi t register to define their output function: 3-bit lut10 is defined by reg<1263:1256> 9.6.2 3-bit lut or pipe delay macrocells used as pipe delay r egister settings table 63. pipe delay register settings signal function register bit address register definition lut3_10 or pipe delay output select reg<1270> 0: lut3_10 1: 1 pipe delay output out0 select reg<1259:1256> out1 select reg<1263:1260> pipe delay out1 polarity select bit reg<1271> 0: non-inverted 1: inverted table 62. 3-bit lut10 truth table in2 in1 in0 out 0 0 0 reg <1256> lsb 0 0 1 reg <1257> 0 1 0 reg <1258> 0 1 1 reg <1259> 1 0 0 reg <1260> 1 0 1 reg <1261> 1 1 0 reg <1262> 1 1 1 reg <1263> msb
SLG46531_ds_109 page 65 of 169 SLG46531 9.7 3-bit lut or 8-bit counter / delay macrocells there are five macrocells that c an serve as either 3-bit luts o r as counter / delays. when used to implement lut function, the 3-bit lut takes in three input signals from the connection matr ix and produces a single output, which goes back into the conne c- tion matrix. when used to implem ent 8-bit counter / delay funct ion, two of the three input signal s from the connection matrix go to the external clock (ext_clk) and reset (dly_n/cnt_reset) for the counter/delay, with the ou tput going back to the connectio n matrix. these macrocells can also operate in a one-shot mode, which wil l generate an output puls e of user-defined width. these macrocells can also operate in a frequency detection or e dge detection mode. two of the five macrocells can have their active count value re ad via i 2 c (cnt4 and cnt6). see section 19.4.6.3 for further details 9.7.1 3-bit lut or 8- bi t cnt/dly block diagrams figure 23. 3-bit lut5 or cnt/dly2 cnt/dly2 out clk dly_n/cnt_reset 3-bit lut5 out in0 in1 16-bits nvm 1-bit nvm in2 reg <1543:1536> reg <1198> from connection matrix output <83> from connection matrix output <84> to connection matrix input <17> from connection matrix output <85> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut5 in1 1: cnt/dly2 clk 0: 3-bit lut5 out 1: cnt/dly2 out 0: 3-bit lut5 in0 1: cnt/dly2 rst
SLG46531_ds_109 page 66 of 169 SLG46531 figure 24. 3-bit lut6 or cnt/dly3 figure 25. 3-bit lut7 or cnt/dly4 cnt/dly3 out clk dly_n/cnt_reset 3-bit lut6 out in0 in1 16-bits nvm 1-bit nvm in2 reg <1551:1544> reg <1197> from connection matrix output <86> from connection matrix output <87> to connection matrix input <18> from connection matrix output <88> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut6 in1 1: cnt/dly3 clk 0: 3-bit lut6 out 1: cnt/dly3 out 0: 3-bit lut6 in0 1: cnt/dly3 rst cnt/dly4 out clk dly_n/cnt_reset 3-bit lut7 out in0 in1 16-bits nvm 1-bit nvm in2 reg <1559:1552> reg <1196> from connection matrix output <89> from connection matrix output <90> to connection matrix input <19> from connection matrix output <91> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut7 in1 1: cnt/dly4 clk 0: 3-bit lut7 out 1: cnt/dly4 out 0: 3-bit lut7 in0 1: cnt/dly4 rst
SLG46531_ds_109 page 67 of 169 SLG46531 figure 26. 3-bit lut8 or cnt/dly5 figure 27. 3-bit lut9 or cnt/dly6 cnt/dly5 out clk dly_n/cnt_reset 3-bit lut8 out in0 in1 16-bits nvm 1-bit nvm in2 reg <1567:1560> reg <1195> from connection matrix output <92> from connection matrix output <93> to connection matrix input <20> from connection matrix output <94> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut8 in1 1: cnt/dly5 clk 0: 3-bit lut8 out 1: cnt/dly5 out 0: 3-bit lut8 in0 1: cnt/dly5 rst cnt/dly6 out clk dly_n/cnt_reset 3-bit lut9 out in0 in1 16-bits nvm 1-bit nvm in2 reg <1575:1568> reg <1194> from connection matrix output <95> from connection matrix output <96> to connection matrix input <21> from connection matrix output <97> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut9 in1 1: cnt/dly6 clk 0: 3-bit lut9 out 1: cnt/dly6 out 0: 3-bit lut9 in0 1: cnt/dly6 rst
SLG46531_ds_109 page 68 of 169 SLG46531 9.7.2 3-bit lut or cnt/d lys used as 3-bit luts each macrocell, when programmed for a lut function, uses a 8-bi t register to define their output function: 3-bit lut5 is defined by reg<1543:1536> 3-bit lut6 is defined by reg<1551:1544> 3-bit lut7 is defined by reg<1559:1552> 3-bit lut8 is defined by reg<1567:1560> 3-bit lut9 is defined by reg<1575:1568> table 64. 3-bit lut5 truth table in2 in1 in0 out 0 0 0 reg <1536> lsb 0 0 1 reg <1537> 0 1 0 reg <1538> 0 1 1 reg <1539> 1 0 0 reg <1540> 1 0 1 reg <1541> 1 1 0 reg <1542> 1 1 1 reg <1543> msb table 65. 3-bit lut6 truth table in2 in1 in0 out 0 0 0 reg <1544> lsb 0 0 1 reg <1545> 0 1 0 reg <1546> 0 1 1 reg <1547> 1 0 0 reg <1548> 1 0 1 reg <1549> 1 1 0 reg <1550> 1 1 1 reg <1551> msb table 66. 3-bit lut7 truth table in2 in1 in0 out 0 0 0 reg <1552> lsb 0 0 1 reg <1553> 0 1 0 reg <1554> 0 1 1 reg <1555> 1 0 0 reg <1556> 1 0 1 reg <1557> 1 1 0 reg <1558> 1 1 1 reg <1559> msb table 67. 3-bit lut8 truth table in2 in1 in0 out 0 0 0 reg <1560> lsb 0 0 1 reg <1561> 0 1 0 reg <1562> 0 1 1 reg <1563> 1 0 0 reg <1564> 1 0 1 reg <1565> 1 1 0 reg <1566> 1 1 1 reg <1567> msb table 68. 3-bit lut9 truth table in2 in1 in0 out 0 0 0 reg <1568> lsb 0 0 1 reg <1569> 0 1 0 reg <1570> 0 1 1 reg <1571> 1 0 0 reg <1572> 1 0 1 reg <1573> 1 1 0 reg <1574> 1 1 1 reg <1575> msb
SLG46531_ds_109 page 69 of 169 SLG46531 9.7.3 3-bit lut or 8-bit count er / delay macrocells used as 8 -bit counter / delay register settings table 69. cnt/dly2 register settings signal function register bit address register d efinition lut3_5 or counter2 select reg<1198> 0: lut3_5 1: counter2 delay2 mode select or asynchronous counter reset reg<1273:1272> 00: on both falli ng and rising edges (for delay & counter reset) 01: on falling edge only (fo r delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or rising edges / high level res et counter/delay2 clock source select reg<1276:1274> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter1 overflow counter/delay2 output selection for counter mode reg<1277> 0: default output 1: edge detector output counter/delay2 mode selection reg<1279:1278> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay2 control data reg<1543:1536> 1 C 256 (delay time = (counter contr ol data +1) / freq) table 70. cnt/dly3 register settings signal function register bit address register d efinition lut3_6 or counter3 select reg<1197> 0: lut3_6 1: counter3 delay3 mode select or asynchronous counter reset reg<1281:1280> 00: on both falli ng and rising edges (for delay & counter reset) 01: on falling edge only (fo r delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or rising edges / high level res et counter/delay3 clock source select reg<1284:1282> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter2 overflow counter/delay3 output selection for counter mode reg<1285> 0: default output 1: edge detector output counter/delay2 mode selection reg<1287:1286> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay3 control data reg<1551:1544> 1 C 256 (delay time = (counter contr ol data +1) / freq)
SLG46531_ds_109 page 70 of 169 SLG46531 table 71. cnt/dly4 register settings signal function register bit address register definition lut3_7 or counter4 select reg<1196> 0: lut3_7 1: counter4 delay4 mode select or asynchronous counter reset reg<1289:1288> 00: on both falling and risi ng edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only ( for delay & counter reset) 11: no delay on either falling or rising edges / high level res et counter/delay4 clock source select reg<1292:1290> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter3 overflow counter/delay4 output selection for counter mode reg<1293> 0: default output 1: edge detector output counter/delay4 mode selection reg<1295:1294> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay4 control data reg<1559:1552> 1 C 256 (delay time = (counter contr ol data +1) / freq) table 72. cnt/dly5 register settings signal function register bit address register definition lut3_8 or counter5 select reg<1195> 0: lut3_8 1: counter5 delay5 mode select or asynchronous counter reset reg<1297:1296> 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or r ising edges / high level res et counter/delay5 clock source select reg<1300:1298> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter4 overflow counter/delay5 output selection for counter mode reg<1301> 0: default output 1: edge detector output counter/delay5 mode selection reg<1303:1302> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay5 control data reg<1567:1560> 1 C 256 (delay time = (counter contr ol data +1) / freq)
SLG46531_ds_109 page 71 of 169 SLG46531 table 73. cnt/dly6 register settings signal function register bit address register definition lut3_9 or counter5 select reg<1194> 0: lut3_9 1: counter6 delay6 mode select or asynchronous counter reset reg<1305:1304> 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or r ising edges / high level res et counter/delay6 clock source select reg<1308:1306> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter5 overflow counter/delay6 output selection for counter mode reg<1309> 0: default output 1: edge detector output counter/delay6 mode selection reg<1311:1310> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay6 control data reg<1575:1568> 1 C 256 (delay time = (counter contr ol data +1) / freq)
SLG46531_ds_109 page 72 of 169 SLG46531 9.7.4 cnt/dly timing diagrams figure 28. delay mode timing figure 29. counter mode timing delay_in rc osc: force power on (always running) delay output asynchronous delay variable asynchronous delay variable delay = period x (counter data + 1) + variable variable is from 0 to 1 clock period delay = period x (counter data + 1) + variable variable is from 0 to 1 clock period delay mode (edge select: both, counter data:3) delay_in rc osc: auto power on (powers up from delay in) delay output offset offset delay = offset + period x (counter data + 1) see offset in table 3 delay = offset + period x (counter data + 1) see offset in table 3 reset_in clk counter out count start in 0 clk after reset 4 clk period pulse count mode (count data:3), co unter reset (rising edge detect)
SLG46531_ds_109 page 73 of 169 SLG46531 9.7.4.1 one-shot mode this macrocell will generate a pulse whenever a selected edge i s detected on its input. register bits set the edge selection. the pulse width determines by counter data and clock selection properties. the output pulse polarity (non-inverted or inverted) is selected by register bit. any incoming edges will be ignored du ring the pulse width generation. the following diagram shows one-shot function for non-inverted output. this macrocell generates a high level pulse with a set width (d efined by counter data) when detecting the respective edge. it does not restart while pulse is high. figure 30. one-shot function
SLG46531_ds_109 page 74 of 169 SLG46531 9.7.4.2 frequenc y detection mode rising edge: the output goes high if the time between two succe ssive edges is less than the set time. the output goes low if t he second rising edge has not come a fter the last rising edge in s pecified time. falling edge: the output goes high if the time between two fall ing edges is less than the set time. the output goes low if the second falling edge has not come after the last falling edge in specified time. both edge: the output goes high if the time betwe en the rising and falling edges is less than the set time, which is equivalen t to the length of the pulse. the output goes low if after the last rising/falling edge and specified time, the second edge has not come. figure 31. frequency detection mode
SLG46531_ds_109 page 75 of 169 SLG46531 9.7.4.3 edge detection mode the macrocell generates high leve l short pulse wh en detecting t he respective edge. figure 32. edge detection mode
SLG46531_ds_109 page 76 of 169 SLG46531 9.7.4.4 delay mode the macrocell shifts the respective edge to a set time and rest arts by appropriate edge. it works as a filter if the input sig nal is shorter than the delay time. figure 33. delay mode
SLG46531_ds_109 page 77 of 169 SLG46531 9.8 4-bit lut or 16-bit counter / delay macrocells there are two macrocells that can serve as either 4-bit luts or as 16-bit counter / delays. when used to implement lut functio n, the 4-bit lut takes in four input signals from the connection m atrix and produces a single output, which goes back into the connection matrix. when used to implement 16-bit counter / delay function, four input signals fr om the connection matrix go to the external clock (ext_clk), reset (dly_in/cnt_reset), keep an d up for the counter/delay, with the output going back to the connection matrix. these two macrocells have an optional finite state machine (fsm) function. there are two ma trix inputs for up and keep to support fsm functionality these macrocells can also operate in a one-shot mode, which wil l generate an output puls e of user-defined width. these macrocells can also operate in a frequency detection or e dge detection mode. both of these macrocells can hav e their active count value read via i 2 c. see section 19.4.6.3 reading counter data via i2c for further details 9.8.1 4-bit lut or 16-bi t cnt/dly block diagram figure 34. 4-bit lut0 or cnt/dly0 cnt/dly0 out clk dly_n/cnt_reset 4-bit lut0 out in0 in1 16-bits nvm 1-bit nvm in2 in3 reg <1591:1576> reg <1193> from connection matrix output <101> from connection matrix output <104> from connection matrix output <102> to connection matrix input <22> fsm up keep from connection matrix output <103> lut truth table cnt data 0: 4-bit lut0 in1 1: cnt/dly0 clk 0: 4-bit lut0 out 1: cnt/dly0 out 0: 4-bit lut0 in0 1: cnt/dly0 rst 0: 4-bit lut0 in2 1: fsm up 0: 4-bit lut0 in3 1: fsm keep s0 s1 s0 s1 s0 s1 s0 s1
SLG46531_ds_109 page 78 of 169 SLG46531 figure 35. 4-bit lut1 or cnt/dly1 cnt/dly1 out clk dly_n/cnt_reset 4-bit lut1 out in0 in1 16-bits nvm 1-bit nvm in2 in3 reg <1607:1592> reg <1192> from connection matrix output <105> from connection matrix output <108> from connection matrix output <106> to connection matrix input <23> fsm up keep from connection matrix output <107> lut truth table cnt data 0: 4-bit lut1 in1 1: cnt/dly1 clk 0: 4-bit lut1 out 1: cnt/dly1 out 0: 4-bit lut1 in0 1: cnt/dly1 rst 0: 4-bit lut1 in2 1: fsm up 0: 4-bit lut1 in3 1: fsm keep s0 s1 s0 s1 s0 s1 s0 s1 s0 s1
SLG46531_ds_109 page 79 of 169 SLG46531 9.8.2 4-bit lut or 16-bit coun ter / delay macrocells used as 4-bit luts each macrocell, when programmed for a lut function, uses a 16-b it register to define their output function: 4-bit lut0 is defined by reg<1591:1576> 4-bit lut1 is defined by reg<1607:1592> table 76. 4-bit lut stand ard digital functions function msb lsb and-4 1000000000000000 nand-40111111111111111 or-4 1111111111111110 nor-4 0000000000000001 xor-4 0110100110010110 xnor-41001011001101001 table 74. 4-bit lut0 truth table in3 in2 in1 in0 out 0 0 0 0 reg <1576> lsb 0 0 0 1 reg <1577> 0 0 1 0 reg <1578> 0 0 1 1 reg <1579> 0 1 0 0 reg <1580> 0 1 0 1 reg <1581> 0 1 1 0 reg <1582> 0 1 1 1 reg <1583> 1 0 0 0 reg <1584> 1 0 0 1 reg <1585> 1 0 1 0 reg <1586> 1 0 1 1 reg <1587> 1 1 0 0 reg <1588> 1 1 0 1 reg <1589> 1 1 1 0 reg <1590> 1 1 1 1 reg <1591> msb table 75. 4-bit lut1 truth table in3 in2 in1 in0 out 0 0 0 0 reg <1592> lsb 0 0 0 1 reg <1593> 0 0 1 0 reg <1594> 0 0 1 1 reg <1595> 0 1 0 0 reg <1596> 0 1 0 1 reg <1597> 0 1 1 0 reg <1598> 0 1 1 1 reg <1599> 1 0 0 0 reg <1600> 1 0 0 1 reg <1601> 1 0 1 0 reg <1602> 1 0 1 1 reg <1603> 1 1 0 0 reg <1604> 1 1 0 1 reg <1605> 1 1 1 0 reg <1606> 1 1 1 1 reg <1607> msb
SLG46531_ds_109 page 80 of 169 SLG46531 9.8.3 4-bit lut or 16-bit coun ter / delay macrocells used as 16-bit counter / delay register settings table 77. cnt/dly0 register settings signal function register bit address register d efinition lut4_0 or counter0 select reg<1193> 0: lut4_0 1: counter0 delay0 mode select or asynchronous counter reset reg<1313:1312> 00: on both falli ng and rising edges (for delay & counter reset) 01: on falling edge only (fo r delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or rising edges / high level res et counter/delay0 clock source select reg<1316:1314> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter6 overflow c n t 0 / f s m 0 ' s q a r e set to data or reset to 0s selection reg<1317> 0: reset to 0s 1: set to data (reg<1583:1576, 1591:1584>) counter/delay0 mode selection reg<1319:1318> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay0 control data reg<1591:1576> 1 - 16384 (delay time = [counter control data + 1 ] / freq) table 78. cnt/dly1 register settings signal function register bit address register definition lut4_1 or counter1 select reg<1192> 0: lut4_1 1: counter1 delay1 mode select or asynchronous counter reset reg<1321:1320> 00: on both falling and risin g edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level res et counter/delay1 clock source select reg<1324:1322> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter0 overflow c n t 0 / f s m 0 ' s q a r e set to data or reset to 0s selection reg<1325> 0: reset to 0s 1: set to data (reg<1599:1592, 1607:1600>) counter/delay1 mode selection reg<1327:1326> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay1 control data reg<1607:1592> 1 - 16384 (delay tim e = [counter control data + 1 ] / freq)
SLG46531_ds_109 page 81 of 169 SLG46531 9.9 wake and sleep controller (ws) the SLG46531 has a wake and sleep function for all acmps. the m acrocell cnt/dly0 can be reconfigured for this purpose reg<1319:1318>=11 and reg<1495>=1. the ws serves for power savi ng, it allows to switch on and off selected acmps on selected bit of 16-bit counter. to use any acmp under ws controller the following settings must be done: ? acmp power up input f rom matrix = 1 (for each acmp separately) ? cnt/dly0 must be set to wake an d sleep controller function (fo r all acmps) ? register ws => enable (for each acmp separately) ? cnt/dly0 set/reset inpu t = 0 (for all acmps) as the osc any oscillator with any pre divider can be used. the user can select a period of time while the acmps are sleeping in a range of 1 - 65535 clock cycles. before they are sent to sleep their outputs are latched so the acmps remain their state (high or low) while sleeping. ws controller has the following settings: ? wake and sleep output state (high/low) if osc is powered off (power down option is selected; power dow n input = 1) and wake and sleep output state = high, the acmp is continuously on figure 36. ws controller osc ck_osc ws_pd 000:/1 001:/4 010:/12 011:/24 100:/64 cnt_end ws out ws_pd power control from connection matrix output<58> analog control block reg<1316:1314> ws_pd to w&s out state selection block ws clock freq. selection reg<1591:1576> ws ratio control data reg<1494> ws out state for osc off acmps_pdb ws out bg/regulator pdb ws time selection reg<1489> acmp0..3 out to connection matrix input <60:57> from connection matrix output <54:51> reg<1493:1490> acmp ws enable ws out latchs note: ws_pd is high at ws osc (25 khz/2mhz osc) power down ws controller cnt0 out to connection matrix input <22> ck cnt 4 4 4 4 4 acmps_pdb + -
SLG46531_ds_109 page 82 of 169 SLG46531 if osc is powered off (power down option is selected; power dow n input = 1) and wake and sleep output state = low, the acmp is continuously off both cases ws func tion is turned off ? counter data (range: 1 - 65535) user can select wake and sleep ratio of the acmp; counter data = sleep time, one clock = wake time ? q mode - defines the state of ws counter data when set/reset s ignal appears reset - when active signal appears, the ws counter will reset t o zero and high level signal on its output will turn the acmps on. when reset signal goes out, t he ws counter will go low and turn the acmps off until the c ounter counts up to the end set - when active signal appear s, the ws count er will stop and low level signal on it s output will turn the acmps off. when set signal goes out, the ws counter will go on counting and hig h level signal will turn the acmps on while counter is counting up to the end ? edge select defines the edge for q mode high level set/reset - switches mode set/reset when level is hi gh note: q mode operates only in ca se of "high le vel set/reset ? wake time selection - time re quired for wake signal to turn th e acmps on normal wake time - when ws signal is high, it takes a bg time ( 100/550 s) to turn the acmps on they will stay on until ws signal is low again. wake time is one clock period. it shoul d be longer than bg turn on time and minimal required comparing time of the acmp short wake time - when ws signal is high, it takes a bg time (1 00/550 s) to turn the acmps on. they will stay on for 1 s and turn off regardless of ws si gnal. the ws signal width does not matter. ? keep - pauses counting while keep = 1 ? up - reverses counting if up = 1, cnt is counting up fr om user selected value to 65535 if up = 0, cnt is c ounting down from user selected value to 0
SLG46531_ds_109 page 83 of 169 SLG46531 9.9.1 ws register settings table 79. ws register settings signal function register bit address register definition counter/delay0 clock source select reg<1316:1314> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter6 overflow ws time selection reg<1489> 0: short wake time 1: normal wake time acmp0 wake & sleep function enable reg<1490> 0: disable 1: enable acmp1 wake & sleep function enable reg<1491> 0: disable 1: enable acmp2 wake & sleep function enable reg<1492> 0: disable 1: enable acmp3 wake & sleep function enable reg<1493> 0: disable 1: enable wake sleep output state when ws oscillator is power down if dly/cnt0 mode selection is "11" reg<1494> 0: low 1: high wake sleep ratio control mode selection if dly/cnt0 mode selection is "11" reg<1495> 0: default mode 1: wake sleep ratio control mode dly/cnt0 (16bits, <15:0> = <1591:1576>) control data reg<1591:1576> 1 - 65535
SLG46531_ds_109 page 84 of 169 SLG46531 10.0 analog comparators (acmp) there are four analog comparator (acmp) macro cells in the SLG46531. in order for the acmp cells to be used in a greenpak design, the power up signals (acmpx_pdb) need to be active. by connecting to signals coming fr om the connection matrix, it is possible to have each acmp be always on, always off, or power c ycled based on a digital signal coming from the connection matrix. when acmp is powered down, output is low. pwr up = 1 => acmp is powered up. pwr up = 0 => acmp is powered down. during acmp power up, its output will remain low, and then beco mes valid 1.03 ms (max) after acmp power up signal goes high, see figure 38 . if vdd is greater or equal to 2.7 v, it is possible to decrea se turn-on time by setting the bg ok delay to 100 s, see figure 39 . the acmp cells have an input "low bandwidth" signal selection , which can be used to save power and reduce noise impact when lower bandwid th signals are being compared. t o ensure proper chip startup operation, it is recommended to enable the acmps with the por s ignal, and not t he vdd signal. note: regulator and charge pu mp set to automatic on/off. figure 37. maximum power on delay vs. vdd, bg = auto-delay. 120 140 160 180 200 220 240 1.71 1.8 2.5 2.7 3 3.3 3.6 4.2 4.5 5 5.5 power on delay (s) vdd (v) -40?c +25?c +85?c
SLG46531_ds_109 page 85 of 169 SLG46531 each of the acmp cells has a positive input signal that can be provided by a variety of external sources. there is also a sele ctable gain stage (1x, 0.5x, 0.33x, 0.2 5x) before connec tion to the an alog comparator. the gain divider is unbuffered and consists of 250 k (typ.) resistors, see table 80 . for gain divider accuracy refer to table 81 . in- voltage range: 0 - 1.2 v. can use vref selection vdd/4 and vdd/3 to maintain this input range. input bias current < 1 na (typ). figure 38. maximum power on delay vs. vdd, bg = 550 s. 600 650 700 750 800 850 900 950 1000 1050 1100 1.71 1.8 2.5 2.7 3 3.3 3.6 4.2 4.5 5 5.5 power on delay (s) vdd (v) -40?c +25?c +85?c figure 39. maximum powe r on delay vs. vdd, bg = 100 s. 120 130 140 150 160 170 180 190 200 210 220 1.71 1.8 2.5 2.7 3 3.3 3.6 4.2 4.5 5 5.5 power on delay (s) vdd (v) -40?c +25?c +85?c
SLG46531_ds_109 page 86 of 169 SLG46531 each cell also has a hysteresis selection, to offer hysteresis of 0 mv, 25 mv, 50 mv or 200 mv. the 50 mv and 200 mv hysteresi s options can be used with internal voltage reference only, while 25 mv hysteresis option can be used with both internal and ext ernal voltage reference. the 50 mv and 200 mv hysteresis options are one way hysteresis. it means t hat the actual thresholds will be vref (high threshold) and vref - hysteresis (low threshold). th e acmp output will retain its previous value, if the input volt age is within threshold window (between vref and vref - hysteresis). p lease note: for the 25 mv hysteresis option threshold levels wi ll be vref + hysteresis/2 (high th reshold) and vref C hysteresis/2 (low threshold). note: any acmp powered on enables the bandgap internal circuit as well. an analog voltage will appear on vref even when the force bandgap option is set as disabled. for high input impedance when using the gain divider (x0.25, x0.33, x0.5), it is possible to use the input buffer. however, th is will add some offset, see figure 40. it is not recommended to use acmp buffer when vdd < 2.5 v. table 80. gain divider input resistance gain x1 x0.5 x0.33 x0.25 input resistance 100 m 1 m 0.75 m 1 m table 81. gain di vider accuracy gain x0.5 x0.33 x0.25 accuracy 0.51% 0.34% 0.25% figure 40. typical buffer input voltage offset vs. voltage refer ence at t = (-40.... +85)c, buffer bandwidth = 1 khz, vhys = 0 mv, gain = 1. -80 -60 -40 -20 0 20 40 60 80 50 250 600 850 1200 voffset (mv) voltage reference (mv) upper limit @ vdd3.3v lower limit @ vdd3.3v upper limit @ vdd=1.71v lower limit @ vdd=1.71v
SLG46531_ds_109 page 87 of 169 SLG46531 note: when vdd < 1.8v voltage reference should not exceed 1100 mv. figure 41. typical input threshold variation (including vref var iation, acmp offset) vs. voltage reference at t = (-40.... +85)c, lmb mode - disable, v hys = 0 mv. table 82. built-in hysteres is tolerance at t = 25c vhys (mv) vdd=(1.7-1.8) v vdd=(1.89-5.5) v vref = (50-500) mv vref = (550-1000) mv vref = (1050-1200) mv vref = (50-500) mv vref = (550-1000) mv vref = (1050-1200) mv min max min max min max min max min max min max 25 8.6 32.2 8.6 32.3 7.0 32. 5 8.5 32.3 8.5 32.3 7.8 34.0 50 44.8 56.5 43.9 56.7 42.7 56.4 44.2 56.8 43.6 57.3 43.1 56.0 200 192.8 207.9 194.0 208.0 192.7 205.4 192.0 208.6 193.0 209.5 190.8 207.7 -25% -20% -15% -10% -5% 0% 5% 10% 15% 20% 50 150 250 350 450 550 650 750 850 950 1050 1150 input threshold variation (%) voltage reference (mv) upper limit lower limit
SLG46531_ds_109 page 88 of 169 SLG46531 10.1 acmp0 block diagram figure 42. acmp0 block diagram 11011 11010 11100 11101 internal vref pin7: acmp0(-) pin12: acmp0(-) 110 100 0x1 pin6: acmp0(+) external vdd 1.71 v ~ 5.5 v external vdd 2.7 v ~ 5.5 v selectable gain reg <1630:1629> to acmp1, acmp2, ac- mp3s mux input vref + - from connection matrix output <51> pdb lbw selection reg <1631> hysteresis selection reg <1175:1174> l/s to connection matrix input<57> reg <1628:1624> *pin6_aio_en; reg <1173>; reg <1172> *pin6_aio_en: if reg <1062:1061>=11 then 1, otherwise: 0 bg_ok latch 0 1 reg <1490> pin7: acmp0(-)/2 pin12: acmp0(-)/2 11001- 00000 acmp0 wake & sleep function enable
SLG46531_ds_109 page 89 of 169 SLG46531 10.2 acmp0 register settings table 83. acmp0 register settings signal function register bit address register definition acmp0 positive input source select vdd reg<1172> 0: disable 1: enable acmp0 analog buffer enable reg<1173> 0: disable analog buffer 1: enable analog buffer acmp0 hysteresis enable reg<1175:1174> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) (01: for both external & internal vref; 10 & 11: for only inter nal vref; external vref will not have 50mv & 200mv hysteresis.) acmp0 wake & sleep function enable reg<1490> 0: disable 1: enable acmp0 in voltage select reg<1628:1624> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref(pin12) 11011: ext_vref(pin7) 11100: ext_vref(pin12)/2 11101: ext_vref(pin7)/2 acmp0 positive input divider reg<1630:1629> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp0 low bandwidth (max: 1 mhz) enable reg<1631> 0: off 1: on
SLG46531_ds_109 page 90 of 169 SLG46531 10.3 acmp1 block diagram figure 43. acmp1 block diagram 11011 11010 11100 11101 internal vref pin12: acmp1(-) pin12: acmp1(-) 11x 10x 0x1 pin10: acmp1(+) from acmp0's mux output external vdd 2.7 v ~ 5.5 v selectable gain reg <1638:1637> vref + - from connection matrix output <52> pdb lbw selection reg <1639> hysteresis selection avd = 1.8 v l/s to connection matrix input<58> reg <1636:1632> *pin10_aio_en; reg <1169>; reg <1168> *pin10_aio_en: if reg <1093:1092>=11 then 1, otherwise: 0 bg_ok latch 0 1 reg <1491> pin12: acmp1(-)/2 pin12: acmp1(-)/2 11100- 00000 100 a current source acmp1 wake & sleep function enable en reg <1183> note: when 100 a current source is enabled input voltage on pi n 10 should not exceed 1.8 v
SLG46531_ds_109 page 91 of 169 SLG46531 10.4 acmp1 register settings table 84. acmp1 register settings signal function register bit address register definition acmp1 100ua current source enable reg<1183> 0: disable 1: enable acmp1 positive input source select pin10 reg<1168> 0: disable 1: enable acmp1 analog buffer enable (max. band width 1 mhz) reg<1169> 0: disable analog buffer 1: enable analog buffer acmp1 hysteresis enable reg<1171:1170> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) (01: for both external & internal vref; 10 & 11: for only inter nal vref; external vref will not have 50mv & 200mv hysteresis.) acmp1 wake & sleep function enable reg<1491> 0: disable 1: enable acmp1 in voltage select reg<1636:1632> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref(pin12) 11011: ext_vref(pin12) 11100: ext_vref(pin12)/2 11101: ext_vref(pin12)/2 acmp1 positive input divider reg<1638:1637> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp1 low bandwidth (max: 1 mhz) enable reg<1639> 0: off 1: on
SLG46531_ds_109 page 92 of 169 SLG46531 10.5 acmp2 block diagram figure 44. acmp2 block diagram internal vref pin14: acmp2(-) pin12: acmp2(-) 10 01 pin13: acmp2(+) from acmp0s mux output selectable gain reg <1646:1645> vref + - from connection matrix output <53> pdb lbw selection reg <1647> hysteresis selection reg <1182:1181> l/s to connection matrix input<59> reg <1644:1640> *pin13_aio_en; reg <1180> *pin13_aio_en: if reg <1109:1108>=11 then 1, otherwise: 0 bg_ok latch 0 1 reg <1492> acmp2 wake & sleep function enable 11011 11010 11100 11101 pin12: acmp2(-)/2 pin14: acmp2(-)/2 11001- 00000
SLG46531_ds_109 page 93 of 169 SLG46531 10.6 acmp2 register settings table 85. acmp2 register settings signal function register bit address register definition acmp2 positive input source select pin 13 reg<1180> 0: disable 1: enable acmp2 hysteresis enable reg<1182:1181> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) (01: for both external & internal vref; 10 & 11: for only inter nal vref; external vref will not have 50mv & 200mv hysteresis.) acmp2 wake & sleep function enable reg<1492> 0: disable 1: enable acmp2 in voltage select reg<1644:1640> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref(pin12) 11011: ext_vref(pin14) 11100: ext_vref(pin12)/2 11101: ext_vref(pin14)/2 acmp2 positive input divider reg<1646:1645> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp2 low bandwidth (max: 1 mhz) enable reg<1647> 0: off 1: on
SLG46531_ds_109 page 94 of 169 SLG46531 10.7 acmp3 block diagram figure 45. acmp3 block diagram internal vref pin14: acmp3(-) pin12: acmp3(-) 100 010 001 pin15: acmp3(+) pin13: acmp2(+) selectable gain reg <1654:1653> vref + - from connection matrix output <54> pdb lbw selection reg <1655> hysteresis selection reg <1179:1178> l/s reg <1652:1648> *pin15_aio_en; reg<1177>; reg<1176> *pin15_aio_en: if reg <1126:1125>=11 then 1, otherwise: 0 from acmp0s mux output to connection matrix input<60> bg_ok latch 0 1 reg <1493> acmp3 wake & sleep function enable 11011 11010 11100 11101 pin12: acmp3(-)/2 pin14: acmp3(-)/2 11001- 00000
SLG46531_ds_109 page 95 of 169 SLG46531 10.8 acmp3 register settings table 86. acmp3 register settings signal function register bit address register definition acmp3 positive input source select pin 15 reg<1176> 0: disable 1: enable acmp3 positive input source select pin 13 reg<1177> 0: disable 1: enable acmp3 hysteresis enable reg<1179:1178> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) (01: for both external & internal vref; 10 & 11: for only inter nal vref; external vref will not have 50 mv & 2 00 mv hysteresis.) acmp3 wake & sleep function enable reg<1493> 0: disable 1: enable acmp3 in voltage select reg<1652:1648> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref(pin12) 11011: ext_vref(pin14) 11100: ext_vref(pin12)/2 11101: ext_vref(pin14)/2 acmp3 positive input divider reg<1654:1653> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp3 low bandwidth (max: 1 mhz) enable reg<1655> 0: off 1: on
SLG46531_ds_109 page 96 of 169 SLG46531 11.0 pipe delay (pd) the SLG46531 has a pipe delay logic cell that is shared with th e lut3_10 in one of the combination function macrocells. the user can select one of these functions to use in a design, but not both. please see section 9.6 3-bit lut or pipe delay macroc ell for the description of this combination function macrocell.
SLG46531_ds_109 page 97 of 169 SLG46531 12.0 programmable delay / edge detector the SLG46531 has a programmable time delay logic cell available that can generate a delay that is selectable from one of four timings configured in the greenpak designer. the programmable time delay cell can generate one of four different delay pattern s, rising edge detection, falling edge detection, both edge detect ion and both edge delay. see the timing diagrams below for furt her information. 12.1 programmable delay timing diagram - edge detector output please refer to table 4. expected delays and widths (typical) figure 46. programmable delay figure 47. edge detector output programmable delay out in reg <1267:1266> from connection matrix output <57> to connection matrix input <61> reg <1265:1264> edge mode selection delay value selection time1 edge detector output in rising edge detector falling edge detector both edge detector both edge delay time1 time1 is a fixed value time2 delay value is selected via register time2 time2 width width
SLG46531_ds_109 page 98 of 169 SLG46531 12.2 programmable de lay register settings table 87. programmable de lay register settings signal function register bit address register definition select the edge mode of programmable delay & edge detector reg<1265:1264> 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay delay value select for programmable delay & edge detector (vdd = 3.3v, typical condition) reg<1267:1266> 00: 165 ns 01: 300 ns 10: 440 ns 11: 575 ns
SLG46531_ds_109 page 99 of 169 SLG46531 13.0 additional logic functions the SLG46531 has two additional logic functions that are connec ted directly to the connection m atrix inputs and outputs. there are two deglitch filters, each w ith edge detector functions. se e section 5.11 typical pulse width performance. 13.1 deglitch filter / edge detector 13.2 deglitch filter register settings figure 48. deglitch filter / edge detector table 88. programmable de lay register settings signal function register bit address register definition filter_1/edge detector_1 output polarity select reg<1458> 0: filter_1 output 1: filter_1 out put inverted filter_1 or edge detector_1 select (typ. 30 ns @vdd=3.3 v) reg<1459> 0: filter_1 1: edge detector_1 filter_0/edge detector_0 output polarity select reg<1462> 0: filter_0 output 1: filter_0 out put inverted filter_0 or edge detector_0 select (typ. 47 ns @vdd=3.3 v) reg<1463> 0: filter_0 1: edge detector_0 from connection matrix output <55> to connection matrix input <30> from connection matrix output <56> to connection matrix input <31> filter_0 filter_1 reg <1462> reg <1458> c c r r reg <1463> reg <1459> edge detect edge detect
SLG46531_ds_109 page 100 of 169 SLG46531 14.0 voltage reference (vref) 14.1 voltage reference overview the SLG46531 has a voltage reference macrocell to provide refer ences to the four analog comparators. this macrocell can supply a user selectio n of fixed voltage references, /3 and /4 reference off of the v dd power supply to the dev ice, and externally supplied voltage references from pins 7,12 and 14. the macrocel l also has the option to output reference voltages on pins 18 and 19. see table below for the available selections for each analog comparator. also see figure 49 below, which shows the reference output structure. 14.2 vref selection table table 89. vref selection table sel<4:0> cmp0_vref cmp1_vref cmp2_vref cmp3_vref 11101 vref_ext_acmp0/2 vref_ext_acm p1/2 vref_ext_acmp2/2 vref_ext_a cmp2/2 11100 vref_ext_acmp1/2 vref_ext_acm p1/2 vref_ext_acmp1/2 vref_ext_a cmp1/2 11011 vref_ext_acmp0 vref_ext_acmp 1 vref_ext_acmp2 vref_ext_acmp2 11010 vref_ext_acmp1 vref_ext_acmp 1 vref_ext_acmp1 vref_ext_acmp1 11001 vdd / 4 vdd / 4 vdd / 4 vdd / 4 11000 vdd / 3 vdd / 3 vdd / 3 vdd / 3 10111 1.20 1.20 1.20 1.20 1 0 1 1 01 . 1 51 . 1 51 . 1 51 . 1 5 10101 1.10 1.10 1.10 1.10 10100 1.05 1.05 1.05 1.05 1 0 0 1 11 . 0 01 . 0 01 . 0 01 . 0 0 10010 0.95 0.95 0.95 0.95 10001 0.90 0.90 0.90 0.90 10000 0.85 0.85 0.85 0.85 01111 0.80 0.80 0.80 0.80 0 1 1 1 00 . 7 50 . 7 50 . 7 50 . 7 5 01101 0.70 0.70 0.70 0.70 01100 0.65 0.65 0.65 0.65 0 1 0 1 10 . 6 00 . 6 00 . 6 00 . 6 0 01010 0.55 0.55 0.55 0.55 01001 0.50 0.50 0.50 0.50 01000 0.45 0.45 0.45 0.45 00111 0.40 0.40 0.40 0.40 0 0 1 1 00 . 3 50 . 3 50 . 3 50 . 3 5 00101 0.30 0.30 0.30 0.30 00100 0.25 0.25 0.25 0.25 0 0 0 1 10 . 2 00 . 2 00 . 2 00 . 2 0 00010 0.15 0.15 0.15 0.15 00001 0.10 0.10 0.10 0.10 00000 0.05 0.05 0.05 0.05 vdd practical vref range note 2.0 v - 5.5 v 50 mv ~ 1.2 v 1.7 v - 2.0v 50 mv ~ 1.0 v do not operate above 1.0 v
SLG46531_ds_109 page 101 of 169 SLG46531 14.3 vref block diagram figure 49. voltage refe rence block diagram cmp0_vref cmp1_vref cmp2_vref cmp3_vref reg <1628:1624> reg <1636:1632> reg <1644:1640> reg <1652:1648> vdd / 3 vdd / 4 ext_vref_acmp2 (pin14) ext_vref_acmp1 (pin12) ext_vref_acmp0 (pin7) reg <1476> 000 001 100 101 110 000 001 100 101 110 reg <1474> vdd / 2 vdd / 3 vdd / 4 reg <1486:1484> reg <1482:1480> 1 0 op reg <1487> vref out_1 (pin19) pin19_aio_en reg<1157:1156>=11 1 0 op reg <1483> vref out_2 (pin18) pin18_aio_en reg<1149:1148>=11 external vdd 2.7 v - 5.5 v
SLG46531_ds_109 page 102 of 169 SLG46531 15.0 rc oscillator (rc osc) the SLG46531 has three internal o scillators. rc oscillator that runs at 25 khz / 2 mhz (osc0), oscillator that runs at 25 mhz (osc1) and crystal oscillator. it is possible to use all three oscillators simultaneously. the fundamental frequency can also come from clock input (pin 18 or pin 20 for 25 khz / 2 mhz and pin 17 for 25 mhz or crystal osc), see section 21.0 external clockin g. 15.1 25 khz/2 mhz and 25 mhz rc oscillators there are two divider stages that allow the user flexibility fo r introducing clock signals on various connection matrix input lines. the predivider allows the selection of /1, /2, /4 or /8 divide down frequency from the fundamental. the second stage divider ( only for 25 khz / 2 mhz oscillator) has an input of frequency from t he predivider, and outputs one of seven different frequencies o n connection matrix input lines <27> and <28>. see figure 50 and figure 51 below for details. there are two modes of the power control pin, (reg<1658> for 25 khz / 2 mhz osc and reg<1657> for 25 mhz osc): ? power down <0> . if pwr control input of oscillator is low, the oscillator will be turned on. if pwr control input of oscillator is high the osc illator will be t urned off. ? force on <1> . if pwr control input of oscilla tor is high, the oscillator wi ll be turned on. if pwr control input of oscillator is low the oscillator will be turned off. the pwr control signal has the highest priority. the SLG46531 has a 25 khz / 2 mhz osc fast start-up function re g<1338> (1 C on, 0 C off). it allows the osc to run immediately after power-up. start-up time is less than one cycl e. note that when osc fast start-up is on, the current consumption will rise. the user can select two osc power modes (reg<1343 for 25 khz / 2 mhz osc and reg<1341> for 25 mhz osc): ?if auto power on <0> is selected, the osc will run when the SLG46531 is powered on. ?if force power on <1> is selected, the osc will run only when a ny block that uses os c is powered on. osc can be turned on by: ? register control (force power on) ? delay mode, when delay requires osc ?pwm ? cnt/fsm
SLG46531_ds_109 page 103 of 169 SLG46531 figure 50. 25 khz / 2 mh z rc osc block diagram figure 51. 25 mhz rc osc block diagram internal rco reg <1342> 0: 25 khz 1: 2 mhz pin 20 ext. clock ext. clk sel reg <1358> / 2 / 3 / 4 / 8 / 12 / 24 / 64 0 1 2 3 4 5 6 7 to connection matrix input <27> reg <1349:1347> div /1 /2 /4 /8 reg <1340:1339> predivider second stage divider 0 1 from connection matrix output <58> pwr down to connection matrix input <28> reg <1346:1344> 0 1 pin 18 ext. clock ext. clk sel reg <1355> auto power on 0 1 force power on osc power mode reg <1343> internal rco 25 mhz osc pin 17 ext. clock ext. clk sel reg <1357> to connection matrix input <29> div /1 /2 /4 /8 reg <1337:1336> divider 0 1 from connection matrix output <59> pwr down auto power on 0 1 force power on osc power mode reg <1341>
SLG46531_ds_109 page 104 of 169 SLG46531 15.2 oscillator power on delay note 1: osc power mode: auto power on. note 2: osc enable signal appear s when any block that uses os c is powered on. figure 52. oscillator startup diagram figure 53. rc oscillator maximum power on delay vs. vdd at room temperature, osc0 = 2 mhz 150 250 350 450 550 650 750 850 950 1,050 1.7 1.8 1.9 2.3 2.5 2.7 3.0 3.3 3.6 4.2 4.5 5.0 5.5 power on delay (ns) vdd (v) normal start-up mode fast start-up mode
SLG46531_ds_109 page 105 of 169 SLG46531 15.3 oscillator accuracy note: osc power setting: force power on; clock to matrix input - enable; bandgap: turn on by register - enable. figure 54. rc oscillator maximum power on delay vs. vdd at room temperature, osc0 = 25 khz figure 55. osc1 (25 mhz) maximum power on delay vs. vdd at room temperature 0 5 10 15 20 25 1.7 1.8 1.9 2.3 2.5 2.7 3.0 3.3 3.6 4.2 4.5 5.0 5.5 power on delay ( s) vdd (v) normal start-up mode fast start-up mode 40 50 60 70 80 90 100 110 120 130 140 1.7 1.8 1.9 2.3 2.5 2.7 3.0 3.3 3.6 4.2 4.5 5.0 5.5 power on delay ( s) vdd (v)
SLG46531_ds_109 page 106 of 169 SLG46531 figure 56. rc oscillator frequency vs. temperature, rc osc0=2 mh z figure 57. rc oscillator frequency vs. temperature, rc osc0=25 k hz 1.75 1.8 1.85 1.9 1.95 2 2.05 2.1 2.15 2.2 -40 -20 0 20 40 60 80 f (mhz) t (c) fmax @ vdd=1.8 v fmin @ vdd=1.8 v fmax @ vdd=3.3 v fmin @ vdd=3.3 v fmax @ vdd=5.0 v fmin @ vdd=5.0 v 23.5 24 24.5 25 25.5 26 26.5 27 -40 -20 0 20 40 60 80 f (khz) t (c) fmax @ vdd=1.8 v fmin @ vdd=1.8 v fmax @ vdd=3.3 v fmin @ vdd=3.3 v fmax @ vdd=5.0 v fmin @ vdd=5.0 v
SLG46531_ds_109 page 107 of 169 SLG46531 note 1: for more info rmation see section 5.12 osc specification s. note 2: 25 mhz rc osc1 performanc e is not guaranteed at vdd < 2 .5 v. figure 58. osc1 (25 mhz) frequency vs. temperature 17 19 21 23 25 27 29 31 -40 -20 0 20 40 60 80 f (mhz) t (c) fmax @ vdd=1.8 v fmin @ vdd=1.8 v fmax @ vdd=3.3 v fmin @ vdd=3.3 v fmax @ vdd=5.0 v fmin @ vdd=5.0 v
SLG46531_ds_109 page 108 of 169 SLG46531 16.0 crystal oscillator the crystal osc provides high precision and stability of the ou tput frequency. pin 17 and pin 16 are input and output, respect ively, of an inverting amplifier which is configured for use as an on- chip oscillator, as shown in figure 60 . either a quartz crystal or a ceramic resonator may be used. the optimal value of the capacit ors depends on the crystal or r esonator in use, the amount of stray capacitance, and the electromagnetic noise of the environ ment. refer to table 90 . for ceramic resonators, the capacitor values given by the manufacturer should be used. it is possible to use an external clock source , in which case no other extern al components are required, but the clock source must be connected to pin 17. the power down mode is paired wit h temperature sensor. if it is enabled for crystal osc, it is not available for temp sensor a nd vice versa. however, it is possible to enable power down mode f or crystal osc and temp sensor simultaneously. figure 59. crystal osc block diagram figure 60. external crystal connection table 90. external components selection table f c1 c2 r1 r2 32.768 khz 10 pf 330 pf 20 m ? 20 k ? 4 - 40 mhz 12 pf 12 pf 1 m ? 0 ? crystal osc to connection matrix input <53> from connection matrix output <109> pwr down disable 0 1 enable osc power mode reg <1136> pin 17 pin 16 crystal SLG46531 pin 17 pin 16 c2 c1 r1 r2
SLG46531_ds_109 page 109 of 169 SLG46531 17.0 power on reset (por) the SLG46531 has a power-on reset (por) macrocell to ensure cor rect device initialization and operation of all macrocells in the device. the purpose of the por circuit is to have consisten t behavior and predictable results when the vdd power is first ramping to the device, and also while the vdd is falling during power-down. to accomplish this goal, the por drives a defined sequence of internal events that trigger changes to the states of different macrocells inside th e device, and finally to the s tate of the i/o pins. this application note is created to explain the w hole process of por operation and greenpak chip behavior during the time while it is power ing up and powering down. 17.1 general operation the SLG46531 is guaranteed to be powered down and non-operation al when the vdd voltage (voltage on pin1) is less than 0.6v, but not less than -0.6 v. another essential condition for the chip to be powered down is that no voltage higher (see not e 1) than the vdd voltage is applied to any other pin. for example, if vdd voltage is 0.3 v, applying a voltage higher than 0.3 v t o any other pin is incorrect, and can lead to inco rrect or unexpe cted device behavior. note 1. there is a 0.6v margin due to forward drop voltage of t he esd protection diodes. to start the por sequence in the SLG46531, the voltage applied on the vdd should be higher than the power_on threshold (see note 2). the full operational vdd range for the SLG46531 i s 1.71 v C 5.5 v (1.8 v 5% - 5 v10%). this means that the vdd voltage must ramp up to the operational voltage value, but the por sequence will start earlier, as soon as the vdd voltage rises to the power_on threshold. after the por sequence has sta rted, the SLG46531 will have a typical period of time to go through all the steps in the s equence (noted in the datasheet f or that device), and will be r eady and completely operational a fter the por sequence is complete. note 2. the power_on threshold can vary by pvt, but typically it is 1.6v. to power down the chip the vdd voltage should be lower than the operational and to guarantee that chip is powered down it should be less than 0.6 v. all pins are in high impedance st ate when the chip is powered d own and while the por sequence is taking place. the last step in the por sequence releases the i/o structures from the high i mpedance state, at which time the device is operational. the pi n configuration at this point in time is defined by the design pr ogrammed into the chip. also as it was mentioned before the vol tage on pins cant be bigger than t he vdd, this rule also applies to the case when the chip is powered on.
SLG46531_ds_109 page 110 of 169 SLG46531 17.2 por sequence the por system generat es a sequence of signals that enable cert ain macrocells. the sequence is shown in figure 61 . as can be seen from figure 61 after the vdd has start ramping up and crosses the power_on th reshold, first, the on-chip nvm memory is reset. next the chip reads the data from nvm, and tra nsfers this information to sram registers that serve to configu re each macrocell, and the connection matrix which routes signals between macrocells. the third stage causes the reset of the inp ut pins, and then to enable them. after that, the luts are reset a nd become active. after luts the delay cells, rc osc, dffs, latches and pipe delay are initialized. only after all macrocel ls are initialized internal por s ignal (por macrocell output) g oes from low to high. the last portion of the device to be initiali zed are the output pins, which t ransition from high impedance t o active at this point. the typical time that takes to complete the por sequence varies by device type in the greenpak family. it also depends on many environmental factors, such as: slew rate, vdd value, temperatu re and even will vary from chip to chip (process influence). figure 61. por sequence vdd por_nvm (reset for nvm) nvm_ready_out, i 2 c enable por_gpi (reset for input enable) por_lut (reset for lut output) por_core (reset for dly/rco/dff /latch/pipe dly) por_out (generate low to high to matrix) por_gpo asm enable (reset for output enable) t t t t t t t t input: ignore transition output: initial state (determined by reg<1354:1352>)
SLG46531_ds_109 page 111 of 169 SLG46531 17.3 blocks output stat es during por sequence to have a full picture of SLG46531 operation during powering an d por sequence, review the overview the macrocell output states during the por sequence ( figure 62 describes the output signals states). first, before the nvm has been res et, all macrocells have their output set to logic low (exc ept the output pins which are in h igh impedance state). before the nv m is ready, all macrocell output s are unpredictable (except the output pins). on the next step, some of the macrocells start ini tialization: input pins output state becomes low; luts also output low. only p dly macrocell configured as edge detector becomes active at this time. after that input pins are enabled. next, only luts are configured. ne xt, all other macrocells are initialized. after macrocells are init ialized, internal por matrix signa l switches from low to high. the last are output pins that become active and determined by the i nput signals. figure 62. internal block states during por sequence unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable vdd input pin_out to matrix lut_out to matrix programmable delay_out to matrix prog. edge_detector_out to matrix dff/latch_out to matrix delay_out to matrix por_out to matrix ext. gpo vdd_out to matrix determined by input signals determined by input signals starts to detect input edges determined by input signals determined by input signals determined by input signals starts to detect input edges determined by input signals determined by external signal guaranteed high before por_gpi determined by input signals out = in without delay determined by initial state determined by input signals out = in without delay tri-state t t t t t t t t t t output state unpredictable
SLG46531_ds_109 page 112 of 169 SLG46531 17.3.1 initialization all internal blocks by d efault have initial low level. starting from indicated power-up time of 1.15 v - 1.6 v, blocks in gpak 3 are powered on while forced to the re set state, all outputs are in hi-z and chip starts loading data from nvm. then the reset sign al is released for inter nal blocks and they sta rt to init ialize ac cording to the following sequence: 1. input pins, acmp , pull up/down; 2. luts; 3. dffs, delays/counters, pipe delay; 4. por output to matrix; 5. output pin corresponds to the internal logic the vref output pin driving signal can precede por output signa l going high by 3 ? s - 5 ? s. the por signal going high indicates the mentioned power-up sequence is complete. note: the maximum voltage appli ed to any pin should not be high er than the vdd level. there are esd diodes between pin C > vdd and pin C> gnd on each pin. so if the input signal applie d to pin is higher than vdd, then current will sink through the diode to vdd. exceeding vdd results in leakage current on the i nput pin, and vdd will be pulled up, following the voltage on the input pin.there is no effec t from input pin when input volt age is applied at the same time as vdd. 17.3.2 power down during powerdown, blocks in slg46 531 are powered off and logic blocks may switch states after falling below 1.4 v. the i/o buffers are disabled when por goes low at vdd ~1 v. please note that during a slow rampdown, outputs can possibly switch state during this time. figure 63. power down outputs can possibly switch state during this time vdd (v) time 1.6 v 1.15 v 2 v 1 v 1 v vref out signal
SLG46531_ds_109 page 113 of 169 SLG46531 18.0 asynchronous state machine (asm) macrocell 18.1 asm macrocell overview the asynchronous state machine (asm) macrocell is designed to a llow the user to create state machines with between 2 to 8 states. the user has flexibility to define the available states , the available state transiti ons, and the input signals (a, b, c ) that will cause transitions from one state to another state, as show n in figure 64 . this macrocell has a total of 25 inputs, as shown in figure 65 , which come from the connection matrix outputs. of these 25 in puts, 24 are user selectable for driving general state transitions, a nd 1 is for driving a state transition to an initial / reset st ate. each of the 24 inputs is level sensitiv e and active high, meaning that a high level input will drive th e user selected transition from one state to another. the fact that there are 24 inputs puts the upper bo und of 24 possible state transitions total in the user defined state machine design. there is on nreset input which will drive an im mediate state transition to the user-defined initial / reset st ate when active, shown in red, in the figure 64 . there are a total of 8 outputs, which go to the connections mat rix inputs, and from there can be routed to other internal macr ocells or pins. the 8 outputs are user d efined for each of the possibl e 8 states. this information is held in the connection matrix o utput ram. in using this macrocell, the user must take into consideration the critical timing required on all input and output signals. t he timing waveforms and timing specifications for this macrocell are all measured relative to the input signals (which come into the mac rocell on the connection matrix outputs ) and on the outputs from the m acrocell (which are direct connections to connection matrix inputs). the user must consider any delays from other logic and internal chip connections, including i/o delays, to insure tha t signals are properly processed, a nd state transiti ons are deter ministic. the gpak designer development tools support user designs for th e asm macrocell at both the physical level and logic level. figure 64 is a representation of the user design at the logical level, a nd figure 65 shows the physical resources inside the macrocell. to best utilize this macrocell, the user must develo p a logical representation of t heir desired state machine, as w ell as a physical mapping of t he input and outputs required for the de sired functionality. figure 64. asynchronous state machine state transitions a c g d e f h b high speed normal speed standby off fault
SLG46531_ds_109 page 114 of 169 SLG46531 figure 65. asynchronous state machine state transition signal routing state 0 in state 1 in state 2 in state 3 in state 4 in state 5 in state 6 in state 7 in state 0 state 0 output bits (8) state 1 state 2 state 3 state 4 state 5 state 6 state 7 connection matrix output ram (8x8) nreset from connection matrix state holding dffs state 1 output bits (8) state 2 output bits (8) state 3 output bits (8) state 4 output bits (8) state 5 output bits (8) state 6 output bits (8) state 7 output bits (8) to connection matrix
SLG46531_ds_109 page 115 of 169 SLG46531 18.2 asm inputs the asm macrocell has a total of 25 inputs which come from the connection matrix outputs. of these 25 inputs, 24 are user selectable for driving general state transitions, and 1 is for driving a state transition to an initial / reset state. there are a total of 24 inputs t o the asm macrocell for general state transitions, highlighted in red in figure 66 . each of these inputs is level sensitive, and a ctive high. a high level input will trigger a state transition. these inputs are grouped so that each set of 3 inputs can drive a state transition going into a particular stat e. as an example, there are three inputs that can drive a state transition to sta te 1. this sets an upper bound on the number of transitions tha t the user can select going into a par ticular state to be 3, shown in figure 67 . there is no limitation on the number of transitions that can be supported coming out of a parti cular state, the user can selec t to have transitions going from a sta te to all other states, shown in figure 68 . the asm macrocell also has a nreset input highlighted in blue i n figure 66 . this input is level sensitive and active low. an active signal on this input will drive an immediate state transition t o the user-defined initial / reset state. the user can choose w hich state within the asm ed itor inside gpak designer is the initial state. figure 66. asynchronous state machine inputs state transition signal routing state 0 in state 1 in state 2 in state 3 in state 4 in state 5 in state 6 in state 7 in state 0 state 0 output bits (8) state 1 state 2 state 3 state 4 state 5 state 6 state 7 nreset from connection matrix state holding dffs state 1 output bits (8) state 2 output bits (8) state 3 output bits (8) state 4 output bits (8) state 5 output bits (8) state 6 output bits (8) state 7 output bits (8) to connection matrix connection matrix output ram (8x8)
SLG46531_ds_109 page 116 of 169 SLG46531 figure 67. maximum 3 state tr ansitions into given state figure 68. maximum 7 state tran sitions out of a given state state 2 state 3 state 1 state 0 state 3 state 6 state 1 state 0 state 4 state5 state 2 state 7
SLG46531_ds_109 page 117 of 169 SLG46531 18.3 asm outputs there are a total of 8 outputs from the asm macrocell, which go to the connections matrix inp uts, and from ther e can be routed to other internal macrocells or pins. the 8 outputs are user de fined for each of the possible 8 states, this information is he ld in the connection matrix output ram, shown in figure 69 . the connection matrix output ram has a total of 64 bits, arra nged as 8 bits per state. the values loaded in each of t he 8 bits defin e the signal level on each of the 8 asm macrocell outputs. the asm editor inside the gpak designer software allows the use r to make their selections for the value of each bit in the connection matrix output ram, wh ich selects the level of the macrocell outputs based on the curr ent state of the asm block, as shown in figure 73 . figure 69. connection matrix output ram state transition signal routing state 0 in state 1 in state 2 in state 3 in state 4 in state 5 in state 6 in state 7 in state 0 state 0 output bits (8) state 1 state 2 state 3 state 4 state 5 state 6 state 7 nreset from connection matrix state holding dffs state 1 output bits (8) state 2 output bits (8) state 3 output bits (8) state 4 output bits (8) state 5 output bits (8) state 6 output bits (8) state 7 output bits (8) to connection matrix connection matrix output ram (8x8)
SLG46531_ds_109 page 118 of 169 SLG46531 table 91. asm editor - conn ection matrix output ram ram state name connection matrix output ram out7 out6 out5 out4 out3 out2 out1 out0 state 0 0 0 0 0 0 0 0 1 state 1 0 0 0 0 0 0 1 0 state 2 0 0 0 0 0 1 0 0 state 3 0 0 0 0 1 0 0 0 state 4 0 0 0 1 0 0 0 0 state 5 0 0 1 0 0 0 0 0 state 6 0 1 0 0 0 0 0 0 state 7 1 0 0 0 0 0 0 0
SLG46531_ds_109 page 119 of 169 SLG46531 18.4 basic asm timing the basic state transition timi ng from input on matrix connecti on output to output on matrix connection input is shown in figure 70 and figure 71 . the time from a valid input signal to the time that there is a valid change of state and valid signals being available on the state outputs is state machine output delay time (tst_ou t_delay). the minimum and maximum values of tst_out_delay define the differential timing between the shortest state trans ition (input on matrix output an d output on matrix input) and t he longest state transition (input on matrix output and output on matrix input). 18.5 asynchronous state machin es vs. synchronou s state machin es it is important to note that this macrocell is designed for asynchronous operation, which means the following: 1. no clock source is needed, it reacts only to input signals 2. the input signals do not have to be synchronized to each othe r, the macrocell will react to t he earliest valid signal for state transition. 3. this block does not have traditional set-up and hold time spe cifications which are related to incoming clock, as this macroc ell has no clock source. 4. the macrocell only consumes p ower while in state transition. 18.6 asm power considerations a benefit of the asynchronous nat ure of this macrocell is that it will consume power only during state transitions. shown in figure 70 and figure 72 below, the current consumption of the macrocell will be a frac tion of a a between state transitions, and will rise only during state transitions. s ee section 5.7 i dd estimator to find average current dur ing state transitions. figure 70. state transition figure 71. state transition timing figure 72. state transition a state 0 state 1 input signal (a) tst_out_delay state outputs state 0 state 1 a state 0 state 1
SLG46531_ds_109 page 120 of 169 SLG46531 18.7 asm logical vs. physical design a successful design with the asm macrocell must include both th e logic level design as well as the physical level design. the gpak designer development software support user designs for the asm macrocell at both the logic level and physical level. the logic level design of the user defined state machine takes plac e inside the asm editor. in the asm editor, the user can select and name states, define and name allo wed state transitions, define the initial / reset state and define the output values for the 8 outputs in the output ram matri x. the physical level design tak es place in the general gpak designer window, and here the user makes connections for the sources for asm input signals, a s well as making connections f or destinations for asm output signals. 18.8 asm special case timing considerations 18.8.1 state transition pulse input timing all inputs to the asm macrocell are level sensitive. if the inp ut to the state machine block for a state transition is a pulse , there is a minimum pulse width on the input to the state machine block ( as measured at the matrix input to the block) which is guarante ed to result in a state transition shown in figure 74 and figure 75 . this pulse width is defined by the state machine input pulse acceptance time (tst_pulse). if a pulse width that is shorter t han tst_pulse is input to the state machine block, it is indete rminate whether the state transition wi ll happen or not. if a pulse tha t is rejected (invalid due to the pulse width being narrower th an the guaranteed minimum of tst_pulse), this will not stop a valid pu lse on another state transition input that does meet minimum pu lse width. figure 73. state transition timing and power consumption figure 74. state transition figure 75. state transition pulse input timing input signal (a) tst_out_delay state outputs state 0 state 1 asm power consumption average active asm power sub ? a inactive asm power consumption a state 0 state 1 input signal (a) ts t _ p u l s e state outputs tst_pulse tst_out_delay state 0 state 1
SLG46531_ds_109 page 121 of 169 SLG46531 18.8.2 state transition competing input timing there will be situations where two input signals can be valid i nputs that will drive two different state transitions from a gi ven state. in that sense, the two signals are competing (signals a and b in figure 76 ), and the signal that arrives sooner should drive the state transition that will win, or drive the state transition . if one signal arrives tst_comp before the other one, it is guaranteed to win, and the state transition that it codes for will be taken, as shown in figure 77 . if the two signals arrive within tst_comp of each other, it will be indeterminate which state transition will win , but one of the transitions will take place as long as the win ning signal satisfies the pulse width crite ria described in the paragraph a bove, as shown in figure 78 . figure 76. state transition - competing inputs figure 77. state transition timing - competing inputs indetermin ate figure 78. state transition timin g - competing inputs determinab le a state 0 state 2 state 1 b input signal (b) tst_out_delay state outputs state 0 state 1 or state 2 input signal (a) ts t _ c o m p input signal (b) tst_out_delay state outputs state 0 state 1 input signal (a) ts t _ c o m p
SLG46531_ds_109 page 122 of 169 SLG46531 18.8.3 asm state transition sequential timing it is possible to have a valid input signal for a transition ou t from a particular state be active before the state is active. if this is the case, the block will only stay in that particular state for tst _out_delay time before making the transition to the next state. an example of this sequentia l behavior is shown in figure 79 and the associated timing is shown in figure 80 . 18.8.4 state transition closed cycling it is possible to have a closed cycle of state transitions that will run continuously if there if there are valid inputs that are active at the same time. the rate at which the state transitions will tak e place is determined by tst_out_delay. the example shown here in figure 81 involves cycling between two states, but any number of two C e ight states can be included in state transition closed cycling of this nature. figure 82 shows the associated ti ming for closed cycling. figure 79. state transition - sequential figure 80. state transition - sequential timing figure 81. state transition - closed cycling figure 82. state transition - closed cycling timing a state 0 state 1 b state 2 input signal (b) tst_out_delay state outputs state 0 state 1 input signal (a) tst_out state 2 a state 0 state 1 b input signal (b) tst_out_delay state outputs state 0 state 1 input signal (a) tst_out state 0 state 1 tst_out
SLG46531_ds_109 page 123 of 169 SLG46531 19.0 i 2 c serial communications block 19.1 i 2 c serial commu nications bl ock overview in the standard use case for the greenpak devices, the configur ation choices made by the user are stored as bit settings in th e non-volatile memory (nvm), and this information is transferred at startup time to volatile ram registers that enable the confi gu- ration of the macrocells. other ram registers in the device are responsible for setting the connections in the connection matr ix to route signals in th e manner most appropri ate for the users application. the i 2 c serial communications macrocell in this device allows an i 2 c bus master to read and write this information via a serial channel directly to the ram registers, allowing the remote re-c onfiguration of macrocells, and remote changes to signal chains within the device. an i 2 c bus master is also able read and write other register bits th at are not associated with nvm memory. as an example, the input lines to the connection matrix can be read as digital reg ister bits. these are the signal outputs of each of the macroce lls in the device, giving an i 2 c bus master the capability to re motely read the current value of any macrocell. the user has the flexibility to control read access and write a ccess via registers bits reg<1832> and reg<1871>. see section 19.4.6.1 for more details on i 2 c read/write memory protection. note: greenpak i 2 c is fully compati ble with standard i 2 c protocol. 19.2 i 2 c serial communicati ons device addressing each command to the i 2 c serial communications block begins with a control byte. the b its inside this control byte are shown in figure 83 . after the start bit, the first four bits are a control code, which can be set by the user i n reg<1867:1864>. this gives the user flexibility on the chip level addressing of this devic e and other devices on the same i 2 c bus. the block address is the next three bits (a10,a9, a8), which will define the most signif icant bits in the addressing of the data to be read or written by the command. the last bit in t he control byte is the r/w bit, which selects whether a read command or write command is requested, with a 1 selecting for a read command, and a 0 selecting fo r a write command. this control byte will be followed by an acknowledge bit (ack), which is sent by this device to indicate successful communication of the control byte data. in the read and write command address structure, there are a to tal of 11 bits of addressing, each pointing to a unique byte of information, resulting in a total address space of 2k bytes. of this 2k byte address space, the valid addresses accessible to the i 2 c macrocell on the SLG46531 are in the range from 0 (0x00) to 2 55 (0xff). the msb address bits (a10, a9 and a8) will be 0 for all commands to the SLG46531. with the exception of the current address read command, all com mands will have the control byte followed by the word address. figure 83 shows this basic co mmand structure. figure 83. basic command structure x x x x a 1 0 a 9 a 8 r/w a 7 a 0 control byte word address control code block address read/write bit (1 = read, 0 = write) s ack acknowledge bit start bit n o t u s e d , s e t t o 0
SLG46531_ds_109 page 124 of 169 SLG46531 19.3 i 2 c serial general timing shown in figure 84 is the general timing characteristics for the i 2 c serial communications block. timing specifications can be found in the ac charac teristics section. 19.4 i 2 c serial communi cations commands 19.4.1 byte write command following the start condition from the master, the control code [4 bits], the block address [3 bits] and the r/w bit (set to 0), are placed onto the i 2 c bus by the master. after the SLG46531 sends an acknowledge bi t (ack), the next byte transmitted by the master is the word address. the block address (a10, a9, a8), co mbined with the word address (a7 through a0), together set the internal address pointer in the SLG46531 where the data byt e is to be written. after the SLG46531 sends another acknowledg e bit, the master will transmit the data byte to be written into the addressed memory location. the SLG46531 again provides an acknowledge bit and then the master generates a stop condition. the internal write cycle for t he data will take place at the t ime that the SLG46531 generates the acknowledge bit. figure 84. i 2 c general timing characteristics figure 85. byte write command, r/w = 0 scl t f t r t su sto t buf t high t low t su dat t hd dat t hd sta t su sta t aa t dh sda in sda out x x x x a 1 0 a 9 a 8 w a 7 a 0 control byte word address control code block address r/w bit = 0 s ack acknowledge bit start bit ack d 7 d 0 data p stop bit acknowledge bit sda line bus activity acknowledge bit ack n o t u s e d , s e t t o 0
SLG46531_ds_109 page 125 of 169 SLG46531 19.4.2 sequential write command the write control byte, word address and the first data byte ar e transmitted to the SLG46531 in the same way as in a byte writ e command. however, instead of generating a stop condition, the master continues to transmit data bytes to the SLG46531. each subsequent data byte will incre ment the internal address counte r, and will be written into the next higher byte in the command addressing. as in the case of the byte write command, the inter nal write cycle will take place at the time that the SLG46531 generates the acknowledge bit. 19.4.3 current address read command the current address read command reads from the current pointer address location. the address pointer is incremented at the first stop bit following any write control byte. for example, i f a write or random read (which contains a write control byte) writes or reads data up to address n, t he address pointer would get in cremented to n+1 upon the stop of that command. subsequently, a current address read that follows would start reading data at n+1. the current address read command contains the control byte sent by the master, with the r/w bit = 1. the SLG46531 will issue an acknowledge bit, and the n transmit eight data bits for the requested byte. the master will not issue an acknowledg e bit, and follow immediately with a stop condition. figure 86. sequential write command, r/w = 0 figure 87. current address read command, r/w = 1 x x x x a 1 0 a 9 a 8 w control byte word address (n) control code block address r/w bit = 0 s ack acknowledge bit start bit data (n) stop bit sda line bus activity ack data (n + 1) ack ack data (n + x) p acknowledge bit ack n o t u s e d , s e t t o 0 x x x x a 1 0 a 9 a 8 r control byte data (n) control code block address r/w bit = 1 s ack acknowledge bit start bit p stop bit no ack bit sda line bus activity n o t u s e d , s e t t o 0
SLG46531_ds_109 page 126 of 169 SLG46531 19.4.4 random read command the random read command starts with a control byte (with r/w bit set to 0, indicating a wr ite command) and word address to set the internal byte address, followed by a start bit, and then the control byte for the read (exactly the same as the byt e write command). the start bit in the middle of the command will halt the decoding of a write command, but will set the internal addr ess counter in preparation for the second half of the command. after the start bit, the master issu es a second control byte with t he r/w bit set to 1, after which t he SLG46531 issues an acknowledge bit, followed by the reque sted eight data bits. 19.4.5 sequential read command the sequential read command is initiated in the same way as a current address read or random read command, except that once the SLG46531 transmits the first data byte, the master iss ues an acknowledge bit as opposed to a stop condition in a rand om read. the master can continue r eading sequential bytes of data, and will terminate the comma nd with a stop condition. figure 88. random read command figure 89. sequential read command x x x x a 1 0 a 9 a 8 w control byte word address (n) control code block address r/w bit = 0 s ack acknowledge bit start bit control byte stop bit sda line bus activity ack data (n) ack p xxxx a 1 0 a 9 a 8 r s r/w bit = 1 no ack bit n o t u s e d , s e t t o 0 control code x x x x a 1 0 a 9 a 8 r control byte data (n) control code block address r/w bit = 1 s ack acknowledge bit start bit data (n+1) stop bit sda line bus activity ack data (n + 2) ack ack data (n + x) p no ack bit n o t u s e d , s e t t o 0
SLG46531_ds_109 page 127 of 169 SLG46531 19.4.6 i 2 c serial command register map these register addresses are broken down into four banks to giv e the user greater control on access to reading and writing information in each bank. each of the four banks is 512 bits (6 4 bytes) in length. writing information to register bits in these banks will change the configuration of t he device, resulting in eithe r a change in the interconnection options provided by the conne ction matrix, or by changing the configuration of individual macrocel ls. during device use, all regist er bits can be read or written via i 2 c, unless protection bits are set to prevent this. see section 22.0 appendix a - SLG46531 register definition for detailed information on all register bits figure 90. register bank map byte 0 bank 0 bank 1 bank 2 bank 3 byte 63 byte 64 byte 127 byte 128 byte 191 byte 192 byte 255
SLG46531_ds_109 page 128 of 169 SLG46531 19.4.6.1 i 2 c serial command register protection all register bits in the first three banks (0 C 2) can be read and written via i 2 c unless they are protect ed with two register bits stored in the nvm. the two register bits th at select whether th e bits within banks 0 C 2 can be read or written are as follows : ? reg<1832> bank 0/1/2 i 2 c read protection bit ? reg<1871> bank 0/1/2 i 2 c write protection bit register bits in bank 3 are a lways open to rea d and write comma nds via i 2 c with the following exceptions: ? reg<1663> io latching enable during i 2 c write interface is protected from i 2 c write, see note 1 ? reg<1871> bank 0/1/2 i 2 c-write protection bit is protected from i 2 c write ? reg<1867:1864> i 2 c control code bit [3:0] is protected from i 2 c write note1. if reg<1663> = 1, all out puts are latched while inputs a nd internal blocks retain their status during i 2 c write see section 22.0 appendix a - SLG46531 register definition for detailed information on all registers 19.4.6.2 i 2 c serial reset command if i 2 c serial communication is established with the device, it is possible to reset the device to initial power up conditions, incl uding configuration of all macrocells , and all connections provided b y the connection matrix. this is implemented by setting reg<166 2> i 2 c reset bit to 1, which causes the device to re-enable the po wer on reset (por) sequence, including the reload of all regist er data from nvm. during the por sequence, the outputs of the devi ce will be in tri-state. after the reset has taken place, the c ontents of reg<1662> will be set to 0 automatically. the timing diagr am shown below illustrates the s equence of events for this rese t function. figure 91. reset command timing x x x x a 1 0 a 9 a 8 w a 7 a 0 control byte word address control code block address write bit s ack acknowledge bit start bit ack d 7 d 0 data p stop bit acknowledge bit sda line bus activity acknowledge bit ack reset-bit register output reloading nvm into data register internal por internal reset bit by i 2 c stop signal reset-bit register (reg<1662>) is cleared by reloading nvm into data register 1) i 2 c write with reg<1662>=1 (i 2 c reset bit with reloading nvm into data register) 2) por go to low and reloading nvm into data register start aft er stop of i 2 c 3) por go to high after reloading nvm into data register n o t u s e d , s e t t o 0
SLG46531_ds_109 page 129 of 169 SLG46531 19.4.6.3 reading counter data via i 2 c the current count value in four counters in the device can be r ead via i 2 c. the counters that have this additional functionality are 16-bit cnt0 and cnt1, and 8 -bit counters cnt4 and cnt6. 19.4.6.4 user ram and otp memory array there are eight bytes of ram memory that can be read and writte n remotely by i 2 c commands. the initial contents of this memory space can be selected by the u ser, and this information will be transferred from otp memory t o the ram memory space during the power-up sequence. the lowest order byte in this array (use r configurable ram/otp byte 0) is located at i 2 c address 0xd8, and the highest order byte i n this array is located at i 2 c address 0xdf. table 92. ram array table i2c address (hex) highest bit address lowest bit address memory byte d8 1735 1728 user configurable ram/otp byte 0 d9 1743 1736 user configurable ram/otp byte 1 da 1751 1744 user configurable ram/otp byte 2 db 1759 1752 user configurable ram/otp byte 3 dc 1767 1760 user configurable ram/otp byte 4 dd 1775 1768 user configurable ram/otp byte 5 de 1783 1776 user configurable ram/otp byte 6 df 1791 1784 user configurable ram/otp byte 7
SLG46531_ds_109 page 130 of 169 SLG46531 20.0 analog temperature sensor the SLG46531 has an analog temper ature sensor (ts) with an outp ut voltage linearly-proportional to the centigrade tempera- ture. the ts cell shares buffer with vref0, so it is impossible to use both cells simultaneously, its output can be connected directly to the io16. using buffer causes low-output impedance, linear output and makes interfacing to readout or control circuitry esp e- cially easy. the ts is rated to operate over a -40c to 180c t emperature range. the error in the whole temperature range does not exceed 10.3% (5.7% in a range from -40c to 100c). ts ou tput voltage variation over vdd at constant temperature is less than 10.3% (6.3% without buffer). for mor e detail refer to section 5.13 analog temperature s ensor (ts) specifications . figure 92. analog temperature sensor structure diagram + - vref0 reg <1464> vcp, reg <1474:1472>=100 (always cp should be on) reg<1476>=1 forced bandgap on reg<1470>=0 vref op amp offset chopper clock frequency 2 mhz reg<1469>=1 bandgap op amp offset chopper enable ts vdd 1 0 0 1 0 1 reg <1486:1484> vref select reg <1487> reg <1478> io16 closed ts_on reg<1464>=1 reg <1464>=1 ts_o open from connection matrix output <109> pwr down
SLG46531_ds_109 page 131 of 169 SLG46531 figure 93. ts output vs tempe rature, vdd = (1.715.5) v table 93. ts register settings signal function register bit address register definition enable temp. sensor (separately, needs to turn on io16 vref buffer) reg<1464> 0: disable 1: enable cp function selection & power divider (vdd/3, vdd/4) on/off (must be set to auto on/off when using ts) reg<1474:1472> 100: cp a uto on/off (use for 1.71v 0: auto-mode 1: enable (if chip is power down, the bandgap will power down even if it is set to 1) temp output range control reg <1478> 0: 0.62v ~ 0.99v (typ) 1: 0.75v ~ 1.2v (typ) vref1 and ts output ac- tive buffer control reg<1487> 0: disabled (bypass active buffer) 1: enabled 0.2 0.4 0.6 0.8 1 1.2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 ts out (v) t (c) output range 1 (buffered) output range 2 (buffered) unbuffered output
SLG46531_ds_109 page 132 of 169 SLG46531 21.0 external clocking the SLG46531 supports several ways to use an external, higher a ccuracy clock as a reference so urce for internal operations. 21.1 crystal mode when reg<1136> is set to 1, an external crystal can be connecte d to pins 16 and 17 for supplying an accurate clock source. see section 16.0 crystal o scillator. an external clocking signal on pin 17 can be used in place o f the crystal. the high and low l imits for crystal frequency that can be s elected are 32. 768 khz and 4 0 mhz. 21.2 pin 20 or pin 18 source for 25 khz / 2 mhz clock when reg<1358> is set to 1, an external clocking signal on pins 18 or 20 will be routed in place of the internal rc oscillator derived 25 khz/2 mhz clock source. when reg<1355> is set to 0, pin 20 i s in use, when 1 C pin 18 is in use. see figure 50 . the high and low limits for external frequency that can be sel ected are 0 mh z and 77 mhz. 21.3 pin 17 source for 25 mhz clock when reg<1357> is set to 1, an external clo cking signal on pin 17 will be routed in pla ce of the internal rc oscillator derive d 25 mhz clock source. see figure 51 . the high and low limits for e xternal frequen cy that can be se lected are 0 mhz and 84 mhz.
SLG46531_ds_109 page 133 of 169 SLG46531 22.0 appendix a - SLG46531 register definition address signal function register bit definition i 2 c interface byte register bit read write note: for reg<0> to reg<1495>, i 2 c read is valid (assuming reg <1832> = 0), i 2 c write is valid (assuming reg <1871> = 0) matrix 64-to-1 mux's 6 selection bits 00 reg<5:0> matrix out asm-state0-en0 valid valid reg<7:6> reserved valid valid 01 reg<13:8> matrix out asm-state0-en1 valid valid reg<15:14> reserved valid valid 02 reg<21:16> matrix out asm-state0-en2 valid valid reg<23:22> reserved valid valid 03 reg<29:24> matrix out asm-state1-en0 valid valid reg<31:30> reserved valid valid 04 reg<37:32> matrix out asm-state1-en1 valid valid reg<39:38> reserved valid valid 05 reg<45:40> matrix out asm-state1-en2 valid valid reg<47:46> reserved valid valid 06 reg<53:48> matrix out asm-state2-en0 valid valid reg<55:54> reserved valid valid 07 reg<61:56> matrix out asm-state2-en1 valid valid reg<63:62> reserved valid valid 08 reg<69:64> matrix out asm-state2-en2 valid valid reg<71:70> reserved valid valid 09 reg<77:72> matrix out asm-state3-en0 valid valid reg<79:78> reserved valid valid 0a reg<85:80> matrix out asm-state3-en1 valid valid reg<87:86> reserved valid valid 0b reg<93:88> matrix out asm-state3-en2 valid valid reg<95:94> reserved valid valid 0c reg<101:96> matrix out asm-state4-en0 valid valid reg<103:102> reserved valid valid 0d reg<109:104> matrix out asm-state4-en1 valid valid reg<111:110> reserved valid valid 0e reg<117:112> matrix out asm-state4-en2 valid valid reg<119:118> reserved valid valid 0f reg<125:120> matrix out asm-state5-en0 valid valid reg<127:126> reserved valid valid 10 reg<133:128> matrix out asm-state5-en1 valid valid reg<135:134> reserved valid valid 11 reg<141:136> matrix out asm-state5-en2 valid valid reg<143:142> reserved valid valid 12 reg<149:144> matrix out asm-state6-en0 valid valid reg<151:150> reserved valid valid
SLG46531_ds_109 page 134 of 169 SLG46531 13 reg<157:152> matrix out asm-state6-en1 valid valid reg<159:158> reserved valid valid 14 reg<165:160> matrix out asm-state6-en2 valid valid reg<167:166> reserved valid valid 15 reg<173:168> matrix out asm-state7-en0 valid valid reg<175:174> reserved valid valid 16 reg<181:176> matrix out asm-state7-en1 valid valid reg<183:182> reserved valid valid 17 reg<189:184> matrix out asm-state7-en2 valid valid reg<191:190> reserved valid valid 18 reg<197:192> matrix out asm-state-nrst valid valid reg<199:198> reserved valid valid 19 reg<205:200> matrix out pin3 digital output source valid valid reg<207:206> reserved valid valid 1a reg<213:208> matrix out pin3 output enable valid valid reg<215:214> reserved valid valid 1b reg<221:216> matrix out pin4 digital output source valid valid reg<223:222> reserved valid valid 1c reg<229:224> matrix out pin5 digital output source valid valid reg<231:230> reserved valid valid 1d reg<237:232> matrix out pin5 output enable valid valid reg<239:238> reserved valid valid 1e reg<245:240> matrix out pin6 digital output source valid valid reg<247:246> reserved valid valid 1f reg<253:248> matrix out pin7 digital output source valid valid reg<255:254> reserved valid valid 20 reg<261:256> matrix out pin7 output enable valid valid reg<263:262> reserved valid valid 21 reg<269:264> matrix out pin8 digital output source (scl with vi/in- put & nmos open-drain) valid valid reg<271:270> reserved valid valid 22 reg<277:272> matrix out pin9 digital output source (sda with vi/input & nmos open-drain) valid valid reg<279:278> reserved valid valid 23 reg<285:280> matrix out pin10 digital output source valid valid reg<287:286> reserved valid valid 24 reg<293:288> matrix out pin10 output enable valid valid reg<295:294> reserved valid valid 25 reg<301:296> matrix out pin12 digital output source valid valid reg<303:302> reserved valid valid 26 reg<309:304> matrix out pin13 digital output source valid valid reg<311:310> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 135 of 169 SLG46531 27 reg<317:312> matrix out pin13 output enable valid valid reg<319:318> reserved valid valid 28 reg<325:320> matrix out pin14 digital output source valid valid reg<327:326> reserved valid valid 29 reg<333:328> matrix out pin14 output enable valid valid reg<335:334> reserved valid valid 2a reg<341:336> matrix out pin15 digital output source valid valid reg<343:342> reserved valid valid 2b reg<349:344> matrix out pin16 digital output source valid valid reg<351:350> reserved valid valid 2c reg<357:352> matrix out pin16 output enable valid valid reg<359:358> reserved valid valid 2d reg<365:360> matrix out pin17 digital output source valid valid reg<367:366> reserved valid valid 2e reg<373:368> matrix out pin18 digital output source valid valid reg<375:374> reserved valid valid 2f reg<381:376> matrix out pin18 output enable valid valid reg<383:382> reserved valid valid 30 reg<389:384> matrix out pin19 digital output source valid valid reg<391:390> reserved valid valid 31 reg<397:392> matrix out pin19 output enable valid valid reg<399:398> reserved valid valid 32 reg<405:400> matrix out pin20 digital output source valid valid reg<407:406> reserved valid valid 33 reg<413:408> matrix out acmp0 p db (power down) valid valid reg<415:414> reserved valid valid 34 reg<421:416> matrix out acmp1 p db (power down) valid valid reg<423:422> reserved valid valid 35 reg<429:424> matrix out acmp2 p db (power down) valid valid reg<431:430> reserved valid valid 36 reg<437:432> matrix out acmp3 p db (power down) valid valid reg<439:438> reserved valid valid 37 reg<445:440> matrix out input of filter_0 with fixed time edge detec- tor valid valid reg<447:446> reserved valid valid 38 reg<453:448> matrix out input of filter_1 with fixed time edge detec- tor valid valid reg<455:454> reserved valid valid 39 reg<461:456> matrix out input of programmable delay & edge de- tector valid valid reg<463:462> reserved valid valid 3a reg <469:464> matrix out osc 25khz/2 mhz pdb (power down) valid valid reg<471:470> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 136 of 169 SLG46531 3b reg<477:472> matrix out osc 25mhz pdb (power down) valid valid reg<479:478> reserved valid valid 3c reg<485:480> matrix out in0 of lut2_0 or clock input of dff0 valid valid reg<487:486> reserved valid valid 3d reg<493:488> matrix out in1 of lut2 _0 or data input of dff0 valid v alid reg<495:494> reserved valid valid 3e reg<501:496> matrix out in0 of lut2_1 or clock input of dff1 valid valid reg<503:502> reserved valid valid 3f reg<509:504> matrix out in1 of lut2 _1 or data input of dff1 valid v alid reg<511:510> reserved valid valid 40 reg<517:512> matrix out in0 of lut2_2 or clock input of dff2 valid valid reg<519:518> reserved valid valid 41 reg<525:520> matrix out in1 of lut2 _2 or data input of dff2 valid v alid reg<527:526> reserved valid valid 42 reg<533:528> matrix out in0 of lut2_3 or clock input of pgen valid valid reg<535:534> reserved valid valid 43 reg<541:536> matrix out in1 of lut2_3 or nrst of pgen valid valid reg<543:542> reserved valid valid 44 reg<549:544> matrix out in0 of lut3_0 or clock input of dff3 valid valid reg<551:550> reserved valid valid 45 reg<557:552> matrix out in1 of lut3 _0 or data input of dff3 valid v alid reg<559:558> reserved valid valid 46 reg<565:560> matrix out in2 of lut3_0 or nrst (nset) of dff3 valid valid reg<567:566> reserved valid valid 47 reg<573:568> matrix out in0 of lut3_1 or clock input of dff4 valid valid reg<575:574> reserved valid valid 48 reg<581:576> matrix out in1 of lut3 _1 or data input of dff4 valid v alid reg<583:582> reserved valid valid 49 reg<589:584> matrix out in2 of lut3_1 or nrst (nset) of dff4 valid valid reg<591:590> reserved valid valid 4a reg<597:592> matrix out in0 of lut3_2 or clock input of dff5 valid valid reg<599:598> reserved valid valid 4b reg<605:600> matrix out in1 of lut3 _2 or data input of dff5 valid v alid reg<607:606> reserved valid valid 4c reg<613:608> matrix out in2 of lut3_2 or nrst (nset) of dff5 valid valid reg<615:614> reserved valid valid 4d reg<621:616> matrix out in0 of lut3_3 or clock input of dff6 valid valid reg<623:622> reserved valid valid 4e reg<629:624> matrix out in1 of lut3 _3 or data input of dff6 valid v alid re g<631:630> reserved valid valid 4f reg<637:632> matrix out in2 of lut3_3 or nrst (nset) of dff6 valid valid reg<639:638> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 137 of 169 SLG46531 50 reg<645:640> matrix out in0 of lut3_4 or clock input of dff7 valid valid reg<647:646> reserved valid valid 51 reg<653:648> matrix out in1 of lut3 _4 or data input of dff7 valid v alid reg<655:654> reserved valid valid 52 reg<661:656> matrix out in2 of lut3_4 or nrst (nset) of dff7 valid valid reg<663:662> reserved valid valid 53 reg<669:664> matrix out in0 of lut3_5 or delay2 input (or counter2 rst input) valid valid reg<671:670> reserved valid valid 54 reg<677:672> matrix out in1 of lut3_5 or external clock input of delay2 (or counter2) valid valid reg<679:678> reserved valid valid 55 reg<685:680> matrix out in2 of lut3_5 valid valid reg<687:686> reserved valid valid 56 reg<693:688> matrix out in0 of lut3_6 or delay3 input (or counter3 rst input) valid valid reg<695:694> reserved valid valid 57 reg<701:696> matrix out in1 of lut3_6 or external clock input of delay3 (or counter3) valid valid reg<703:702> reserved valid valid 58 reg 709:704> matrix out in2 of lut3_6 valid valid reg<711:710> reserved valid valid 59 reg<717:712> matrix out in0 of lut3_7 or delay4 input (or counter4 rst input) valid valid reg<719:718> reserved valid valid 5a reg<725:720> matrix out in1 of lut3_7 or external clock input of delay4 (or counter4) valid valid reg<727:726> reserved valid valid 5b reg<733:728> matrix out in2 of lut3_7 valid valid reg<735:734> reserved valid valid 5c reg<741:736> matrix out in0 of lut3_8 or delay5 input (or counter5 rst input) valid valid reg<743:742> reserved valid valid 5d reg<749:744> matrix out in1 of lut3_8 or external clock input of delay5 (or counter5) valid valid reg<751:750> reserved valid valid 5e reg<757:752> matrix out in2 of lut3_8 valid valid reg<759:758> reserved valid valid 5f reg<765:760> matrix out in0 of lut3_9 or delay6 input (or counter6 rst input) valid valid reg<767:766> reserved valid valid 60 reg<773:768> matrix out in1 of lut3_9 or external clock input of delay6 (or counter6) valid valid reg<775:774> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 138 of 169 SLG46531 61 reg<781:776> matrix out in2 of lut3_9 valid valid reg<783:782> reserved valid valid 62 reg<789:784> matrix out in0 of lut3 _10 or input of pipe delay vali dvalid reg<791:790> reserved valid valid 63 reg<797:792> matrix out in1 of lut3 _10 or nrst of pipe delay valid valid reg<799:798> reserved valid valid 64 reg<805:800> matrix out in2 of lut3 _10 or clock of p ipe delay vali dvalid reg<807:806> reserved valid valid 65 reg<813:808> matrix out in0 of lut4_0 or delay0 input (or counter0 rst/set input) valid valid reg<815:814> reserved valid valid 66 reg<821:816> matrix out in1 of lut4_0 or external clock input of delay0 (or counter0) valid valid reg<823:822> reserved valid valid 67 reg<829:824> matrix out in2 of lut4 _0 or up input of fsm0 valid val id reg<831:830> reserved valid valid 68 reg<837:832> matrix out in3 of lut4_0 or keep input of fsm0 valid v alid reg<839:838> reserved valid valid 69 reg<845:840> matrix out in0 of lut4_1 or delay1 input (or counter1 rst/set input) valid valid reg<847:846> reserved valid valid 6a reg<853:848> matrix out in1 of lut4_1 or external clock input of delay1 (or counter1) valid valid reg<855:854> reserved valid valid 6b reg<861:856> matrix out in2 of lut4 _1 or up input of fsm1 valid val id reg<863:862> reserved valid valid 6c reg<869:864> matrix out in3 of lut4_1 or keep input of fsm1 valid v alid reg<871:870> reserved valid valid 6d reg<877:872> matrix out pd of either temp-output with bg and/or crystal oscillator by reg<1268> valid valid reg<879:878> reserved valid valid 6e reg<887:880> reserved valid valid 6f reg<895:888> reserved valid valid 70 reg<903:896> reserved valid valid 71 reg<911:904> reserved valid valid 72 reg<919:912> reserved valid valid 73 reg<927:920> reserved valid valid 74 reg<935:928> reserved valid valid 75 reg<943:936> reserved valid valid 76 reg<951:944> reserved valid valid 77 reg<959:952> reserved valid valid 78 reg<967:960> reserved valid valid 79 reg<975:968> reserved valid valid 7a reg<983:976> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 139 of 169 SLG46531 7b reg<991:984> reserved valid valid 7c reg<999:992> reserved valid valid 7d reg<1007:1000> reserved valid valid 7e reg<1015:1008> reserved valid valid 7f reg<1023:1016> reserved valid valid pin 2 80 reg<1024> reserved valid valid reg<1025> reserved valid valid reg<1027:1026> reserved valid valid reg<1029:1028> pin2 pull down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1031:1030> pin2 mode control 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved valid valid pin 3 80 reg<1032> reserved valid valid 81 reg<1033> pin3 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1035:1034> pin3 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1037:1036> pin3 mode control (sig_pin3_oe=0) 00: digital input without schmitt trigger, 01: digital input with schmitt trigger, 10: low voltage digital input 11: reserved valid valid reg<1039:1038> pin3 mode control (sig_pin3_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid pin 4 82 reg<1040> reserved valid valid reg<1041> pin4 driver strength selection 0: 1x 1: 2x valid valid reg<1042> pin4 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1044:1043> pin4 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1047:1045> pin4 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain nmos valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 140 of 169 SLG46531 pin 5 83 reg<1048> reserved valid valid reg<1049> pin5 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1051:1050> pin5 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1053:1052> pin5 mode control (sig_pin5_oe=0) 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved valid valid reg<1055:1054> pin5 mode control (sig_pin5_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid pin 6 84 reg<1056> reserved valid valid reg<1057> pin6 driver strength selection 0: 1x 1: 2x valid valid reg<1058> pin6 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1060:1059> pin6 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1063:1061> pin6 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain valid valid pin 7 85 reg<1064> reserved valid valid reg<1065> pin7 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1067:1066> pin7 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1069:1068> pin7 mode control (sig_pin7_oe=0) 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1071:1070> pin7 mode control (sig_pin7_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 141 of 169 SLG46531 pin 8 86 reg<1072> reserved valid valid reg<1073> pin8 (or scl) driver strength selection 0: 1x (i 2 c up to 400khz) 1: 2x (i 2 c up to 1mhz) valid valid reg<1074> select scl & virtual input 0 or pin8 0: scl & virtual input 0 1: pin8 valid valid reg<1076:1075> pin8 (or scl) pull down resistor value se- lection 00: floating 01: 10k 10: 100k 11: 1m valid valid 86 reg<1079:1077> pin8 (or scl) mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger, 010: low voltage digital input 011: reserved 100: open drain nmos 101: open drain nmos 110: open drain nmos 111: reserved valid valid pin 9 87 reg<1080> reserved valid valid reg<1081> pin9 (or sda) d river strength selection 0: 1x (i 2 c up to 400khz) 1: 2x (i 2 c up to 1mhz) valid valid reg<1082> select sda & virtual input 1 or pin9 0: sda & virtual input 1 1: pin9 valid valid reg<1084:1083> pin9 (or sda) pull down resistor value se- lection 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1087:1085> pin9 (or sda) mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 0 11 : r e s e r v e d 100: open drain nmos 101: open drain nmos 110: open drain nmos 111: reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 142 of 169 SLG46531 pin 10 88 reg<1088> pin10 super drive (4x, nmos open drain) selection 0: super drive off 1: super drive on (if sig_pin10_oe='1' & pin10 mode control = '1x') valid valid reg<1089> pin10 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1091:1090> pin10 pull up/down resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1093:1092> pin10 mode c ontrol (sig_pin10_oe=0) 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1095:1094> pin10 mode c ontrol (sig_pin10_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid pin 12 89 reg<1096> pin12 super drive (4x, nmos open drain) selection 0: super drive off 1: super drive on (if pin12 mode control = '101') valid valid reg<1097> pin12 driver strength selection 0: 1x 1: 2x valid valid 89 reg<1098> pin12 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1100:1099> pin12 pull up/down resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1103:1101> pin12 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 143 of 169 SLG46531 pin 13 8a reg<1104> reserved valid valid reg<1105> pin13 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1107:1106> pin13 pull up/down resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1109:1108> pin13 mode control (sig_pin13_oe=0) 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1111:1110> pin13 mode control (sig_pin13_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid pin 14 8b reg<1112> reserved valid valid reg<1113> pin14 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1115:1114> pin14 pull up/down resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1117:1116> pin14 mode control (sig_pin14_oe=0) 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1119:1118> pin14 mode control (sig_pin14_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid pin 15 8c reg<:1120> reserved valid valid reg<1121> pin15 driver strength selection 0: 1x 1: 2x valid valid 8c reg<1122> pin15 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1124:1123> pin15 pull up/down resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1127:1125> pin15 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 144 of 169 SLG46531 pin 16 8d reg<1128> reserved valid valid reg<1129> pin16 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1131:1130> pin16 pull up/down resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1133:1132> pin16 mode control (sig_pin16_oe=0) 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: sel for xsoc (x2) valid valid reg<1135:1134> pin16 mode control (sig_pin16_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid pin 17 8e reg<:1136> x1 & x2 for crystal osc enable 0: disable 1: enable valid valid reg<1137> pin17 driver strength selection 0: 1x 1: 2x valid valid reg<1138> pin17 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1140:1139> pin17 pull up/down resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1143:1141> pin17 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: sel for xosc (x1) 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain nmos valid valid pin 18 8f reg<1144> reserved valid valid 8f reg<1145> pin18 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1147:1146> pin18 pull up/down resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1149:1148> pin18 mode control (sig_pin18_oe=0) 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1151:1150> pin18 mode control (sig_pin18_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 145 of 169 SLG46531 pin 19 90 reg<1152> reserved valid valid reg<1153> pin19 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1155:1154> pin19 pull up/down resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1157:1156> pin19 mode control (sig_pin19_oe=0) 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1159:1158> pin19 mode control (sig_pin19_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid pin 20 91 reg<1160> reserved valid valid reg<1161> pin20 driver strength selection 0: 1x 1: 2x valid valid reg<1162> pin20 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1164:1163> pin20 pull up/down resistor value selec- tion 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1167:1165> pin20 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain nmos valid valid acmp1 92 reg<1168> acmp1 positive input source select pin6 0: disable 1: enable valid valid 92 reg<1169> acmp1 analog buffer enable (max. bw 1mhz) 0: disable analog buffer 1: enable analog buffer valid valid reg<1171:1170> acmp1 hysteresis enable 00: 0mv 01: 25mv 10: 50mv, 11: 200mv (01: for both external & internal vref; 10 & 11: for only internal vref; external vref will not have 50mv & 200mv hyster- esis.) valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 146 of 169 SLG46531 acmp0 92 reg<1172> acmp0 positive input source select vdd 0: disable 1: enable valid valid reg<1173> acmp0 analog buffer enable (max. bw 1mhz) 0: disable analog buffer 1: enable analog buffer valid valid reg<1175:1174> acmp0 hysteresis enable 00: 0mv 01: 25mv 10: 50mv, 11: 200mv (01: for both external & internal vref; 10 & 11: for only internal vref; external vref will not have 50mv & 200mv hyster- esis.) valid valid acmp3 93 reg<1176> acmp3 positive input source select pin13 0: disable 1: enable valid valid reg<1177> acmp3 positive input source select pin6 0: disable 1: enable valid valid reg<1179:1178> acmp3 hysteresis enable 00: 0mv 01: 25mv 10: 50mv, 11: 200mv (01: for both external & internal vref; 10 & 11: for only internal vref; external vref will not have 50mv & 200mv hyster- esis.) valid valid acmp2 93 reg<1180> acmp2 positive input source select pin13 0: disable 1: enable valid valid reg<1182:1181> acmp2 hysteresis enable 00: 0mv 01: 25mv 10: 50mv, 11: 200mv (01: for both external & internal vref; 10 & 11: for only internal vref; external vref will not have 50mv & 200mv hyster- esis.) valid valid acmp1 100 ua current source enable 93 reg<1183> acmp1 100ua current source enable 0: disable 1: enable valid valid lut3_x function select 94 reg<1184> lut3_3 or dff 6 with nrst/nset select 0: lut3_3 1: dff6 with nrst/nset valid valid reg<1185> lut3_2 or dff 5 with nrst/nset select 0: lut3_2 1: dff5 with nrst/nset valid valid reg<1186> lut3_1 or dff 4 with nrst/nset select 0: lut3_1 1: dff4 with nrst/nset valid valid reg<1187> lut3_0 or dff3 with nrst/nset select (two consecutive dffs if reg<1471>=1 for sm) 0: lut3_0 1: dff3 with nrst/nset valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 147 of 169 SLG46531 lut2_x function select 94 reg<1188> lut2_3 or pgen select 0: lut2_3 1: pgen valid valid reg<1189> lut2_2 or dff2 select 0: lut2_2 1: dff2 valid valid reg<1190> lut2_1 or dff1 select 0: lut2_1 1: dff1 valid valid reg<1191> lut2_0 or dff0 select 0: lut2_0 1: dff0 valid valid lut4_x function select 95 reg<1192> lut4_1 or dly/cnt1(16bits) select 0: lut4_1 1: dly/cnt1(16bits) valid valid reg<1193> lut4_0 or dly/cnt0(16bits) select 0: lut4_0 1: dly/cnt0(16bits) valid valid lut3_x function select 95 reg<1194> lut3_9 or dly/cnt6(8bits) select 0: lut3_9 1: dly/cnt6(8bits) valid valid reg<1195> lut3_8 or dly/cnt5(8bits) select 0: lut3_8 1: dly/cnt5(8bits) valid valid reg<1196> lut3_7 or dly/cnt4(8bits) select 0: lut3_7 1: dly/cnt4(8bits) valid valid reg<1197> lut3_6 or dly/cnt3(8bits) select 0: lut3_6 1: dly/cnt3(8bits) valid valid reg<1198> lut3_5 or dly/cnt2(8bits) select 0: lut3_5 1: dly/cnt2(8bits) valid valid reg<1199> lut3_4 or dff 7 with nrst/nset select 0: lut3_4 1: dff7 with nrst/nset valid valid lut2_1 / dff1 96 reg<1200> lut2_1 <0> valid valid reg<1201> lut2_1 <1> / dff1 initial polarity select 0: low 1: high valid valid reg<1202> lut2_1 <2> / dff1 output select 0: q output 1: qb output valid valid reg<1203> lut2_1 <3> / dff1 or latch select 0: dff function 1: latch function valid valid lut2_0 / dff0 96 reg<1204> lut2_0 <0> valid valid 96 reg<1205> lut2_0 <1> / dff0 initial polarity select 0: low 1: high valid valid reg<1206> lut2_0 <2> / dff0 output select 0: q output 1: qb output valid valid reg<1207> lut2_0 <3> / dff0 or latch select 0: dff function 1: latch function valid valid lut2_3 / pgen 97 reg<1211:1208> lut2_3<3:0> or pge n 4bit counter da- ta<3:0> valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 148 of 169 SLG46531 lut2_2 / dff2 97 reg<1212> lut2_2 <0> valid valid reg<1213> lut2_2 <1> / dff2 initial polarity select 0: low 1: high valid valid reg<1214> lut2_2 <2> / dff2 output select 0: q output 1: qb output valid valid reg<1215> lut2_2 <3> / dff2 or latch select 0: dff function 1: latch function valid valid lut3_0 / dff3 98 reg<1219:1216> lut3_0 <3:0> valid valid reg<1220> lut3_0 <4> / dff3 initial polarity select 0: low 1: high valid valid reg<1221> lut3_0 <5> / dff3 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1222> lut3_0 <6> / dff3 output select 0: q output 1: qb output valid valid reg<1223> lut3_0 <7> / dff3 or latch select 0: dff function 1: latch function valid valid lut3_1 / dff4 99 reg<1227:1224> lut3_1 <3:0> valid valid reg<1228> lut3_1 <4> / dff4 initial polarity select 0: low 1: high valid valid reg<1229> lut3_1 <5> / dff4 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1230> lut3_1 <6> / dff4 output select 0: q output 1: qb output valid valid reg<1231> lut3_1 <7> / dff4 or latch select 0: dff function 1: latch function valid valid lut3_2 / dff5 9a reg<1235:1232> lut3_2 <3:0> valid valid reg<1236> lut3_2 <4> / dff5 initial polarity select 0: low 1: high valid valid reg<1237> lut3_2 <5> / dff5 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1238> lut3_2 <6> / dff5 output select 0: q output 1: qb output valid valid 9a reg<1239> lut3_2 <7> / dff5 or latch select 0: dff function 1: latch function valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 149 of 169 SLG46531 lut3_3 / dff6 9b reg<1243:1240> lut3_3 <3:0> valid valid reg<1244> lut3_3 <4> / dff6 initial polarity select 0: low 1: high valid valid reg<1245> lut3_3 <5> / dff6 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1246> lut3_3 <6> / dff6 output select 0: q output 1: qb output valid valid reg<1247> lut3_3 <7> / dff6 or latch select 0: dff function 1: latch function valid valid lut3_4 / dff7 9c reg<1251:1248> lut3_4 <3:0> valid valid reg<1252> lut3_4 <4> / dff7 initial polarity select 0: low 1: high valid valid reg<1253> lut3_4 <5> / dff7 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1254> lut3_4 <6> / dff7 output select 0: q output 1: qb output valid valid reg<1255> lut3_4 <7> / dff7 or latch select 0: dff function 1: latch function valid valid lut3_10 / pipe delay 9d reg<1259:1256> lut3_10 <3:0> / pipe delay out0 select valid valid reg<1263:1260> lut3_10 <7:4> / pipe delay out1 select valid valid 9e reg<1265:1264> select the edge mode of programmable de- lay & edge detector 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay valid valid reg<1267:1266> delay value select for programmable delay & edge detector (vdd=3.3v, typical) 00: 125ns 01: 250ns 10: 375ns 11: 500ns valid valid reg<1269:1268> power down enable between temp output and crystal oscillator 00: no matrix pd 01: matrix pd for crystal oscillator 10: matrix pd for temp sensor 11: matrix pd for both xosc & temp sensor valid valid reg<1270> lut3_10 or pipe delay select 0: lut3_10 1: pipe delay valid valid reg<1271> pipe delay out1 polarity select 0: non-inverted 1: inverted valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 150 of 169 SLG46531 dly/cnt2 9f reg<1273:1272> dly2 mode select or asynchronous cnt2 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & count- er reset) 10: on rising edge only (for delay & count- er reset) 11: no delay on either falling or rising edges / high level reset valid valid reg<1276:1274> dly/cnt2 clock source select 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter1 overflow valid valid reg<1277> dly/cnt2 output sel ection if dly/cnt2 mode selection is "11". 0: default output 1: edge detector output valid valid reg<1279:1278> dly/cnt2 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid dly/cnt3 a0 reg<1281:1280> dly3 mode select or asynchronous cnt3 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & count- er reset) 10: on rising edge only (for delay & count- er reset) 11: no delay on either falling or rising edges / high level reset valid valid reg<1284:1282> dly/cnt3 clock source select 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter2 overflow valid valid reg<1285> dly/cnt3 output sel ection if dly/cnt3 mode selection is "11". 0: default output 1: edge detector output valid valid reg<1287:1286> dly/cnt3 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 151 of 169 SLG46531 dly/cnt4 a1 reg<1289:1288> dly4 mode select or asynchronous cnt4 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & count- er reset) 10: on rising edge only (for delay & count- er reset) 11: no delay on either falling or rising edges / high level reset valid valid reg<1292:1290> dly/cnt4 clock source select 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter3 overflow valid valid reg<1293> dly/cnt4 output sel ection if dly/cnt4 mode selection is "11". 0: default output 1: edge detector output valid valid reg<1295:1294> dly/cnt4 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid dly/cnt5 a2 reg<1297:1296> dly5 mode select or asynchronous cnt5 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & count- er reset) 10: on rising edge only (for delay & count- er reset) 11: no delay on either falling or rising edges / high level reset valid valid reg<1300:1298> dly/cnt5 clock source select 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter4 overflow valid valid reg<1301> dly/cnt5 output sel ection if dly/cnt5 mode selection is "11". 0: default output 1: edge detector output valid valid reg<1303:1302> dly/cnt5 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 152 of 169 SLG46531 dly/cnt6 a3 reg<1305:1304> dly6 mode select or asynchronous cnt6 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & count- er reset) 10: on rising edge only (for delay & count- er reset) 11: no delay on either falling or rising edges / high level reset valid valid reg<1308:1306> dly/cnt6 clock source select 000: internal osc clock 001: osc/4 010: osc/12, 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter5 overflow valid valid reg<1309> dly/cnt6 output sel ection if dly/cnt6 mode selection is "11". 0: default output 1: edge detector output valid valid reg<1311:1310> dly/cnt6 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid dly/cnt0 a4 reg<1313:1312> dly0 mode select or asynchronous cnt0 reset (16bits) 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & count- er reset) 10: on rising edge only (for delay & count- er reset) 11: no delay on either falling or rising edges / high level reset valid valid reg<1316:1314> dly/cnt0 clock source select (16bits) 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter6 overflow valid valid reg<1317> cnt0/fsm0's q are set to data or reset to 0s selection (16bits) 0: reset to 0s 1: set to data (reg<1583:1576, 1591:1584>) valid valid reg<1319:1318> dly/cnt0 mode selection (16bits) 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 153 of 169 SLG46531 dly/cnt1 a5 reg<1321:1320> dly1 mode select or asynchronous cnt1 reset (16bits) 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & count- er reset) 10: on rising edge only (for delay & count- er reset) 11: no delay on either falling or rising edges / high level reset valid valid reg<1324:1322> dly/cnt1 clock source select (16bits) 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter0 overflow valid valid reg<1325> cnt1/fsm1's q are set to data or reset to 0s selection (16bits) 0: reset to 0s 1: set to data (reg<1599:1592, 1607:1600>) valid valid reg<1327:1326> dly/cnt1 mode selection (16bits) 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid dly/cntx one-shot / freq. detect output polarity a6 reg<1328> reserved valid valid reg<1329> select the polarity of dly/cnt6's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1330> select the polarity of dly/cnt5's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1331> select the polarity of dly/cnt4's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1332> select the polarity of dly/cnt3's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1333> select the polarity of dly/cnt2's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1334> select the polarity of dly/cnt1's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1335> select the polarity of dly/cnt0's one shot / freq. detect output 0: default output 1: inverted output valid valid oscillator a7 reg<1337:1336> osc clock pre-divider for 25mhz 00: div1 01: div2 10: div4 11: div8 valid valid reg<1338> osc fast start-up enable for 25khz/2mhz 0: disable 1: enable valid valid reg<1340:1339> osc clock pre-divider for 25khz/2mhz 00: div1 01: div2 10: div4 11: div8 valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 154 of 169 SLG46531 a7 reg<1341> force 25mhz oscillator on 0: auto power on (if any cnt/dly use 25mhz source) 1: force power on valid valid reg<1342> oscillator (25khz: ring osc, 2m: rc-osc) select 0: 25khz ring osc 1: 2mhz rc-osc valid valid reg<1343> force 25khz/2mhz oscillator on 0: auto power on (if any cnt/dly use 25k/2mhz source) 1: force power on valid valid a8 reg<1346:1344> internal osc 25khz/2mhz frequency di- vider control for matrix input <28> 000: osc/1 001: osc/2 010: osc/3 011: osc/4 100: osc/8 101: osc/12 110: osc/24 111: osc/64 valid valid reg<1349:1347> internal osc 25khz/2mhz frequency di- vider control for matrix input <27> 000: osc/1 001: osc/2 010: osc/3 011: osc/4 100: osc/8 101: osc/12 110: osc/24 111: osc/64 valid valid reg<1350> osc clock 25khz/2mhz to matrix input <28> enable 0: disable 1: enable valid valid reg<1351> osc clock 25khz/2mhz to matrix input <27> enable 0: disable 1: enable valid valid a9 reg<1354:1352> asm_reg_init<2:0> for asm state default setup bits valid valid reg<1355> external oscillator pin selection for 25khz/2mhz 0: pin20 1: pin18 valid valid reg<1356> osc clock 25 mhz to matrix input <29> en- able 0: disable 1: enable valid valid reg<1357> external clock source select instead of 25mhz 0: internal oscillator 1: external clock from pin17 valid valid reg<1358> external clock source select instead of 25khz/2mhz 0: internal oscillator 1: external clock fr om pin18 or pin 20 valid valid reg<1359> reserved valid valid asm 8-to-1 muxs 3 selection bits aa reg<1362:1360> asm_state0_dec8x1_en1 valid valid reg<1363> reserved valid valid reg<1366:1364> asm_state0_dec8x1_en0 valid valid reg<1367> reserved valid valid ab reg<1370:1368> asm_state1_dec8x1_en0 valid valid reg<1371> reserved valid valid reg<1374:1372> asm_state0_dec8x1_en2 valid valid reg<1375> reserved valid valid ac reg<1378:1376> asm_state1_dec8x1_en2 valid valid reg<1379> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 155 of 169 SLG46531 ac reg<1382:1380> asm_state1_dec8x1_en1 valid valid reg<1383> reserved valid valid ad reg<1386:1384> asm_state2_dec8x1_en1 valid valid reg<1387> reserved valid valid reg<1390:1388> asm_state2_dec8x1_en0 valid valid reg<1391> reserved valid valid ae reg<1394:1392> asm_state3_dec8x1_en0 valid valid reg<1395> reserved valid valid reg<1398:1396> asm_state2_dec8x1_en2 valid valid reg<1399> reserved valid valid af reg<1402:1400> asm_state3_dec8x1_en2 valid valid reg<1403> reserved valid valid reg<1406:1404> asm_state3_dec8x1_en1 valid valid reg<1407> reserved valid valid b0 reg<1410:1408> asm_state4_dec8x1_en1 valid valid reg<1411> reserved valid valid reg<1414:1412> asm_state4_dec8x1_en0 valid valid reg<1415> reserved valid valid b1 reg<1418:1416> asm_state5_dec8x1_en0 valid valid reg<1419> reserved valid valid reg<1422:1420> asm_state4_dec8x1_en2 valid valid reg<1423> reserved valid valid b2 reg<1426:1424> asm_state5_dec8x1_en2 valid valid reg<1427> reserved valid valid reg<1430:1428> asm_state5_dec8x1_en1 valid valid reg<1431> reserved valid valid b3 reg<1434:1432> asm_state6_dec8x1_en1 valid valid reg<1435> reserved valid valid reg<1438:1436> asm_state6_dec8x1_en0 valid valid reg<1439> reserved valid valid b4 reg<1442:1440> asm_state7_dec8x1_en0 valid valid reg<1443> reserved valid valid reg<1446:1444> asm_state6_dec8x1_en2 valid valid reg<1447> reserved valid valid b5 reg<1450:1448> asm_state7_dec8x1_en2 valid valid reg<1451> reserved valid valid reg<1454:1452> asm_state7_dec8x1_en1 valid valid reg<1455> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 156 of 169 SLG46531 filter / edge detector b6 reg<1457:1456> select the edg e mode of edge detector_1 00: rising edge 01: falling edge 10: both edge 11: delay valid valid reg<1458> filter_1/edge detector _1 output polarity se- lect 0: filter_1 output 1: filter_1 out put inverted valid valid reg<1459> filter_1or edge detector_1 select (typ. 30 ns @vdd=3.3 v) 0: filter_1 1: edge detector_1 valid valid reg<1461:1460> select the edg e mode of edge detector_0 00: rising edge 01: falling edge 10: both edge 11: delay valid valid reg<1462> filter_0/edge detector _0 output polarity se- lect 0: filter_0 output 1: filter_0 out put inverted valid valid reg<1463> filter_0 or edge d etector_0 select (typ. 47 ns @vdd=3.3 v) 0: filter_0 1: edge detector_0 valid valid vref / bandgap b7 reg<1464> reserved valid valid reg<1465> reserved valid valid reg<1466> bandgap ok for acmp output delay time select, the start time is "resetb_core go to high" 0: 500 us 1: 50 us valid valid reg<1467> reserved valid valid reg<1468> reserved valid valid reg<1469> reserved valid valid reg<1470> reserved valid valid reg<1471> two consecutive dffs enable for sm 0: disable 1: enable valid valid b8 reg<1474:1472> power divider (vdd/3, vdd/4) on/off 0xx: power divider off (if there is no use of vdd/3, vdd/4 @ ac mp negative in) 100: reservedb x10: reserved xx1:reserved valid valid reg<1475> vdd bypass enable when device power is 1.8 v 0: regulator auto on 1: regulator off (vdd bypass) valid valid reg<1476> force bandgap on 0: auto-mode 1: enable (if chip is power down, the band- gap will power down ev en if it is s et to 1). valid valid reg<1477> nvm power down 0: none (or programming enable) 1: power down (or programming disable) valid valid reg<1478> reserved valid valid reg<1479> gpio quick charge enable 0: disable 1: enable valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 157 of 169 SLG46531 b9 reg<1482:1480> vref2 output source select 000: acmp2 vref 001: acmp3 vref 100: vdd/2 101: vdd/3 110: vdd/4 111: hi-z valid valid reg<1483> vref2 output active buffer control 0: disabled (bypass active buffer) 1: enabled valid valid reg<1486:1484> vref1 output source select 000: acmp0 vref 001: acmp1 vref 100: vdd/2 101: vdd/3 110: vdd/4 111: hi-z valid valid reg<1487> vref1 output active buffer control 0: disabled (bypass active buffer) 1: enabled valid valid ba reg<1488> reserved valid valid reg<1489> wake time selection in wake sleep mode 0: short wake time 1: normal wake time valid valid reg<1490> acmp0 wake & sleep function enable 0: disable 1: enable valid valid reg<1491> acmp1 wake & sleep function enable 0: disable 1: enable valid valid reg<1492> acmp2 wake & sleep function enable 0: disable 1: enable valid valid reg<1493> acmp3 wake & sleep function enable 0: disable 1: enable valid valid reg<1494> wake sleep output state when ws oscilla- tor is power down if dly/cnt0 mode selec- tion is "11" 0: low 1: high valid valid reg<1495> wake sleep ratio control mode selection if dly/cnt0 mode selection is "11" 0: default mode 1: wake sleep ratio control mode valid valid bb reg<:1503:1496> reserved valid valid bc reg<:1511:1504> reserved valid valid bd reg<:1519:1512> reserved valid valid be reg<:1527:1520> reserved valid valid bf reg<:1535:1528> reserved valid valid lut / dly/cnt control data c0 reg<1543:1536> lut3_5 <7:0> or dly/cnt2 control data 1 - 256 (delay time = [counter control data + 1] / freq) valid valid c1 reg<1551:1544> lut3_6 <7:0> or dly/cnt3 control data 1 - 256 (delay time = [counter control data + 1] / freq) valid valid c2 reg<1559:1552> lut3_7 <7:0> or dly/cnt4 control data 1 - 256 (delay time = [counter control data + 1] / freq) valid valid c3 reg<1567:1560> lut3_8 <7:0> or dly/cnt5 control data 1 - 256 (delay time = [counter control data + 1] / freq) valid valid c4 reg<1575:1568> lut3_9 <7:0> or dly/cnt6 control data 1 - 256 (delay time = [counter control data + 1] / freq) valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 158 of 169 SLG46531 c5 reg<1583:1576> lut4_0 <15:0> or dly/cnt0 (16bits, <15:0> = <1591:1576>) control data 1 - 16384 (delay time = [counter control data + 2] / freq) valid valid c6 reg<1591:1584> valid valid c7 reg<1599:1592> lut4_1 <15:0> or dly/cnt1 (16bits, <15:0> = <1607:1592>) control data 1 - 65536 (delay time = [counter control data + 2] / freq) valid valid c8 reg<1607:1600> valid valid c9 reg<1615:1608> pgen pattern data <15:0> = <1623:1608> valid valid ca reg<1623:1616> valid valid acmp0 cb r e g < 1 6 2 8 : 1 6 2 4 > a c m p 0 - i n v o l t a g e s e l e c t : 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref(pin12) 11011: ext_vref(pin7) 11100: ext_vref(pin12)/2 11101:ext_vref(pin7)/2 valid valid r e g < 1 6 3 0 : 1 6 2 9 > a c m p 0 p o s i t i v e i n p u t d i v i d e r 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x valid valid reg<1631> acmp0 low bandwidth (max: 1mhz) en- a b l e 0: off 1:on valid valid acmp1 cc r e g < 1 6 3 6 : 1 6 3 2 > a c m p 1 - i n v o l t a g e s e l e c t : 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref(pin12) 11011: ext_vref(pin12) 11100: ext_vref(pin12)/2 11101: ext_vref(pin12)/2 valid valid reg<1638:1637> acmp1 positive input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x valid valid reg<1639> acmp1 low bandwidth (max: 1mhz) en- a b l e 0: off 1: on valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 159 of 169 SLG46531 acmp2 cd reg<1644:1640> acmp2-in voltage select 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref(pin12) 11011: ext_vref(pin14) 11100: ext_vref(pin12)/2 11101: ext_vref(pin14)/2 valid valid reg<1646:1645> acmp2 positive input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x valid valid reg<1647> acmp2 low bandwidth (max: 1mhz) en- a b l e 0: off 1: on valid valid acmp3 ce r e g < 1 6 5 2 : 1 6 4 8 > a c m p 3 - i n v o l t a g e s e l e c t : 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref(pin12) 11011: ext_vref(pin14) 11100: ext_vref(pin12)/2 11101: ext_vref(pin14)/2 valid valid r e g < 1 6 5 4 : 1 6 5 3 > a c m p 3 p o s i t i v e i n p u t d i v i d e r 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x valid valid reg<1655> acmp3 low bandwidth (max: 1mhz) en- a b l e 0: off 1: on valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 160 of 169 SLG46531 misc. cf reg<1656> reserved valid valid reg<1657> switch from matrix out: osc 25mhz pd to matrix out: osc 25mhz force on 0: osc pd 1: osc force on (matrix output <59>) valid valid reg<1658> switch from matrix out: osc 25khz/2mhz pd to matrix out: osc 25khz/2mhz force on 0: osc pd 1: osc force on (matrix output <58>) valid valid reg<1659> reserved valid valid cf reg<1660> reserved valid valid reg<1661> reserved valid valid reg<1662> i 2 c reset bit with relo ading nvm into data register (tbd) 0: keep existing condition 1 : r e s e t e x e c u t i o n valid valid reg<1663> io latching enable during i 2 c write inter- face 0: disable 1: enable valid valid d0 reg<1671:1664> ram 8 outputs for asm-state0 valid valid d1 reg<1679:1672> ram 8 outputs for asm-state1 valid valid d2 reg<1687:1680> ram 8 outputs for asm-state2 valid valid d3 reg<1695:1688> ram 8 outputs for asm-state3 valid valid d4 reg<1703:1696> ram 8 outputs for asm-state4 valid valid d5 reg<1711:1704> ram 8 outputs for asm-state5 valid valid d6 reg<1719:1712> ram 8 outputs for asm-state6 valid valid d7 reg<1727:1720> ram 8 outputs for asm-state7 valid valid d8 reg<1735:1728> user configurabl e ram / otp byte 0 valid valid d9 reg<1743:1736> user configurabl e ram / otp byte 1 valid valid da reg<1751:1744> user configurabl e ram / otp byte 2 valid valid db reg<1759:1752> user configurabl e ram / otp byte 3 valid valid dc reg<1767:1760> user configurabl e ram / otp byte 4 valid valid dd reg<1775:1768> user configurabl e ram / otp byte 5 valid valid de reg<1783:1776> user configurabl e ram / otp byte 6 valid valid df reg<1791:1784> user configurabl e ram / otp byte 7 valid valid e0 reg<1799:1792> reserved invalid invalid e1 reg<1807:1800> reserved invalid invalid e2 reg<1815:1808> reserved invalid invalid e3 reg<1823:1816> reserved invalid invalid e4 reg<1831:1824> 8-bit pattern id byte 1 (from nvm): id[39:32] valid valid e5 reg<1832> nvm data read disable (from nvm): id[24] for bank0/1/2 only 0: disable (progr ammed data can be read.), 1: enable (programmed dat a can't be read.) valid invalid reg<1833> reserved valid invalid reg<1835:1834> reserved valid invalid reg<1839:1836> reserved valid invalid e6 reg<1847:1840> 8-bit pattern id byte 0 (from nvm): id[23:16] valid valid e7 reg<1855:1848> reserved valid invalid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 161 of 169 SLG46531 e8 reg<1863:1856> reserved valid invalid e9 reg<1867:1864> i 2 c control code bit [3:0] value for slave address valid invalid reg<1868> reserved valid valid reg<1869> reserved valid valid reg<1870> reserved valid valid reg<1871> bank0/1/2 i 2 c-write protection bit 0: writable 1: non-writable valid invalid ea reg<1879:1872> cnt4 counted value valid invalid eb reg<1887:1880> cnt0 (16bits) = <1895:1880> counted val- ue valid invalid ec reg<1895:1888> valid invalid ed reg<1903:1896> cnt6 counted value valid invalid ee reg<1911:1904> cnt1 (16bits) = <1919:1904> counted val- ue valid invalid ef reg<1919:1912> valid invalid matrix input f0 reg<1920> matrix input 0 gnd valid invalid reg<1921> matrix input 1 pin2 digital input valid invalid reg<1922> matrix input 2 pin3 digital input valid invalid reg<1923> matrix input 3 pin4 digital input valid invalid reg<1924> matrix input 4 pin5 digital input valid invalid reg<1925> matrix input 5 pin6 digital input valid invalid reg<1926> matrix input 6 pin7 digital input valid invalid reg<1927> matrix input 7 pin10 digital input valid invalid f1 reg<1928> matrix input 8 lut2_0 / dff0 output valid invalid reg<1929> matrix input 9 lut2_1 / dff1 output valid invalid reg<1930> matrix input 10 lut2_2 / dff2 output valid invalid reg<1931> matrix input 11 lut2_3 / pgen output valid invalid reg<1932> matrix input 12 lut3_0 / dff3 output valid invalid reg<1933> matrix input 13 lut3_1 / dff4 output valid invalid reg<1934> matrix input 14 lut3_2 / dff5 output valid invalid reg<1935> matrix input 15 lut3_3 / dff6 output valid invalid f2 reg<1936> matrix input 16 lut3_4 / dff7 output valid invalid reg<1937> matrix input 17 lut3_5 / cnt_dly2(8bit) output valid inva lid reg<1938> matrix input 18 lut3_6 / cnt_dly3(8bit) output valid inva lid reg<1939> matrix input 19 lut3_7 / cnt_dly4(8bit) output valid inva lid reg<1940> matrix input 20 lut3_8 / cnt_dly5(8bit) output valid inva lid reg<1941> matrix input 21 lut3_9 / cnt_dly6(8bit) output valid inva lid reg<1942> matrix input 22 lut4_0 / cnt_dly0(16bit) output valid in valid reg<1943> matrix input 23 lut4_1 / cnt_dly1(16bit) output valid inv alid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 162 of 169 SLG46531 f3 reg<1944> matrix input 24 lut3_10 / pipe delay (1st stage) output valid invalid reg<1945> matrix input 25 pipe delay output0 valid invalid reg<1946> matrix input 26 pipe delay output1 valid invalid reg<1947> matrix input 27 fixed "l " output because it is osc cloc k. valid invalid reg<1948> matrix input 28 fixed "l " output because it is osc cloc k. valid invalid reg<1949> matrix input 29 fixed "l " output because it is osc cloc k. valid invalid reg<1950> matrix input 30 filter0 / edge detect0 output valid inva lid reg<1951> matrix input 31 filter1 / edge detect1 output valid inva lid f4 reg<1952> matrix input 32 virtual input <0> valid valid reg<1953> matrix input 33 virtual input <1> valid valid reg<1954> matrix input 34 virtual input <2> valid valid f4 reg<1955> matrix input 35 virtual input <3> valid valid reg<1956> matrix input 36 virtual input <4> valid valid reg<1957> matrix input 37 virtual input <5> valid valid reg<1958> matrix input 38 virtual input <6> valid valid reg<1959> matrix input 39 vi rtual input <7> valid valid f5 reg<1960> matrix input 40 ram_0 output for asm-state valid invalid reg<1961> matrix input 41 ram_1 output for asm-state valid invalid reg<1962> matrix input 42 ram_2 output for asm-state valid invalid reg<1963> matrix input 43 ram_3 output for asm-state valid invalid reg<1964> matrix input 44 ram_4 output for asm-state valid invalid reg<1965> matrix input 45 ram_5 output for asm-state valid invalid reg<1966> matrix input 46 ram_6 output for asm-state valid invalid reg<1967> matrix input 47 ram_7 output for asm-state valid invalid f6 reg<1968> matrix input 48 pin12 digital input valid invalid reg<1969> matrix input 49 pin13 digital input valid invalid reg<1970> matrix input 50 pin14 digital input valid invalid reg<1971> matrix input 51 pin15 digital input valid invalid reg<1972> matrix input 52 pin16 digital input valid invalid reg<1973> matrix input 53 pin17 digital input valid invalid reg<1974> matrix input 54 pin18 digital input valid invalid reg<1975> matrix input 55 pin19 digital input valid invalid f7 reg<1976> matrix input 56 pin20 digital input valid invalid reg<1977> matrix input 57 acmp_0 output valid invalid reg<1978> matrix input 58 acmp_1 output valid invalid reg<1979> matrix input 59 acmp_2 output valid invalid reg<1980> matrix input 60 acmp_3 output valid invalid reg<1981> matrix input 61 programmable delay with edge detector output valid invalid reg<1982> matrix input 62 resetb_core valid invalid reg<1983> matrix input 63 vdd valid invalid reserved f8 reg<1991:1984> reserved valid invalid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 163 of 169 SLG46531 f9 reg<1999:1992> reserved valid invalid fa reg<2007:2000> reserved valid invalid fb reg<2015:2008> reserved valid valid fc reg<2023:2016> reserved valid invalid fd reg<2031:2024> reserved valid invalid fe reg<2039:2032> reserved valid valid ff reg<2047:2040> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46531_ds_109 page 164 of 169 SLG46531 23.0 package top marking system definition part code datecode lot revision ? part id field: identifies the specific device configuration ? date code field: coded date of manufacture ? lot code: designates lot # ? assembly site/coo: specifies assembly site/country of origin ? revision code: device revision xxxxx dd lll c rr coo
SLG46531_ds_109 page 165 of 169 SLG46531 24.0 package drawing and dimensions stqfn 20l 2x3mm 0.4p col package jedec mo-220, variation wece ic net weight: 0.0090 g
SLG46531_ds_109 page 166 of 169 SLG46531 25.0 tape and reel specifications 25.1 carrier tape drawing and dimensions package type # of pins nominal package size [mm] max units reel & hub size [mm] leader (min) trailer (min) tape width [mm] part pitch [mm] per reel per box pockets length [mm] pockets length [mm] stqfn 20l 2x3 mm 0.4p col 20 2 x 3 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4 package type pocket btm length pocket btm width pocket depth index hole pitch pocket pitch index hole diameter index hole to tape edge index hole to pocket center tape width a0 b0 k0 p0 p1 d0 e f w stqfn 20l 2x3 mm 0.4p col 2.2 3.15 0.76 4 4 1.5 1.75 3.5 8 refer to eia-481 specification
SLG46531_ds_109 page 167 of 169 SLG46531 26.0 recommended land pattern 27.0 recommended reflow soldering profile please see ipc/jedec j-std-020: latest revision for reflow prof ile based on package volume of 3.30 mm 3 (nominal). more information can be f ound at www.jedec.org. units: ? m
SLG46531_ds_109 page 168 of 169 SLG46531 28.0 revision history date version change 10/21/2016 1.09 removed references to gpak families 10/11/2016 1.08 updated random read command diagram clarified pipe delay description added temp sensor spec 8/30/2016 1.07 updated section a nalog comparators updated ic net weight 8/5/2016 1.06 replaced figure asm editor - co nnection matrix ou tput ram with the table fixed typos and formatting corrected figures state transition - closed cycling timing and state transition - sequential timing 8/1/2016 1.05 added por to overview updated front page block diagram updated programmable dela y for clarification 6/22/2016 1.04 updated table typica l delay estimated for each blo ck 5/30/2016 1.03 updated acmp power on delay graph added acmp maximum power on delay 4/21/2016 1.02 clarified text in cryst al oscillator section reorganized i2c and asm electrical spec 3/21/2016 1.01 updated s ubsection i2c serial command register pro tection 3/16/2016 1.00 prod uction release
SLG46531_ds_109 page 169 of 169 SLG46531 silego website & support silego technology website silego technology provides online support via our website at http://www.silego.com/ .this website is used as a means to make files and information easily available to customers. for more information regarding si lego green products, please vi sit our website. our green product lines feature: greenpak: programmable mixed signal matrix products greenfet1 / greenfet3: mosfet drivers and ultra-small, low rdso n load switches greenclk1 / greenclk2 / greenclk 3: crystal replacement technolo gy products are also available for purchase directly from silego a t the silego on line store at http://www.silego.com /buy/ . silego technical support datasheets and errata, application notes and example designs, u ser guides, and hardware support documents and the latest software releases are available at the silego website or can be requested directly at info@silego.com . for specific greenpak design or applications questions and supp ort please send e-mail requests to greenpak@silego.com users of silego products can receive assistance through several channels: contact your local sales representative customers can contact their local sales representative or field application engineer (fae) for support. local sales offices are also available to help customers. more information regarding your lo cal representative is available at the silego website or send a request to info@silego.com contact silego directly silego can be contacted d irectly via e-mail at info@silego.com or user submission form, l ocated at the f ollowing url: http://support.silego.com/ other information the latest silego technology press releases, listing of seminars and events, listings of world wide silego technology offices and representatives are all available at http://www.silego.com/ this product has been designed an d qualified for the consumer m arket. applications or uses as critical components in life support devices or systems are n ot authorized. silego technolog y does not assume any liability arising out of such applica- tions or uses of its products. silego technology reserves the r ight to improve product design , functions and reliability without noti

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