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1 for more information www.linear.com/lt8390a typical application features description 60v 2mhz synchronous 4-switch buck-boost controller with spread spectrum the lt ? 8390a is a synchronous 4- switch buck-boost dc/dc controller that regulates output voltage, input or output current from an input voltage above, below , or equal to the output voltage. the proprietar y peak-buck peak-boost current mode control scheme allows adjustable and syn - chronizable 600khz to 2mhz fixed frequency operation, or internal 25% triangle spread spectrum frequency modula - tion for low emi. with a 4v to 60v input voltage range, 0v to 60v output voltage capability, and seamless low noise transitions between operation regions, the lt8390 a is ideal for voltage regulator, battery and supercapacitor charger applications in automotive, industrial, telecom, and even battery-powered systems. the lt8390 a provides input or output current monitor and power good flag. fault protection is also provided to detect output short-circuit condition, during which the lt8390a retries, latches off, or keeps running. 95% efficient 48w (12v 4a) 2mhz buck-boost voltage regulator applications n 4-switch single inductor architecture allows v in above, below or equal to v out n up to 95% efficiency at 2mhz n proprietary peak-buck peak-boost current mode n wide v in range: 4v to 60v n 1.5% output voltage accuracy: 1v v out 60v n 3% input or output current accuracy with monitor n spread spectrum frequency modulation for low emi n high side pmos load switch driver n no top mosfet refresh noise in buck or boost n adjustable and synchronizable: 600khz to 2mhz n v out disconnected from v in during shutdown n available in 28-lead tssop with exposed pad and 28-lead qfn (4mm 5mm) n automotive, industrial, telecom systems n high frequency battery-powered system l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of analog devices, inc. all other trademarks are the property of their respective owners. efficiency vs v in lt8390a 8390afa 20 100v 2 intv cc intv cc intv cc 8390a ta01a 25 30 35 40 50 60 70 80 90 continuous operation with highest component temperature below 90c (t a = 25c) 100 efficiency (%) 8390a ta01b 169k 22nf 0.1f 0.1f 22f 383k 4.7f i out = 4a 100k 0.47f 59.0k 2.2nf 10k 110k 10k 0.1f 133k 100k i out = 2a 0.1f 1f 1f 1h 1f 10 10 22f 22f 4.7f input voltage (v) 5m 10m en/uvlo v ref ctrl pgood bg2 bst2 tg2 intv cc 0 loaden fb v out isp isn sync/sprd test v in 6v to 28v continuous 4v to 56v transient 2mhz 5 63v 100v 2 16v 2 ismon pgood 16v v out 12v 10 4a lsp lsn sw1 sw2 bst1 tg1 bg1 v in lt8390a 15 loadtg ismon ss v c rt gnd ssfm off ssfm on 16v 2
2 for more information www.linear.com/lt8390a absolute maximum ratings v in , en / uvlo , v out , isp , isn .................................... 60 v ( i sp - isn ) .......................................................... C1 v to 1v bst 1, bst 2 ................................................................ 66 v s w 1, sw 2, lsp , lsn ..................................... C6 v to 60 v intv cc , ( bst 1- sw 1), ( bst 2- sw 2) .............................. 6 v ( bst 1- lsp ), ( bst 1- lsn ) ............................................. 6 v (note 1) order information lead free finish tape and reel part marking* package description temperature range lt8390aefe#pbf lt8390aefe#trpbf lt8390afe 28-lead plastic tssop C40c to 125c lt8390aife#pbf lt8390aife#trpbf lt8390afe 28-lead plastic tssop C40c to 125c lt8390ahfe#pbf lt8390ahfe#trpbf lt8390afe 28-lead plastic tssop C40c to 150c lt8390aeufd#pbf lt8390aeufd#trpbf 8390a 28-lead (4mm 5mm) plastic qfn C40c to 125c lt8390aiufd#pbf lt8390aiufd#trpbf 8390a 28-lead (4mm 5mm) plastic qfn C40c to 125c lt8390ahufd#pbf lt8390ahufd#trpbf 8390a 28-lead (4mm 5mm) plastic qfn C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view fe package 28-lead plastic tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 bg1 bst1 sw1 tg1 lsp lsn v in intv cc en/uvlo test loaden v ref ctrl isp bg2 bst2 sw2 tg2 v out loadtg sync/sprd rt v c fb ss pgood ismon isn 29 gnd ja = 30c/w, jc = 5c/w exposed pad (pin 29) is gnd, must be soldered to pcb 9 10 top view 29 gnd ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 tg1 lsp lsn v in intv cc en/uvlo test loaden tg2 v out loadtg sync/sprd rt v c fb ss sw1 bst1 bg1 bg2 bst2 sw2 v ref ctrl isp isn ismon pgood 7 17 18 19 20 21 22 16 8 15 ja = 43c/w, jc = 3.4c/w exposed pad (pin 29) is gnd, must be soldered to pcb pin configuration http://www.linear.com/product/lt8390a#orderinfo fb , loaden , sync / sprd , ctrl , pgood ................... 6 v operating junction temperature range ( notes 2, 3) lt 83 90ae ........................................... C 40 c to 125 c lt 83 90 ai ............................................ C 40 c to 125 c lt 83 90 a h ........................................... C 40 c to 150 c storage temperature range ................... C 65 c to 150 c lt8390a 8390afa
3 for more information www.linear.com/lt8390a electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v en/uvlo = 1.5v unless otherwise noted. parameter conditions min typ max units supply v in operating voltage range l 4 60 v v in quiescent current v en/uvlo = 0.3v v en/uvlo = 1.1v not switching 1 270 2.1 2 2.8 a a ma v out voltage range l 0 60 v v out quiescent current v en/uvlo = 0.3v, v out = 12v v en/uvlo = 1.1v, v out = 12v not switching, v out = 12v 20 0.1 0.1 40 0.5 0.5 60 a a a linear regulators intv cc regulation voltage i intvcc = 20ma 4.85 5.0 5.15 v intv cc load regulation i intvcc = 0ma to 80ma 1 4 % intv cc line regulation i intvcc = 20ma, v in = 6v to 60v 1 4 % intv cc current limit v intvcc = 4.5v 110 145 190 ma intv cc dropout voltage (v in C intv cc ) i intvcc = 20ma, v in = 4v 160 mv intv cc undervoltage lockout threshold falling 3.44 3.54 3.64 v intv cc undervoltage lockout hysteresis 0.24 v v ref regulation voltage i vref = 100a l 1.97 2.00 2.03 v v ref load regulation i vref = 0ma to 1ma 0.4 1 % v ref line regulation i vref = 100a, v in = 4v to 60v 0.1 0.2 % v ref current limit v ref = 1.8v 2 2.5 3.2 ma v ref undervoltage lockout threshold falling 1.78 1.84 1.90 v v ref undervoltage lockout hysteresis 50 mv control inputs/outputs en/uvlo shutdown threshold l 0.3 0.6 1.0 v en/uvlo enable threshold falling l 1.196 1.220 1.244 v en/uvlo enable hysteresis 13 mv en/uvlo hysteresis current v en/uvlo = 0.3v v en/uvlo = 1.1v v en/uvlo = 1.3v C0.1 2.1 C0.1 0 2.5 0 0.1 2.9 0.1 a a a ctrl input bias current v ctrl = 0.75v, current out of pin 0 20 50 na ctrl latch-off threshold falling l 285 300 315 mv ctrl latch-off hysteresis 25 mv load switch driver loaden threshold rising l 1.3 1.4 1.5 v loaden hysteresis 220 mv minimum v out for loadtg to be on v loaden = 5v 2.4 3 v loadtg on voltage v (vout-loadtg) v out = 12v 4.5 5 5.5 v loadtg off voltage v (vout-loadtg) v out = 12v C0.1 0 0.1 v loaden to loadtg turn on propagation delay loaden to loadtg turn off propagation delay c loadtg = 3.3nf to v out , 50% to 50% c loadtg = 3.3nf to v out , 50% to 50% 90 40 ns ns loadtg turn on fall t ime loadtg turn off rise time c loadtg = 3.3nf to v out , 10% to 90% c loadtg = 3.3nf to v out , 90% to 10% 300 10 ns ns lt8390a 8390afa
4 for more information www.linear.com/lt8390a electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v en/uvlo = 1.5v unless otherwise noted. parameter conditions min typ max units error amplifier full scale current regulation v (isp-isn) v ctrl = 2v, v isp = 12v v ctrl = 2v, v isp = 0v l l 97 97 100 100 103 103 mv mv 1/10th current regulation v (isp-isn) v ctrl = 0.35v, v isp = 12v v ctrl = 0.35v, v isp = 0v l l 8 8 10 10 12 12 mv mv ismon monitor output v ismon v (isp-isn) = 100mv, v isp = 12v/0v v (isp-isn) = 10mv, v isp = 12v/0v v (isp-isn) = 0mv, v isp = 12v/0v l l l 1.20 0.30 0.20 1.25 0.35 0.25 1.30 0.40 0.30 v v v isp/isn input common mode range l 0 60 v isp/isn low side to high side switchover voltage v isp = v isn 1.8 v isp/isn high side to low side switchover voltage v isp = v isn 1.7 v isp input bias current v loaden = 5v, v isp = v isn = 12v v loaden = 5v, v isp = v isn = 0v v en/uvlo = 0v, v isp = v isn = 12v or 0v 23 C10 0 a a a isn input bias current v loaden = 5v, v isp = v isn = 12v v loaden = 5v, v isp = v isn = 0v v en/uvlo = 0v, v isp = v isn = 12v or 0v 23 C10 0 a a a isp/isn current regulation amplifier g m 2000 s fb regulation voltage v c = 1.2v l 0.985 1.00 1.015 v fb line regulation v in = 4v to 60v 0.2 0.5 % fb load regulation 0.2 0.8 % fb voltage regulation amplifier g m 660 s fb input bias current fb in regulation, current out of pin 10 40 na v c output impedance 10 m v c standby leakage current v c = 1.2v, v loaden = 0v C10 0 10 na current comparator maximum current sense threshold v (lsp-lsn) buck, v fb = 0.8v boost, v fb = 0.8v l l 35 40 50 50 65 60 mv mv lsp pin bias current v lsp = v lsn = 12v 60 a lsn pin bias current v lsp = v lsn = 12v 60 a fault fb overvoltage threshold (v fb ) rising l 1.08 1.1 1.12 v fb overvoltage hysteresis l 35 50 65 mv fb short threshold (v fb ) falling l 0.24 0.25 0.26 v fb short hysteresis hysteresis l 35 50 65 mv isp/isn over current threshold v (isp-isn) v isp = 12v 750 mv pgood upper threshold offset from v fb rising l 8 10 12 % pgood lower threshold offset from v fb falling l C12 C10 C8 % pgood pull-down resistance 100 200 ss hard pull-down resistance v en/uvlo = 1.1v 100 200 ss pull-up current v fb = 0.4v, v ss = 0v 10 12.5 15 a ss pull-down current v fb = 0.1v, v ss = 2v 1 1.25 1.5 a ss fault latch-off threshold 1.7 v ss fault reset threshold 0.2 v lt8390a 8390afa
5 for more information www.linear.com/lt8390a electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v en/uvlo = 1.5v unless otherwise noted. parameter conditions min typ max units oscillator rt pin voltage r t = 100k 1.00 v switching frequency v sync/sprd = 0v, r t = 226k v sync/sprd = 0v, r t = 100k v sync/sprd = 0v, r t = 59.0k l 645 1290 1900 685 1360 2000 725 1430 2100 khz khz khz sync frequency 600 2100 khz sync/sprd input bias current v sync/sprd = 5v C0.1 0 0.1 a sync/sprd threshold voltage 0.4 1.5 v highest spread spectrum above oscillator frequency v sync/sprd = 5v 21 23 25 % region transition buck-boost to boost (v in /v out ) 0.73 0.75 0.77 boost to buck-boost (v in /v out ) 0.83 0.85 0.87 buck to buck-boost (v in /v out ) 1.23 1.25 1.27 buck-boost to buck (v in /v out ) 1.31 1.33 1.35 peak-buck to peak-boost (v in /v out ) 0.96 0.98 1.00 peak-boost to peak-buck (v in /v out ) 1.00 1.02 1.04 nmos drivers tg1, tg2 gate driver on-resistance gate pull-up gate pull-down v (bst-sw) = 5v 2.6 1.4 b g1, bg2 gate driver on-resistance gate pull-up gate pull-down v intvcc = 5v 3.2 1.2 t g1, tg2 rise t ime tg1, tg2 fall time c l = 3.3nf, 10% to 90% c l = 3.3nf, 90% to 10% 25 20 ns ns bg1, bg2 rise t ime bg1, bg2 fall time c l = 3.3nf, 10% to 90% c l = 3.3nf, 90% to 10% 25 20 ns ns tg off to bg on delay c l = 3.3nf 25 ns bg off to tg on delay c l = 3.3nf 25 ns tg1 minimum duty cycle in buck region peak-buck current mode 10 % tg1 maximum duty cycle in buck region peak-buck current mode 90 % tg1 fixed duty cycle in buck-boost region peak-boost current mode 80 % bg2 fixed duty cycle in buck-boost region peak-buck current mode 20 % bg2 minimum duty cycle in boost region peak-boost current mode 10 % bg2 maximum duty cycle in boost region peak-boost current mode 90 % note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt8390ae is guaranteed to meet performance specifications from 0c to 125c operating junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt8390ai is guaranteed over the C40c to 125c operating junction temperature range. the lt8390ah is guaranteed over the C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 3: the lt8390a includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability . lt8390a 8390afa
6 for more information www.linear.com/lt8390a typical performance characteristics efficiency vs load current (buck region) efficiency vs load current (buck-boost region) efficiency vs load current (boost region) t a = 25c, unless otherwise noted. switching waveforms (buck region) switching waveforms (buck-boost region) switching waveforms (boost region) v out vs i out (cv/cc) v in shutdown current v in quiescent current temperature (c) ?50 0.0 i q (a) 2.5 2.0 1.5 1.0 0.5 3.0 125100 150 ?25 0 25 8390a g08 7550 v in = 60v v in = 12v v in = 4v temperature (c) ?50 1.8 i q (ma) 2.6 2.4 2.2 2.0 2.8 125100 150 ?25 0 25 8390a g09 7550 v in = 60v v in = 12v v in = 4v lt8390a 8390afa 2.5 12 14 output voltage (v) 8390a g07 3 3.5 4 40 50 60 70 80 90 front page application 100 efficiency (%) 8390a g01 front page application v in = 12v, v out = 12v, f sw = 2mhz load current (a) 0 0.5 1 1.5 v in = 24v, v out = 12v, f sw = 2mhz 2 2.5 3 3.5 4 40 50 60 70 80 load current (a) 90 100 efficiency (%) 8390a g02 front page application v in = 8v, v out = 12v, f sw = 2mhz load current (a) 0 0.5 1 0 1.5 2 2.5 3 3.5 4 40 50 60 70 0.5 80 90 100 efficiency (%) 8390a g03 200ns/div front page application v in = 24v, i out = 2a v sw1 20v/div v sw2 20v/div i l 2a/div 1 v out 500mv/div 8390 g04 200ns/div front page application v in = 12v, i out = 2a v sw1 20v/div v sw2 20v/div i l 2a/div v out 500mv/div 8390 g05 200ns/div 1.5 front page application v in = 8v, i out = 2a v sw1 20v/div v sw2 20v/div i l 2a/div v out 500mv/div 8390 g06 load current (a) 0 1 2 2 3 4 5 6 7 2 4 6 8 10
7 for more information www.linear.com/lt8390a typical performance characteristics t a = 25c, unless otherwise noted. intv cc voltage vs temperature intv cc voltage vs v in intv cc uvlo threshold v ref voltage vs temperature v ref voltage vs v in v ref uvlo threshold en/uvlo enable threshold en/uvlo hysteresis current ctrl latch-off threshold temperature (c) ?50 4.85 v intvcc (v ) 5.10 5.05 5.00 4.95 4.90 5.15 125100 150 ?25 0 25 8390a g10 7550 i intvcc = 0ma i intvcc = 80ma v in (v) 0 4.85 v intvcc (v) 5.10 5.05 5.00 4.95 4.90 5.15 5040 60 10 20 8390a g11 30 i intvcc = 20ma temperature (c) ?50 3.2 v intvcc (v) 3.8 3.9 3.7 3.5 3.6 3.4 3.3 4.0 125100 150 ?25 0 25 50 8390a g12 75 rising falling temperature (c) ?50 1.96 v ref (v) 2.02 2.03 2.01 1.99 2.00 1.98 1.97 2.04 125100 150 ?25 0 25 50 8390a g13 75 i vref = 0ma i vref = 1ma v in (v) 0 1.96 v ref (v) 2.02 2.03 2.01 1.99 2.00 1.98 1.97 2.04 5040 60 10 20 8390a g14 30 i vref = 100a temperature (c) ?50 1.70 v ref (v) 1.90 1.95 1.85 1.80 1.75 2.00 125100 150 ?25 250 50 8390a g15 75 rising falling temperature (c) ?50 1.200 v en/uvlo (v) 1.230 1.235 1.225 1.220 1.215 1.210 1.205 1.240 125100 150 ?25 250 50 8390a g16 75 rising falling temperature (c) ?50 2.0 i hys (a) 2.8 2.6 2.4 2.2 3.0 125100 150 ?25 250 50 8390a g17 75 lt8390a 8390afa 75 100 125 150 0.20 0.25 0.30 0.35 0.40 v ctrl (v) rising 8390a g18 falling temperature (c) ?50 ?25 0 25 50
8 for more information www.linear.com/lt8390a typical performance characteristics v (isp-isn) regulation vs v ctrl v (isp-isn) regulation vs v isp v (isp-isn) regulation vs temperature t a = 25c, unless otherwise noted. v (isp-isn) regulation vs v fb fb regulation vs temperature maximum current sense vs temperature fb overvoltage threshold fb short threshold pgood thresholds v isp (v) 0 94 v (isp-isn) (mv) 102 104 100 98 96 106 5040 60 10 20 8390a g20 30 temperature (c) ?50 ?25 94 v (isp-isn) (mv) 102 104 100 98 96 106 125100 150 0 25 8390a g21 7550 isp = 60v isp = 12v isp = 0v v fb (v) 0.96 0.97 0 v (isp-isn) (mv) 80 100 60 40 20 120 1.031.02 1.04 0.98 0.99 8390a g22 1.011.00 temperature (c) ?50 ?25 0.97 v fb (v) 1.01 1.02 1.00 0.99 0.98 1.03 125100 150 0 25 8390a g23 7550 v in = 60v v in = 12v v in = 4v temperature (c) ?50 ?25 30 current limit (mv) 60 65 55 50 45 40 35 70 125100 150 0 25 8390a g24 7550 boost buck temperature (c) ?50 ?25 0.10 v fb (v) 0.30 0.35 0.25 0.20 0.15 0.40 125100 150 0 25 8390a g26 7550 rising falling lt8390a 8390afa 1.75 2 0 25 50 75 100 125 v (isp-isn) (mv) 8390a g19 v ctrl (v) rising falling temperature (c) ?50 ?25 0 25 50 75 100 0 125 150 0.90 0.95 1.00 1.05 1.10 1.15 1.20 v fb (v) 0.25 8390a g25 upper rising upper falling lower rising lower falling temperature (c) ?50 ?25 0 25 0.50 50 75 100 125 150 ?20 ?15 ?10 ?5 0 0.75 5 10 15 20 threshold offset (%) 8390a g27 1 1.25 1.50
9 for more information www.linear.com/lt8390a typical performance characteristics t a = 25c, unless otherwise noted. ismon voltage vs v (isp-isn) ss current vs temperature oscillator frequency vs temperature temperature (c) ?50 ?25 0.0 i ss (a) 10.0 12.5 7.5 5.0 2.5 15.0 125100 150 0 25 8390a g29 7550 pull-up pull-down pin functions bg1: buck side bottom gate drive. drives the gate of buck side bottom n-channel mosfet with a voltage swing from ground to intv cc . bst1: buck side bootstrap floating driver supply. the bst1 pin has an integrated bootstrap schottky diode from the intv cc pin and requires an external bootstrap capacitor to the sw1 pin. the bst1 pin swings from a diode voltage drop below intv cc to (v in + intv cc ). sw1: buck side switch node. the sw1 pin swings from a schottky diode voltage drop below ground up to v in . tg1: buck side top gate drive. drives the gate of buck side top n-channel mosfet with a voltage swing from sw1 to bst1. lsp: positive terminal of the buck side inductor current sense resistor (r sense ). ensure accurate current sense with kelvin connection. lsn: negative terminal of the buck side inductor current sense resistor (r sense ). ensure accurate current sense with kelvin connection. v in : input supply. the v in pin must be tied to the power input to determine the buck, buck-boost, or boost operation regions. locally bypass this pin to ground with a minimum 1f ceramic capacitor. intv cc : internal 5v linear regulator output. the intv cc linear regulator is supplied from the v in pin, and powers the internal control circuitry and gate drivers. locally bypass this pin to ground with a minimum 4.7f ceramic capacitor. en/uvlo: enable and undervoltage lockout. force the pin below 0.3v to shut down the part and reduce v in qui- escent current below 2a . force the pin above 1.233v for normal operation. the accurate 1.220v falling threshold can be used to program an undervoltage lockout (uvlo) threshold with a resistor divider from v in to ground. an accurate 2.5a pull-down current allows the programming of v in uvlo hysteresis. if neither function is used, tie this pin directly to v in . test: factory test. this pin is used for testing purpose only and must be directly connected to ground for the part to operate properly. loaden: load switch enable input. the loaden pin is used to control the on/off of the high side pmos load switch. if the load switch control is not used, tie this pin to v ref or intv cc . forcing the pin low turns off t g1 and tg2, turns on bg1 and bg2, disconnects the v c pin from all internal loads, and turns off loadtg. v ref : voltage reference output. the v ref pin provides an accurate 2v reference capable of supplying 1ma current. locally bypass this pin to ground with a 0.47f ceramic capacitor. lt8390a 8390afa 0.25 0.50 0.75 1.00 1.25 1.50 v ismon (v) 8390a g28 r t = 59.0k r t = 100k v (isp-isn) (mv) r t = 226k temperature (c) ?50 ?25 0 25 50 75 100 125 0 150 0 0.5 1.0 1.5 2.0 2.5 switching frequency (mhz) 8390a g30 20 40 60 80 100 0
10 for more information www.linear.com/lt8390a ctrl: control input for isp/isn current sense threshold. the ctrl pin is used to program the isp/isn current limit: i is(max) = min v ctrl ? 0.25v,1v ( ) 10 ? r is the v ctrl can be set by an external voltage reference or a resistor divider from v ref to ground. for 0.3v v ctrl 1.15v , the current sense threshold linearly goes up from 5mv to 90mv. for v ctrl 1.35v , the current sense threshold is constant at 100mv full scale value. for 1.15v v ctrl 1.35v , the current sense threshold smoothly transitions from the linear function of v ctrl to the 100mv constant value. tie ctrl to v ref for the 100mv full scale threshold. force the pin below 0.3v to stop switching. isp: positive terminal of the isp/isn current sense re - sistor (r is ). ensure accurate current sense with kelvin connection. isn: negative terminal of the isp/isn current sense resistor (r is ). ensure accurate current sense with kelvin connection. ismon: isp/isn current sense monitor output. the ismon pin generates a voltage that is equal to ten times v (isp-isn) plus 0.25v offset voltage. for parallel applications, tie the master lt8390 a ismon pin to the slave lt8390a ctrl pin. pgood: power good open drain output. the pgood pin is pulled low when the fb pin is within 10% of the final regulation voltage. to function, the pin requires an external pull-up resistor. ss: soft-start timer setting. the ss pin is used to set soft-start timer by connecting a capacitor to ground. an internal 12.5a pull-up current charging the external ss capacitor gradually ramps up fb regulation voltage. a 22nf capacitor is recommended on this pin. any uvlo or thermal shutdown immediately pulls ss pin to ground and stops switching. using a single resistor from ss to v ref , the lt8390 a can be set in three different fault protection modes during output short-circuit condition : hiccup (no resistor), latch-off ( 499k ), and keep-running (100k). see more details in the application information section. fb: voltage loop feedback input. the fb pin is used for constant-voltage regulation and output fault protection. the internal error amplifier with its output v c regulates v fb to 1.00v through the dc/dc converter. during output pin functions short-circuit (v fb < 0.25v ) condition, the part gets into one fault mode per customer setting. during an overvoltage (v fb > 1.1v ) condition, the part turns off all tg1, bg1, tg2, bg2, and loadtg. v c : error amplifier output to set inductor current com - parator threshold. the v c pin is used to compensate the control loop with an external rc network. during loaden low state, the v c pin is disconnected from all internal loads to store its voltage information. rt : switching frequency setting. connect a resistor from this pin to ground to set the internal oscillator frequency from 600khz to 2mhz. sync/sprd: switching frequency synchronization or spread spectrum. ground this pin for switching at inter - nal oscillator frequency. apply a clock signal for external frequency synchronization. tie to int v cc for 25% triangle spread spectrum above internal oscillator frequency. loadtg: high side pmos load switch top gate drive. a buffered and inverted version of the loaden input signal, the loadtg pin drives an external high side pmos load switch with a voltage swing from the higher voltage of (v out - 5v) and 1.2v to v out . leave this pin unconnected if not used. v out : output supply. the v out pin must be tied to the power output to determine the buck, buck-boost, or boost operation regions. the v out pin also serves as positive rail for the loadtg drive. locally bypass this pin to ground with a minimum 1f ceramic capacitor. tg2: boost side top gate drive. drives the gate of boost side top n-channel mosfet with a voltage swing from sw2 to bst2. sw2: boost side switch node. the sw2 pin swings from a schottky diode voltage drop below ground to v out . bst2: boost side bootstrap floating driver supply. the bst2 pin has an integrated bootstrap schottky diode from the intv cc pin and requires an external bootstrap capacitor to the sw2 pin. the bst2 pin swings from a diode voltage drop below intv cc to (v out + intv cc ). bg2: boost side bottom gate drive. drives the gate of boost side bottom n-channel mosfet with a voltage swing from ground to intv cc . gnd (exposed pad): ground. solder the exposed pad directly to the ground plane. lt8390a 8390afa
11 for more information www.linear.com/lt8390a block diagram + ? + ? ? + + ea2 + ? + ? + ? ? + + ? + ? + + ? ea1 + ? a2=10 a1 a3 5v ldo 2v ref intv cc v ref rt sync/sprd ctrl 0.3v fbov isoc fb osc v os 1.1v v isp-isn 0.75v peak_boost load on v out /bst2 v in /bst1 ismon loaden ss gnd isn 8390a bd isp 0.25v ctrl 1.25v 1v fb bst2 tg2 sw2 bg2 bg1 sw1 tg1 bst1 v c v is load on 1.25a 12.5a 10a 0.25v fb inhibit switch loadtg pgood test v out load on v ref v out ?5v en/uvlo 1.220v 2.5a v in lsn lsp + a4 intv cc intv cc intv cc fault logic short intv cc load on peak_buck + ? + ? 1.1v 0.9v fb fb 1x v is boost logic buck logic charge control lt8390a 8390afa
12 for more information www.linear.com/lt8390a operation the lt8390 a is a current mode dc/dc controller that can regulate output voltage, input or output current from input voltage above, below, or equal to the output voltage. the ltc proprietary peak-buck peak-boost current mode control scheme uses a single inductor current sense resis - tor and provides smooth transition between buck region, buck-boost region, and boost region. its operation is best understood by referring to the block diagram. power switch control figure 1 shows a simplified diagram of how the four power switches a, b, c, and d are connected to the inductor l, the current sense resistor r sense , power input v in , power output v out , and ground. the current sense resistor r sense connected to the lsp and lsn pins provides inductor current information for both peak current mode control and reverse current detection in buck region, buck-boost region, and boost region. figure 2 shows the current mode control as a function of v in /v out ratio and figure 3 shows the operation region as a function of v in /v out ratio. the power switches are properly controlled to smoothly transi - tion between modes and regions. hysteresis is added to prevent chattering between modes and regions. there are total four states : (1) peak-buck current mode control in buck region, (2) peak-buck current mode con - trol in buck-boost region, (3) peak-boost current mode control in buck-boost region, and (4) peak-boost current mode control in boost region. the following sections give detailed description for each state with waveforms, in which the shoot-through protection dead time between switches a and b, between switches c and d are ignored for simplification. figure 1. simplified diagram of the power switches figure 2. current mode vs v in /v out ratio figure 3. operation region vs v in /v out ratio v out d a sw1 sw2 tg2 bg2 8390a f01 tg1 bg1 b c l v in r sense peak-buck peak-boost v in /v out 0.98 1.00 1.02 8390a f02 buck (1) (2) (2) (3) boost buck-boost v in /v out 0.850.75 1.00 1.25 1.33 8390a f03 (4) lt8390a 8390afa
13 for more information www.linear.com/lt8390a operation (1) peak-buck in buck region (v in >> v out ) when v in is much higher than v out , the lt8390a uses peak-buck current mode control in buck region (figure 4). switch c is always off and switch d is always on. at the beginning of every cycle, switch a is turned on and the inductor current ramps up. when the inductor cur - rent hits the peak buck current threshold commanded by v c voltage at buck current comparator a3 during (a+d) phase, switch a is turned off and switch b is turned on for the rest of the cycle. switches a and b will alternate, behaving like a typical synchronous buck regulator. figure 4. peak-buck in buck region (v in >> v out ) figure 5. peak-buck in buck-boost region (v in ~> v out ) 100% off 100% on a b c d i l a+d a+d b+d b+d 8390a f04 (2) peak-buck in buck-boost region (v in ~> v out ) when v in is slightly higher than v out , the lt8390a uses peak-buck current mode control in buck-boost region (figure 5). switch c is always turned on for the beginning 20% cycle and switch d is always turned on for the remain - ing 80% cycle. at the beginning of every cycle, switches a and c are turned on and the inductor current ramps up. after 20% cycle, switch c is turned off and switch d is turned on, and the inductor keeps ramping up. when the inductor current hits the peak buck current threshold commanded by v c voltage at buck current comparator a3 during (a+d) phase, switch a is turned off and switch b is turned on for the rest of the cycle. a b c 20% 80% 80% 20% d i l a+d a+c b+d a+d a+c b+d 8390a f05 lt8390a 8390afa
14 for more information www.linear.com/lt8390a (3) peak-boost in buck-boost region (v in <~ v out ) when v in is slightly lower than v out , the lt8390a uses peak-boost current mode control in buck-boost region (figure 6). switch a is always turned on for the begin - ning 80% cycle and switch b is always turned on for the remaining 20% cycle. at the beginning of every cycle, switches a and c are turned on and the inductor current ramps up. when the inductor current hits the peak boost current threshold commanded by v c voltage at boost current comparator a4 during (a+c) phase, switch c is turned off and switch d is turned on for the rest of the cycle. after 80% cycle, switch a is turned off and switch b is turned on for the rest of the cycle. operation figure 6. peak-boost in buck-boost region (v in <~ v out ) figure 7. peak-boost in boost region (v in << v out ) a b c 20% 80% 80% 20% d i l a+d a+c b+d a+d a+c b+d 8390a f06 (4) peak-boost in boost region (v in << v out ) when v in is much lower than v out , the lt8390a uses peak-boost current mode control in boost region (figure 7). switch a is always on and switch b is always off. at the beginning of every cycle, switch c is turned on and the inductor current ramps up. when the inductor current hits the peak boost current threshold commanded by v c volt- age at boost current comparator a4 during (a+c) phase, switch c is turned off and switch d is turned on for the rest of the cycle. switches c and d will alternate, behaving like a typical synchronous boost regulator. a b c 100% on 100% off d i l a+d a+c a+d a+c 8390a f07 lt8390a 8390afa
15 for more information www.linear.com/lt8390a operation main control loop the lt8390 a is a fixed frequency current mode control- ler. the inductor current is sensed through the inductor sense resistor between the lsp and lsn pins. the current sense voltage is gained up by amplifier a1 and added to a slope compensation ramp signal from the internal os - cillator. the summing signal is then fed into the positive terminals of the buck current comparator a3 and boost current comparator a4. the negative terminals of a3 and a4 are controlled by the voltage on the v c pin, which is the diode-or of error amplifiers ea1 and ea2. depending on the state of the peak-buck peak-boost cur - rent mode control, either the buck logic or the boost logic is controlling the four power switches so that either the fb voltage is regulated to 1v or the current sense voltage between the isp and isn pins is regulated by the ctrl pin during normal operation. the gains of ea1 and ea2 have been balanced to ensure smooth transition between constant-voltage and constant-current operation with the same compensation network. light load current operation at light load, the lt8390a runs either at full switching fre - quency discontinuous conduction mode or pulse-skipping mode, where the switches are held off for multiple cycles (i.e., skipping pulses) to maintain the regulation and improve the efficiency. both the buck and boost reverse current sense thresholds are set to 1mv (typical) so that no reverse inductor current is allowed. such no reverse inductor current from the output to the input is highly desired in certain applications. in the buck region, switch b is turned off whenever the buck reverse current threshold is triggered during (b+d) phase. in the boost region, switch d is turned off whenever the boost reverse current threshold is triggered during (a+d) phase. in the buck-boost region, switch d is turned off whenever the boost reverse current threshold is trig - gered during (a+d) phase, and both switches b and d are turned off whenever the buck reverse current threshold is triggered during (b+d) phase. internal charge path each of the two top mosfet drivers is biased from its floating bootstrap capacitor , which is normally re-charged by int v cc through both the external and internal boot - strap diodes when the top mosfet is turned off. when the lt8390 a operates exclusively in the buck or boost regions, one of the top mosfet s is constantly on. an internal charge path, from v out and bst2 to bst1 or from v in and bst1 to bst2, charges the bootstrap capacitor to 4.6v so that the top mosfet can be kept on. shutdown and power-on-reset the lt8390 a enters shutdown mode and drains less than 2a quiescent current when the en/uvlo pin is below its shutdown threshold (0.3v minimum). once the en/uvlo pin is above its shutdown threshold (1v maximum), the lt8390 a wakes up startup circuitry, generates bandgap reference, and powers up the internal intv cc ldo. the intv cc ldo supplies the internal control circuitry and gate drivers. now the lt8390 a enters undervoltage lockout (uvlo) mode with a hysteresis current (2.5a typical) pulled into the en/uvlo pin. when the intv cc pin is charged above its rising uvlo threshold (3.78v typi - cal), the en/uvlo pin passes its rising enable threshold ( 1.233v typical), and the junction temperature is less than its thermal shutdown (165c typical), the lt8390a enters enable mode, in which the en/uvlo hysteresis current is turned off and the voltage reference v ref is being charged up from ground. from the time of entering enable mode to the time of v ref passing its rising uvlo threshold (1.89v typical), the lt8390 a is going through a power-on-reset (por), waking up the entire internal control circuitry and settling to the right initial conditions. after the por, the lt8390a is ready and waiting for the signals on the ctrl and loaden pins to start switching. lt8390a 8390afa
16 for more information www.linear.com/lt8390a operation start-up and fault protection figure 8 shows the start-up and fault sequence for the lt8390a. during the por state, the ss pin is hard pulled down with a 100 to ground. in a pre-biased condition, the ss pin has to be pulled below 0.2v to enter the init state, where the lt8390a wait 10s so that the ss pin can be fully discharged to ground. after the 10s, the lt8390a enters the up/pre state when the loadon signal goes high. the loadon high signal happens when ctrl pin is above its rising latch-off thresholds (0.325v typical) and the loaden is high. during the up/pre state, the ss pin is charged up by a 12.5a pull-up current while the switching is disabled and the loadtg is turned off. once the ss pin is charged figure 8. start-up and fault sequence above 0.25v , the lt8390 a enters the up/try state, where the loadtg is turned on first while the switching is still disabled. if an excessive current flowing through the current sense resistor triggers the isp/isn over current (isoc) signal, it will reset the lt8390a back into the por state. after 10s in the up/try state without triggering the isoc signal, the lt8390a enters the up/run state. during the up/run state, the switching is enabled and the start-up of the output voltage v out is controlled by the voltage on the ss pin. when the ss pin voltage is less than 1v , the lt8390a regulates the fb pin voltage to the ss pin voltage instead of the 1v reference. this allows the ss pin to be used to program soft-start by connecting an external capacitor from the ss pin to gnd. the internal 12.5a pull-up current charges up the capacitor, creating a voltage ramp on the ss pin. as the ss pin voltage rises linearly from 0.25v to 1v (and beyond), the output voltage v out rises smoothly to its final regulation voltage. once the ss pin is charged above 1.75v, the lt8390a enters the ok/run state, where the output short detec - tion is activated. the output short means v fb < 0.25v. when the output short happens, the lt8390a enters the fault/run state, where a 1.25a pull-down current slowly discharges the ss pin with the other conditions the same as the ok/run state. once the ss pin is discharged below 1.7v , the lt8390a enters the down/stop state, where the switching is disabled and the short detection is deactivated with the previous fault latched. once the ss pin is discharged below 0.2v and the loadon signal is still high, the lt8390a goes back to the up/run state. in an output short condition, the lt8390a can be set to hiccup, latch-off, or keep-running fault protection mode with a resistor between the ss and v ref pins. without any resistor, the lt8390a will hiccup between 0.2v and 1.75v and go around the up/run, ok/run, fault/run, and down/stop states until the fault condition is cleared. with a 499k resistor, the lt8390a will latch off until the en/uvlo is toggled. with a 100k resistor, the lt8390a will keep running regardless of the fault. por ss hard pull down switching disabled loadtg turned off no short detection init ss hard pull down switching disabled loadtg turned off no short detection por = hi or isoc = hi ss < 0.2v up/try ss 12.5a pull up switching disabled loadtg turned on no short detection up/pre ss 12.5a pull up switching disabled loadtg turned off no short detection wait 10s and load on = hi ss > 0.25v up/run ss 12.5a pull up switching enabled loadtg turned on no short detection ok/run ss 12.5a pull up switching enabled loadtg turned on short detection wait 10s ss > 1.75v down/stop ss 1.25a pull down switching disabled loadtg turned on no short detection fault/run ss 1.25a pull down switching enabled loadtg turned on short detection ss < 0.2v and load on = hi short ss < 1.7v 8390a f08 lt8390a 8390afa
17 for more information www.linear.com/lt8390a applications information the front page shows a typical lt8390 a application circuit. this applications information section serves as a guideline of selecting external components for typical applications. the examples and equations in this section assume con - tinuous conduction mode unless otherwise specified. switching frequency selection the lt8390 a uses a constant frequency control scheme between 600khz and 2mhz. selection of the switching frequency is a tradeoff between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switching losses, but requires larger inductor and capacitor values. for high power applica - tions, consider operating at lower frequencies to minimize mosfet heating from switching losses. for low power applications, consider operating at higher frequencies to minimize the total solution size. in addi tion, the specific application also plays an important role in switching frequency selection. in a noise-sensitive system, the switching frequency is usually selected to keep the switching noise out of a sensitive frequency band. switching frequency setting the switching frequency of the lt8390a can be set by the internal oscillator. with the sync/sprd pin pulled to ground, the switching frequency is set by a resistor from the rt pin to ground. table 1 shows r t resistor values for common switching frequencies. table 1. switching frequency vs r t value (1% resistor) f osc (mhz) r t (k) 0.6 267 0.8 191 1.0 147 1.2 118 1.4 97.6 1.6 82.5 1.8 66.5 2.0 59.0 spread spectrum frequency modulation switching regulators can be particularly troublesome for applications where electromagnetic interference (emi) is a concern. to improve the emi performance, the lt8390a implements a triangle spread spectrum frequency modu - lation scheme. with the sync/sprd pin tied to intv cc , the lt8390 a starts to spread its switching frequency 25% above the internal oscillator frequency. figure 9 and figure 10 show the noise spectrum of the front page application when spread spectrum enabled. figure 9. average conducted emi figure 10. peak conducted emi frequency (mhz) 80 90 70 60 50 40 emi (dbv) 30 20 10 0 ?10 0.1 1 10 8390a f09 ssfm on with emi filter noise floor cisper 25 class 5 peak limits lw mw sw cb frequency (mhz) 80 90 70 60 50 40 emi (dbv) 30 20 10 0 ?10 0.1 1 10 8390a f10 ssfm on with emi filter noise floor cisper 25 class 5 peak limits lw mw sw cb frequency synchronization the lt8390 a switching frequency can be synchronized to an external clock using the sync/sprd pin. driving the sync/sprd with a 50% duty cycle waveform is always a good choice, otherwise maintain the duty cycle between 10% and 90%. due to the use of a phase-locked loop (pll) inside, there is no restriction between the synchronization frequency and the internal oscillator frequency. the rising edge of the synchronization clock represents the begin - ning of a switching cycle, turning on switches a and c, or switches a and d. lt8390a 8390afa
18 for more information www.linear.com/lt8390a applications information inductor selection the switching frequency and inductor selection are inter - related in that higher switching frequencies allow the use of smaller inductor and capacitor values. the inductor value has a direct effect on ripple current. the highest current ripple ?i l % happens in the buck region at v in(max) , and the lowest current ripple ?i l % happens in the boost region at v in(min) . for any given ripple allowance set by customers, the minimum inductance can be calculated as: l buck > v out ? v in(max) ? v out ( ) f ?i out(max) ? ? i l % ? v in(max) l boost > v in(min) 2 ? v out ? v in(min) ( ) f ?i out(max) ? ? i l % ? v out 2 where: ? i l % = ? i l i l(avg) f is switching frequency v in(min) is minimum input voltage v in(max) is maximum input voltage v out is output voltage i out(max) is maximum output current slope compensation provides stability in constant fre - quency current mode control by preventing subharmonic oscillations at certain duty cycles. the minimum inductance required for stability when duty cycles are larger than 50% can be calculated as: l > 10 ? v out ? r sense f for high efficiency, choose an inductor with low core loss, such as ferrite. also, the inductor should have low dc resistance to reduce the i 2 r losses, and must be able to handle the peak inductor current without saturating. to minimize radiated noise, use a shielded inductor. r sense selection and maximum output current r sense is chosen based on the required output current. the duty cycle independent maximum current sense thresholds (50mv in peak-buck and 50mv in peak-boost) set the maximum inductor peak current in buck region, buck-boost region, and boost region. in boost region, the lowest maximum average load current happens at v in(min) and can be calculated as: i out(max _ boost) = 50mv r sense ? ? i l(boost) 2 ? ? ? ? ? ? ? v in(min) v out where ?i l(boost) is peak-to-peak inductor ripple current in boost region and can be calculated as: ? i l(boost) = v in(min) ? v out ? v in(min) ( ) f ? l ? v out in buck region, the lowest maximum average load current happens at v in(max) and can be calculated as: i out(max _ buck) = 50mv r sense ? ? i l(buck) 2 ? ? ? ? ? ? where ?i l(buck) is peak-to-peak inductor ripple current in buck region and can be calculated as: ? i l(buck) = v out ? v in(max) ? v out ( ) f ? l ? v in(max) the maximum current sense r sense in boost region is: r sense(boost) = 2 ? 50mv ? v in(min) 2 ?i out(max) ? v out + ? i l(boost) ? v in(min) the maximum current sense r sense in buck region is r sense(buck) = 2 ? 50mv 2 ?i out(max) + ? i l(buck) the final r sense value should be lower than the calculated r sense in both buck and boost regions. a 20% to 30% margin is usually recommended. always choose a low esl current sense resistor. lt8390a 8390afa
19 for more information www.linear.com/lt8390a applications information power mosfet selection the lt8390 a requires four external n-channel power mos - fets, two for the top switches (switches a and d shown in figure 1) and two for the bottom switches (switches b and c shown in figure 1). important parameters for the power mosfet s are the breakdown voltage v br(dss) , threshold voltage v gs(th) , on-resistance r ds(on) , reverse transfer capacitance c rss and maximum current i ds(max) . to achieve 2mhz operation, the power mosfet selection is critical. with typical 25ns shoot-through protection deadtime, high performance power mosfets with low q g and low r ds(on) must be used. since the gate drive voltage is set by the 5v intv cc supply, logic-level threshold mosfets must be used in lt8390a applications. switching four mosfets at higher frequency like 2mhz , the substantial gate charge current from intv cc can be estimated as: i intvcc = f ? q ga + q gb + q gc + q gd ( ) where: f is the switching frequency q ga , q gb , q gc , q gd are the total gate charges of mosfets a, b, c, d make sure the total required intv cc current not exceed - ing the intv cc current limit in the datasheet. typically, mosfets with less than 10nc q g are recommended. the lt8390 a uses the v in /v out ratio to transition between modes and regions. bigger ir drop in the power path caused by improper mosfet and inductor selection may prevent the lt8390 a from smooth transition. to ensure smooth transitions between buck, buck-boost, and boost modes of operation, choose low r ds(on) mosfets and low dcr inductor to satisfy: i out(max) 0.025? v out r a,b + r c,d + r sense + r l where: r a,b is the maximum r ds(on) of mosfets a or b at 25 c r c,d is the maximum r ds(on) of mosfets c or d at 25 c figure 11. normalized r ds(on) vs temperature r l is the maximum dcr resistor of inductor at 25 c the r ds(on) and dcr increase at higher junction temperatures and the process variation have been included in the calculation above. in order to select the power mosfets, the power dis - sipated by the device must be known. for switch a, the m a ximum power dissipation happens in boost region, when it remains on all the time. its maximum power dissipation at maximum output current is given by: p a(boost) = i out(max) ? v out v in ? ? ? ? ? ? 2 ? t ? r ds(on) where t is a normalization factor (unity at 25c) ac- counting for the significant variation in on-resistance with temperature, typically 0.4%/c as shown in figure 11. for a maximum junction temperature of 125c, using a value of t = 1.5 is reasonable. switch b operates in buck region as the synchronous rectifier. its power dissipation at maximum output cur- rent is given by: p b(buck) = v in ? v out v in ?i out(max) 2 ? t ? r ds(on) switch c operates in boost region as the control switch. its power dissipation at maximum current is given by: p c(boost) = v out ? v in ( ) ? v out v in 2 ?i out(max) 2 ? t ? r ds(on) + k ? v out 3 ? i out(max) v in ? c rss ? f junction temperature (c) ?50 t normalized on-resistance () 1.0 1.5 150 8390a f11 0.5 0 0 50 100 2.0 lt8390a 8390afa
20 for more information www.linear.com/lt8390a applications information where c rss is usually specified by the mosfet manufac - turers. the constant k, which accounts for the loss caused by reverse recover y current, is inversely proportional to the gate drive current and has an empirical value of 1.7. for switch d, the maximum power dissipation happens in boost region, when its duty cycle is higher than 50%. its maximum power dissipation at maximum output current is given by: p d(boost) = v out v in ?i out(max) 2 ? t ? r ds(on) for the same output voltage and current, switch a has the highest power dissipation and switch b has the lowest power dissipation unless a short occurs at the output. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following formula: t j = t a + p ? r th(ja) the junction-to-ambient thermal resistance r th(ja) in- cludes the junction-to-case thermal resistance r th(jc) and the case-to-ambient thermal resistance r th(ca) . this value of t j can then be compared to the original, assumed value used in the iterative calculation process. optional schottky diode (d b , d d ) selection the optional schottky diodes d b (in parallel with switch b) and d d (in parallel with switch d) conduct during the dead time between the conduction of the power mosfet switches. they are intended to prevent the body diode of synchronous switches b and d from turning on and storing charge during the dead time. in particular, d b significantly reduces reverse recovery current between switch b turn- off and switch a turn-on, and d d significantly reduces reverse recovery current between switch d turn-off and switch c turn-on. they improve converter efficiency and reduce switch voltage stress. in order for the diode to be effective, the inductance between it and the synchronous switch must be as small as possible, mandating that these components be placed adjacently. c in and c out selection input and output capacitance is necessary to suppress voltage ripple caused by discontinuous current moving in and out the regulator. a parallel combination of capaci - tors is typically used to achieve high capacitance and low equivalent series resistance (esr). dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. capacitors with low esr and high ripple current ratings, such as os-con and poscap are also available. ceramic capacitors should be placed near the regula-tor input and output to suppress high frequency switching spikes. ceramic capacitors, of at least 1f , should also be placed from v in to gnd and v out to gnd as close to the lt8390 a pins as possible. due to their excellent low esr characteristics, ceramic capacitors can significantly reduce input ripple voltage and help reduce power loss in the higher esr bulk capacitors. x5r or x7r dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. many ceramic ca - pacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage. input capacitance c in : discontinuous input current is highest in the buck region due to the switch a toggling on and off. make sure that the c in capacitor network has low enough esr and is sized to handle the maximum rms current. in buck region, the input rms current is given by: i rms i out(max) ? v out v in ? v in v out ? 1 the formula has a maximum at v in = 2v out , where i rms = i out(max) /2. this simple worst-case condition is com - monly used for design because even significant deviations do not offer much relief. output capacitance c out : discontinuous current shifts from the input to the output in the boost region. make sure that the c out capacitor network is capable of reducing the output voltage ripple. the effects of esr and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. the maximum steady state ripple due to charging and discharging the bulk capacitance is given by: lt8390a 8390afa
21 for more information www.linear.com/lt8390a applications information ? v cap(boost) = i out(max) ? v out ? v in(min) ( ) c out ? v out ? f ? v cap(buck) = v out ? 1 ? v out v in(max) ? ? ? ? ? ? ? ? 8 ? l ? f 2 ? c out the maximum steady ripple due to the voltage drop across the esr is given by: ? v esr(boost) = v out ?i out(max) v in(min) ? esr ? v esr(buck) = v out ? 1 ? v out v in(max) ? ? ? ? ? ? ? ? l ? f ? esr intv cc regulator an internal p-channel low dropout regulator produces 5v at the intv cc pin from the v in supply pin. the intv cc powers internal circuitry and gate drivers in the lt8390a. the intv cc regulator can supply a peak current of 145ma and must be bypassed to ground with a minimum of 4.7f ceramic capacitor. good local bypass is necessary to supply the high transient current required by mosfet gate drivers. higher input voltage applications with large mosfets be - ing driven at higher switching frequencies may cause the maximum junction temperature rating for the lt8390a to be exceeded. the system supply current is normally dominated by the gate charge current. additional external loading of the int v cc also needs to be taken into account for the power dissipation calculation. the total lt8390a power dissipation in this case is v in ? i intvcc , and overall efficiency is lowered. the junction temperature can be estimated by using the equation: t j = t a + p d ? ja where ja (in c/w) is the package thermal resistance. to prevent maximum junction temperature from being exceeded, the input supply current must be checked op - erating in continuous mode at maximum v in . figure 12. v in undervoltage lockout (uvlo) top gate mosfet driver supply (c bst1 , c bst2 ) the top mosfet drivers, tg1 and tg2, are driven between their respective sw and bst pin voltages. the boost volt - ages are biased from floating bootstrap capacitors c bst1 and c bst2 , which are normally recharged through both the external and internal bootstrap diodes when the respective top mosfet is turned off. external bootstrap diodes are recommended because the internal bootstrap diodes are not always strong enough to refresh top mosfets at 2mhz . both capacitors are charged to the same voltage as the intv cc voltage. the bootstrap capacitors c bst1 and c bst2 , need to store about 100 times the gate charge required by the top switches a and d. in most applications, a 0.1f to 0.47f, x5r or x7r dielectric capacitor is adequate. programming v in uvlo a resistor divider from v in to the en/uvlo pin implements v in undervoltage lockout (uvlo). the en/uvlo enable falling threshold is set at 1.220v with 13mv hysteresis. in addition, the en/uvlo pin sinks 2.5a when the voltage on the pin is below 1.220v. this current provides user programmable hysteresis based on the value of r1. the programmable uvlo thresholds are: v in(uvlo + ) = 1.233v ? r1 + r2 r2 + 2.5a ? r1 v in(uvlo ? ) = 1.220v ? r1 + r2 r2 figure 12 shows the implementation of external shut-down control while still using the uvlo function. the nmos grounds the en/uvlo pin when turned on, and puts the lt8390 a in shutdown with quiescent current less than 2a . lt8390a v in r1 r2 run/stop control (optional) 8390a f12 en/uvlo gnd lt8390a 8390afa
22 for more information www.linear.com/lt8390a applications information programming input or output current limit the input or output current limit can be programmed by placing an appropriate value current sense resistor, r is , in the input or output power path. the voltage drop across r is is (kelvin) sensed by the isp and isn pins. the ctrl pin should be tied to a voltage higher than 1.35v to get the full-scale 100mv (typical) threshold across the sense resistor. the ctrl pin can be used to reduce the current threshold to zero, although relative accuracy decreases with the decreasing sense threshold. when the ctrl pin voltage is between 0.3v and 1.15v, the current limit is: i is(max) = v ctrl ? 0.25v 10 ? r is when v ctrl is between 1.15v and 1.35v the current limit varies with v ctrl , but departs from the equation above by an increasing amount as v ctrl increases. ultimately, when v ctrl is larger than 1.35v, the current limit no longer varies. the typical v (isp-isn) threshold vs v ctrl is listed in table 2. table 2. v (isp-isn) threshold vs v ctrl v ctrl (v) v (isp-isn) (mv) 1.15 90 1.20 94.5 1.25 98 1.30 99.5 1.35 100 when v ctrl is larger than 1.35v, the current threshold is regulated to: i is(max) = 100mv r is the ctrl pin should not be left open (tie to v ref if not used). the ctrl pin can also be used in conjunction with a thermistor to provide overtemperature protection for the output load, or with a resistor divider to v in to reduce output power and switching current when v in is low. the presence of a time varying differential voltage ripple signal across the isp and isn pins at the switching figure 13. programming input current limit lt8390a isp 8390a f13a isn r is + to drain of switch a from power input lt8390a isp 8390a f13b isn r is c f r f + to drain of switch a from power input r f (13a) (13b) frequency is expected. if the current sense resistor r is is placed between power input and input bulk capacitor (figure 13a ), or between output bulk capacitor and system output (figure 14a ), a filter is typically not necessary. if the r is is placed between input bulk capacitor and input decoupling capacitor (figure 13b), or between output decoupling capacitor and output bulk capacitor (figure 14b), a low pass filter formed by r f and c f is recom- mended to reduce the current ripple and stabilize the current loop. since the bias currents of the isp and isn pins are matched, no offset is introduced by r f . if input or output current limit is not used, the isp and isn pins should be shorted to v in , v out , or ground. ismon current monitor the ismon pin provides a buffered monitor output of the current flowing through the isp/isn current sense resistor, r is . the v ismon voltage is calculated as v (isp-isn) ? 10 + 0.25v . since the ismon pin has the same 0.25v offset as the ctrl pin, the master lt8390a ismon pin can be directly tied to the slave lt8390a ctrl pin for equal current sharing in parallel applications. lt8390a 8390afa
23 for more information www.linear.com/lt8390a figure 14. programming output current limit lt8390a isp 8390a f14a isn r is + to system output from drain of switch d lt8390a isp 8390a f14b isn r is c f r f to system output + from drain of switch d r f (14a) (14b) applications information load switch control the loaden and loadtg pins provide high side pmos load switch control. the loaden pin accepts a logic level on/off signal and then drives the loadtg pin to turn on or off the high side pmos load switch, thereby connect - ing or disconnecting the lt8390a power output from the system output. when the loaden pin is forced low, the lt8390a turns off tg1 and tg2, turns on bg1 and bg2, disconnects the v c pin from all internal loads, and turns off loadtg. the loaden pin should not be left open (tie to intv cc or v ref if not used). high side pmos load switch selection a high side pmos load switch is recommended in some lt8390a applications requiring load switch control. the high side pmos load switch is typically selected for drain- source voltage v ds , gate-source threshold voltage v gs(th) , and continuous drain current i d . for proper operations, v ds rating should exceed the output regulation voltage set by the fb pin, the absolute value of v gs(th) should be less than 3v, and i d rating should be above i out(max) . programming output voltage and thresholds the lt8390 a has a voltage feedback pin fb that can be used to program a constant-voltage output. the output voltage can be set by selecting the values of r3 and r4 (figure 15) according to the following equation: v out = 1v ? r3 + r4 r4 in addition, the fb pin also sets output overvoltage threshold, output power good thresholds, and output short threshold. for an application with small output capacitors, the output voltage may overshoot a lot during lt8390a v out r3 r4 8390a f15 fb figure 15. feedback resistor connection load transient event. once the fb pin hits its overvoltage threshold 1.1v , the lt8390 a stops switching by turning off tg1, bg1, tg2, and bg2, and also turns off loadtg to disconnect the output load for protection. the output overvoltage threshold can be set as: v out(ovp) = 1.1v ? r3 + r4 r4 to provide the output short-circuit detection and protection, the output short falling threshold can be set as: v out(short) = 0.25v ? r3 + r4 r4 power good ( pgood) pin the lt8390 a provides an open-drain status pin, pgood, which is pulled low when v fb is within 10% of the 1.00v regulation voltage. the pgood pin is allowed to be pulled up by an external resistor to intv cc or an external voltage source of up to 6v. lt8390a 8390afa
24 for more information www.linear.com/lt8390a applications information soft-start and short-circuit protection as shown in figure 8 and explained in the operation sec - tion, the ss pin can be used to program the output voltage soft-start by connecting an external capacitor from the ss pin to ground. the internal 12.5a pull-up current charges up the capacitor, creating a voltage ramp on the ss pin. as the ss pin voltage rises linearly from 0.25v to 1v (and beyond), the output voltage rises smoothly into its final voltage regulation. the soft-start time can be calculated as: t ss = 1v ? c ss 12.5a make sure the c ss is at least five to ten times larger than the compensation capacitor on the v c pin for a well-controlled output voltage soft-start. a 22nf ceramic capacitor is a good starting point. the ss pin is also used as a fault timer. once an output short-circuit fault is detected, a 1.25a pull-down current source is activated. using a single resistor from the ss pin to the v ref pin, the lt8390 a can be set to three different fault protection modes: hiccup (no resistor), latch-off (499k), and keep-running (100k). with a 100k resistor in keep-running mode, the lt8390a continues switching normally and regulates the current into ground. with a 499k resistor in latch-off mode, the lt8390a stops switching until the en/uvlo pin is pulled low and high to restart. with no resistor in hiccup mode, the lt8390 a enters low duty cycle auto-retry operation. the 1.25a pull-down current discharges the ss pin to 0.2v and then 12.5a pull-up current charges the ss pin up. if the output short-circuit condition has not been removed when the ss pin reaches 1.75v, the 1.25a pull-down current turns on again, initiating a new hiccup cycle. this will continue until the fault is removed. once the output short-circuit condition is removed, the output will have a smooth short-circuit recovery due to soft-start. loop compensation the lt8390 a uses an internal transconductance error amplifier, the output of which, v c , compensates the con- trol loop. the external inductor, output capacitor, and the compensation resistor and capacitor determine the loop stability . the inductor and output capacitor are chosen based on per formance, size and cost. the compensation resistor and capacitor on the v c pin are set to optimize control loop response and stability. for a typical voltage regulator application, a 2.2nf compensation capacitor on the v c pin is adequate, and a series resistor should always be used to increase the slew rate on the v c pin to maintain tighter output voltage regulation during fast transients on the input supply of the converter. efficiency considerations the power efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. although all dissipative elements in circuits produce losses, four main sources account for most of the losses in lt8390a circuits: 1. dc i 2 r losses. these arise from the resistances of the mosfets, sensing resistor, inductor and pc board traces and cause the efficiency to drop at high output currents. 2. transition loss. this loss arises from the brief amount of time switch a or switch c spends in the saturated region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capacitance, among other factors. 3. int v cc current. this is the sum of the mosfet driver and control currents. 4. c in and c out loss. the input capacitor has the dif - ficult job of filtering the large rms input current to the regulator in buck region. the output capacitor has the difficult job of filtering the large rms output current in boost region. both c in and c out are required to have low esr to minimize the ac i 2 r loss and sufficient capacitance to prevent the rms current from causing additional upstream losses in fuses or batteries. lt8390a 8390afa
25 for more information www.linear.com/lt8390a applications information 5. other losses. schottky diode d b and d d are responsible for conduction losses during dead time and light load conduction periods. inductor core loss occurs predomi - nately at light loads. switch a causes reverse recovery current loss in buck region, and switch c causes reverse recover y current loss in boost region. when making adjustments to improve efficiency, the input current is the best indicator of changes in ef - ficiency . if you make a change and the input current decreases, then the efficiency has increased. if there is no change in the input current, then there is no change in efficiency. pc board layout checklist the basic pc board layout requires a dedicated ground plane layer. also, for high current, a multilayer board provides heat sinking for power components. n the ground plane layer should not have any traces and it should be as close as possible to the layer with power mosfets. n place c in , switch a, switch b and d b in one compact area. place c out , switch c, switch d and d d in one compact area. n use immediate vias to connect the components to the ground plane. use several large vias for each power component. n use planes for v in and v out to maintain good voltage filtering and to keep power losses low. n flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. connect the copper areas to any dc net (v in or gnd). n separate the signal and power grounds. all small-signal components should return to the exposed gnd pad from the bottom, which is then tied to the power gnd close to the sour ces of switch b and switch c. n place switch a and switch c as close to the controller as possible, keeping the pgnd, bg and sw traces short. n keep the high dv/dt sw1, sw2, bst1, bst2, t g1 and tg2 nodes away from sensitive small-signal nodes. n the path formed by switch a, switch b, d b and the c in capacitor should have short leads and pcb trace lengths. the path formed by switch c, switch d, d d and the c out capacitor also should have short leads and pcb trace lengths. n the output capacitor ( C ) terminals should be connected as close as possible to the ( C) terminals of the input capacitor. n connect the top driver bootstrap capacitor c bst1 closely to the bst1 and sw1 pins. connect the top driver bootstrap capacitor c bst2 closely to the bst2 and sw2 pins. n connect the input capacitors c in and output capacitors c out closely to the power mosfets. these capacitors carry the mosfet ac current. n route lsp and lsn traces together with minimum pcb trace spacing. avoid sense lines pass through noisy areas, such as switch nodes. the filter capacitor between lsp and lsn should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the r sense resistor. low esl sense resistor is recommended. n connect the v c pin compensation network close to the ic, between v c and the signal ground. the capacitor helps to filter the effects of pcb noise and output volt - age ripple voltage from the compensation loop. n connect the intv cc bypass capacitor, c intvcc , close to the ic, between the intv cc and the power ground. this capacitor carries the mosfet drivers current peaks. lt8390a 8390afa
26 for more information www.linear.com/lt8390a typical applications 95% efficient 48w (12v 4a) 2mhz buck-boost voltage regulator lt8390a 8390afa 0.47f 59.0k 2.2nf 10k 110k 10k 0.1f 133k 100k 0.1f 169k 1f 1f l1 1h m3 m4 m1 m2 1f 10 22nf 10 22f 22f 4.7f d1 d2 5m r1 10m r2 0.1f en/uvlo v ref ctrl pgood bg2 bst2 tg2 intv cc loaden fb 0.1f v out isp isn sync/sprd test v in 6v to 28v continuous 4v to 56v transient 2mhz 63v 100v 22f 2 16v 2 ismon pgood 16v v out 12v 4a lsp 383k lsn sw1 sw2 bst1 tg1 bg1 v in lt8390a loadtg ismon 4.7f ss v c rt gnd ssfm off ssfm on 16v 2 l1: wurth 74437336010 1h m1, m2: infineon bsz065no6ls5 100k m3, m4: infineon bsz033ne2ls5 d1, d2: nxp bat46wj r1: susumu krl3216d-m-r005-f-t5 100v 2 intv cc intv cc intv cc 8390a ta02a
27 for more information www.linear.com/lt8390a package description please refer to http://www.linear.com/product/lt8390a#packaging for the most recent package drawings. fe28 (eb) tssop rev l 0117 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 13 14 192022 21 151618 17 9.60 ? 9.80* (.378 ? .386) 4.75 (.187) 2.74 (.108) 28 27 26 2524 23 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.75 (.187) 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev l) exposed pad variation eb lt8390a 8390afa
28 for more information www.linear.com/lt8390a package description please refer to http://www.linear.com/product/lt8390a#packaging for the most recent package drawings. 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wghd-3). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0816 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev c) lt8390a 8390afa
29 for more information www.linear.com/lt8390a information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 09/17 added h-grade temperature option clarified block diagram clarified sense resistors descriptiion in route lsp and lsn traces bullet 2, 5 11 25 lt8390a 8390afa
30 for more information www.linear.com/lt8390a ? linear technology corporation 2017 lt 0917 rev a ? printed in usa www.linear.com/lt8390a related parts typical application part number description comments lt8390 60v synchronous 4-switch buck-boost controller with spread spectrum v in : 4v to 60v, v out : 0v to 60v, 1.5% voltage accuracy, 3% current accuracy, tssop-28 and 4mm 5mm qfn-28 lt8391 60v synchronous 4-switch buck-boost led controller with spread spectrum v in : 4v to 60v, v out : 0v to 60v, 1.5% voltage accuracy, 3% current accuracy, tssop-28 and 4mm 5mm qfn-28 lt8391a 60v synchronous 2mhz 4-switch buck-boost led controller with spread spectrum v in : 4v to 60v, v out : 0v to 60v, 1.5% voltage accuracy, 3% current accuracy, tssop-28 and 4mm 5mm qfn-28 lt3790 60v synchronous 4-switch buck-boost controller v in : 4.7v to 60v, v out : 1.2v to 60v, regulates v out , i out , i in , tssop-38 lt8705 80v v in and v out synchronous 4-switch buck-boost dc/dc controller v in : 2.8v to 80v, v out : 1.3v to 80v, regulates v out , i out , v in , i in , 5mm 7mm qfn-38 and modified tssop-38 for high voltage lt c ? 3789 high efficiency synchronous 4-switch buck-boost controller v in : 4v to 38v, v out : 0.8v to 38v, regulates v out , i out or i in , 5mm 5mm qfn-32 and ssop-24 LTC3780 high efficiency synchronous 4-switch buck-boost controller v in : 4v to 36v, v out : 0.8v to 30v, regulates v out , 4mm 5mm qfn-28 and ssop-28 lt3763 60v high current step-down led driver controller v in : 6v to 60v, 4mm 4mm qfn-20 and tssop-20 lt3757/lt3757a boost, flyback, sepic and inverting controller v in : 2.9v to 40v, positive or negative v out , 3mm 3mm dfn-10, msop-10 lt3758 high input voltage, boost, flyback, sepic and inverting controller v in : 5.5v to 100v, positive or negative v out , 3mm 3mm dfn-10, msop-10 lt8710 synchronous sepic/inverting/boost controller with output current control v in : 4.5v to 80v, rail-to-rail output current monitor and control, tssop-28 25w (5v 5a) 2mhz buck-boost voltage regulator lt8390a 8390afa 0.47f 59k 2.2nf 11k 40.2k 10k 0.1f 95.3k 105k 0.1f 169k 1f 1f l1 0.33h m3 m4 m1 m2 1f 10 22nf 10 47f 47f 4.7f d1 d2 5m r1 10m r2 0.1f en/uvlo v ref ctrl pgood bg2 bst2 tg2 intv cc loaden fb 0.1f v out isp isn sync/sprd test v in 4.5v to 20v continuous 4v to 56v transient 2mhz 63v 100v 22f 2 10v 2 ismon pgood 10v v out 5v 5a lsp 383k lsn sw1 sw2 bst1 tg1 bg1 v in lt8390a loadtg ismon 4.7f ss v c rt gnd ssfm off ssfm on 10v 2 l1: coilcraft xel4020-331me 0.33h m1, m2: infineon bsz034n04ls 100k m3, m4: infineon bsz033ne2ls5 d1, d2: nxp bat46wj r1: susumu krl3216d-m-r005-f-t5 100v 2 intv cc intv cc intv cc

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