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| dual pll , quad input , multiservice line card adaptive clock translator data sheet ad9559 r ev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features supports gr - 1244 stratum 3 stability in holdover mode supports smooth reference switchover with virtually no disturbance on output phase supports t elcordia gr - 253 jitter g eneration , t ransfer, and t olerance for sonet/sdh up to oc - 192 systems suppo rts itu - t g.8262 s ynchronous ethernet slave clocks supports itu - t g.823, g.8 24, g.825 , and g.8261 auto/manual holdover and reference switchover adaptive clocking allows dynamic adjustment of feedback dividers for use in otn mapping/demapping applications dual digital pll architecture with four r eference inputs (single - ended or differential) 4x2 crosspoint allow s any reference input to drive either pll in put reference frequencies from 2 k hz to 1250 mhz reference validation and frequency monitoring (2 ppm) programmable input reference switchover priority 20- bit programmable input reference divider 4 pairs of clock output pins with each pair configurable as a single differential lvds/hstl output or as 2 single - ended cmos outputs output fr equencies : 262 khz to 1250 mhz programmable 17- bit integer and 24 - bit fractional feedback divider in digital pll programmable digital loop f ilter co vering loop bandwidths from 0.1 hz to 2 khz lo w noise system clock multiplier optional crystal resonator for system clock input on - chip eeprom to store multiple power - up profile s pin program function for easy frequency translation configuration software controlled power - down 72- lead (10 mm 10 mm) lfcsp package applications network synchronization , including synchronous et hernet and sdh to otn mapping/ demapping cleanup of r eference c lock j itter sonet/sdh c locks up to oc - 192, i ncluding fec stratum 3 holdover, jitter cleanup , and phase transient control wireless b ase station controllers cable i nfrastructure data communications gen eral description the ad9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems , including synchronous optical ne tworks (sonet/sdh). the ad9559 generates an output c lock synchronized to up to four external input references. the digital pll allows for reduction of input time jitter or phase noise associated with the external references. the digitally controlled loop and holdover circuitry of the ad9559 continuously generates a low jitter output clock even when all reference inputs have fai led. the ad9559 operates over a n industrial temperature range of ? 40c to +85c . if a single dpll version of this part is needed, r efer to the ad9557 . functional block dia gram reference input monitor and mux stable source digital pll 0 digital pll 1 clock multiplier analog pll 0 analog pll 1 3 to 11 hf divider 0 3 to 11 hf divider 1 eeprom serial interface (spi or i 2 c) status and control pins channel 0b divider channel 0a divider channel 1a divider channel 1b divider ad9559 10644-001 figure 1.
ad9559 data sheet rev. 0 | page 2 of 120 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision his tory ............................................................................... 3 specifications ..................................................................................... 4 supply voltage ............................................................................... 4 supply current .............................................................................. 4 power dissipation ......................................................................... 5 system clock inputs (xoa, xob) ............................................. 5 reference inputs ........................................................................... 6 reference monitors ...................................................................... 7 reference switchover specifications .......................................... 7 dis tribution clock outputs ........................................................ 8 time duration of digital functions ........................................ 10 digital pll (dpll_0 and dpll_1) ........................................ 10 analog pll (apll_0 and apll_1) ........................................ 10 digital pll lock detection ...................................................... 10 holdover specifications ............................................................. 10 serial port specifications spi mode ...................................... 11 serial port specifications i 2 c mode ...................................... 12 logic inputs ( reset , m5 to m0) ............................................. 12 logic outputs (m5 to m0) ........................................................ 12 jitter generation ......................................................................... 13 absolute maximum ratings .......................................................... 16 esd caution ................................................................................ 16 pin configuration and function descr iptions ........................... 17 typical performance characteristics ........................................... 20 input/output termination recommendations .......................... 26 getting started ................................................................................ 27 chip power monitor and startup ............................................. 27 multifunction pins at reset/power - up ................................... 27 device register programming using a register setup file .. 27 register programming overview ............................................. 28 theory of operation ...................................................................... 31 overview ...................................................................................... 31 reference input physical connections .................................... 32 reference monitors .................................................................... 32 reference input block ................................................................ 32 reference switchover ................................................................. 33 digital pll (dpll) core .......................................................... 34 loop control state machine ..................................................... 36 system clock (sysclk) ................................................................ 37 sysclk inputs ........................................................................... 37 sysclk multiplier ..................................................................... 37 output pll (apll) ....................................................................... 39 apll configuration .................................................................. 39 apll calibration ....................................................................... 39 clock distribution .......................................................................... 40 clock dividers ............................................................................ 40 output enable ............................................................................. 40 output mode and power - down ............................................... 40 clock distribution synchronization ........................................ 41 status and control .......................................................................... 42 multifunction pins (m0 to m5) ............................................... 42 irq function .............................................................................. 42 watchdo g ti me r ......................................................................... 43 eeprom ..................................................................................... 43 serial control port ......................................................................... 49 spi/i2c port selection ................................................................ 49 spi serial port operation .......................................................... 49 i2c serial port operation .......................................................... 53 programming the i/o registers ................................................... 56 buffered/active registers .......................................................... 56 write detect registers ............................................................... 56 autoclear registers ..................................................................... 56 register access restrictions ...................................................... 56 thermal performance .................................................................... 57 power supply partitions ................................................................. 58 3.3 v supplies .............................................................................. 58 1.8 v supplies .............................................................................. 58 bypass capacitors for pin 21 and pin 33 ................................. 58 register map ................................................................................... 59 register map bit descriptions ...................................................... 72 serial control port configuration (register 0x0000 to register 0x0005) ......................................................................... 72 clock part family id (register 0x000c and register 0x000d) ........................................................................ 72 user scratchpad (register 0x000e and register 0x000f) ..... 73 general configuration (register 0x0100 to register 0x0109) ......................................................................... 73 data sheet ad9559 rev. 0 | page 3 of 120 irq mask (register 0x 010a to register 0x112) ..................... 74 system clock (register 0x0200 to register 0x0207) .............. 76 reference input a (register 0x0300 to register 0 x031a) ..... 77 reference input b (register 0x0320 to register 0x033a) ...... 78 reference input c (register 0x0340 to register 0x035a) ..... 79 reference input d (register 0x0360 to register 0x037a) ..... 81 dpll_0 controls (register 0x0400 to register 0x0415) ....... 82 apll_0 configuration (register 0x0420 to register 0x0423) .......................................................................... 84 pll_0 output sync and clock distribution (register 0x0424 to register 0x042e) ....................................... 85 dpll_0 settings for reference input a (refa) (register 0x0440 to register 0x044c) ...................................... 87 dpll_0 settings for reference input b (refb) (register 0x044d to register 0x0459) ...................................... 88 dpll_0 settings for reference input c (refc) (register 0x045a to register 0x0466) ...................................... 89 dpl l_0 settings for reference input d (refd) (register 0x0467 to register 0x0473) ....................................... 90 dpll_1 controls (register 0x0500 to register 0x0515) ....... 91 apll_1 configuration (register 0x0520 to register 0x0523) .......................................................................... 93 pll_1 output sync and clock distribution (register 0x0524 to register 0x052e) ....................................... 94 dpll_1 settings for reference input c (refc) (register 0x0540 to register 0x054c) ...................................... 96 dpll_1 settings for reference input d (refd) (register 0x054d to register 0x0559) ...................................... 97 dpll_1 settings for reference input a (refa) (register 0x055a to register 0x0566) ...................................... 98 dpll_1 settings for reference input b (re fb) (register 0x0567 to register 0x0573) ....................................... 99 digital loop filter coefficients (register 0x0800 to register 0x0817) ........................................................................ 100 common ope rational controls (register 0x0a00 to register 0x0a0e) ...................................................................... 101 pll_0 operational controls (register 0x0a20 to register 0x0a24) ....................................................................... 104 p ll_1 operational controls (register 0x0a40 to register 0x0a44) ....................................................................... 106 status readback (register 0x0d00 to register 0x0d05) ..... 107 irq monitor (register 0x0d08 to register 0x0d10) .......... 108 pll_0 read - only status (register 0x0d20 to register 0x0d2a) ...................................................................... 110 pll_1 read - only status (register 0x0d40 to register 0x0d4a) ...................................................................... 112 eeprom control (register 0x0e00 to register 0x0e03) ... 113 eeprom storage sequence (register 0x0e10 to register 0x0e3c) ....................................................................... 113 outline dimensions ...................................................................... 120 ordering guide ......................................................................... 120 revision h istory 7/1 2 revision 0 : initial version ad9559 data sheet rev. 0 | page 4 of 120 specifications minimum (m in) and maximum ( m ax) values apply for the full range of supply voltage and operating temperature variation s. typical (t yp) values apply for vdd3 = 3.3 v ; vdd = 1.8 v ; t a = 25c , unless othe rwise noted. supply v oltage table 1. parameter min typ max unit test conditions/comments supply voltage vdd 3 3.135 3.30 3.465 v vdd 1.71 1.80 1.89 v supply current the test conditions for the maximum (m ax) supply curren t are at the maximum supply voltage found in table 1 . the test conditions for the typical (t yp) supply current are at the typical supply voltage found in table 1 . the test conditions for t he minimum ( min ) supply current are at the minimum supply voltage found in table 1 . table 2. parameter min typ max unit test conditions/comments supply current for typical configuration typical value s are for the t ypical c onfiguration parameter listed in table 3 i vdd3 34 42 50 ma i vdd 253 316 380 ma supply current for all blocks running configuration maximum values are for the all blocks r unning parameter listed in table 3 i vdd3 75 94 113 ma i vdd 256 320 384 ma data sheet ad9559 rev. 0 | page 5 of 120 power dissipation table 3. parameter min typ max unit test conditions/comments power dissipation typical configuration 0.57 0.71 0.85 w syste m clock: 49.152 mhz crystal; t wo dpll s active; t wo 19.44 mhz input references in differential mode ; t wo hstl driver s at 644.53125 mhz; t wo 3.3 v cmos driver s at 161.1328125 mhz and 80 pf capacitive load on cmos output all blocks running 0.71 0.89 1.1 w s ystem clock: 49.152 mhz crystal; t wo dpll s active, all input references in differential mode ; t wo hstl driver s at 750 mhz ; f our 3.3 v cmos drivers at 250 mhz and 80 pf capacitive load on cmos outputs full power - down 75 110 mw typical configuration with no external pull - up or pull - down resistors; a bou t 2/3 of this power is on vdd3 incremental power dissipation t ypical configuration; table values show the change in power due to the indicated operation complete dpll/apll on/o ff 171 214 257 mw this powe r delta is computed relative to the typical configuration; t he blocks powered down include one reference input, one dpll, one apll, one p divider, two channel dividers, one hstl driver, and one cmos driver ; roughly 2/3 of the power savings is on the 1.8 v supply input reference o n/o ff differential without divide -by -2 19 25 31 mw additional current draw is in the vdd3 domain only differential with divide -by -2 25 32 39 mw additional current draw is in the vdd3 domain only single - ended (without divide - by - 2) 5 6.6 8 mw additional current draw is in the vdd3 domain only output distribution driver on/o ff lvds (at 750 mhz) 12 17 22 mw add itional current draw is in the vdd domain only hstl (at 750 mhz) 14 21 28 mw add itional current draw is in the v dd domain only 1.8 v cmos (at 250 mhz) 14 21 28 mw a single 1.8 v cmos output with an 80 pf load 3.3 v cmos (at 250 mhz) 18 27 36 mw a single 3.3 v cmos output with an 80 pf load system clock inputs ( xoa , xob ) table 4. parameter min typ max unit test conditions/comments system clock multiplier pll output frequency range 750 805 mhz vco ran ge may place limitations on non standard system clock input frequencies phase frequency detector (pfd) rate 150 mhz frequency multi plication range 4 255 assumes valid system clock and pfd rates s ystem c lock r eference i nput p ath input frequency range 10 400 mhz minimum input slew rate 50 v/s min imum limit imposed for jitter performance; j itter performance aff ected if sine wave input 20 mhz common - mode voltage 1.05 1.16 1.27 v internally generated differential input voltage sensitivity 250 mv p -p minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed supply rails; single - ended input can be accommodated by ac grounding comple mentary input ; 1 v p- p recommended for optimal jitter performance system clock in put doubler duty cycle a mount of duty cycle variation that can be tolerated on the system clock input to use the doubler system clock input = 50 mhz 45 50 55 % system clock input = 20 mhz 46 50 54 % system clock input = 16 mhz to 20 mhz 47 50 53 % input capacitance 3 pf single - ended, each pin input resistance 4.1 k? ad9559 data sheet rev. 0 | page 6 of 120 parameter min typ max unit test conditions/comments c rystal r esonator p ath crystal resonator frequency range 10 50 mhz fundamental mode, at cut crystal maximum crystal motional r esistance 100 ? refer ence inputs table 5. parameter min typ max unit test conditions/comments d ifferential operation frequency range the reference input divide -by - 2 block must be engaged for f in > 705 mhz sinusoidal input 10 750 mhz lvpecl input 0.002 1250 m hz lvds input 0.002 75 0 m hz minimum input slew rate 40 v/s minimum limit imposed for jitter performance common - mode input voltage ac -c oupled 1.9 2 2. 1 v internally generated dc -c oupled 1.0 2.4 v differential input voltage sensitivity mv minimum differential voltage across pins required to ensur e switching between logic levels; instantaneous voltage on either pin must not exceed the supply rails f in < 800 mhz 240 mv f in = 800 mhz to 1050 mhz 320 mv f in = 1050 mhz to 1250 mhz 400 mv differential input voltage hysteresis 55 100 mv input resistance 21 k ? input capacitance 3 pf minimum pulse width high lvpecl 390 ps lvds 640 ps minimum pulse width low lvpecl 390 ps lvds 640 ps single - ended operation frequency range (cmos) 0.002 300 mhz minimum input slew rate 40 v/s minimum limit imposed for jitter performance input voltage high (v ih ) 1.2 v to 1.5 v threshold setting 1.0 v 1.8 v to 2.5 v threshold setting 1.4 v 3.0 v to 3.3 v threshold setting 2.0 v input voltage low (v il ) 1.2 v to 1.5 v threshold setting 0.35 v 1.8 v to 2.5 v threshold setting 0.5 v 3.0 v to 3.3 v threshold setting 1.0 v input resistance 47 k? input capacitance 3 pf minimum pulse width high 1.5 ns minimum pulse width low 1.5 ns data sheet ad9559 rev. 0 | page 7 of 120 reference m onitors table 6. parameter min typ max unit test conditions/comments reference monitors reference monitor loss of reference detection t ime 1.15 dpll pfd period n ominal p hase d et ector p eriod = r/ f ref 1 frequency out - of range limits 2 10 5 f/f ref (ppm) programmable (lower bound subject to quality of the system clock ( sysclk )); sysclk accuracy must be less than the lower bound validation timer 0.001 65.535 s ec programmable in 1 ms increments 1 f ref is the frequency of the active reference; r is the frequency division factor determined by the r divider. reference switchover specifications table 7. parameter min typ max unit test conditions/comments reference switchover specifications ma ximum output phase perturbation (phase build - out switchover) assumes a jitter - free reference; satisfies telcordia gr -1244- core requi rement s; base loop f ilter s election b it set to 1 b for all active reference s 50 hz dpll loop bandwidth test con ditions: 19.44 mhz to 174.70308 mhz; dpll bw = 50 hz ; 49.152 mhz signal generator used for system clock source peak 55 100 ps steady s tate 55 100 ps time required to switch to a new reference phase build - out switchover 10 dpll pfd period calculated using the nominal phase detector period (npdp = r/f ref ) ; t he total time required is the time plu s the reference validation time , plus the time require d to lock to the new reference ad9559 data sheet rev. 0 | page 8 of 120 distribution clock outputs table 8. parameter min typ max unit test conditions/comments hstl mode output frequency out0a , out0a and out0b , out0b 0.262 1250 mhz out1a, out 1a and out1b , out 1b 0.302 1250 mhz rise/fall time (20% to 80%) 1 140 250 ps 100 ? term ination across the output pair duty cycle up to f out = 700 mhz 4 4 48 53 % up to f out = 750 mhz 43 48 54 % up to f out = 1250 mhz 43 % differential output voltage swing 700 925 1200 mv magnitude of voltage across pins; o utput driver static common - mode output voltage 750 850 1000 mv output driver static re ference i nput -to - output delay variation o ver t emperature 3.2 ps/c hstl mode; dpll locked to same input reference at all times ; stable system clock source (non - xtal ) static phase offset variation from active reference to output over voltage extremes 0.875 ps/mv valid for hstl, lvds, and 1.8 v cmos output driver modes lvds mode output frequency out0a, out0a and out0b, out0b 0.262 1250 mhz out1a, out 1a and out1b , out 1b 0.302 1250 mhz rise/fall time (20% to 80%) 1 185 280 ps 100 ? term ination across the output pair duty cycle up to f out = 750 mhz 43 48 53 % up to f out = 800 mhz 42.5 48 53 .5 % up to f out = 1250 mhz 43 % differential output voltage swing balanced, v od 247 454 mv voltage swing between output pins; output driver static unbalanced, v od 50 mv absolute difference between voltage swing of normal pin and inverted pin; output driver static offset voltage common mode, v os 1.125 1.25 1.375 v output driver static common - mode difference, v os 50 mv voltage difference between pins; output driver static short - circuit output current 10 24 ma output driver static cmos mode output frequency 1.8 v supply out0a, out0a and out0b, out0b 0.262 250 mhz 10 pf load out1a, out1a and out1b, out1b 0.302 250 mhz 10 pf load 3.3 v supply (out0a and out1a) strong drive strength setting out0a, out0a 0.262 250 mh z 10 pf load out1a, out1a 0.302 250 mhz 10 pf load weak drive strength setting out0a, out0a 0.262 25 mhz 10 pf load out1a, out1a 0.302 25 mhz 10 pf load data sheet ad9559 rev. 0 | page 9 of 120 parameter min typ max unit test conditions/comments rise/fall time (20% to 80%) 1 1.8 v mode 1.5 3 ns 10 pf load 3.3 v s trong mode 0.4 0.6 ns 10 pf load 3.3 v weak mode 8 ns 10 pf load duty cycle 1.8 v mode 50 % 10 pf load 3.3 v strong mode 47 51 56 % 10 pf l oad 3.3 v weak mode 51 % 10 pf load output voltage high (v oh ) output driver static; strong drive strength vdd 3 = 3.3 v, i oh = 10 ma vdd3 ? 0.3 v vdd 3 = 3.3 v, i oh = 1 ma vdd3 ? 0.1 v vdd 3 = 1.8 v, i oh = 1 ma vdd ? 0.2 v output voltage low (v ol ) output driver static; strong drive strength vdd 3 = 3.3 v, i ol = 10 ma 0.3 v vdd 3 = 3.3 v, i ol = 1 ma 0.1 v vdd 3 = 1.8 v, i ol = 1 ma 0.1 v output timing skew 10 pf load between out0a, out0a and out0b, out0b or out1a, out1a and out1b, out1b 116 265 ps hstl mode on both drivers; rising edge only; any divide value additional delay on one driver by changing its logic type hstl to lvds 0 +1 5 +35 ps positive value indicates that the lvds edge is delayed relative to hstl hstl to 1.8 v cmos ?5 0 +5 ps positive value indicates that the cmos edge is delayed relative to hstl out0b, out0b hstl to out0 b, out0b 3.3 v cmos, strong mode ?765 ?280 +250 ns the cmos edge is delayed relative to hstl out1b, out1b hstl to out1b, out1b 3.3 v cmos, strong mode ?765 ?280 +250 ns the cmos edge is delayed relati ve to hstl 1 the listed valu es are for the slower edge (ris ing or fall ing ). ad9559 data sheet rev. 0 | page 10 of 120 time duration of digital functions table 9. parameter min typ max unit test conditions/comments time duration of digital functions eeprom -to- register download time 16 25 ms us es default eeprom storage sequence (see register 0x0e10 to register 0x0e4 f) register -to- eeprom upload time 180 ms us es default eeprom storage sequence (see register 0x0e10 to register 0x0e 4f power - down exit time 1 ms time from power - down exit to s ystem clock lock detect ; system clock stability timer setting should be added to calculate the time needed for system clock stable digital pll (dpll_0 and dpll_1) table 10. parameter min typ max unit test conditions/comments digital pll p hase frequency detector (pfd) input frequency range 2 100 k hz loop bandwidth 0. 1 2 000 hz programmable design parameter ; note that (f pfd /l oop bw) 20 phase margin 45 89 degrees programmable design parameter closed loop peaking < 0.1 db programmable design parameter ; p art can be programmed for < 0.1 db peaking in ac cordance with telcordia gr - 253- core jitter t ransfer analog pll (apll_0 a nd apll_ 1) table 11. parameter min typ max unit test conditions/comments analog pll0 vco frequency range 2940 3543 m hz phase frequency detector (pfd) input frequency range 180 19 5 m hz loop bandwidth 240 k hz programmable design parameter phase margin 68 degrees programmable design parameter analog pll1 vco frequency range 3405 4260 m hz phase frequency detector (pfd) input frequency range 180 19 5 m hz loop bandwidth 240 k hz programmable design parameter phase m argin 68 degrees programmable design parameter digital pll lock det ection table 12. parameter min typ max unit test conditions/comments phase lock detector threshold programming range 10 2 24 ? 1 ps reference -to- feedback p hase difference threshold resolution 1 ps frequency lock detector threshold programming range 10 2 24 ? 1 ps reference -to- feedback period difference threshold resolution 1 ps holdover specificati ons table 13. parameter min typ max unit test conditions/comments holdover specifications initial frequency accuracy < 0.01 ppm excludes frequency drift of sysclk source; excludes frequency drift of input reference prior to entering holdover ; c ompliant with gr - 1244 str atum 3 data sheet ad9559 rev. 0 | page 11 of 120 serial port specifications spi mode table 14. parameter min typ max unit test conditions/comments m5/ e e cs m5/ a cs e a is a dual function pin ; t he value s in this table apply when this pi n is used as a serial port pin , that is, a cs e e a ; s ee table 16 for the specifications w hen this pin is used as a multi function pin (m5) input logic 1 voltage 2.2 v input logic 0 voltage 0.8 v input logic 1 current 20 a input logic 0 current 50 a input capacitance 2 pf sclk internal 1 0 k? pull - down resistor input logic 1 voltage 2.2 v input logic 0 voltage 0.8 v input logic 1 current 20 0 a input logic 0 current 1 a input capacitance 2 pf sdio as an i nput input logic 1 voltage 2.2 v input logic 0 voltage 0.8 v input logic 1 current 1 a input logic 0 current 1 a input capacitance 2 pf as an o utput output logic 1 voltage vdd 3 ? 0.6 v 1 ma load current output logic 0 voltage 0.4 v 1 ma load current m4/sdo m4/sdo is a dual function pin; the value s in this table apply when this pin is used as a serial port pin , that is sdo; see table 16 for the specifications when this pin is used as a multifunction pin (m4) output logic 1 voltage vdd 3 ? 0.6 v 1 ma load current output logic 0 voltage 0.4 v 1 ma load current timing see figure 47 and figure 50 sclk clock rate, 1 /t clk 40 mhz pulse width high, t high 10 ns pulse width low , t lo w 13 ns sdio to sclk setup, t ds 3 ns sclk to sdio hold, t dh 6 ns sclk to valid sdio and sdo, t dv 10 ns a a cs e e aa to sclk setup (t s ) 10 ns a a cs e e aa to sclk hold (t c ) 0 ns a a cs e e aa minimum pulse width high 6 ns ad9559 data sheet rev. 0 | page 12 of 120 serial port specifications i 2 c mode table 15. parameter min typ max unit test conditions/comments sda, scl (as input s) input logic 1 voltage 0.7 vdd 3 v input logic 0 v oltage 0.3 vdd 3 v input current ? 10 +10 a for v in = 10% to 90% of vdd 3 hysteresis of schmitt trigger inputs 0.015 vdd 3 pulse w idth of spikes that must be suppressed by the input filter, t sp 50 ns sda ( as output ) output logic 0 voltage 0.4 v i o = 3 ma output fall t ime from v ihmin to v ilmax 20 + 0.1 c b 2f 1 250 ns 10 pf c b 400 pf timing scl clock rate 400 khz bus - free time between a stop and start condition, t buf 1.3 s repeated start condition setup time, t su; sta 0.6 s repeated hold time start condition, t hd; sta 0.6 s after this period, the first clock pulse is generated stop condition setu p time, t su; sto 0.6 s low period of the scl clock, t lo w 1.3 s high period of the scl clock, t high 0.6 s scl/sda rise time, t r 20 + 0.1 c b 1 300 ns scl/sda fall time, t f 20 + 0.1 c b 1 300 ns data setup time, t su; dat 100 ns data hold time, t hd; dat 100 ns capacitive load for each bus line , c b 1 400 pf 1 c b is the capacitance (pf) of a single bus line. logic inputs ( reset , m5 to m0) table 16. parameter min typ max unit test conditions/comments a reset e a pin a input high voltage (v ih ) 2.1 v input low voltage (v il ) 0.8 v input current (i inh , i inl ) 85 125 a input capacitance (c in ) 3 pf logic inputs (m5 to m0) the m4 and m5 pins are dual function pins; t he value s in this table apply when m4/sdo and m5/ a cs e a are used as m pins; s ee table 14 in the serial port specifications spi mode section for the specifications when these pins are used as serial port pins (sdo, a cs e a ) input high voltage (v ih ) 2.5 v input low voltage (v il ) 0.6 v input current (i inh , i inl ) 1 5 a input capacitance (c in ) 3 pf logic outputs (m5 to m0) table 17. parameter min typ ma x unit test conditions/comments logic outputs (m 5 t o m0 ) output high voltage (v oh ) vdd3 ? 0.4 v i oh = 1 ma output low voltage (v ol ) 0.4 v i ol = 1 m a data sheet ad9559 rev. 0 | page 13 of 120 jitter generation jitter generation (random j itter) 49.152 mhz crystal for system clock input table 18. parameter min typ max unit test conditions/comments jitter generation system clock doubler enabled. h igh phase margin mode enabled . b oth plls are run ning with same output frequency. in cases where the two plls have different jitter, the higher jitter is listed. w he n two driver types are listed, both were tested at those conditions ; the driver type with higher jitter is quoted, although there is usually not a significant jitter difference between driver types . f ref = 19.44 mhz; f out = 622.08 mhz; f loop = 50 hz ; hstl driver bandwidth: 5 khz to 20 mhz 307 fs rms bandwidth: 12 khz to 20 mhz 310 fs rms bandwidth: 20 khz to 80 mhz 313 fs rms bandwidth: 50 khz to 80 mhz 292 fs rms bandwidth: 16 mhz to 320 mhz 149 fs rms f ref = 19.44 mhz; f out = 644.53 mhz; f loop = 50 hz ; hstl driver, lvds driver bandwidth: 5 khz to 20 mhz 313 fs rms bandwidth: 12 khz to 20 mhz 306 fs rms bandwidth: 20 khz to 80 mhz 308 fs rms bandwidth: 50 khz to 80 mhz 286 fs rms bandwidth: 16 mhz to 320 mhz 154 fs rms f ref = 19.44 mhz; f out = 693.48 mhz; f loop = 50 hz ; hstl driver bandwidth: 5 khz to 20 mhz 335 fs rms bandwidth: 12 khz to 20 mhz 328 fs rms bandwidth: 20 khz to 80 mhz 328 fs rms bandwidth: 50 khz to 80 mhz 298 fs rms bandwidth: 16 mhz to 320 mhz 150 fs rms f ref = 19.44 mhz; f out = 174.703 mhz; f loop = 1 khz ; hstl driver bandwidth: 5 khz to 20 mhz 3 96 fs rms bandwidth: 12 khz to 20 mhz 33 5 fs rms bandw idth: 20 khz to 80 mhz 3 69 fs rms bandwidth: 50 khz to 80 mhz 3 47 fs rms bandwidth: 4 mhz to 80 mhz 23 0 fs rms f ref = 19.44 mhz; f out = 174.703 mhz; f loop = 100 hz ; lvds driver, 3.3 v cmos driver bandwidth: 5 khz to 20 mhz 3 37 fs rms bandwidth: 12 khz to 20 mhz 3 30 fs rms bandwidth: 20 khz to 80 mhz 354 fs rms bandwidth: 50 khz to 80 mhz 339 fs rms bandwidth: 4 mhz to 80 mhz 220 fs rms f ref = 25 mhz; f out = 161.1328 mhz; f loop = 100 hz ; hstl driver bandwidth: 5 k hz to 20 mhz 318 fs rms bandwidth: 12 khz to 20 mhz 310 fs rms bandwidth: 20 khz to 80 mhz 384 fs rms bandwidth: 50 khz to 80 mhz 361 fs rms bandwidth: 4 mhz to 80 mhz 267 fs rms ad9559 data sheet rev. 0 | page 14 of 120 parameter min typ max unit test conditions/comments f ref = 2 khz; f out = 70.656 mhz; f loop = 100 hz; hstl dri ver, 3.3 v cmos driver bandwidth: 10hz to 30 mhz 6.5 ps rms bandwidth: 5 khz to 20 mhz 343 fs rms bandwidth: 12 khz to 20 mhz 335 fs rms bandwidth: 10 khz to 400 khz 243 fs rms bandwidth: 100 khz to 10 mhz 2 56 fs rms f ref = 25 mh z; f out = 1 ghz; f loop = 500 hz ; hstl driver bandwidth: 100 hz to 500 mhz (broadband) 881 fs rms bandwidth: 12 khz to 20 mhz 331 fs rms bandwidth: 20 khz to 80 mhz 330 fs rms jitter generation (random jitter) 19.2 mhz tcxo for system clock input table 19. parameter min typ max unit test conditions/comments jitter generation system clock doubler enabled. high phase margin mode enabled. both plls are running with same output frequency. in cases where the two pl ls have different jitter, the higher jitter is listed. where two driver types are listed, both were tested at those conditions; the driver type with higher jitter is quoted, although there is usually not a significant jitter difference between driver types . f ref = 19.44 mhz; f out = 644.53 mhz; f loop = 10 hz ; hstl driver bandwidth: 5 khz to 20 mhz 380 fs rms bandwidth: 12 khz to 20 mhz 373 fs rms bandwidth: 20 khz to 80 mhz 373 fs rms bandwidth: 50 khz to 80 mhz 348 fs rms bandwidth: 1 6 mhz to 320 mhz 148 fs rms f ref = 19.44 mhz; f out = 693.48 mhz; f loop = 10 hz ; hstl driver bandwidth: 5 khz to 20 mhz 390 fs rms bandwidth: 12 khz to 20 mhz 383 fs rms bandwidth: 20 khz to 80 mhz 382 fs rms bandwidth: 50 khz to 80 mh z 350 fs rms bandwidth: 16 mhz to 320 mhz 144 fs rms f ref = 19.44 mhz; f out = 312.5 mhz; f loop = 10 hz ; hstl driver bandwidth: 5 khz to 20 mhz 398 fs rms bandwidth: 12 khz to 20 mhz 392 fs rms bandwidth: 20 khz to 80 mhz 400 fs rms bandwidth: 50 khz to 80 mhz 379 fs rms bandwidth: 4 mhz to 80 mhz 172 fs rms f ref = 25 mhz; f out = 161.1328 mhz; f loop = 10 hz ; hstl driver bandwidth: 5 khz to 20 mhz 384 fs rms bandwidth: 12 khz to 20 mhz 378 fs rms bandwidth: 20 k hz to 80 mhz 416 fs rms bandwidth: 50 khz to 80 mhz 39 6 fs rms bandwidth: 4 mhz to 80 mhz 223 fs rms data sheet ad9559 rev. 0 | page 15 of 120 parameter min typ max unit test conditions/comments f ref = 2 khz; f out = 70.656 mhz; f loop = 10 hz ; hstl driver , 3.3 v cmos driver bandwidth: 10 hz to 30 mhz 3.19 ps rms bandwidth: 12 k hz to 20 mhz 418 fs rms bandwidth: 10 khz to 400 khz 339 fs rms bandwidth: 100 khz to 10 mhz 348 fs rms ad9559 data sheet rev. 0 | page 16 of 120 absolute maximum rat ings table 20. parameter rating 1.8 v supply voltage ( vdd ) 2 v 3.3 v supply voltage ( vdd 3 ) 3.6 v maximum digital input voltage ? 0.5 v to vdd 3 + 0.5 v storage temperature range ? 65c to +150c operating temperature range ? 40c to +85c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause per manent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect device reliability. esd caution data sheet ad9559 rev. 0 | page 17 of 120 pin configuration and function descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vdd3 refa refa vdd vdd gnd vdd vdd vdd ldo_0 lf_0 vdd3 vdd vdd out0a out0a 17vdd 18vdd3 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 out0b out0b vdd gnd reset sclk/scl sdio/sda m5/cs m4/sdo vdd3 m3 m2 m1 m0 gnd vdd 35 out1b 36 out1b 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 vdd3 refc refc vdd vdd gnd vdd vdd vdd ldo_1 lf_1 vdd3 vdd vdd out1a out1a vdd vdd3 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 vdd3 refb refb vdd vdd vdd vdd vdd xoa xob vdd vdd vdd vdd vdd refd refd vdd3 pin 1 indicator ad9559 top view (not to scale) notes 1. the exposed pad is the ground connection on the chip. it must be soldered to the analog ground of the pcb to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 10644-002 figure 2. pin configuration table 21. pin function descriptions pin no. mnemonic inp ut/ output pin type description 1, 12, 18, 28, 37, 43, 54, 55, 72 vdd3 i power 3.3 v power supply. see the power supply partitions section for information about the recommended grouping of the power supply pins. 2 refa i differe ntial input reference a input. this internally biased input is typically ac - coupled; when configured in th is manner, it can accept any differential signal with single - ended swing up to 3.3 v. if dc - coupled, input can be lvpecl, lvds, or single - ended cmos. 3 a refa e i differential input complementary reference a input. complementary signal to the input provided on pin 2 . 4, 5, 7, 8, 9, 13, 14, 17, 21, 34, 38, 41, 42, 46, 47, 48, 50, 51, 58, 59, 60, 61, 62, 65, 66, 67, 68, 69 vdd i power 1.8 v power supply. see the power supply partitions section for information about the recommended grouping of the power supply pins. note that , for pin 34 and pin 21, it is recommended that a size 0201, 0.1 f bypass capacitor b e placed between pin 33 and pin 34, as well as between pin 21 and pin 22, as close as possible to the ad9559. 6, 22, 33, 49 gnd o ground connect these pins (along with the exposed die pad) to ground. 10 ldo_0 i ldo bypass output pll0 loop filter voltage regulator. connect a 0.47 f capacitor from this pin to ground. this pin is also the ac ground reference for the integrated output pll external loop filter. 11 lf_0 i/o loop filter for apll_0 loop filter node for the output pll0 . connect an external 6.8 nf capacitor from this pin to pin 10 (ldo_0). 15 a out0a e o hstl, lvds, 1.8 v cmos pll0 complementary output 0a. this output can be configured as hstl, lvds, or single - ended 1.8 v cmos. 16 out0a o hstl, lvds, 1.8 v cmos pll0 output 0 a. this output can be configured as hstl, lvds, or single - ended 1.8 v cmos. lvpecl levels can be achieved by ac - coupling and using the thevenin - equivalent termination as described in the input/output termination recommendations section. ad9559 data sheet rev. 0 | page 18 of 120 pin no. mnemonic inp ut/ output pin type description 19 a out0b e o hstl, lvds, 1.8 v cmos, 3.3 v cmos pll0 complementary output 0b. this output can be configured as hstl, lvds, or single - ended 1.8 v or 3.3 v cmos. 20 out0b o hstl, lvds, 1.8 v cmos, 3.3 v cmos pll0 output 0b. this output can be configured as hstl, lvds, or single - ended 1.8 v or 3.3 v cmos. lvpecl levels can be achieved by ac - coupling and using the thevenin - equivalent termination as described in the input/output termination recommenda tions section. 23 a reset e i 3.3 v cmos logic chip r eset. when this active low pin is asserted, the chip goes into reset. this pin has an internal 50 k ? pull - up resistor. 24 sclk/scl i 3.3 v cmos serial programming clock in spi mode (sclk). data clock for serial programming. serial clock p in i n i 2 c mode (scl). 25 sdio/sda i/o 3.3 v cmos serial data input/output (sdio). when the device is in 4 - wire spi mode, data is written via this pin. in 3 - wire spi mode, data reads and writes both occur on this pin. there is no internal pull - up/pull - down resistor on this pin. serial data p in in i 2 c mode (sda). 26 m5/ a cs e i /o 3.3 v cmos configurable i/o pin (m5). used for status and control of the ad9559 . chip select in spi mode ( a cs e a ). active low input . when programming a device in spi , this pin must be held low. in systems where more than one ad9559 is present, this pin enables individual programming of each ad9559 . t his pin has an internal 10 k ? pull - up resistor. 27 m4/sdo i/o 3.3 v cmos configurable i/o pin (m4). used for status and control of the ad9559 . serial data output (sdo) . in 4 - wire spi mode, this pin is u sed f or reading serial data. 29, 30, 31, 32 m3, m2, m1, m0 i/o 3.3 v cmos configurable i/o pins. these pins are used for status and control of the ad9559 . these pins are also used at power - up and reset to control th e serial port configuration and eeprom loading. see table 23 and table 25 for more information. these pins do not have internal pull - down resistors. 35 out1b o hstl, lvds, 1.8 v cmos, 3.3 v cmos pll1 output 1b. this output can be configured as hstl, lvds, or single - ended 1.8 v or 3.3 v cmos. lvpecl levels can be achieved by ac - coupling and using the thevenin - equivalent termination as described in the input/output termination recommendations section. 36 a out1b e o hstl, lvds, 1.8 v cmos, 3.3 v cmos pll1 complementary output 1b. this output can be configured as hstl, lvds, or single - ended 1.8 v or 3.3 v cmos. 39 out1a o hstl, lvds, 1.8 v cmos pll1 output 1a. this output can be configured as hstl, lvds, or single - ended 1.8 v cmos. lvpecl levels can be achieved by ac - coupling and using the thevenin - equivalent termination as described in the input/outp ut termination recommendations section. 40 a out1a e o hstl, lvds, 1.8 v cmos pll1 complementary output 1a. this output can be configured as hstl, lvds, or single - ended 1.8 v cmos. 44 lf_1 i/o loop filter for apll_1 loop filter node for the output pll1 . connect an external 6.8 nf capacitor from this pin to pin 45 (ldo_1). 45 ldo_1 i ldo bypass output pll1 loop filter voltage regulator. connect a 0.47 f capacitor from this pin to ground. this pin is also the ac ground reference for t he integrated output pll external loop filter. 52 a refc e i differential input complementary reference c input. complementary signal to the input provided on pin 53. 53 refc i differential input reference c input. this internally biased input is typically ac - coupled ; when configured in that manner , it can accept any differential signal with single - ended swing up t o 3.3 v. if dc - coupled, input can be lvpecl, lvds, or single - ended cmos. 56 a refd e i differential inpu t complementary reference d input. complementary signal to the input provided on pin 57. 57 refd i differential input reference d input. this internally biased input is typically ac - coupled; when configured in th is manner, it can accept any differential s ignal with single - ended swing up to 3.3 v. if dc - coupled, input can be lvpecl, lvds, or single - ended cmos. data sheet ad9559 rev. 0 | page 19 of 120 pin no. mnemonic inp ut/ output pin type description 63 xob i differential input complementary system clock input. complementary signal to xoa. xob contains internal dc biasing and should be ac -c oupled with a 0. 1 f capacitor except when using a crystal. when a crystal is used, connect the crystal across xoa and xob. 64 xoa i differential input system clock input. xoa contains internal dc biasing and should be ac -c oupled with a 0.01 f capacitor except when using a crystal. when a crystal is used, connect the crystal across xoa and xob. single - ended 1.8 v cmos is also an option , but a spur may be introduced if the duty cycle is not 50%. when using xoa as a single - ended input, connect a 0. 1 f capacitor from xob to ground. 70 refb i differential input reference b input. this internally biased input is typically ac - coupled; when configured in th is manner, it can accept any differential signal with single - ended swing up to 3.3 v. if dc - coupled, input can b e lvpecl, lvds, or single - ended cmos. 71 a refb e i differential input complementary reference b input. complementary signal to the input provided on pin 70 . ep gnd o exposed pad the exposed pad is the ground connection on the chip. it must be soldered to the analog ground of the pcb to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. ad9559 data sheet rev. 0 | page 20 of 120 typical performance characteristics f r = input reference clock frequency; f out = output clock frequency; f sys = sysclk input frequency; vdd3 and vdd at nominal supply voltage . ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 1k 10 100 10k 100k 1m 10m 100m phase noise (dbc/hz) frequenc y offset (hz) integr a ted rms jitter (12khz t o 20mhz): 331fs phase noise (dbc/hz): offset level 10hz ?75 100hz ?92 1khz ?116 10khz ?126 100khz ?130 1mhz ?143 10mhz ?152 floor ?158 10644-300 absolute phase noise (output driver = hstl), f r = 19.44 mhz, f out = 156.25 mhz, dpll loop bw = 50 hz, f sys = 49.152 mhz crystal ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 1k 10 100 10k 100k 1m 10m 100m phase noise (dbc/hz) frequenc y offset (hz) integr a ted rms jitter (12khz t o 20mhz): 310fs phase noise (dbc/hz): offset level 10hz ?71 100hz ?82 1khz ?105 10khz ?114 100khz ?117 1mhz ?133 10mhz ?142 floor ?153 10644-003 figure 3 . absolute phase n oise (output driver = hstl), f r = 19.44 mhz, f o ut = 622.08 mhz, dpll loop bw = 50 hz, f sys = 49.152 mhz crystal ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 phase noise (dbc/hz) frequenc y offset (hz) 1k 10 100 10k 100k 1m 10m 100m integr a ted rms jitter (12khz t o 20mhz): 306fs phase noise (dbc/hz): 10hz ?70 100hz ?86 1khz ?105 10khz ?114 100khz ?117 1m hz ?134 10m hz ?141 floor ?153 10644-004 figure 4 . absolute phase noise (output driver = hstl ), f r = 19.44 mhz, f out = 644.53125 mhz, dpll loop bw = 50 hz, f sys = 49.152 mhz crystal ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 phase noise (dbc/hz) frequenc y offset (hz) 1k 10 100 10k 100k 1m 10m 100m integr a ted rms jitter (12khz t o 20mhz): 328fs phase noise (dbc/hz): offset level 10hz ?70 100hz ?85 1khz ?105 10khz ?112 100khz ?115 1mhz ?133 10mhz ?142 10644-005 figure 5 . absolute phase noise (output driver = hstl ), f r = 19.44 m hz, f out = 693.482991 mhz, dpll loop bw = 50 hz, f sys = 49.152 mhz c rystal data sheet ad9559 rev. 0 | page 21 of 120 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 phase noise (dbc/hz) frequency offset (hz) 1k 10 100 10k 100k 1m 10m 100m integrated rms jitter (12khz to 20mhz): 335fs phase noise (dbc/hz): offset level 10hz ?82 100hz ?90 1khz ?96 10khz ?119 100khz ?128 1mhz ?143 10mhz ?152 floor ?158 10644-006 figure 6 . absolute phase noise (output driver = hstl ), f r = 19.44 mhz, f out = 174.703 mhz, dpll loop bw = 1 k hz, f s ys = 49.152 mhz crystal ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 phase noise (dbc/hz) frequency offset (hz) 1k 10 100 10k 100k 1m 10m 100m integrated rms jitter (12khz to 20mhz): 309fs phase noise (dbc/hz): offset level 10hz ?84 100hz ?93 1khz ?116 10khz ?125 100khz ?130 1mhz ?144 10mhz ?152 floor ?158 10644-007 figure 7 . absolute phase noise (output driver = 3.3.v cmos), f r = 19.44 mhz, f out = 161.1328125 mhz, dpll lo op bw = 100 hz, f sys = 49.152 mhz crystal ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 phase noise (dbc/hz) frequency offset (hz) 1k 10 100 10k 100k 1m 10m 100m integrated rms jitter (12khz to 20mhz): 321fs phase noise (dbc/hz): offset level 10hz ?61 100hz ?69 1khz ?108 10khz ?127 100khz ?132 1mhz ?146 10mhz ?153 10644-008 figure 8 . absolute phase noise (output driver = hstl ), f r = 2 khz , f out = 125 mhz, dpll loop bw = 10 0 hz, f sys = 49.152 mhz crystal ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 phase noise (dbc/hz) frequency offset (hz) 1k 10 100 10k 100k 1m 10m 100m integrated rms jitter (12khz to 20mhz): 331fs phase noise (dbc/hz): offset level 10hz ?70 100hz ?75 1khz ?86 10khz ?108 100khz ?112 1mhz ?129 10mhz ?142 floor ?152 10644-009 figure 9 . absolute p hase noise (output driver = hstl ), f r = 25 mhz, f out = 1 g hz, dpll loop bw = 500 hz, f sys = 49.152 mhz crystal ad9559 data sheet rev. 0 | page 22 of 120 ?160 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 1k 10 100 10k 100k 1m 10m 100m phase noise (dbc/hz) frequenc y offset (hz) 10644-010 integrated rms jitter (12khz to 20mhz): 373fs phase noise (dbc/hz): 10hz ?60 100hz ?85 1khz ?104 10khz ?113 100khz ?114 1mhz ?132 10mhz ?142 floor ?153 figure 10 . absolute phase noise (output driver = hstl), f r = 19.44 mhz, f out = 644.53 mhz, dpll loo p bw = 10 hz, f sys = 19.2 mhz tcxo ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 phase noise (dbc/hz) frequency offset (hz) 1k 10 100 10k 100k 1m 10m 100m integrated rms jitter (12khz to 20mhz): 383fs phase noise (dbc/hz): 10hz ?60 100hz ?85 1khz ?104 10khz ?112 100khz ?114 1mhz ?132 10mhz ?141 floor ?153 10644-011 figure 11 . absolute phase noise (output driver = hstl), f r = 19.44 mhz, f out = 693.482991 mhz, dpll loop bw = 1 0 hz , f sys = 19.2 mhz tcxo ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 phase noise (dbc/hz) frequency offset (hz) 1k 10 100 10k 100k 1m 10m 100m 10644-012 integrated rms jitter (12khz to 20mhz): 392fs phase noise (dbc/hz): offset level 10hz ?66 100hz ?91 1khz ?110 10khz ?119 100khz ?121 1mhz ?136 10mhz ?146 floor ?156 figure 12 . absolute pha se noise (output driver = hstl), f r = 19.44 mhz, f out = 312.5 mhz, dpll loop bw = 0.1 hz, f sys = 19.2 mhz tcxo ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 phase noise (dbc/hz) frequency offset (hz) 1k 10 100 10k 100k 1m 10m 100m 10644-013 integrated rms jitter (12khz to 20mhz): 378fs phase noise (dbc/hz): offset level 10hz ?74 100hz ?97 1khz ?116 10khz ?125 100khz ?127 1mhz ?143 10mhz ?153 floor ?158 figure 13 . absolute phase noise (output driver = 3.3 v cmos), f r = 19.44 mhz, f out = 161.1328125 mhz, dpll loop b w = 1 0 hz , f sys = 19.2 mhz tcxo ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 phase noise (dbc/hz) frequency offset (hz) 1k 10 100 10k 100k 1m 10m 100m 10644-014 integrated rms jitter (12khz to 20mhz): 418fs phase noise (dbc/hz): offset level 10hz ?71 100hz ?96 1khz ?122 10khz ?132 100khz ?134 1mhz ?149 10mhz ?157 floor ?161 figure 14 . absolute phase noise (output driver = 1.8v cmos ), f r = 2 k hz, f out = 70.656 mhz, dpll loop bw = 1 0 hz , f sys = 19.2 mhz tcxo data sheet ad9559 rev. 0 | page 23 of 120 differential peak-to-peak amplitude (mv) 0 100 200 300 400 600 800 1000 1200 500 700 900 1100 frequency (mhz) 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1. 90 1. 95 2.00 10644- 1 16 figure 15 . amplitude vs. togg le rate, hstl mode (lvpecl - compatible mode) 0 1200 1000 800 600 400 200 differential peak-to-peak amplitude (mv) 0 100 200 300 400 500 600 700 800 frequency (mhz) lvds (default) lvds (boost) 10644- 1 17 figure 16 . amplitude vs. toggle rate, lvds 3.5 3.0 1.0 1.5 2.0 2.5 0 300 250 200 150 100 50 peak-to-peak amplitude (v) frequency (mhz) 1.8 v mode 3.3v strong mode 10644- 1 18 figure 17 . amplitude vs. toggle rate with 10 pf load, 3.3 v (strong mode) and 1.8 v cmos 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 0 100 80 60 40 20 peak-to-peak amplitude (v) frequency (mhz) 3.3v weak mode 10644- 1 19 figure 18 . amplitude vs. toggle rate with 10 pf load, 3.3 v (weak mode) cmos 0 10 20 30 40 50 60 70 0 1400 1200 1000 800 600 400 200 power (mw) frequency (mhz) 10644-120 figure 19 . power consumption vs. frequency, hstl mode on outpu t driver power supply o nly (pin 17, pin 21, pin 34, and pin 38 ) 0 5 10 15 20 25 30 35 40 45 50 0 100 200 300 400 500 600 700 900800 power (mw) frequency (mhz) 10644-121 figure 20 . power consumption vs. frequency , lvds mode on output driver power supply o nly (pin 17, pin 21, pin 34, and pin 38 ) ad9559 data sheet rev. 0 | page 24 of 120 0 10 20 30 40 50 60 80 70 0 20018016014012010080604020 power (mw) frequency (mhz) 10644-122 1.8v cmos 3.3v cmos weak 3.3v cmos strong figure 21 . power consumption vs. frequency for two cmos drivers; power is measure d on output driver power supply only (pin 17, pin 21, pin 34, and pin 38 for 1.8 v cmos mode or on pin 18 and pin 37 for 3.3 v cmos m ode ); c load = 80 pf ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 ?1 0 1 2 3 4 5 differential amplitude (v) time (ns) 10644-123 figure 22 . output waveform, hstl (400 mhz) ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 ?1 0 1 2 3 4 differential amplitude (v) time (ns) 10644-124 figure 23 . output waveform, lvds (400 mhz) ?0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 ?1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 amplitude (v) time (ns) 10pf load 2pf load 10644-126 figure 24 . output waveform, 3.3 v cmos (100 mhz, strong mode) ?1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 amplitude (v) time (ns) ?0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 10pf load 2pf load 10644-127 figure 25 . output waveform, 1.8 v cmos (100 mhz) 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 ?5 5 15 25 35 45 55 65 75 85 95 amplitude (v) time (ns) 10pf load 2pf load 10644-128 figure 26 . outp ut waveform, 3.3 v cmos (20 mhz, weak mode) data sheet ad9559 rev. 0 | page 25 of 120 ?30 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 10 100 1k 10k 100k frequency offset (hz) loop gain (db) 10644-129 loop bw = 100hz; high phase margin; peaking: 0.06db; ?3db: 69hz loop bw = 2khz; high phase margin; peaking: 0.097db; ?3db: 1.23khz loop bw = 5khz; high phase margin; peaking: 0.14db; ?3db: 4.27khz figure 27 . closed -l oop transfer function for 100 hz , 2 khz, and 5 khz loop bandwidth s etting s; h igh phase margin loop filter s etting (this figure is compliant with telcordia gr - 253 j itter transfer t est for l oop b andwidths < 2 khz .) note that bandwidth is defined as the point where the open loop gain = 0 db. ?30 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 10 100 1k frequency offset (hz) loop gain (db) 10k 100k 10644-230 loop bw = 100hz; normal phase margin; peaking: 0.09db; ?3db: 117hz loop bw = 2khz; normal phase margin; peaking: 1.6db; ?3db: 2.69khz figure 28 . closed -l oop transfer function for 100 hz and 2 khz l oop b andwidth s ettings; normal phase margin loop filter setting note that bandwidth is defined as the point where the open loop gain = 0 db. ad9559 data sheet rev. 0 | page 26 of 120 input/output termina tion recommendations ad9559 hstl or lvds downstream device with high impedance input and internal dc bias 0.1f 0.1f 100? 10644-130 z 0 = 50? z 0 = 50? single-ended (not coupled) figure 29 . a c- coupled lvds or hstl output driver (100 ? r esistor c an be placed on e ither s ide of d ecoupling capacitor s and s hould b e as cl ose t o the d estination r eceiver as p ossible .) ad9559 hstl or lvds z 0 = 50? z 0 = 50? single-ended (not coupled) lvds or 1.8v hstl high impedance differential receiver 100? 10644-131 figure 30 . dc - coupled lvds or hstl output driver single-ended (not coupled) v s = 3.3v 3.3v lvpecl 82? 82? 127? 127? 0.1f 0.1f ad9559 1.8v hstl z 0 = 50? z 0 = 50? 10644-132 figure 31 . interfacing the hstl d river to a 3.3 v lvpecl i nput (this m ethod i ncorporates i mpedance m atching and dc -b iasing for b ipolar lvpecl r eceivers. if the r eceiver is s elf -b iased, the t ermination s cheme s hown in figure 29 is r ecommended .) xoa xob ad9559 10mhz to 50mhz fundamental at-cut crystal with 10pf load capacitance 10pf 10pf 10644-133 figure 32 . system clock input (xoa/xob) in crystal mode ( the recommended c load = 10 pf is shown. the values of 10 pf shunt c apacitors shown h ere should equal the c load of the crystal .) xoa 300? 150? 0.1f xob ad9559 3.3v cmos tcxo 0.1f 10644-134 figure 33 . syst em clock input (xoa, xob) w hen u sing a tcxo/ocxo with 3.3 v cmos output data sheet ad9559 rev. 0 | page 27 of 120 getting started chip power monitor a nd start up the ad9559 monitors the voltage on the power supplies at power - up. when vdd 3 is greater than 2.35 v 0.1 v and vdd is greater than 1.4 v 0.05 v, the device generates a 20 ms reset pulse. the power - up reset pulse is internal and independent of the a reset e a pin. this internal power - up reset sequence eliminates the need for th e user to provide external power supply sequencing. within 45 ns after the internal reset pulse, the m5 to m0 multifunction pins behave as high impedance digital inputs and continue to do so until programmed otherwise. during a device reset (either via th e power - up reset pulse or the a reset e a pin), the m3 to m0 multifunction pins behave as high impedance inputs; and at the point where the reset condition is cleared, level - sensitive latches capture the logic pattern that is present on the mul tifunction pins. multifunction pins at reset/ power -up at start - up, the m0 and m1 pins allow the user to either bypass eeprom loading or load one of three eeprom profiles. see table 23 for information on setting the m0 and m1 pins . pin m3 select s spi or i2c mode : spi mode is set by pulling m3 low at start up. i f m3 is high, i2c mode is set, and the m4 and m5 pins determine the i2c address. see table 25 for information on spi/i2c configuratio n. if 4 - wire spi mode is selected , by setting bit 7 of register 0x0000, the m4/sdo pin functions as sdo and is not available for other functions as an m pin. however, i n i2c mode and in 3 - wire spi mode , m4 is ava ilable as the fifth m pin. a sixth m pin , m5 , is available if the serial port is in i2c mode or 2- wire spi mode . in 2 - wire spi mode, there is no a cs e a pin available, and it is assumed that the ad9559 is the only device on the spi bus. device register prog ramming using a register setup f ile the evaluation software contains a programming wizard and a convenient graphical user interface that assists the user in determining the optimal configuration for the dpll s, apll s, and sysclk based on the desired input and output frequencies. it generates a register setup file with a .stp extension that is easily readable using a text editor. the user can configure pll_0 and pll_1 independently. to do so , the user should program the common registers (such as the system clock and reference inputs) first. next, the registers that are unique to pll_0 or pll_1 can be configured independently . after using the evaluation software to create the setup file, use the following sequence to program the ad9559 : 1. set user free run mode . dpll_0: register 0x0a22 = 0x01 . dpll_1: register 0x0a42 = 0x01 . 2. update all registers (also referred to as io_update ). register 0x0005 = 0x01 . 3. write the register values in the stp file fro m address 0x0000 to addr ess 0x0 207 . 4. io_update. register 0x0005 = 0x01. 5. ver if y that sysclk is stable . register 0x0d01[1] = 1. the user must issue an io_update each time before polling register 0x0d01. 6. for the outputs to toggle prior to dpll phase or frequen cy lock, set the following: apll_0: register 0x0a20 = 0x40 (soft sync) . apll_1: register 0x0a40 = 0x40 (soft sync) . 7. write the rest of the registers in the stp file starting at addres s 0x0 3 00. 8. calibrate apll on next io_update. apll_0: register 0x0 a20 = 0x2 0. apll_1: register 0x0 a40 = 0x20 . 9. io_update. register 0x0005 = 0x01 . 10. clear user free run mode . dpll_0: register 0x0a22[0] = 0b . dpll_1: register 0x0a42[0] = 0b . 11. io_update. register 0x0005 = 0x01 . ad9559 data sheet rev. 0 | page 28 of 120 register programming overview this section provides a prog ramming overview of the register blocks in the ad9559 , describing what they do and why they are important. this is sup plemental information only, needed only if the user wishes to load the registers without usi ng the stp file. the ad9559 evaluation software contains a wizard that determin es the register s ettings based on the users input and output frequencies . it is strongly recommended that the evaluation software be used to determine these settings. multifunction pins (optional) this step is required only if the user intends to use any of the multifunction pins for status or control. the multifunction pin parameters are at register 0x0 100 to register 0x0107 . table 196 has a list of m pin output functions, and table 197 has a list of m pin input functions. irq functions (optional) this step is required only if the user intends to use the irq feature . the irq functio ns are divided into three groups: common, pll_0, and pll_1. the user must first choose the events that trigger an irq and then set them in register 0x010a to register 0x0112. next, an m pin must be assigned to the irq function. t he user can choose to dedic ate one m pin to each of the three irq groups , or o ne m pin can be assigned for all irqs. the irq monitor registers are located at register 0x0d08 to register 0x0d10 . if the desired bits in the irq mask registers at register 0x01 0a to register 0x0112 are s et high , the appropriate irq monitor bit at register 0x0d08 to register 0x0d10 is set high w hen the indicated event occurs. individual irq events are cleared by using the irq clearing registers at register 0x0a05 to register 0x0a0e or by setting the clear all irqs bit ( register 0x0a05[0 ]) to 1 b. the default values of the irq mask registers are such that interrupts are not generated. the default irq pin mode is open - drain nmos. watchdog timer (optional) this step is required only if the user intends to use t he watchdog timer. the watchdog timer control is at register 0x0 108 and register 0x0 109 . the watchdog timer is disabled by default. the watchdog timer is useful for generating an irq after a fixed amount of time. the timer is reset by setting the clear w at chdog timer bit in register 0x0a05[7] to 1. the user can also program an m pin for the watchdog timer output. in this mode, the m pin generate s a 40 ns pulse every time the watchdog timer expires. system clock configuration the system clock multiplier (sy sclk ) parameters are at register 0x0200 to register 0x0207 . for optimal performance, u se the following steps: 1. set the system clock pll input type and divider values . 2. set the s ystem clock period . it is essential to program the system clock period because ma ny of the ad9559 subsystems rely on this value. 3. s et the s ystem clock stability timer . it is highly recommended that the system clock stability timer be program med . this is especially important when using the sy stem clock multiplier and also applies when using an external system clock source, especially if the external source is not expected to be completely stable when power is applied to the ad9559 . the system clock stability timer specifies the amount of time that the system clock pll must be locked before the part declares that the system clock is stable. the default value is 50 ms. 4. update all registers ( register 0x0005 = 0x01 ). important note t he system clock must be stable for the digital pll blocks to function correctly and read back the registers updated on the system clock domain. these registers include the status registers , as well as the free running tuning word. therefore, when debug - ging the ad9559 , the user mu s t first ensure that the system clock is stable by checking bit 1 in register 0x0d01. reference inputs the reference input parameters and reference dividers are common to both plls; there is only one reference divider (r divider) for each reference input. the register address for each reference input is as follows : ? refa: register 0x 0300 to register 0x031a ? refb: register 0x 032 0 to register 0x033a ? refc: register 0x 034 0 to register 0x035a ? refd: register 0x 036 0 to register 0x037a these registers include the following settings : ? reference logic family ? reference divider (r divider value) ? reference input period and tolerance ? reference validation timer ? phase and frequency lock detector settings data sheet ad9559 rev. 0 | page 29 of 120 other reference input settings can be found at the following register addresses: ? reference input enable information is found in the dpll feedback dividers section. ? reference power-down is found in register 0x0a01. ? reference priority settings are found in the dpll profiles. dpll_0: registers 0x0440 through 0x0473 dpll_1: registers 0x0540 through 0x0573 ? reference switching mode settings are found in dpll_0: register 0x0a22 dpll_1: register 0x0a42 dpll controls and settings the dpll control parameters are separate for dpll_0 and dpll_1. they reside in the following locations: ? dpll_0: register 0x0400 to register 0x0415 ? dpll_1: register 0x0500 to register 0x0515 these registers include the following settings: ? 30-bit free running frequency ? dpll pull-in range limits ? dpll closed-loop phase offset ? tuning word history control (for holdover operation) ? phase slew control (for controlling the phase slew rate during a closed-loop phase adjustment) with the exception of the free running tuning word, the default values of these registers are fine for normal operation. the free running frequency of the dpll determines the frequency that appears at the apll input when user free run mode is selected. the correct free running frequency is required for the apll to calibrate and lock correctly. note that the user free run bits, which enable user free run mode, can be found in the following registers: ? dpll_0: register 0x0a22 = 0x01 ? dpll_1: register 0x0a42 = 0x01 output plls (aplls) and output drivers the registers controlling the aplls and output drivers reside at the following locations: ? apll_0: register 0x0420 to register 0x042e ? apll_1: register 0x0520 to register 0x052e the following functions are controlled in these registers: ? apll settings (feedback divider, charge pump current) ? output synchronization mode ? output divider values ? output enable/disable (disabled by default) ? output logic type note that the apll calibration and synchronization bits can be found in the following registers: ? apll_0: register 0x0a20 ? apll_1: register 0x0a40 dpll feedback dividers each digital pll has separate feed back divider settings for each reference input. this allows the user to have each digital pll perform a different frequency translation. however, there is only one reference divider (r divider) for each reference input. the feedback divider register settings reside in the following locations: ? dpll_0, refa: register 0x0440 to register 0x044c ? dpll_0, refb: register 0x044d to register 0x0459 ? dpll_0, refc: register 0x045a to register 0x0466 ? dpll_0, refd: register 0x0467 to register 0x0473 ? dpll_1, refc: register 0x0540 to register 0x054c ? dpll_1, refd: register 0x054d to register 0x0559 ? dpll_1, refa: register 0x055a to register 0x0566 ? dpll_1, refb: register 0x0567 to register 0x0573 these registers include the following settings: ? reference priority ? reference input enable (separate for each dpll) ? dpll loop bandwidth ? dpll loop filter ? dpll feedback divider (integer portion) ? dpll feedback divider (fractional portion) common operational controls the common operational controls reside at register 0x0a00 to register 0x0a0e and include the following: ? simultaneous calibration and synchronization of both plls ? global power-down ? reference power-down ? reference validation override ? irq clearing (for all irqs) pll_0 and pll_1 operational controls the pll_0 and pll_1 operational controls are located at register 0x0a20 to register 0x0a44 and include the following: ? apll calibration and synchronization ? output driver enable and power-down ? dpll reference input switching modes ? dpll phase offset control ad9559 data sheet rev. 0 | page 30 of 120 apl l vco calibration vco calibration ensures that , at the time of calibration, the dc control voltage of the apll vco is centered in the middle of its operating range. the user can calibrate vco_0 independently of vco_1, and vice versa. it is important to re member the following conditions when calibrating the apll vco: ? the system clock must be stable. ? the apll vco must have the correct frequency from the 30- bit dco (digitally controlled oscillator) during calibration. the free running tuning word is found in dpll_0: registers 0x0400 to 0x0403 dpl l_1: registers 0x0500 to 0x0503 ? the apll vco must be recalibrated any time the apll frequency changes. ? apll vco calibration occurs on the low - to - high transition of the apll vco calibration bit . apll_0: register 0x0a20[ 1] apll_1: register 0x0a40[1 ] ? the vco calibration bit is not an auto clearing bit . therefore, this bit must be cleared (and an io_update issued) before the apll is recalibrated . ? the best way to monitor succ es sful apll calibration is by monitoring the apll l ock ed bit , in the following registers : apll_0: register 0x0d20 [3] apll_1: register 0x0d40[3] generate the output clock if register 0x042 5 (for pll_0) and/or register 0 x0525 (for pll_1) is programmed for automatic clock distribution synchronization via the dpll phase or frequency lock, the synthesized output signal appears at the clock distribution outputs. otherwise, set and then clear the soft sync bit ( bit 2 in register 0x 0a20 for apll_0 and register 0x0a40 for appl_1 ) or use a multifunction pin input (i f programmed accordingly) to generate a clock distribution sync pulse, which causes the synthesized output signal to appear at the clock distribution outputs. generate the reference acquisition after the registers are programmed, clear the user free run bi t (bit 0 in register 0x 0a22 for d pll_0 and register 0x0a42 for d ppl_1) and issue an io_update using register 0x0005[0] to invoke all of the register settings programmed up to this point. t he dpll s lock to the first available reference tha t has the highest priority. data sheet ad9559 rev. 0 | page 31 of 120 theory of operation xoa xob refa refa a refb refb b refc refc c refd refd d 2 2, 4, 8 2 r a 2 r b 2 r c 2 r d reference monitors and crosspoint mux sysclk multiplier ref or xtal system clock dpfd loop filter tw clamp nco_0 frac0 mod0 n0 m0 p0 (3 to 11) pfd/cp lf free run tuning word vco_0 2940mhz to 3543mhz q0_a out0a out0a q0_b out0b out0b 262khz to 1.25ghz q1_a dpfd loop filter tw clamp nco_1 frac1 mod1 n1 m1 p1 (3 to 11) pfd/cp lf free run tuning word vco_1 3405mhz to 4260mhz q1_b out1a out1a out1b out1b 302khz to 1.25ghz reset sclk/scl sdio/sda m5/cs m4/sdo m3 m2 m1 m0 control interface/logic and eeprom input reference frequency range: 2khz to 1.25ghz 10644-035 figure 34 . detailed block diagram overview the ad9559 provides clocking outputs that are directly related in phase and frequency to the selected (activ e) reference but with jitter characteristics governed by the system clock , the digitally controlled oscillator ( dco ) , and the analog output pll ( apll ). t he ad9559 can be thought of as two copies of the ad9557 inside one package , with a 4:2 crosspoint controlling the reference inputs. the ad9559 supports up to four reference inputs and input frequencies ranging from 2 khz to 12 5 0 mhz . the core s of this product a re two digital phase - locked loop s (dpll s). each dpll has a programmable digital loop filter that greatly reduces jitter transferred from the active reference to the output , and these two dplls operate completely independen tly of each other. the ad9559 supports both manual and automatic holdover. while in holdover, the ad9559 continues to provide an output as long as the system clock is p resent. the holdover output frequency is a time average of the output frequency history just prior to the transition to the holdover condition. the device offers manual and automatic reference switchover capability if the active reference is degraded or fa ils completely. the ad9559 also has adaptive clocking capability that allows the user to dynamically change the dpll divide ratios whi le the dpll s are locked. the ad9559 include s a system clock multiplier, two d pll s, and two apll s . th e input signal goes first to the d pll, which performs the jitter cleaning and most of the frequency translation. each dpll features a 30 - bit digitally controlled oscillator (dco) output that generates a signal in the range of 175 mhz to 200 mhz . the d co output goes to the apll, which mu ltiplies the signal up to a rang e of 2.9 ghz to 4.2 ghz . that signal is then sent to the clock distribution section, which has a divide - by - 3 to divide - by - 11 p divider cascaded with 10- bit integer channel dividers ( divide - by - 1 to divide - by - 1024) . the xoa and xob input s provi de the input for the system clock. these bits accept a reference clock in the 10 mhz to 600 mhz range or a 10 mhz to 50 mhz crystal connect ed directly across the xoa and xob inputs. the system clock provides the clocks to the frequency monitors, the d pll s , and internal switching logic. each apll on t he ad9559 has two differential output drivers . each of the four output driver s has a dedicated 10 - bit program - mable post divider. each differential driver is programmable as either a single differential or dual single - ended cmos output. the clock distributi on section operates at up to 1250 mhz. in differ ential mode, the output drivers run on a 1.8 v power supply to offer very high performance with minimal power consumption. there are two differential modes: lvds and 1.8 v hstl. in 1.8 v hstl mode, the voltage swing is compatibl e with lvpecl. if lvpecl sig nal levels are required, the designer can ac - couple the ad9559 output and use the v enin - equivalent termination at the destination to drive lvpecl inputs. in single - ended mode, each differential output driver can operate as two single -e nded cmos outputs. out0a, out0a and out1a , out1 a support only 1.8 v cmos operation. out0 b, out 0b and out1b, out1b support either 1.8 v or 3.3 v cmos operation. ad9559 data sheet rev. 0 | page 32 of 120 reference input physical connections four pairs of pins (refa, refa through refd, ref d ) provide access to the reference clock receivers. to accommodate input signals with slow rising and fa lling edges, both the differential and single - ended input receivers employ hysteresis. hysteresis also ensures that a disconnected or floating input does not cause the receiver to oscillate . when configured for differential operation, the input receivers a ccommodate either ac - or dc - coupled input signals. the input receivers are capable of accepting dc - coupled lvds and 2.5 v and 3.3 v lvpecl signals. the receiver is internally dc biased to handle ac - coupled operation, but there is no internal 50 ? or 100 ? termination. when configured for single - ended operation, the input receivers exhibit a pull - down load of 4 7 k? (typical). three user - programmable threshold voltage ranges are available for each single - ended receiver. see register 0x0300 to regis ter 0x037a for the settings for the reference inputs . reference monitors the accuracy of the input reference monitors depend s on a known and accurate system clock period. therefore, the functioning of the reference monitors is not operable until the syste m clock is stable. reference period monitor each reference input has a dedicated monitor that repeatedly measures the reference period. the ad9559 uses the reference period measurements to determine the validity of the r eference based on a set of user - provided parameters in the r eference input area of the register map . see register 0x0304 through register 0x030e for the settings for reference a. there are corresponding registers for reference b, c, and d. the mon itor works by com paring the measured period of a particular reference input with the parameters stored in the profile register assigned to that same reference input. the parameters include the reference period, an inner tolera nce, and an outer tolerance. a 40- bit number defines the reference period in units of femtoseconds (fs) . the 4 0- bit range allows for a refer ence period entry of up to 1.1 ms . a 20 - bit number defines the inner and outer tolerances. the value stored in the register is the reciprocal of t he tolerance spec ification. for example, a tolerance specification of 50 ppm yields a register value of 1/(50 ppm) = 1/0.000050 = 20,000 (0x04e20). the use of two tolerance values provides hysteresis for the monitor decision logic. the inner tolerance app lies to a previously faulted reference and specifies the largest period tolerance that a previously faulted reference can exhibit before it qualifies as un faulted. the outer tolerance applies to an already un faulted reference. it specifies the largest peri od tolerance t hat an un faulted reference can exhibit before being faulted. to produce decision hysteresis, the inner tolerance must be less than the outer tolerance. that is, a faulted reference must meet tighter requirements to become unfaulted than an un faulted reference must meet to become faulted. reference validation timer each reference input has a dedicated validation timer. the validation timer establishes the amount of time that a previously faulted reference must remain un fault ed before the ad9559 declare s that it is valid . the timeout period of the validation timer is programmable via a 16 - bit register ( address 0x 0 30f and address 0x0310 for reference a ) . the 16 - bit number stored in the validation registe r repr esents units of milliseconds (ms) , which yields a maximum timeout period of 65,535 ms. it is possible to disable the validation timer by programming the validation timer to 0. with the validation timer disabled, the user must validate a reference manually via the m anual r eference v alidation override controls register (address 0x0a02 ). reference validation override control the user can also override the reference validation logic, and can either force an invalid reference to be treated as valid, or for ce a valid reference to be treated as an invalid reference. these controls are in register 0x0a02 to register 0x0a0 3. reference input block unlike the ad9557 , t he ad9559 separates the dpll reference dividers from the feedback dividers. the reference input block includes the input receiver, the reference divider (r divider), and the reference input frequency monitor for each reference input. the reference input settings are grouped together in register 0x0300 to register 0x037a. these registers include the following settings : ? reference logic type (such as differential, single - ended) ? reference divider (20 - bit r divider value) ? reference input period and tolerance ? reference validation timer ? phase and frequency lock detector settings the reference prescaler reduces the frequency of this signal by an integer factor, r + 1, where r is the 20 - bit value stored in the appropriate profile register and 0 r 1,048,575. therefore, the freq uency at the output of the r divider (or the input to the time - to - digital converter, tdc) is as follows: 1 + = r f f r tdc after the r divider, the signal passes to a 4:2 crosspoint that allows any r eference input signal to go to either dpll. each dpll on the ad9559 has an independent set of feedback dividers for each reference input , and a description of these settings can be found in the digital pll (dpll) core section. data sheet ad9559 rev. 0 | page 33 of 120 the ad9559 evaluation software includes a frequency planning wizard that configure s the profile parameters , based on the input and output frequencies. reference switchove r an attractive feature of the ad9559 is its versatile reference switchover capability. the flexibility of the reference switchover functionality resides in a sophisticated prioritization algorithm that is couple d with register - based controls. this scheme provides the user with maximum control over the state machine that handles reference switchover. the main reference switchover control resides in the user mode registers in the pll_0/pll_1 operational controls re gisters. the reference switch ing mode bits ( bits[4:2] in register 0x0a 22 for d pll_0 and register 0x0a42 for dpll_1) allow the user to select one of the f ive operating modes of the reference switchover state ma chine , as follows: ? automatic revertive mo de ? aut omatic non revertive mode ? manual with a utomatic f allback mod e ? manual with automatic h oldover mod e ? full manual mode without holdover in the automatic modes, a fully automatic priority - based algorithm selects the active reference. when programmed for an autom atic mode, the device chooses the highest priority valid reference. when two or more references have the same priority, refa has preference over refb, and so on in alphabetical order . however, the reference position is used only as a tie breaker and does no t initiate a reference switch. the following list gives an overview of the five operating modes: ? automatic revertive mode. t he device selects the highest priority valid reference and switches to a higher priority reference if it becomes available, even if the reference in use is still valid. in this mode, the user reference is ignored. ? a utomatic non revertive mode. t he device stays with the currently selected reference as long as it is valid, even if a higher priority reference becomes available. the u ser r eference is ignored in this mode. ? manual with a utomatic fallback mode. t he device uses the user reference for as long as it is valid. if it becomes invalid, the reference input with the highest priority is chosen in accordance with the priority - based algor ithm. ? manual with automatic holdover mode. t he user reference is the active reference until it becomes invalid. at that point, the device automatically goes into holdover. ? full m anual mode without holdover. t he user reference is the active reference , rega rdless of whether or not it is valid. the user also has the option to force the device directly into holdover or free run operation via the user holdover and us er free run bits . in free run mode, the free run frequency tuning word register defines the fre e run output frequency. in holdover mode, the output frequency depends on the holdover control settings (see the holdover section). phase build - out reference switching the ad9559 suppo rts phase build - out reference switching, which is the term given to a reference switchover that completely masks any phase difference between the previous reference and the new reference. that is, there is virtually no phase change detectable at the output when a phase build - out switchover occurs. ad9559 data sheet rev. 0 | page 34 of 120 digital pll (dpll) c ore dpll overview d iagram s of th e d pll core s of the ad9559 (dpll_ 0 and dpll_1 ) are shown in figure 35 and figure 36 , respectively . the blocks shown in these diagrams are purely digit al . the start of the dpll signal chain is the reference signal, f r , which has been divided by the r divider and then routed through the crosspoint switch to the dpll. the frequency of this signal, f tdc , is: 1 + = r f f r tdc this is the frequency used by the time - to - digital converter, tdc , inside the dpll. a tdc samples the output of the r divider. the tdc/pfd produces a time series of digital words and delivers them to the digital loop filter. the digital loop filter offers the following: ? the d etermination of the filter response by numeric coefficients rather than by discrete component values ? the absence of analog components (r/l/c), which eliminates tolerance v ariations due to aging ? the absence of thermal noise associated with analog components ? the absence of control node leakage current associated with analog components (a source of reference feed - through spurs in the output spectrum of a traditional apll) the digital loop filter produces a time series of digital words at its output and delivers them to the frequency tuning input of a sigma - delta ( - ) modulator. the digital words from the loop filter steer the sdm frequency toward frequency and phase lock with the input signal ( f tdc ). each dpll includes a feedback divider that causes the digital loop to operate at an integer - plus - fractional multip le. the output of the dpll is ? ? ? ? ? ? ++= mod frac nf f tdc dpll out )1( _ w here n is the 17 - bit value stored in the appropriate profile registers (register 0x0 44 0 to register 0x0 44c for dpll_0 refa). frac and mod are the 24 - bit numerators and denominators of the fractional feedback divider block. the fractional portion of the feedback divider can be bypassed by setting frac to 0. mo d can be set to 0 , but never change mod from 0 to nonzero without first entering free run mode. note that there are two dplls. in the register map and register map bit descriptions sections, n0, frac0, and mod0 are used for dpll_0; n1, frac1, and mod1 are used for dpll_1 . for optimal performance, t he dpll output frequency is typic ally 175 mhz to 200 mhz. tdc/pfd the phase frequency detector (pfd) is an all - digital block. it compares the digital output from the tdc (which relates to the active reference edge) with the digital word from the feedback block. it uses a digital code pump and digital integr ator (rather than a conventional charge pump and capacitor) to generate the error signal that steers the sdm frequency toward phase lock. digital loop filter n0 24-bit/24-bit resolution frac0/ mod0 17-bit integer tuning word clamp and history 2 free run tw + 30-bit nco dpfd system clock from apll_0 to apll_0 10644-137 r divider (20-bit) ref input mux ref input figure 35 . d pll _0 core digital loop filter n1 24-bit/24-bit resolution frac1/ mod1 17-bit integer tuning word clamp and history 2 free run tw + 30-bit nco dpfd system clock from apll_1 to apll_1 10644-136 r divider (20-bit) ref input mux ref input figure 36 . d pll _1 core data sheet ad9559 rev. 0 | page 35 of 120 programmable di gital loop filter the ad9559 loop filter is a third - order digital iir filter that is analogous to the third order analog filter shown in figure 37 . c 3 c 2 c 1 r 2 r 3 10644-015 figure 37 . t hird order analog loop filter the ad9559 has default loop filter coefficients for two dpll settings: nominal (70 ) phase margin, and high (88 .5 ) phase margin. the high phase margin setting is intended for applic ations that require < 0.1 db of closed - loop peaking. while these settings do not normally need to be changed, the user can contact analog devices , inc. for a tool to calculate new coefficients to tailor the loop filter to specific requirements. the ad9559 loop filter block features a simplified architecture in which the user enters the desired loop characteristics (such as loop bandwidth) directly into the dpll registers. this architecture makes the calculation of individual coefficients unnecessary in most cases, while still offering complete flexibility. to change a digital loop filter coefficient on a profile that is cur - rently in use, the user must momentarily break the loop for the new setting to take effect. t he user can do this by selecting free run or holdover mode, or by invalidating (and then revalidating) the reference input. dpll digitally controlled oscillator free run frequency the ad9559 uses a - modulator as a digitally controlled oscillator (dco). the dco free run frequency can be calculated from the follow ing equation : 30 _ 2 0 8 2 ftw f f sys freerun dco + = w her e ft w0 is the value in register 0x04 00 to register 0x0403 for dpll_0 (or register 0x0500 to register 0x0503 for dpll_1) , and f sys is the system clock frequency. see the system clock section for information on calculating the system clock frequency . adaptive clocking the ad9559 can support adaptive clocking applications such as asynchronous mapping and demapping. for t hese applications, the output frequency can be dynamically adjusted by up to 100 ppm from the nominal output frequency without manually breaking the dpll loop and reprogramming the part. the following registers are used in this function: ? register 0x0444 to register 0x0446 (dpll n 0 divider) ? register 0x0447 to register 0x 0449 (dpll frac 0 divider) ? register 0x044a to register 0x044c (dpll mod0 divider) note that the register values shown are for refa/dpll_0. there are corresponding registers for all referen ce input and dpll combinations. writing to these registers requires an io_update by writing 0x01 to register 0x0005 before the new values take effect. to make small adjustments to th e output frequency, the user can vary the frac (frac0 or frac1) and issue an io_update . t he advantage to using only frac to adjust the output frequency is that the d pll does not briefly enter holdover. therefore, the frac bit can be updated as quickly as t he phase detector frequency of the dpll. writing to the n (n0 or n1) and mod (m0 or m1) dividers allow s for larger changes to the output frequency. when the ad9559 detects a change in the n or mod value , it autom atically enter s and exit s holdover for a brief instant without any disturbance in the output f requency. this limit s how quickly the output frequency can be adapted. it is important to note that the amount of frequency adjustment is limited to 100 ppm befo re the output pll (apll) need s a recalibration. variations larger than 100 ppm are possible, but such variations may compromise the ability of the ad9559 to maintain lock over temperature extremes. it is also i mportant to remember that the rate of change in output frequency depend s on the dpll loop bandwidth. dpll phase lock detector the dpll contains an all - digital phase lock detector. the user controls the threshold sensitivity and hysteresis of the phase dete ctor via the profile registers. the phase lock detector behaves in a manner analogous to water in a tub (see figure 38 ). t he total capacity of the tub is 4096 units , with ?2048 denoting empty, 0 denoting the 50% point, and +2048 denoting full. the tub also has a safeguard to prevent overflow. furthermore, the tub has a low water mark at ? 1024 and a high water mark at +1024. to change the water level, the user adds water with a fill bucket or removes water with a drain bucket. the user specifies the size of the f ill and drain buckets via the 8- bit fill rate and drain rate values in the profile registers. 0 2048 ?2048 1024 ?1024 lock level unlock level locked unlocked previous state fill rate drain rate 10644-017 figure 38 . lock detector diagram the water level in the tub is what the lock detector uses to determin e the lock and unlock conditions. when the water level is below the low water mark (?1024), the detector indicates an unlock condition. conversely, when the water level is above the high water mark (+1024), the detector indicates a lock condition. when the water level is between the marks, the detector h olds its last condition. this concept appears graphically in figure 38, with an overlay of an example of the instantaneous water level (vertical) vs. time (horizontal) and the resulting lock/unlock states. ad9559 data sheet rev. 0 | page 36 of 120 during any given pfd p hase error sample, the detector either adds water with the fill bucket or removes water with the drain bucket (one or the other but not both). the decision of whether to add or remove water depends on the threshold level specified by the user. the phase lo ck threshold value is a 24 - bit number stored in the profile registers and is expressed in picoseconds. thus, the phase lock threshold extends from 0 ns to 65.535 ns and repre - sents the magnitude of the phase error at the output of the pfd. the phase lock detector compares each phase error sample at the output of the pfd to the programmed phase threshold value. if the absolute value of the phase error sample is less than or equal to the programmed phase threshold value, the detector control logic dumps one fill bucket into the tub. otherwise, it removes one drain bucket from the tub. note that it is the magnitude , relati ve to the phase threshold value , that dete rmines whether to fill or drain, and not the pol arity of the phase error sample. if more filling i s taking place than draining, the water level in the tub eventually rises above the high water mark (+1024), which causes the phase lock detector to indicate lock. if more draining is taking place than filling, the water level in the tub eventually falls b elow the low water mark (?1024), which causes the phase lock detector to indicate unlock. the ability to specify the threshold level, fill rate, and drain rate enables the user to tailor the operation of the phase lock detector to the statistics of the tim ing jitter associated with the input reference signal. note that whenever the ad9559 enters the free run or holdover mode, the dpll phase lock detector indicates an unlocked state . however , when the ad9559 performs a reference switch, the state of the lock detector prior to the switch is preserved during the transition period. dpll frequency lock detector the operation of the frequency lock detector is identical to that of the phase lock detector. the only difference is that the fill or drain decision is based on the period deviation between the reference and feedback signals of the dpll instead of the phase error at the output of the pfd. the frequency lock detector uses a 24 - bit frequency threshold register specified in units of picoseconds. thus, the frequency threshold value extends from 0 s to 16.777215 s. it represents the magnitude of the difference in period between the reference and feedback signals at the inp ut to the dpll. for example, if the divided down reference signal is 80 k hz and the feedback signal is 79 .32 k hz, the period di fference is approximately 75.36 ns (|1/ 80 ,000 ? 1/ 79,320 | 107.1 6 ns). frequency clamp the ad9559 digital pll features a digital tuning wor d clamp that ensures that the digital pll output f requency stays within a defined range. this feature is very useful to eliminate undesirable behavior in cases where the reference input clocks may be unpredict able. the tuning word clamp is also useful to guaran tee that the apll never loses lock by ensurin g that the apll vco frequency stays with in its tuning range. frequency tuning word history the ad9559 has the ability to track the history of the tuning word samples generated by the dpll digital loop filter out put. it does so by periodically computing the average tuning word value over a user - specified interval. this average tuning word is used during holdover mode to maintain the average frequency when no input references are present. loop control state machine switchover switchover occurs when the loop controller switches directly from one input reference to another. t he ad9559 handles a reference switchover by briefly entering holdover mode , loading the new dpll para meters, and then immediately recovering. during the switchover event, however, the ad9559 preserves the status of the lock detectors to avoid phantom unlock indications. holdover the holdover state of the dpll is typically used when none of the input references are present, although the user can also manually engage holdover mode. in holdover mode , the output frequency remains constant . the accuracy of the ad9559 in hold over mode is dependent on the device programming and availability of tuning word history. recovery from holdover when in holdover and a valid reference becomes available, the device exits holdover operation. the loop state machine restores the dpll to clos ed - loop operation, locks to the selected reference , and sequences the recovery of all the loop parameters based on the profile settings for the active reference. note that, if the user hol dover bit is set, the device does not automatically exit holdover when a valid reference is available. however, automatic recovery can occur after clearing the user holdover bit. data sheet ad9559 rev. 0 | page 37 of 120 system clock (sys clk) sysclk inputs functional description the sysclk circuit provides a low jitter, stable, high frequency clock for use by th e rest of the chip. the xoa and xob pins connect to the internal sysclk multiplier. the sysclk multiplier can synthesize the system clock by connecting a c rystal resonator across the xoa and xob input pins or by connecting a low frequency clock source. the optimal signal for the system clock input is either a crystal in the 50 mhz range or an ac - coupled square wave with a 1 v p - p amplitude. sysclk period for the ad9559 to accurately measure the frequency of incomi ng reference signals, the user must enter the system clock period into the nominal system clock period registers (register 0x0202 to register 0x0204). the sysclk period is entered in units of femt oseconds (fs). choosing the sysclk source there are two inte rnal paths for the sysclk input signal: low frequency non - xtal) (lf) and crystal resonator (xtal). using a tcxo for the system clock is a common use for the lf path. applications requiring dpll loop bandwidths of less than 50 hz or high stability in holdov er require a tcxo or ocxo . as an alternative to the 49.152 mhz crystal for these applications, t he ad9559 reference design uses a 19.2 mhz tcxo, which offers excellent holdover stability and a good combination of low jitter and low spurious content . the 1.8 v differential receiver connected to the xoa and xob pins is self - biased to a dc level of ~1 v, and ac coupling is strongly recommended to maintain a 50% input duty cycle. when a 3.3 v cmos oscillator is in use , it is important to use a voltage divider to reduce the input high voltage to a maximum of 1.8 v. see figure 33 for details on connecting a 3.3 v cmos tcxo to the system clock input. the non - xtal) input path permits the user to p rovide an lvpecl, lvds, 1.8 v cmos, or sinusoidal low frequency clock for multiplication by the integrated sysclk pll. the lf path handles input frequencies from 10 mhz up to 100 mhz. however, when using a sinusoidal input signal, it is best to use a frequ ency of 20 mhz. otherwise, the resulting low slew rate can lead to poor noise performance. note that there is an optional 2 frequency multiplier to double the rate at the input to the sysclk pll and potentially reduce the pll in - band noise. however, to avoid exc eeding the maximum pfd rate of 150 mhz, the 2 frequency multiplier is only for input frequencies that are below 75 mhz. the non - xtal) path also includes an input divider (m) that is pro grammable for divide - by -1, -2, - 4, or - 8. the purpose of the divider i s to limit the frequency at the input to the plls to less than 150 mhz (the maximum pfd rate). the xtal path enables the connection of a crystal resonator (typically 10 mhz to 50 mhz) across the xoa and xob pins. an internal amplifier provides the negative resistance required to induce oscillation. the internal amplifier expects an at cut, fundamental mode crystal with a maximum motional resistance of 100 . the following crystals, listed in alphabetical order, may meet these criteria. analog devices does n ot guarantee their operation with the ad9559 , nor does analog devices endorse one crystal supplier over another. the ad9559 reference design uses a 49.152 mhz crystal, which is high performance, low spurious content, and readily available. ? avx/kyocera cx3225sb ? ecs ecx - 32 ? epson/toyocom tsx - 3225 ? fox fx3225bs ? ndk nx3225sa ? siward sx - 3225 ? suntsu scm10b48 - 49.152 mhz sysclk multiplier the sysclk pll multiplier is an integer - n d esign with an integrated vco. it provides a means to convert a low frequency clock input to the desired system clock frequency, f sys (750 mhz to 805 mhz). the sysclk pll multiplier accepts input signals of between 10 mhz and 4 00 mhz, but frequencies that a re in excess of 150 mhz require the j1 divider of the system clock to ensure compliance with the maximum pfd rat e (150 mhz). the pll contains a feedback divider ( k ) that is programmable for divide values between 4 and 255. jdiv sysclk kdiv sysclk ff osc sys _ _ = w here : f o sc is the frequency at the xoa and xob pins. sysclk_ k div is the value stored in register 0x02 00. sysclk_ j div is the system clock j1 divider that is determined by the setting of register 0x0 2 01[2:1]. if the system clock doubler is used, the value of syscl k_ k div should be half of its original value. the system clock multiplier features a simple lock detector that compares the time difference between the reference and feedback edges. the most common cause of the sysclk multiplier not locking is a non - 50% dut y cycle at the sysclk input while the system clock doubler is enabled. ad9559 data sheet rev. 0 | page 38 of 120 system clock stability timer because the reference monitors depend on the system clock being at a known frequency, it is important that the system clock be stable before activating the monitors. at initial power - up, the s ystem clock status is not known; therefore, it is reported as being unstable. after the part has been programmed , the system clock pll eventually locks. when a stable operating condition is detected, a timer is run for the duration that is stored in the system clock stability period registers. if , at any time during this waiting period, the condition is violated, the timer is reset and halted until a stable condition is reestablished. after the specified period elapses , the ad9559 reports the system clock as stable. note that , any time the system clock stability timer is changed in register 0x0205 through register 0x0207, it is reset automatically. the system clock stability ti mer starts counting when the next io_udate is issued. data sheet ad9559 rev. 0 | page 39 of 120 output pll (apll) the re are two output pll s (aplls ) on the ad9559 . they provide the frequency up conversion from the digital pll ( dpll ) output s. the frequency range is 2940 m hz to 3543 m hz for the apll_0 and 3405 mhz to 4260 m hz for the apll_1, while also providing noise filter on the d pll output. the apll reference input is the output of the dpll. the feedback divider is an integer divider. the loop filter is partially integrated with the one external 6.8 nf capacitor that connects to an internal ldo. the nominal loop bandwidth for both of the a pll s is 24 0 khz. the apll _0 and apll_1 block diagram s are shown in figure 39 and figure 40 , respectively . 10644-138 lf_0 cap lf_0 pin vco_0 3405mhz to 4260mhz pfd from dpll_0 to p0 divider lf cp integer divider output pll divider (apll_0) n0 11 ldo_0 pin 10 figure 39 . a pll _0 block diagram 10644-140 vco_1 3405mhz to 4260mhz pfd from dpll_1 to p1 divider lf cp integer divider output pll divider (apll_1) n1 lf_1 cap lf_1 pin 44 ldo_1 pin 45 figure 40 . a pll _1 block diagram apll configuration the frequency wizard that is included in the evaluation software configure s the a pll, and the user should not need to make changes to the apll settings . however, there may be special cases where the user may wish to adjust the apll loop bandwidth to meet a specific phase noise requirement. the easiest way to change the apll loop bandwidth is to adjust the apll charg e pump current in register 0x042 0 ( apll_0) or register 0x0520 ( apll _1) . there is sufficient stability ( 68 of phase margin) in the apll default settings to permit a broad range of adjustment without causing the apll to be unstable. the user should contact analog devices directly if more information is needed. apll calibration calibration of the a pll s must be performed at start up and whenever the nominal input f requency to the apll changes by more than 100 ppm, althou gh the a pll maintain s lock over voltage and temperature extremes without recalibration . calibration centers the dc operating voltage at the input to the apll vco. apll c alibration at start up is normally performed during initial register loading by followi ng the instructions in the device register programming using a register setup file section of this datasheet. to recalibrate the apll vco after the chip has been running, first input the new settings (if any). e nsure that the system clock is still locked and stable, and that the dpll is in free run mode with the free run tuning word set to the same output frequency that is used when the dpll is locked. the user can calibrate apll_0 without disturbing apll_1 and v ice versa. use the following steps to re calibrate the apll vco. important: an io_update (r egister 0x0005 = 0x01) is needed after each of these steps. 1. ensure that the sy stem clock is locked and stable . (register 0x0d01[1] = 1b). 2. ensure that t he dpll free run tuning word is set. dpll_0: register 0x0400 to register 0x0403 dpll_1: register 0x0500 to register 0x0503 3. set free run mode for the appropriate dpll . dpll_0: register 0x0a22[0] = 1b dpll_1: register 0x0a42[0] = 1b 4. clear apll calibration bit. apll_0: r egi ster 0x0 a20 = 0x00 apll_1: regi ster 0x0a 40 = 0x00 5. set apll calibration bit. apll_0: regi ster 0x0a20 = 0x02 apll_1: regi ster 0x0a 40 = 0x02 6. poll the apll lock status . apll_0: register 0x0d20 [3] = 1b indicates lock. apll_1: register 0x0d40 [3] = 1b indicate s lock. 7. clear the dpll mode for the appropriate dpll . dpll_0: register 0x0a22[0] = 0b dpll_1: register 0x0a42[0] = 0b ad9559 data sheet rev. 0 | page 40 of 120 clock distribution 10644-139 from vco_0 (2940mhz to 3543mhz) chip reset sync 10-bit integer 262khz to 1.25ghz channel sync block max 1.25ghz max 1.25ghz channel sync (to q0 _a and q 0 _ b) out0a out0a out0b out0b p0 divider 10-bit integer q0 _a q0 _b figure 41 . clock distribution block diagram from vco_0 from vco_1 (3405mhz to 4260mhz) chip reset sync 10-bit integer 302khz to 1.25ghz 10-bit integer channel sync block max 1.25ghz max 1.25ghz channel sync (to q1 _a and q1 _b ) out1a out1a out1b out1b 10644-141 q1 _a q1 _b figure 42 . clock distribution block diagram from vco_1 the ad9559 has two identical clock distribution sections: one for pll_0 from vco_0 and the other for pll_1. see figure 41 for a diagram of the clock distribution block for pll_0 and figure 42 for the pll_1 block. clock dividers p0 and p1 dividers the first block in each clock distribution section is the p divider. the p divider divides the vco output frequency dow n to a maximum frequency of 1.25 ghz and has special circuitry to maintain a 50% duty cycle for any divide ratio. the following register addresses contain the p divider settings: ? pll_0, p0 divider : register 0x0424[3:0] ? pll_1, p1 divider : register 0x0524[ 3:0] channel dividers the channel divider blocks, q0_a, q0_b, q1_ b, and q1_ a, are 10- bit integer dividers with a divide range of 1 to 1024 . the channel divider block contains duty cycle correction that guarantees 50% duty cycle for both even and odd divide ratios. the maximum input frequency to the channel dividers is 1.25 ghz. the channel dividers are at the following register addresses: ? q0 _ a divider: register 0x042 8 to register 0x042a ? q0 _ b divider : register 0x042c to register 0x042e ? q1 _ a divider: registe r 0x052 8 to register 0x052a ? q1 _b divider: register 0x052c to register 0x052e output enable each of the output channels offers independent control of enable / disable functionality via the distributi on enable register . the distribution outputs use synchroni zation logic to control enable/disable activity to avoid the production of runt pulses and to ensure that outputs with the same divide ratios become active/inactive in unison. output mode and power - down the output drivers can be individually powered down. the output mode control (including power - down) can be found at the following register addresses: ? out0a: register 0x0427[6:4] ? out0b: register 0x042b[7:4] ? out1a: register 0x0527[6:4] ? out1b: register 0x052b[7:4] the operating mode control includes ? logic type and pin function ? output drive strength ? output polarity ? divide ratio ? phase of each output channel out0b and out1 b provide the 3.3 v cmos, 1.8 v cmos, lvds, and hstl modes. out0a and out1 a provide the 1.8 v cmos, lvds, and hstl modes. data sheet ad9559 rev. 0 | page 41 of 120 the 3.3 v cmos drivers feature a cmos drive strength that allows the user to choose between a strong, high performance cmos driver or a lower power setting with less emi and crosstalk. the best setting is application dependent. ? all outputs have an lvds boost mode that provid es increased output amplitude in applications that require it. ? for applications where lvpecl levels are required, the user should choose the hstl mode and then ac - couple the output signal. see the input/output termination recomme ndations section for recommended termination schemes. clock distribution synchronization divider synchronization the dividers in the channels can be synchronized with each other. at pow er - up , they are held static until a sync signal is initiated through serial port, eeprom event, dpll locked sync , or a reference edge - initiated sync. this provides time for program - ming the dividers and for the dpll to lock before the outputs are enabled. a user - initiated sync signal can also be supplied to the divi ders at any time (as a manual synchronization) using an m pin. a channel can be programmed to ignore the sync function . when programmed to ignore the sync, the channel sync block issues a sync pulse immediately, and the channel ignores all other sync signal s. the digital logic trigger s a sync event from one of the following sources: ? register programming through serial port ? eeprom programming ? a multi function pin configured for the sync signal ? other automatic conditions determined by the dpll configuration: dpll lock or feedback divider pulse ad9559 data sheet rev. 0 | page 42 of 120 status and control multifunction pins (m0 to m5) the ad9559 has six digital cmos i/o pins (m0 to m5) that are configurable for a variety of uses. to use these functions, the user must set them by writing to register 0x0100 and register 0x0101. the function of these pins is programmable via the register map. each pin can control or monitor an assortment of internal functions based on register 0x0102 to register 0x0107. the m pins feature a special write detection logic that prevents them from behaving unpredictably when their function changes. when the when the user writes to these registers, the existing m pin function stops. the new m pin function takes effect on the next io_update (register 0x0005 = 0x01). the m4 and m5 pins are multiplexed with serial port functions. for the m4/sdo pin to function as m4, the ad9559 must not be in 4-wire spi mode. for the m5/ cs pin to function as m5, either i2c or 2-wire spi mode must be in use. the m pins operate in one of four modes: active high cmos, active low cmos, open-drain pmos, and open-drain nmos. 00active high cmos: the m pin is logic 0 when deasserted and logic 1 when asserted. this is the default operating mode. 01active low cmos: the m pin is logic 1 when deasserted and logic 0 when asserted. 10open-drain pmos: the m pin is high impedance when deasserted and active high when asserted; it requires an external pull-down resistor. 11open-drain nmos: the m pin is high impedance when deasserted and active low when asserted; it requires an external pull-up resistor. to monitor an internal function with a multifunction pin, write a logic 1 to the most significant bit of the register associated with the desired multifunction pin. the value of the seven least significant bits of the register defines the control function, as shown in table 196. to control an internal function with a multifunction pin, write a logic 0 to the most significant bit of the register associated with the desired multifunction pin. the monitored function depends on the value of the seven least significant bits of the register, as shown in table 197. if more than one multifunction pin operates on the same control signal, internal priority logic ensures that only one multifunction pin serves as the signal source. the selected pin is the one with the lowest numeric suffix. for example, if both m0 and m3 operate on the same control signal, m0 is used as the signal source and the redundant pins are ignored. at power-up, the multifunction pins can force the device into certain configurations as defined in the multifunction pins at reset/power-up section. this behavior is valid only during power-up or following a reset, after which the pins can be reconfigured via the serial programming port or via the eeprom. irq function the ad9559 irq function can be assigned to any m pin. there are three irq categories: pll0, pll1, and common. this means an m pin can be set to respond only to irqs that relate to pll0, pll1, or to common functions. an m pin can also be set to respond to all irqs. the ad9559 asserts the irq pin when any bit in the irq monitor register (address 0x0d08 to address 0x0d10) is a logic 1. each bit in this register is associated with an internal function that is capable of producing an interrupt. furthermore, each bit of the irq monitor register is the result of a logical and of the associated internal interrupt signal and the corresponding bit in the irq mask register (address 0x010a to address 0x0112). that is, the bits in the irq mask register have a one-to-one correspondence with the bits in the irq monitor register. when an internal function produces an interrupt signal and the associated irq mask bit is set, the corresponding bit in the irq monitor register is set. be aware that clearing a bit in the irq mask register removes only the mask associated with the internal interrupt signal. it does not clear the corresponding bit in the irq monitor register. the irq function is edge-triggered. this means that if the condition that generated an irq (for example, loss of dpll_0 lock) still exists after an irq is cleared, the irq does not reactivate until dpll_0 lock is restored and lost again. however, if the irqs are enabled when dpll_0 is not locked, an irq is generated. the irq function of an m pin is the result of a logical or of all the irq monitor register bits. the ad9559 asserts an irq as long as any of the irq monitor register bits is a logic 1. note that it is possible to have multiple bits set in the irq monitor register. therefore, when the ad9559 asserts an irq, it may indicate an interrupt from several different internal functions. the irq monitor register provides a way to interrogate the ad9559 to determine which internal function(s) produced the interrupt. typically, when the ad9559 asserts an irq, the user interrogates the irq monitor register to identify the source of the interrupt request. after servicing an indicated interrupt, the user should clear the associated irq monitor register bit via the irq clearing register (address 0x0a05 to address 0x0a0e). the bits in the irq clearing register have a one-to-one correspondence with the bits in the irq monitor register. note that the irq clearing registers are autoclearing. the m pin associated with an irq remains asserted until the user clears all of the bits in the irq monitor register that indicate an interrupt. data sheet ad9559 rev. 0 | page 43 of 120 all irq monitor register bits can be cleared by setting the clear all irqs bit in the irq register (register 0x0a05). note that the bits in register 0x0a05 are autoclearing. setting bit 0 results in the deassertion of all irqs. alternatively, the user can program any of the multifunction pins to clear all irqs, which allows the user to clear all irqs by means of a hardware pin rather than by a serial i/o port operation. watchdog timer the watchdog timer is a general-purpose programmable timer. to set the timeout period, the user writes to the 16-bit watchdog timer register (address 0x0108 to address 0x0109). a value of 0x0000 in this register disables the timer. a nonzero value sets the timeout period in milliseconds, giving the watchdog timer a range of 1 ms to 65.535 sec. the relative accuracy of the timer is approximately 0.1% with an uncertainty of 0.5 ms. if enabled, the timer runs continuously and generates a timeout event when the timeout period expires. the user has access to the watchdog timer status via the irq mechanism and the multifunction pins (m0 to m3). the m4 and m5 multifunction pins are available if they are not used for the serial port. in the case of the multifunction pins, the timeout event of the watchdog timer is a pulse that lasts 32 system clock periods. there are two ways to reset the watchdog timer (thereby preventing it from causing a timeout event). the first method is to write a logic 1 to the autoclearing clear watchdog timer bit in the clear irq groups register (register 0x0a05, bit 7). alternatively, the user can program any of the multifunction pins to reset the watchdog timer. this allows the user to reset the timer by means of a hardware pin rather than by a serial i/o port operation. eeprom eeprom overview the ad9559 contains an integrated 2048-byte, electrically erasable, programmable read-only memory (eeprom). the ad9559 can be configured to perform a download at power-up via the multifunction pins (m1 and m0), but uploads and downloads can also be performed on demand via the eeprom control registers (address 0x0e00 to address 0x0e03). the eeprom provides the ability to upload and download configuration settings to and from the register map. figure 43 shows a functional diagram of the eeprom. register 0x0e10 to register 0x0e4f represent a 64-byte eeprom storage sequence area (referred to as the scratchpad in this section) that enables the user to store a sequence of instructions for transferring data to the eeprom from the device settings portion of the register map. note that the default values for these registers provide a sample sequence for saving/retrieving all of the ad9559 eeprom-accessible registers. figure 43 shows the connectivity between the eeprom and the controller that manages data transfer between the eeprom and the register map. the controller oversees the process of transferring eeprom data to and from the register map. there are two modes of operation handled by the controller: saving data to the eeprom (upload mode) or retrieving data from the eeprom (download mode). in either case, the controller relies on a specific instruction set. eeprom (0x000 to 0x7ff) data data dat a eeprom address pointer register map device settings scratch pad (0x0e10 to 0x0e4f) serial input/output port condition 0x0e01[3:0] eeprom controller m1 m0 device settings address pointer scratch pad address pointer 10644-024 figure 43. eeprom fu nctional diagram ad9559 data sheet rev. 0 | page 44 of 120 eeprom instructions table 22 lists the eeprom controller instruction set. the controller recognizes all instruction types whether it is in upload or download mode, except for the pause instruction, which is only recognizes in upload mode. the io_update , calibrate, distribution sync, and end instruct - tions are, for the most part, self - explanatory. the others, however, warrant further det ail, as described in the following paragraphs. data instructions are those that have a value from 0x00 to 0x7f . a data instruction tells the controller to transfer d ata between the eeprom and the register map. the controller needs the following two parameters to carry out the data transfer: ? the number of bytes to transfer ? the register map target address table 22 . eeprom controller instruction set instruction value (hex) instruction type bytes needed description 0x 00 to 0x 7f data 3 a data instruction tells the controller to transfer data to or from the device settings part of the register map. a data instruction requires two additional bytes that , together , indicate a starting address in the register map. encoded in the data instruc tion is the number of bytes to transfer, which is one more than the instruction value. 0x80 io_update 1 t he controller issues a soft io_update (which is analogo us to the user writing register 0x0005 = 0x01) . 0x90 calibrate both aplls 1 t he controller initiates an apll calibration sequence to both apll_0 and apll_1 while downloading from the eeprom. apll calibration is gated by the system clock being stable. 0x91 calibrate apll_0 1 when the controller encounters this instruction while downloading from the eeprom, it initiates a n apll_0 calibration sequence. apll calibration is gated by the system clock being stable. 0x92 calibrate apll_1 1 when the controller encounters this instruction while downloading from the eeprom, it initiates an apll_1 calibration sequence. apll calibration is gated by the system clock being stable. 0x98 set user free run mode (both plls) 1 when the controller encounters this instruction while downloading from the eeprom, it forces both of the dplls into user free run mode. 0x99 set user free run mode (dpll_0) 1 when the controller encounters this instruction while downloading from the eeprom, it forces both of the dpl ls into user free run mode. 0x9a set user free run mode (dpll_1) 1 when the controller encounters this instructio n while downloading from the eeprom, it forces both of the dplls into user free run mode. 0x a0 distribution sync (a ll outputs) 1 when the controller encounters this instruction while downloading from the eeprom, it issues a sync pulse to the pll0 and pll1 channel di viders. note that the apll_0 must be locked before the sync pulse reaches the pll_0 channel dividers, and apll_1 must be locked bef ore the sync pulse reaches the pll_1 channel dividers , unless overridden. 0xa1 distribution sync ( pll0 outputs) 1 when the controller encounters this instruction while downloading from the eeprom, it issues a sync pulse to the pll_0 channel dividers. note that , u nless overridden, t his sync pulse is gated by the apll_0 lock detect signal . 0xa2 distribution sync ( pll1 outputs) 1 when the controller encounters this instruction while downloadin g from the eeprom, it issues a sync pulse to the pll1 channel dividers. note that , unless overridden, this sync pulse is gated by the apll_ 1 lock detect signal . 0xb0 clear c ond ition 1 0x b0 is t he null condition instruction (s ee the eeprom conditional processing section ). 0x b1 to 0xbf condition 1 0x b1 t o 0xb f are condition instructions and correspond to condition 1 throu gh condition 15 , respectively ( s ee the eeprom conditional processing section) . 0x fe pause 1 when the controller encounters this instruction in the scratch pad while uploading to th e eeprom, it resets the scratch pad address pointer and holds the eeprom address pointer at its last value. this allows storage of more than one instruction sequence in the eeprom. note that the controller does not copy this instruction to the eeprom during upload. 0x ff end of data 1 when the controller encounters this instruction in the scr atch pad while uploading to the eeprom, it resets both the scratchpad address pointer and the eeprom address pointer and then enters an idle state. when the controller encounters this instruction while downloading from the eeprom, it resets the eep rom address pointer and then enters an idle state. data sheet ad9559 rev. 0 | page 45 of 120 the controller decodes the number of bytes to transfer directly from the data instruction itself by adding 1 to the value of th e instruction. for example, d ata instruction 0x1a has a decimal value of 2 6; therefore, the controller knows to transfer 27 bytes (one more than the value of the instruction). when the controller encounters a data instruction, it knows to read the next two bytes in the scratchpad because these contain the register map target add ress. note that, in the eeprom scratchpad , the two registers that comprise the address portion of a data instruction have the msb of the address in the d7 position of the lower register address. the bit weight increases left to right, from the lower regist er address to the higher register address. furthermore, the starting address always indicates the lowest numbered register map address in the range of bytes to transfer. that is, the controller always starts at the register map target address and counts up ward , regardless of whether the serial i/o port is operating in i 2 c, spi lsb - first, or spi msb - first mode. as part of the data transfer process during an eeprom upload, the controller calculates a 1 - byte checksum and stores it as the final byte of the dat a transfer. as part of the data transfer process during an eeprom download, however, the controller again calculates a 1 - byte checksum value but compares the newly calculated checksum with the one that was stored during the upload process. if an upload/dow nload checksum pair does not match, the controller sets the eeprom fault status bit. if the upload/download checksums match for all data instructions encountered during a download sequence, the controller sets the eeprom complete status bit. condition inst ructions are those that have a value from 0xb0 to 0x b f. the 0x b1 to 0x b f condition instructions represent condition 1 to condition 15 , respectively . the 0x b0 condition instruction is special because it rep resents the null condition (see the eeprom conditional processing section). a pause instruction, like an end instruction, is stored at the end of a sequence of instructions in the scratchpad . when the con - troller encounters a pause instruction during an upload sequence, it keeps the eeprom address pointer at its last value. then the user can store a new instruction sequence in the scratchpad and upload the new sequence to the eeprom. the new sequence is stored in the eeprom address locations immediately follow ing the previously s aved sequence. this process is repeatable until an upload sequence contains an end instruction. the pause instruction is also useful when used in conjunction with condition processing. it allows the eeprom to contain multiple occurrences of the same regist er s , with each occurrence linked to a set of conditions (see the eeprom conditional processing section). eeprom upload to upload data to the eeprom, the user must first ensure that the write enable bit (register 0x 0e00, bit 0) i s set. then, on setting the autoclearing save to eeprom bit (register 0x 0e02, bit 0), the controller initiates the eeprom data storage process. uploading eeprom data requires the user to first write an instruction sequence into the scratchpad registers. du ring the upload process, the controller reads the scratchpad data byte - by - byte, starting at register 0x 0e10 and incrementing the scratchpad address pointer , as it goes , until it reaches a pause or e nd instruction. as the controller reads the scratchpad da ta, it tr ansfers the data from the scratchpad to t he eeprom (byte - by - byte) and increments the eeprom address pointer accordingly, unless it encounters a data instruction. a data instruction tells the controller to transfer data from the device settings portion of the register map to the eeprom. the number of bytes to transfer is encoded within the data instruction, and the starting address for the transfer appears in the next two bytes in the scratchpad . when the controller encounters a data instruction, i t stores the instruction in the eeprom, increments the eeprom address pointer, decodes the number of bytes to be transferred, and increments the scratchpad address pointer. then it retrieves the next two bytes from the scratchpad (the target address) and i ncrements the scratchpad address pointer by 2. next, the controller transfers the specified number of bytes from the register map (beginning at the target address) to the eeprom. when it completes the data tra nsfer, the controller stores an extra byte in the eeprom to serve as a checksum for the transferred block of data. to acc ount for the checksum byte, the controller increments the eeprom address pointer by one more than the number of bytes transferred. note that, when the controller transfers data asso ciated with an active register, it actually transfers the buffered contents of the register (refer to the buffered/active registers section for details on the difference between buffered and active registers). this allows for th e transfer of nonzero autoclearing register contents. note that conditional processing (see the eeprom conditional processing section) does not occur during an upload sequence. manual eeprom download an eeprom download results i n data transfer from the eeprom to the device register map. to download data, the user sets the autoclearing load from eeprom bit (register 0x 0e03, bit 1). this commands the controller to initiate the eeprom download process. during download, the controlle r reads the eeprom data byte by byte, incrementing the eeprom address pointer as it goes, until it reaches an end instruction. as the controller reads the eeprom data, it executes the stored instructions, which includes transferring stored data to the devi ce settings portion of the register map whenever it encounters a data instruction. note that conditional processing (see the eeprom conditional processing section) is applicable only when downloading. ad9559 data sheet rev. 0 | page 46 of 120 automatic eeprom download following a power - up, an assertion of the reset pin, or a soft reset (register 0x 0000, bit 5 = 1), if either the m1 pin or m0 pin is high (see tabl e 23 ), the instruction sequence stored in the eeprom executes a utomatically with one of three condition s. if m1 and m0 are low , the eeprom is bypassed and the factory defaults are used. in this way, a previously stored set of register values downloads automatically on power - up or with a hard or soft reset. see the eeprom conditional processing section for details regarding conditional processing and the way it modifies the download process. table 23 . eeprom download m pin setup m1 m0 id eeprom download 0 0 0 no 0 1 1 yes, eeprom condition 1 1 0 2 yes, eeprom condition 2 1 1 3 yes, eeprom condition 3 eeprom conditional processing the condition instructions allow conditional execution of eeprom instructions during a download sequence. during an upload sequence, ho wever, they are stored as is and have no effect on the upload process. note that, during eeprom downloads, the condition instructions themselves and the end instruction always execute unconditionally . conditional processing makes use of two elements: the condition ( from condition 1 to condition 15 ) and the condition tag board. the relationships among the condition, the condition tag board, and the eeprom controller appear schematically in figure 44 . eeprom eeprom controller upload procedure condition handler download procedure condition tag board 1 6 5 4 3 2 11 10 9 8 7 15 14 13 12 if 0xb1 instruction 0xcf, then tag decoded condition scratch pad m1 m0 if instruction = 0xb0, then clear all tags fncinit, bits[1:0] register 0x0e01, bits[3:0] store condition instructions as they are read from the scratch pad. watch for occurrence of condition instructions during download. if {no tags} or {condition = 0} execute instructions else if {condition is tagged} execute instructions else skip instructions endif endif 4 4 2 if {0x0e01, bits[3:0] 0} condition = 0x0e01, bits[3:0] else condition = fncinit, bits[1:0] endif example condition 3 and condition 13 are tagged execute/skip instruction(s) condition 10644-025 figure 44 . eeprom conditional processing data sheet ad9559 rev. 0 | page 47 of 120 the condition is a 4- bit value with 16 possibilities. condition = 0 is the null condition. when the null condition is in effect, the eeprom controller executes all instructions u nconditionally. the remaining 15 po ssibilities, cond ition = 1 through condition = 15 , modify the eeprom controllers handling of a download sequence. the condition originates from one of two sources (see figure 44 ), as follows: ? fncinit, bits[ 1:0 ], which is the st ate of the m 1 and m0 multifunction pins at power - up ( see table 23 ) (note that only condition 1 through condition 3 are accessible via the m pins.) ? register 0x 0e01, bits[3 :0] if register 0x 0e01, bits[ 3 :0] 0, then the condition is the value stored in register 0x 0e01, bits[ 3 :0]; otherwise, the condition is fncinit, bits[ 1:0 ]. note that a nonzero condition present in register 0x 0e01, bits[ 3:0], takes precedence over fncinit, bits[ 1:0 ]. the condition tag board is a table that is maint ained by the eeprom controller. when the controller encounters a condition instruct ion, it decodes the 0x b1 through 0xb f instructions as cond ition = 1 through condition = 15 , respectively, and tags that particular condition in the condition tag board. howe ver, the 0x b0 condition instruction decodes as the null condition, for which the controller clears the condition tag board, and subsequent download instructions execute unconditionally (until the controller encounters a new condition instruction). during d ownload, the eeprom controller executes or skips instructions depending on the value of the condition and the contents of the condition tag board. note, however, that condition instructions and the end instruction always execute unconditionally during download. if condition = 0, then all instructions during download execute unconditionally. if condition 0 and there are any tagged conditions in the condition tag board, then the controller executes instructions only if the condition is tagged. if the condition is not tagged, then the controller skips instructions until it encounters a condition instruction that decodes as a tagged condition. note that the condition tag board allows for multiple conditions to be tagged at any given moment. this conditional pr ocessing mechanism enables the user to have one download instruction sequence with many possible outcomes depending on the value of the condition and the order in which the controller encounters condition instructions. table 24 li sts a sample eeprom download instruction sequence. it illustrates the use of condition instructions and how they alter the download sequence. the table begins with the assumption that no conditions are in effect. that is, the most recently executed conditi on instruction is 0x b0 or no conditional instructions have been processed. table 24 . eeprom conditional processing example instruction action 0x08, 0x01, 0x00 transfer the system clock register contents regardless of the current condition. 0xb1 tag condition 1 0x19, 0x04, 0x00 transfer the clock distribution register contents only if tag condition = 1 0xb2 tag condition 2 0xb3 tag condition 3 0x07, 0x05, 0x00 transfer the reference input register contents only if tag conditi on = 1, 2, or 3 0x0a calibrate the system clock only if tag condition = 1, 2, or 3 0xb0 clear the tag condition tag board 0x80 execute an io_update, regardless of the value of the tag condition 0x0a calibrate the system clock regardless of the value of the tag condition storing multiple device setups in eeprom conditional processing makes it possible to create a number of different device setups, store them in eeprom, and download a specific setup on demand. to do so, first program the device control r egisters for a specific setup. then, store an upload sequence in the eeprom scratchpad with the following general form: 1. condition instruction ( 0x b1 to 0x b f) to identify the setup with a specific condition (1 to 15 ) 2. data instructions (to save the register c ontents) along with any required calibrate and/or io_update instructions 3. pause instruction ( 0x fe) with the upload sequence written to the scratchpad , set the write enable bit (register 0x0e00, bit 0) and perform an eeprom upload (register 0x 0e02, bit 0). r eprogram the device control registers for the next desired setup. then store a new upload sequence in the eeprom scratchpad with the following general form: 1. condition instruction ( 0xb0) 2. the next desired condition instruction ( 0x b1 to 0x b f, but different fr om the one used during the previous upload to identify a new setup) 3. data instructions (to save the register contents) along with any required calibrate and/or io_update instructions 4. pause instruction ( 0x fe) with the upload sequence written to the scratchpa d , perform an eeprom upload (register 0x 0e02, bit 0). ad9559 data sheet rev. 0 | page 48 of 120 repeat the process of programming the device control registers for a new setup, storing a new upload sequence in the eeprom scratchpad (step 1 through step 4), and executing an eeprom upload (register 0x 0e02, bit 0) until all of the desired setups have been uploaded to the eeprom. note that, on the final upload sequence stored in the scratchpad , the pause instruction ( 0x fe) must be replaced with an end instruction ( 0x ff). to download a specific setup on demand, first store the condition associated with the desired setup in register 0x0e01, bits[ 3 :0]. then perform an eeprom download (register 0x 0e03, bit 1). alternatively, to download a specific setup at power - up, apply the required logic levels necessary to encode the desired condition on the m 1 to m 0 multifunction pins. (note that only condition 1 through condition 3 are accessible via the m pins.) then power up the device; an automatic eeprom download occurs. the condition (as established by the m 1 and m0 multifunction pins) guides the download sequence and results in a specific setup. keep in mind that the number of setups that can be stored in the eeprom is limited. the eeprom can hold a total of 2048 bytes. each nondata instruction requires one byte of storage. each data instruction, however, requires n + 4 bytes of storage, where n is the number of transferred register bytes and the other four bytes include the data instruction itself (one byte ), the target address (two bytes), and the checksum calcu lated by the eeprom controller during the upload sequence (one byte). data sheet ad9559 rev. 0 | page 49 of 120 serial control port the ad9559 serial control port is a flexible, synchronous serial communications port that provides a convenient inte rface to many industry - standard microcontrollers and microprocessors. the ad9559 serial control port is compatible with most synchronous transfer formats, including i2c, motorola spi, and intel ssr protocols. the serial control port allows read/write access to the ad9559 register map. in spi mode, single or multiple byte transfers are supported. the spi port configuration is programmable via register 0x 0000. this regist er is integrated into the spi control logic rather than in the register map and is distinct from the i 2 c register 0x 0000. it is also inaccessible to the eeprom controller. although the ad9559 supports both the sp i and i 2 c serial port protocols, only one is active following power - up (as determined by the m3, m4/sdo, and m5/ cs multifunction pins during the start - up sequence). that is, the only way to change the serial port protocol is to rese t the device (or cycle the device power supply). spi/i2c port selecti on because the ad9559 supports both spi and i2c protocols, the active serial port protocol de pends on the logic state of m3 , m4/sdo, and the m 5/ cs pins. see table 25 for the i 2 c address assignments. note that t here are no internal pull - up or pull - down resistors on these pins. table 25 . spi/i2c serial port setup m3 m4/sdo m5/ cs spi/i2c address low dont care dont care spi high low low i2c, 1101000 high low high i2c, 1101001 high high low i2c, 1101010 high high high i2c, 11010 11 spi serial port operation pin descriptions the sclk (serial clock ) pin serves as the serial shift clock. this pin is an input. sclk synchronizes serial control port read and write operations. the rising edge sclk registers write data bits, and the falling edge registers read data bits. the sclk pin supports a maxi mum cl ock rate of 40 mhz. the sdio (serial data input/output) pin is a dual - purpose pin and acts either as an input only (unidirectional mode) or as both an input and an output (bidirectional mode). the ad9559 default spi mode is bidirectional. the sdo (serial data output) pin is useful only in unidirectional i/o mode. it serves as the data output pin for read operations. the e e a ( chip select) pin is an active low control that gates read and wr ite operations. this pin is internally connected to a 30 k? pull - up resistor. when a a cs e e aa is high, the sdo and sdio pins go into a high impedance state. cs spi mode operation the spi port supports both 3 - wire (bidirectional) and 4 - wire (unidirectional) hardware configurations and both msb - first and lsb - first data formats. both the hardware configuration and data format features are programmable. by default, the ad9559 uses the bidirectional msb - first mode. the reason that bidirectional is the default mode is so that the user can still write to the device, if it is wired for unidirectional operation, to switch to unidirectional mode. assertion (active low) of the a a cs e e aa pin initiates a write or read operation to the ad9559 spi port. for data transfers of three bytes or fewer (excluding the instruction word), the device supports the a a cs e e aa stalled high mode. in this mode, the a a cs e e aa pin can be temporarily deasserted on any byte boundary, allowing time for the system controller to process the next byte. a a cs e e aa can be deasserted only on byte boundaries, however. this appl ies to both the instruction and data portions of the transfer. during stall high periods, the serial control port state machine enters a wait state until all data is sent. if the system controller decides to abort a transfer midstream, the state machine mu st be reset by either completing the transfer or by asserting the a a cs e e aa pin for at least one complete sclk cycle (but less than eight sclk cycles). deasserting the a a cs e e aa pin on a nonbyte boundary terminates the serial transfer and flushes the buffer. in the streaming mode (see table 26 ), any number of data bytes can be transferred in a continuous stream. the register address is automatically incremented or decremented. a a cs e e aa must be deasserted at the end of the last byte transferred, thereby ending the stream mode. table 26 . byte transfer count w1 w0 bytes to transfer 0 0 1 0 1 2 1 0 3 1 1 streaming mode ad9559 data sheet rev. 0 | page 50 of 120 communication cycle instructi on plus data the ad9559 supports the long instruction mode only. the spi protocol consists of a two - part communication cycle. the first part is a 16 - bit instruction word that is coincident with the first 16 sclk rising edges and a payload. the instruction word provides the ad9559 serial control port with information regarding the payload. the instruction word includes the r/ a a w e e aa bit that indicates the direction of the payload transfer (that is, a read or write operation). the instruction word also indicates the number of bytes in the payload and the starting register address of the first payload byte. write if the instruction word indicates a write operation, the payload is written into the serial control port buffer of the ad9559 . data bits are registered on the rising edge of sclk. t he length of the transfer (1, 2, or 3 bytes or streaming mode) depends o n the w0 and w1 bits (see table 26 ) in the instruction byte. when not streaming, a a cs e e aa can be deasserted after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cyc le). when the bus is stalled, the serial transfer resumes when a a cs e e aa is asserted. deasserting the a a cs e e aa pin on a nonbyte boundary resets the serial control port. reserved or blank registers are not skipped over automatically during a write sequence. therefore, the user must know what bit pattern to write to the reserved registers to preserve proper operation of the part. generally, it does not matter what data is written to blank registers, but it is customary t o use 0s. most of the serial port registers are buffered (see the buffered/active registers section for details on the difference between buffered and active registers). therefore, data written into buffered registers does not t ake effect immediately. an additional operation is needed to transfer buffered serial control port contents to the registers that actually control the device. this is accomplished with an io_update operation, which is performed in one of two ways. one meth od is to write a logic 1 to register 0x 0005, bit 0 (this bit is an auto clearing bit ). the other method is to use an external signal via an appropriately programmed multifunction pin. the user can change as many register bits as desired before executing an io_update . the io_update operation transfers the buffer register contents to their active register counterparts. read if the instruction word indicates a read operation, the next n 8 sclk cycles clock out the data from the address specified in the instru ction word. n is the number of data bytes read and depends on the w0 and w1 bits of the instruction word. the readback data is valid on the falling edge of sclk. blank registers are not skipped over during readback. a readback operation takes data from ei ther the serial control port buffer registers or the active registers, as determined by register 0x 0004, bit 0. spi instruction word (16 bits) the msb of the 16 - bit instruction word is r/ a a w e e aa , which indicates whether the instruction is a read or a write. the next two bits, w1 and w0, indicate the number of bytes in the transfer (see table 26 ). the final 13 bits are the register address (a12 to a0), which indicates the starting register address of the read/ write operation (see table 28 ). spi msb - /lsb - first transfers the ad9559 instruction word and payload can be msb first or lsb first. the default for the ad9559 is msb first. the lsb - first mode can be set by writing a 1 to register 0x 0 000, bit 6. immed iately after the lsb - first bit is set, subsequent serial control port operations are lsb first. when msb - first mode is active, the instruction an d data bytes must be written from msb to lsb. multibyte data transfers in msb - first format start with an instruction byte that includes the register address of the most significant payload byte. subsequent data bytes must follow in order from high address to low address. in msb - first mode, the serial control port internal address generator decrements for each data byte of the multi - byte transfer cycle. when register 0x 0000, bit 6 = 1 (lsb first), the instruction and data bytes must be written from lsb to m sb. multibyte data transfers in lsb - first format start with an instruction byte that includes the register address of the least significant payload byte followed by multiple data bytes. the serial control port internal byte address generator increments for each byte of the multibyte transfer cycle. for multibyte msb - first (default) i/o operations, the serial control port register address decrements from the specified starting address toward address 0x 0000. for multibyte lsb - first i/o operations, t he serial control port register address increments from the starting address toward address 0x 1fff. reserved addresses are not skipped during multibyte i/o operations; therefore, the user should write the default value to a reserved register and 0s to unmapped regis ters. note that it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved (or unmapped) registers. table 27 . streaming mode (no addresses are skipped) write mode address direction stop sequence lsb first increment 0x00000x1fff msb first decrement 0x1fff0x0000 data sheet ad9559 rev. 0 | page 51 of 120 table 28 . serial control port, 16 - bit instruction word, msb first msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/ a a w e e w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 cs sclk don't care sdio a12 w0w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care don't care 16-bit instruction header register (n) data register (n ? 1) data 10644-029 figure 45 . serial control port write msb first, 16 - bit instruction, two bytes of data cs sclk sdio sdo register (n) data 16-bit instruction header register (n ? 1) data register (n ? 2) data register (n ? 3) data a12 w0w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 don't care don't care don't care don't care d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 10644-030 figure 46 . serial control port read msb first, 16 - bit instruction, four bytes of data t s don't care don't care w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 d4 d3 d2 d1 d0 don't care don't care r/w t ds t dh t high t low t clk t c cs sclk sdio 10644-031 figure 47 . serial control port write msb first, 16 - bit instruction, timing measurements data bit n ? 1 data bit n cs sclk sdio sdo t dv 10644-032 figure 48 . timing diagram for serial control por t register read cs sclk don't care don't care 16-bit instruction header register (n) data register (n + 1) data sdio don't care don't care a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d1d0r/w w1w0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 10644-033 figure 49 . serial control port write lsb first, 16 - bit instruction, two bytes of data ad9559 data sheet rev. 0 | page 52 of 120 cs sclk sdio t high t low t clk t s t ds t dh t c bit n bit n + 1 10644-034 figure 50 . serial control port timing write table 29 . serial control port timing parameter description t ds setup time between data and the rising edge of sclk t dh hold time between data and the rising edge of sclk t clk period of the clock t s setup time between the a a cs e e aa falling edge and the sclk rising edge (start of the communication cycle) t c setup time between the sclk rising edge and a a cs e e aa rising edge (end of the communication cycle) t high minimum period that sclk should be in a logic high state t lo w minimum period that sclk should b e in a logic low state t dv sclk to valid sdio and sdo (see figure 48 ) data sheet ad9559 rev. 0 | page 53 of 120 i2c serial port operation the i 2 c interface has the advantage of requiring only two control pins and is a de facto standard throughout the i 2 c industr y. ho wever , its disadvantage is programming speed, which is 400 kbps maximum. the ad9559 i2c port design is base d on the i2c fast mode standard ; it supports both the 100 khz standard mode and 400 khz fast mode. fast m ode imposes a glitch tolerance requirement on the control signals. that is, the input receivers ignore pulses of less than 50 ns duration. the ad9559 i2c port consists of a serial data line (sda) and a serial clock line (scl). in an i2c bus system, the ad9559 is connected to the serial bus (data bus sda and clock bus scl) as a slave device; that is, no clock is generated by the ad9559 . the ad9559 uses direct 16 - bit memory addressing instead of traditional 8 - bit memory addressing. the ad9559 allows up to seven unique slave devices to occupy the i 2 c bus. these are accessed via a 7 - bit slave address transmitted as part of an i 2 c packet. only the device with a matching slave address responds to subsequent i 2 c commands. table 25 lists t he supported device slave address es . i 2 c bus characteristics a summary of the various i 2 c abbreviations appears in table 30 . table 30. i 2 c bus abbreviation definitions abbreviation definition s start sr repeated start p stop a ackno wledge a a e e nonacknowledge a a w e write r read the transfer of data is shown in figure 51 . one clock pulse is generated for each data bit transferred. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can change only when the clock signal on the scl line is low. data line stable; data valid change of data allowed sda scl 10644-049 figure 51 . valid bit transfer start/stop functionality is shown in figure 52 . the start condition is characterized by a high - to - low transition on the sda line while scl is high. the start condition is always generated by the master to initialize a data transfer. the stop condition is characterized by a low - to - high transition on the sda line while scl is high. the stop condition is always generat ed by the master to terminate a data transfer. every byte on the sda line must be eight bits long. each byte must be followed by an acknowledge bit; bytes are sent msb first. the acknowledge bit (a) is the ninth bit attached to any 8 - bit data byte. an acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received. it is done by pulling the sda line low dur ing the ninth clock pulse after each 8 - bit data byte. the nonacknowledge bit ( a a e a ) is the ninth bit attached to any 8 - bit data byte. a nonacknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has not been received. it is done by leaving the sda line high during the ninth clock pulse after each 8 - bit data byte. data transfer process the master initiates data transfer by asserting a start condition. this indicates that a data stream follows. all i2c slave devices connected to the serial bus respond to the start condition. the master then sends an 8 - bit address byte over the sda line, consisting of a 7 - bit slave address (msb first) plus an r / a w e a bit. this bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). the peripheral whose address corresponds to the transmitted address responds by sending an acknowledge bit. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/ a w e a a bit is 0, the master (transmitter) writes to the slave device (receiver). if the r/ a a w e aa bit is 1, the master (receiver) reads from the slave device (transmitter). the format for these commands is described in the data transfer format section. data is then sent over the serial bus in the format of nine clock pulses, one data byte (eight bits) from either master (write mode) or slave (read mode) followed by an acknowledge bit from the receiving device. the number of bytes that can be transmitted per transfer is unrestricted. in write mode, the first two data bytes immedia tely after the slave address byte are the internal memory (control registers) address bytes, with the high address byte first. this addressing scheme gives a memory address of up to 2 16 ? 1 = 65,535. the data bytes after these two memory address bytes are register data written to or read from the control registers. in read mode, the data bytes after the slave address byte are register data written to or read from the control registers. ad9559 data sheet rev. 0 | page 54 of 120 when all the data bytes are read or written, stop conditions are established. in write mode, the master (transmitter) asserts a stop condition to end data transfer during the 10 th clock pulse following the acknowledge bit for the last data byte from the slave device (receiver). in read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but does not pull sda low during the ninth clock pulse. this is known as a nonacknowledge bit. by receiving the nonacknowled ge bit, the slave device knows that the data transfer is finished and enters idle mode. the master then takes the data line low during the low period before the 10 th clock pulse, and high during the 10 th clock pulse to assert a stop condition. a start con dition can be used in place of a stop condition. furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded. sda start condition stop condition scl s p 10644-036 figure 52 . start and stop conditions 1 2 8 9 1 2 3 to 7 3 to 7 8 9 10 sda scl s msb ack from slave receiver ack from slave receiver p 10644-037 figure 53 . acknowledge bit 1 2 8 9 1 2 3 to 7 3 to 7 8 9 10 ack from slave receiver ack from slave receiver sda scl s msb p 10644-038 figure 54 . data transfer process (master write mode, 2 - byte transfer) 1 2 8 9 1 2 3 to 7 3 to 7 8 9 10 ack from master receiver nonack from master receiver sda scl s p 10644-039 figure 55 . data transfer process (master read mode, 2 - byte transfer) data sheet ad9559 rev. 0 | page 55 of 120 data transfer format write byte fo rmat the write byte protocol is used to write a register address to the ram starting from the specified ram address. s slave address a w e a ram address high byte a ram address low byte a ram data 0 a ram data 1 a ram data 2 a p send byte format the send byte protocol is used to set up the register address for subsequent reads. s slave address a a w e a ram address high byte a ram address low byte a p receive byte format the receive byte protocol is used to read the data byte(s) from ram starting from the current address. s slave address r a ram data 0 a ram data 1 a ram data 2 a a a e p read byte format the combined format of the send byte and the receive byte. s slave a ddress a a w e a ram a ddress h igh b yte a ram a ddress l ow b yte a sr slave a ddress r a ram data 0 a ram data 1 a ram data 2 a a a e p i2c serial port timing s sr s p sda scl t sp t hd; sta t su; sta t su; dat t hd; dat t hd; sta t su; sto t buf t r t f t r t f t high t low 10644-040 figure 56 . i2c serial port timing table 31 . i2c timing definitions parameter description f scl serial clock t buf bus free time between stop and start conditions t hd; sta repeated hold time start condition t su; sta repeated start condition setup time t su; sto stop condition setup time t h d; dat data hold time t su; dat date setup time t lo w scl clock low period t high scl clock high period t r minimum/maximum receive scl and sda rise time t f minimum/maximum receive scl and sda fall time t sp pulse width of voltage spikes that must be supp ressed by the input filter ad9559 data sheet rev. 0 | page 56 of 120 programming the i/o registers the register map (see table 34 ) spans an address range from 0x0000 through 0x0e4f . each address provides access to one byte (eight bits) of data. each individual reg ister is identified by its four - digit hexadecimal address (for example, register 0x0a23 ). in some cases, a group of addresses collectively defines a register. in general, when a group of registers defines a control parameter, the lsb of the value resides in the d0 position of the register with the lowest address. the bit weight increases right to left, from the lowest register address to the highest register address. note that the eeprom storage sequence registers (address 0x0e10 to address 0x0e4f ) are an e xception to th is convention (see the eeprom instructions section). buffered/active regi sters there are two copies of most registers: buffered and active. the value in the active registers is the one that is in use. the buffered registers are the ones that take effect the next time the user writes 0 x01 to register 0 x0005 ( io_update) . buffering the registers allows the user to update a group of registers (like the apll settings ) simultaneously , avoid ing the potential of unpredictab le behavior in the pa rt. registers with an l in the o ption co lumn of the register map (see table 34 ) are live, meaning that they take effect the moment the serial port transfers that data byte. write detect registe rs a w in the option column of the register map (see table 34 ) identifies a register with write detection. these registers contain additional logic to avoid glitches or unwanted operation. write detection can be disabled by settin g register 0x0004, bit 3 to 1b. table 32. register write detection description option register operation w0 the input reference is immediately faulted when these registers are written to, and the input reference validation timer re starts when the next io_u pdate occurs (register 0x0005 = 0x01). w1 the lock detector declares unlock immediately when these registers are written to, and the lock detection restarts when the next io_ update occurs. w2 a fter these registers are written to, t he dpll automatically enters holdover for one pfd cycle (and then exits) when an io_u pdate is issued . w5 the watchdog timer resets automatically when these registers are changed, and then resumes counting on the next io_update. w6 the system clock stab ility timer is automatically reset when these registers are changed, and then resumes counting on the next io_update. w7 if these registers are written to while they are assigned to an existing function, the existing function stops immediately. the new fu nction starts when the next io_update occurs. autoclear registers an a in the o pt ion column of the register map (see table 34 ) identifies an auto clearing register. typically, the active value for an auto - clear ing register takes effect foll owing an io_update. the bit is cleared by the internal device logic upon completion of the prescribed action. register access rest rictions read and write access to the register map may be restricted , depending on the register in question, the source and direction of access, and the current state of the device. each register can be classified into one or more access types. when more than one type applies, the most restrictive condition is the one th at applies . when access is denied to a register, all attempts to read the register return a 0 byte, and all attempts to write to the register are ignored. access to nonexistent registers is handled in the same way as for a denied register. regular access registers with regular access do not fall into any other category. both read and write access to registers of this type can be from either the serial ports or eeprom controller. however, only one of these sources can have access to a register at any given time (access is mutually exclusive). when the eepr om controller is active, either in load or store mode, it has exclusive access to these registers. read - only access an r in the o pt ion column of the register map (see table 34 ) identifies read - only registers. access is available a t all times, including when the eeprom controller is active. note that read - only registers (r) are inaccessible to the eeprom as well. exclusion from eeprom access an e in the o pt ion column of the register map (see table 34 ) ident ifies a register with contents that are inaccessible to the eeprom. that is, the contents of this type of register cannot be transferred directly to the eeprom or vice versa. note that read - only registers (r) are inaccessible to the eeprom as well. data sheet ad9559 rev. 0 | page 57 of 120 therma l performance table 33 . thermal parameters for the 72- lead lfcsp package symbol thermal characteristic using a jedec 51- 7 plus jedec 51- 5 2s2p test board 1 value 2 unit ja junction -to - ambient thermal resistance, 0. 0 m/s ec airflow pe r jedec jesd51 -2 (still air) 20.0 c/w jma junction -to - ambient thermal resistance, 1. 0 m/s ec airflow per jedec jesd51 -6 (moving air) 18.0 c/w jma junction -to - ambient thermal resistance, 2.5 m/s ec airflow per jedec jesd51 - 6 (moving air) 16.0 c/w jb junction -to - board thermal resistance, 0.0 m/sec airflow per jedec jesd51 - 8 (still air) 10.7 c/w jc junction -to - case thermal resistance (die -to - heat sink) per mil - std 883, method 1012.1 1.1 c/w jt junction -to - top - of - package characterization parameter, 0 m/sec airflow per jedec jesd51 - 2 (still air) 0.1 c/w jt junction -to - top - of - package characterization parameter, 1.0 m/sec airflow per jedec jesd51 - 6 (moving air) 0.1 c/w jt junction - to - top - of - packa ge characterization parameter, 2.5 m/sec airflow pe r jedec jes d51 - 6 (moving air) 0. 2 c/w 1 the exposed pad on the bottom of the package must be soldered to analog ground to achieve the specified thermal performance. 2 results are from simulations. the pcb is a jedec multilayer type. thermal performance f or actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations. the ad9559 is specified for a case temperature (t case ) . to ensure that t case is not exceeded, an airflow source can be used. use the following equation to determine the junction tempera - ture on the application pcb: t j = t case + ( jt pd ) where: t j is the junction temperature (c). t case is the case tem perature (c) measured by the customer at the top center of the package. jt is the value as indicated in table 33 . pd is the power dissipation (see the table 3 ). va lu e s of ja are provided for packag e comparison and pcb design considerations. ja can be used for a first - order approx - imation of t j by the equation t j = t a + ( ja pd ) where t a is the ambient temperature (c). va lu e s of jc are provided for package comparison and pcb design consideration s when an external heat sink is required. va lu e s of jb are provided for package comparison and pcb design considerations. ad9559 data sheet rev. 0 | page 58 of 120 power supply partiti ons the ad9559 powe r supplies are in two groups: vdd3 and vdd. all power and ground pins should be connected, even if certain blocks of the chip are powered down. ferrite beads with low (< 0.7 ?) dc resistance and approximately 600 ? impedance at 100 mhz are suitable for this application. 3.3 v supplies all of the 3.3 v supplies can be supplied from one 3.3v power supply. pin 28 is a serial port power supply and does no t require a ferrite bead from the 3.3 v source. pin 1, pin 12, pin 18, and pin 72 belong to pll _0. it is advisable, but not mandatory, to have a place for a ferrite bead to isolate them from the 3.3 v source . the need for a ferrite bead depends on how quiet the 3.3 v sour ce is. this group of pins never consume s more than 90 ma. pin 37, pin 43, pin 54, and pin 55 belong to pll _1, and the same recommendation g iven for the pll _ 0 3.3 v pins applies here as well. 1.8 v supplies a ll of the 1.8 v supplies can be connected to one common 1.8 v source. s ix f errite beads should be used in the following locations: ? b etween the 1.8 v source and pin 13 ? b etween the 1.8 v source and pin 14 ? b etween the 1.8 v source and pin 17 ? b etween the 1.8 v source and pin 38 ? b etween the 1.8 v source and pin 41 ? b etween the 1.8 v source and pin 42 the remaining vdd pins can be connected directly to the 1.8 v source . bypass capacitors fo r pi n 21 and pin 33 the performance of the ad9559 is enhanced by the use of a s ize 0201 , 0.1 f capacitor between pin 21 and pin 22, as well as between pin 33 and pin 34, placed as close to the ad9559 as possible and without the use of vias. data sheet ad9559 rev. 0 | page 59 of 120 re gister map register addresses that are not listed in table 34 are not used, and writing to those registers has no effect. the user should write the defau lt value to sections of registers marked reserved. r = r ead only. a = a uto clear. e = e xcluded from eeprom loading . w1, w2, w5, w6, and w7 = write detection (see table 32 for more information). l = l ive ( io_update not required for register to take eff ect or for a read - only register to be updated.) table 34. reg addr (hex) opt name d7 d6 d5 d4 d3 d2 d1 d0 def (hex) serial control port and part identification 0x0000 l, e spi c ontrol sdo e nable lsb f irst / in crement a ddress soft r eset reserved 0x00 0x0000 l i2c c ontrol reserved soft r eset reserved 0x00 0x0004 readback control reserved reset sans r eg map disable a uto a ctions reserved 2-w ire spi read buffer register 0x00 0x0005 a, l io_update reserved io_ up date 0x00 0x000a r , l reserved 0x 12 0x000b r , l reserved 0x0f 0x000c r, l part family id clock part family id, bits[7:0] 0x02 0x000d r, l clock part family id, bits[15:8] 0x00 0x000e l user s cratchpad user scratchpad , bits [7:0] 0x00 0x000f l user scratchpad , bits [15:8] 0x00 general configuration 0x0100 m pin d rivers m3 driver m ode , bits [1:0] m2 driver m ode , bits [1:0] m1 driver m ode , bits [1:0] m0 driver mode, bits[1:0] 0x00 0x0101 reserved m5 driver m ode , bits [1:0] m4 driver mode, bits[1:0] 0x00 0x0102 w7 m0func m0 output/ a input e e m0 f unction, bits[6:0] 0x00 0x0103 w7 m1func m1 output/ a input e e m1 f unction, bits[6:0] 0x00 0x0104 w7 m2func m2 output/ a input e e m2 f unction, bits[ 6:0] 0x00 0x0105 w7 m3func m3 output/ a input e e m3 f unction, bits[6:0] 0x00 0x0106 w7 m4func m4 output/ a input e e m4 f unction, bits[6:0] 0x00 0x0107 w7 m5func m5 output/ a input e e m5 f unction, bits[6:0] 0x00 0x0108 w5 watchdog timer watchdog timer (ms), bits[7:0] 0x00 0x0109 w5 watchdog timer (ms), bits[15:8] 0x00 0x010a irq mask common reserved sysclk unlocked sysclk stable sysclk locked watchdog timer reserved eeprom fault eeprom complet e 0x00 0x010b reserved refb validated refb fault cleared refb fault reserved refa validated refa fault cleared refa fault 0x00 0x010c reserved refd validated refd fault cleared refd fault reserved refc validated refc fault cleared refc fault 0x00 0x010d irq m ask dpll _0 frequency unclamped frequency clamped phase slew unlimited phase slew limited frequency unlocked frequency locked phase unlocked phase locked 0x00 0x010e switching free run holdover history updated r efd a ctivated refc a ctivated refb a ctivated refa a ctivated 0x00 0x010f reserved sync cl ock dist ribution apll _ 0 unlocked apll _ 0 locked apll _0 c al complete apll _0 c al started 0x00 0x0110 irq m ask dpll _1 frequency unclamped frequency clamped phase slew unlimited phase sl ew limited frequency unlocked frequency locked phase unlocked phase locked 0x00 0x0111 switching free run holdover history updated refd activated refc activated refb activated refa activated 0x00 0x0112 reserved sync clock dist ribution apll_1 unlocked apll _ 1 locked apll _ 1 cal complete apll _ 1 cal started 0x00 ad9559 data sheet rev. 0 | page 60 of 120 reg addr (hex) opt name d7 d6 d5 d4 d3 d2 d1 d0 def (hex) system clock 0x0200 sysclk pll feedback divider and config system clock k divider , bits [7:0] 0x08 0x0201 reserved sysclk xtal enable sysclk j1 divider , bits [1:0] sysclk doubler enable (j0 divide r) 0x09 0x0202 sysclk period nominal system clock period (fs) , bits [7:0] (1 ns at 1 ppm accuracy) 0x0e 0x0203 nominal system clock period (fs), bits [15:8] (1 ns at 1 ppm accuracy) 0x67 0x0204 reserved nominal system clock period , bits [20:16] 0x 13 0x0205 w6 sysclk stability system clock stability period (ms), bits[7:0] 0x32 0x0206 w6 system clock stability period (ms), bits[15:8] 0x00 0x0207 w6 reserved system clock stability period (ms), bits[19:16] 0x00 reference input a 0x0300 refa l ogic type reserved enable refa divide - by -2 reserved refa logic type , bits [1:0] 0x00 0x0301 refa r divider (20 bits) r divider , bits [7:0] 0x cf 0x0302 r divider , bits [15:8] 0x00 0x0303 reserved r divider , bits [19:16] 0x00 0x0304 w0 refa period (u p to 1.1 ms) nominal period (fs), bits[7:0] (default: 51.44 ns =1/(19.44 mhz) for default system clock setting) 0xc9 0x0305 w0 nominal period (fs) , bits[15:8] 0xea 0x0306 w0 nominal period (fs), bits[23:16] 0x10 0x0307 w0 nominal period (fs), bits[31 :24] 0x03 0x0308 w0 nominal period (fs), bits[39:32] 0x00 0x0309 w0 refa frequency tolerance inner tolerance (1 ppm), bits[7:0] (for unlock to lock condition; max: 10 %, min: 2 ppm) (default: 5%) 0x14 0x030a w0 inner tolerance (1 ppm), bits[15:8] ( for unlock to lock condition; max: 10 %, min: 2 ppm) 0x00 0x030b w0 reserved inner tolerance, bits[19:16] 0x00 0x030c w0 outer tolerance (1 ppm), bits[7:0] (for lock to unlock; max: 10%, min: 2 ppm) (default: 10%) 0x0a 0x030d w0 outer tolerance (1 ppm), bits[15:8] (for lock to unlock; max: 10% , min: 2 ppm) 0x00 0x030e w0 reserved outer tolerance, bits[19:16] 0x00 0x030f w0 refa validation validation timer (ms), bits[7:0] (up to 65.5 sec) 0x0a 0x0310 w0 validation timer (ms), bits[15:8] (up to 65.5 sec ) 0x00 0x0311 w1 refa phase lock detector phase lock threshold (ps), bits[7:0] 0xbc 0x0312 w1 phase lock threshold (ps), bits[15:8] 0x02 0x0313 w1 phase lock threshold (ps), bits [23:16] 0x00 0x0314 w1 phase lock fill rate, bits[7:0] 0x0a 0x0315 w1 phase lock drain rate, bits[7:0] 0x0a 0x0316 w1 refa frequency lock detector frequency lock threshold, bits[7:0] 0xbc 0x0317 w1 frequency lock threshold, bits[15:8] 0x02 0x0318 w1 frequency lock threshold, bits[23:16] 0x00 0x0319 w1 frequ ency lock fill rate, bits[7:0] 0x0a 0x031a w1 frequency lock drain rate, bits[7:0] 0x0a reference input b 0x032 0 refb logic type reserved enable refb divide - by -2 reserved refb logic type , bits[1:0] 0x00 0x0321 refb r divider (20 bits) r divider, bits[7:0] 0xcf 0x0322 r divider, bits[15:8] 0x00 0x032 3 reserved r divider, bits[19:16] 0x00 0x0324 w0 refb reference period (up to 1.1 ms) nominal period (fs), bits[7:0] (default: 51.44 ns =1/(19.44 mhz) for default system clock setting) 0xc9 0x0325 w0 nominal period (fs) , bits[15:8] 0xea 0x0326 w0 nominal period (fs), bits[23:16] 0x10 0x0327 w0 nominal period (fs), bits[31:24] 0x03 0x0328 w0 nominal period (fs), bits[39:32] 0x00 0x0329 w0 refb frequency tolerance inner tolerance (1 p pm), bits[7:0] (for unlock to lock condition; max: 10% , min: 2 ppm) (default: 5%) 0x14 0x032a w0 inner tolerance (1 ppm), bits[15:8] (for unlock to lock condition; max: 10% , min: 2 ppm) 0x00 0x032b w0 reserved inner tolerance, bits[19:16] 0x00 0x032 c w0 outer tolerance (1 ppm), bits[7:0] (for lock to unlock; max: 10% , min: 2 ppm) (default: 10%) 0x0a 0x032d w0 outer tolerance (1 ppm), bits[15:8] (for lock to unlock; max: 10% , min: 2 ppm) 0x00 0x032e w0 reserved outer tolerance , bits[19:16] 0x00 data sheet ad9559 rev. 0 | page 61 of 120 reg addr (hex) opt name d7 d6 d5 d4 d3 d2 d1 d0 def (hex) 0x032f w0 refb validation validation timer (ms), bits[7:0] (up to 65.5 sec) 0x0a 0x0330 w0 validation timer (ms), bits[15:8] (up to 65.5 sec ) 0x00 0x0331 w1 refb phase lock detector phase lock threshold (ps), bits[7:0] 0xbc 0x0332 w1 phase lock t hreshold (ps), bits[15:8] 0x02 0x0333 w1 phase lock threshold (ps), bits [23:16] 0x00 0x0334 w1 phase lock fill rate, bits[7:0] 0x0a 0x0335 w1 phase lock drain rate, bits[7:0] 0x0a 0x0336 w1 refb frequency lock detector frequency lock threshold, bit s[7:0] 0xbc 0x0337 w1 frequency lock threshold, bits[15:8] 0x02 0x0338 w1 frequency lock threshold, bits[23:16] 0x00 0x0339 w1 frequency lock fill rate, bits[7:0] 0x0a 0x033a w1 frequency lock drain rate, bits[7:0] 0x0a reference input c 0x0340 refc logic type reserved enable refc divide - by -2 reserved refc logic type, bits[1:0] 0x00 0x0341 refc r divider (20 bits) r divider, bits[7:0] 0xcf 0x0342 r divider, bits[15:8] 0x00 0x0343 reserved r divider, bits[19:16] 0x00 0x0344 w0 refc p eriod (up to 1.1 ms) nominal period (fs), bits[7:0] (default: 51.44 ns =1/(19.44 mhz) for default system clock setting) 0xc9 0x0345 w0 nominal period (fs) , bits[15:8] 0xea 0x0346 w0 nominal period (fs), bits[23:16] 0x10 0x0347 w0 nominal period (fs) , bits[31:24] 0x03 0x0348 w0 nominal period (fs), bits[39:32] 0x00 0x0349 w0 refc frequency tolerance inner tolerance (1 ppm), bits[7:0] (for unlock to lock condition; max: 10% , min: 2 ppm) (default: 5%) 0x14 0x034a w0 inner tolerance (1 ppm), bit s[15:8] (for unlock to lock condition; max: 10% , min: 2 ppm) 0x00 0x034b w0 reserved inner tolerance, bits[19:16] 0x00 0x034c w0 outer tolerance (1 ppm), bits[7:0] (for lock to unlock; max: 10% , min: 2 ppm) (default: 10%) 0x0a 0x034d w0 outer toler ance (1 ppm), bits[15:8] (for lock to unlock; max: 10% , min: 2 ppm) 0x00 0x034e w0 reserved outer tolerance, bits[19:16] 0x00 0x034f w0 refc validation validation timer (ms), bits[7:0] (up to 65.5 sec) 0x0a 0x0350 w0 validation timer (ms), bits[15:8 ] (up to 65.5 sec ) 0x00 0x0351 w1 refc phase lock detector phase lock threshold (ps), bits[7:0] 0xbc 0x0352 w1 phase lock threshold (ps), bits[15:8] 0x02 0x0353 w1 phase lock threshold (ps), bits [23:16] 0x00 0x0354 w1 phase lock fill rate, bits[7: 0] 0x0a 0x0355 w1 phase lock drain rate, bits[7:0] 0x0a 0x0356 w1 refc frequency lock detector frequency lock threshold, bits[7:0] 0xbc 0x0357 w1 frequency lock threshold, bits[15:8] 0x02 0x0358 w1 frequency lock threshold, bits[23:16] 0x00 0x0359 w1 frequency lock fill rate, bits[7:0] 0x0a 0x035a w1 frequency lock drain rate, bits[7:0] 0x0a reference input d 0x0360 refd logic type reserved enable ref d divide - by -2 reserved refd logic type , bits[1:0] 0x00 0x0361 refd r divider (20 bits) r divider, bits[7:0] 0xcf 0x0362 r divider, bits[15:8] 0x00 0x0363 reserved r divider, bits[19:16] 0x00 0x0364 w0 refd period (up to 1.1 ms) nominal period (fs), bits[7:0] (default: 51.44 ns =1/(19.44 mhz) for default system clock setting) 0xc9 0 x0365 w0 nominal period (fs) , bits[15:8] 0xea 0x0366 w0 nominal period (fs), bits[23:16] 0x10 0x0367 w0 nominal period (fs), bits[31:24] 0x03 0x0368 w0 nominal period (fs), bits[39:32] 0x00 0x0369 w0 refd frequency tolerance inner tolerance (1 ppm) , bits[7:0] (for unlock to lock condition; max: 10% , min: 2 ppm) (default: 5%) 0x14 0x036a w0 inner tolerance (1 ppm) , bits[15:8] (for unlock to lock condition; max: 10% , min: 2 ppm) 0x00 0x036b w0 reserved inner tolerance, bits[19:16] 0x00 0x036c w0 outer tolerance (1 ppm) , bits[7:0] (for lock to unlock; max: 10 % , min: 2 ppm) (default: 10%) 0x0a 0x036d w0 outer tolerance (1 ppm) , bits[15:8] (for lock to unlock; max: 10 % , min: 2 ppm) 0x00 0x036e w0 reserved outer tolerance, bits[19:16] 0x0 0 ad9559 data sheet rev. 0 | page 62 of 120 reg addr (hex) opt name d7 d6 d5 d4 d3 d2 d1 d0 def (hex) 0x036f w0 refd validation validation timer (ms), bits[7:0] (up to 65.5 sec) 0x0a 0x0370 w0 validation timer (ms), bits[15:8] (up to 65.5 sec ) 0x00 0x0371 w1 refd phase lock detector phase lock threshold (ps), bits[7:0] 0xbc 0x0372 w1 phase lock th reshold (ps), bits[15:8] 0x02 0x0373 w1 phase lock threshold (ps), bits [23:16] 0x00 0x0374 w1 phase lock fill rate, bits[7:0] 0x0a 0x0375 w1 phase lock drain rate, bits[7:0] 0x0a 0x0376 w1 refd frequency lock detector frequency lock threshold, bits [7:0] 0xbc 0x0377 w1 frequency lock threshold, bits[15:8] 0x02 0x0378 w1 frequency lock threshold, bits[23:16] 0x00 0x0379 w1 frequency lock fill rate, bits[7:0] 0x0a 0x037a w1 frequency lock drain rate, bits[7:0] 0x0a dpll_ 0 general settings 0 x0400 dpll_0 free run frequency tw 30- bit free running frequency tuning word , bits [7:0] 0x12 0x0401 30- bit free running frequency tuning word , bits [15:8] 0x15 0x0402 30- bit free running frequency tuning word , bits [23:16] 0x64 0x0403 reserved 30- bit free running frequency tuning word , bits [29:24] 0x1b 0x0404 dco_0 control reserved digital oscillator sdm integer part , bits [3:0] 0x08 0x0405 dpll_0 frequency clamp lower limit of pull - in range , bits [7:0] 0x 51 0x0406 lower limit of pull - in range , bits [15:8] 0x b8 0x0407 reserved lower limit of pull - in range , bits [19:16] 0x02 0x0408 upper limit of pull - in range , bits[7:0] 0x3e 0x0409 upper limit of pull - in range , bits[15:8] 0x0a 0x040a reserved upper limit of pull - in range , bit s[19:16] 0x0b 0x040b dpll_0 h oldover history history accumulation timer ( ms ) , bits [7:0 ] (up to 65 sec ) 0x0a 0x040c history accumulation timer (m s) , bits[15:8] ( up to 65 sec ) 0x00 0x040d dpll_0 history mode reserved single sample fallback persiste nt history incremental average 0x00 0x040e dpll_0 c losed loop phase offset (0.5 ms) fixed phase of fset (signed; p s) , bits [7:0] 0x00 0x040f fixed phase offset (signed; ps ) , bits [15:8] 0x00 0x0410 fixed phase offset (signed; ps ) , bits [23:16] 0x00 0x0411 reserved fixed phase offset (signed; ps), bits[29:24] 0x00 0x0412 incremental phase offset step size ( ps /step) , bits [7:0] (up to 65.5 ns/step) 0x00 0x0413 incremental phase offset step size ( ps /step) , bits [15:8] (up to 65.5 ns/step) 0x0 0 0x0414 dpll_0 p hase slew limit phase slew rate limit (s/sec) , bits [7:0] (315 s/sec up to 65.536 ms/sec) 0x00 0x0415 phase slew rate limit (s/sec) , bits [15:8] (315 s/sec up to 65.536 ms/sec) 0x00 output pll_0 (apll_0) and channel 0 output driv ers 0x0420 apll _0 charge pump output pll0 (apll_0 ) charge pump current , bits [7:0] 0x81 0x0421 apll_0 m0 divider output pll0 (apll_0 ) feedback ( m0 ) divider , bits [7:0] 0x14 0x0422 apll_0 loop filter control apll_0 loop filter control , bits [7:0] 0x07 0x0423 reserved bypass internal rzero 0x0 0 0x0424 p0 divider reserved p0 d ivider divide ratio , bits [3:0] 0x 04 0x0425 out0 sync reserved sync source selection auto sync mode 0x00 0x0426 reserved apll_0 locked controlled sync disable mask out0 b sync mask out0 a sync 0x00 data sheet ad9559 rev. 0 | page 63 of 120 reg addr (hex) opt name d7 d6 d5 d4 d3 d2 d1 d0 def (hex) 0x0427 o ut0 a reserved out0 a format , bits [2:0] out0 a polarity , bits [1:0] out0 a lvds boost reserved 0x10 0x0428 q 0_a divider , bits [7:0] 0x00 0x0429 reserved q 0_a divider , bits [9:8 ] 0x00 0x042a reserved q 0_a divider p hase , bits [5:0] 0x00 0x042b out 0b enable 3.3 v cmos driver out0 b format[2:0] out0 b polarity , bits [1:0] out0 b lvds boost reserved 0x10 0x042c q 0_b divider , bits [7:0] 0x03 0x042d reserved q 0_b divider, bits[9:8 ] 0x00 0x042e reserved q 0_b divid er phase, bits[5:0] 0x00 dpll_0 settings for reference input a 0x0440 reference priority reserved refa priority , bits [1:0] enable refa 0x01 0x0441 w2 dpll_0 loop bw (16 bits) digital pll _ 0 loop bw scaling factor , bits [7:0] (default: 0x01f4 = 50 hz) 0x f4 0x0442 w2 digital pll _ 0 loop bw scaling factor , bits [15:8] 0x01 0x0443 w2 reserved base filter reserved 0x00 0x0444 w2 dpll_0 n0 divider (17 bits) digital pll feedback divider integer part n0, bits[7:0] 0xcb 0x0445 w2 digital pll feedback divid er integer part n0, bits[15:8] 0x07 0x0446 w2 reserved digital pll feedback divider, i nteger p art n0, bit 16 0x00 0x0447 dpll_0 fractional feedback divider (24 bits) digital pll f ractional feedback divider f rac 0 , bits [7:0] 0x04 0x0448 digital pll f ractional feedback divider f rac 0 , bits [15:8] 0x00 0x0449 digital pll f ractional feedback divider f rac 0 , bits [23:16] 0x00 0x044a w2 dpll_0 fractional feedback divider modulus (24 bits) digital pll feedback divider modulus m od 0 , bits [7:0] 0x05 0x044b w2 digital pll feedback divider modulus m od 0 , bits [15:8] 0x00 0x044c w2 digital pll feedback divider modulus m od 0 , bits [23:16] 0x00 dpll_0 settings for reference input b 0x044d reference priority reserved refb priority , bits [1:0] enable refb 0x01 0x044e w2 dpll_0 loop bw (16 bits) digital pll _ 0 loop bw scaling factor, bits[7:0] (default: 0x01f4 = 50 hz) 0xf4 0x044f w2 digital pll _ 0 loop bw scaling factor, bits[15:8] 0x01 0x0450 w2 reserved base filter reserved 0x00 0x0451 w2 dpll_0 n0 divide r (17 bits) digital pll feedback divider integer part n0, bits[7:0] 0xcb 0x0452 w2 digital pll feedback divider integer part n0, bits[15:8] 0x07 0x0453 w2 reserved digital pll feedback divider, i nteger p art n0, bit 16 0x00 0x0454 dpll_0 fractional fe edback divider (24 bits) digital pll fractional feedback divider f rac 0 , bits [7:0] 0x04 0x0455 digital pll fractional feedback divider f rac 0 , bits [15:8] 0x00 0x0456 digital pll fractional feedback divider f rac 0 , bits [23:16] 0x00 0x0457 w2 dpll_0 fr actional feedback divider modulus (24 bits) digital pll feedback divider modulus m od 0 , bits [7:0] 0x05 0x0458 w2 digital pll feedback divider modulus m od 0 , bits [15:8] 0x00 0x0459 w2 digital pll feedback divider modulus m od 0 , bits [23:16] 0x00 ad9559 data sheet rev. 0 | page 64 of 120 reg addr (hex) opt name d7 d6 d5 d4 d3 d2 d1 d0 def (hex) dpll_0 se ttings for reference input c 0x045a reference priority reserved refc priority , bits [1:0] enable refc 0x00 0x045b w2 dpll_0 loop bw (1 6 bits) digital pll _ 0 loop bw scaling factor, bits[7:0] (default: 0x01f4 = 50 hz) 0xf4 0x045c w2 digital pll _ 0 loop bw scaling factor, bits[15:8] 0x01 0x045d w2 reserved base filter reserved 0x00 0x045e w2 dpll_0 n0 divider (17 bits) digital pll feedback divider integer part n0, bits[7:0] 0xcb 0x045f w2 digital pll feedback divider integer part n0, bits[15:8] 0x07 0 x0460 w2 reserved digital pll feedback divider integer part n0, bit 16 0x00 0x0461 dpll_0 fractional feedback divider (24 bits) digital pll fractional feedback divider f rac 0 , bits [7:0] 0x04 0x0462 digital pll fractional feedback divider f rac 0 , b its [15:8] 0x00 0x0463 digital pll fractional feedback divider f rac 0 , bits [23:16] 0x00 0x0464 w2 dpll_0 fractional feedback divider modulus (24 bits) digital pll feedback divider modulus m od 0 , bits [7:0] 0x05 0x0465 w2 digital pll feedback divider mod ulus m od 0 , bits [15:8] 0x00 0x0466 w2 digital pll feedback divider modulus m od 0 , bits [23:16] 0x00 dpll_0 settings for reference input d 0x0467 reference priority reserved refd priority , bits [1:0] enable refd 0x00 0x0468 w2 dpll_0 loop bw (1 6 bits) digital pll_0 loop bw scaling factor, bits[7:0] (default: 0x01f4 = 50 hz) 0xf4 0x0469 w2 digital pll _ 0 loop bw scaling factor, bits[15:8] 0x01 0x046a w2 reserved base f ilter reserved 0x00 0x046b w2 dpll_0 n0 divider (17 bits) digital pll feedback divi der integer part n0, bits[7:0] 0xcb 0x046c w2 digital pll feedback divider integer part n0, bits[15:8] 0x07 0x046d w2 reserved digital pll feedback divider integer part n0 , bit 16 0x00 0x046e dpll_0 fractional feedback divider (24 bits) digital pll fractional feedback divider f rac 0 , bits [7:0] 0x04 0x046f digital pll fractional feedback divider f rac 0 , bits [15:8] 0x00 0x0470 digital pll fractional feedback divider f rac 0 , bits [23:16] 0x00 0x0471 w2 dpll_0 fractional feedback divider modulus (24 bits) digital pll feedback divider modulus m od 0 , bits [7:0] 0x05 0x0472 w2 digital pll feedback divider modulus m od 0 , bits [15:8] 0x00 0x0473 w2 digital pll feedback divider modulus m od 0 , bits [23:16] 0x00 dpll_1 general settings 0x0500 dpll_1 free run frequency tw 30- bit free running frequency tuning word , bits [7:0] 0x12 0x0501 30- bit free running frequency tuning word , bits [15:8] 0x15 0x0502 30- bit free running frequency tuning word , bits [23:16] 0x64 0x0503 reserved 30- bit free running frequency tuning word , bits [29:24] 0x1b 0x0504 dco_1 control reserved digital oscillator sdm integer part , bits [3:0] 0x08 0x0505 dpll_1 frequency clamp lower limit of pull - in range, bits [7:0] 0x51 0x0506 lower limit of pull - in range, bits [15:8] 0x b8 0x0507 reserved lower limit of pull - in range, bits [19:16] 0x02 0x0508 upper limit of pull - in range, bits [7:0] 0x3e 0x0509 upper limit of pull - in range, bits [15:8] 0x0a 0x050a reserved upper limit of pull - in range, bits [19:16] 0x0b data sheet ad9559 rev. 0 | page 65 of 120 reg addr (hex) opt name d7 d6 d5 d4 d3 d2 d1 d0 def (hex) 0x050b dpll_1 holdover history history accumulation timer (ms) , bits [7:0] (up to 65 sec ) 0x0a 0x050c history accumulation timer (ms) , bits [15:8] ( up to 65 sec ] 0x00 0x050d dpll_1 history mode reserved single sample fallback persistent history incremen tal average 0x00 0x050e dpll_1 closed loop phase offset [0.5 ms] fixed phase offset (signed; ps) , bits [7:0] 0x00 0x050f fixed phase offset (signed; ps) , bits [15:8] 0x00 0x0510 fixed phase offset (signed; ps) , bits [23:16] 0x00 0x0511 reserv ed fixed phase offset (signed; ps), bits[29:24] 0x00 0x0512 incremental phase offset step size (ps/step) , bits [7:0] (up to 65.5 ns/step) 0x00 0x0513 incremental phase offset step size (ps/step) , bits [15:8] (up to 65.5 ns/step) 0x00 0x0514 dpll_1 phase slew limit phase slew rate limit (s/sec) , bits [7:0] (315 s/sec up to 65.536 ms/sec) 0x00 0x0515 phase slew rate limit (s/sec) , bits [15:8] (315 s/sec up to 65.536 ms/sec) 0x00 output pll_1 (apll_1) and channel 1 output drivers 0x0520 ap ll _1 charge pump output pll1 (apll_1) charge pump current , bits [7:0] 0x81 0x0521 apll_1 m1 divider output pll0 (apll_1) feedback (m1) divider , bits [7:0] 0x14 0x0522 apll_1 loop filter control apll_1 loop filter control , bits [7:0] 0x07 0x0523 rese rved bypass internal rzero 0x0 0 0x0524 p1 divider reserved p1 d ivider divide ratio , bits [3:0] 0x04 0x0525 out1 sync reserved sync source selection auto sync mode 0x00 0x0526 reserved apll_1 locked controlled sync disable mask out1b sync mask out1 a sync 0x00 0x0527 out1 a reserved out1a format, bits[2:0] out1 a polarity, bits[1:0] out1 a lvds boost reserved 0x10 0x0528 q1 _a divider, bits[7:0] 0x00 0x0529 reserved q 1_a divider, bits[9:8] 0x00 0x052a reserved q 1_a divider phase, bits[5:0] 0 x00 0x052b out1 b enable 3.3 v cmos driver out1 b format, bits[2:0] out1 b polarity, bits[1:0] out1 b lvds boost reserved 0x10 0x052c q 1_b divider, bits[7:0] 0x03 0x052d reserved q 1_b divider, bits[9:8] 0x00 0x052e reserved q 1_b divider phase , b its [5:0] 0x00 dpll_1 settings for reference input c 0x0540 reference priority reserved refc priority, bits [1:0] enable refc 0x01 0x0541 w2 dpll_1 loop bw (16 bits) digital pll _ 1 loop bw scaling factor, bits[7:0] (default: 0x01f4 = 50 hz) 0xf4 0x0542 w2 digital pll _ 1 loop bw scaling factor, bits[15:8] 0x01 0x0543 w2 reserved base filter reserved 0x00 0x0544 w2 dpll_1 n1 divider (17 bits) digital pll _ 1 feedback divider integer part n1, bits[7:0] 0xcb 0x0545 w2 digital pll _ 1 feedback divider integ er part n1, bits[15:8] 0x07 0x054 6 w2 reserved digital pll feedback divider integer part n1, bit 16 0x00 0x0547 dpll_1 fractional feedback divider (24 bits) digital pll _1 fractional feedback divider f rac 1 , bits [7:0] 0x04 0x0548 digital pll _1 fract ional feedback divider f rac 1 , bits [15:8] 0x00 0x0549 digital pll _1 fractional feedback divider f rac 1 , bits [23:16] 0x00 ad9559 data sheet rev. 0 | page 66 of 120 reg addr (hex) opt name d7 d6 d5 d4 d3 d2 d1 d0 def (hex) 0x054a w2 dpll_1 fractional feedback divider modulus (24 bits) digital pll _1 feedback divider modulus m od 1 , bits [7:0] 0x05 0x054b w2 digital pll _1 feedback divider modulus m od 1 , bits [15:8] 0x00 0x054c w2 digital pll _1 feedback divider modulus m od 1 , bits [23:16] 0x00 dpll_1 settings for reference input d 0x054d reference priority reserved refd priority , bits [1:0] enable refd 0x01 0x054e w2 dpll_1 loop bw (16 bits) digital pll _ 1 loop bw scaling factor, bits[7:0] (default: 0x01f4 = 50 hz) 0xf4 0x054f w2 digital pll _ 1 loop bw scaling factor, bits[15:8] 0x01 0x0550 w2 reserved base filter reserved 0x00 0x0551 w2 dpll_1 n1 divi der (17 bits) digital pll _ 1 feedback divider integer part n1, bits[7:0] 0xcb 0x0552 w2 digital pll _ 1 feedback divider integer part n1, bits[15:8] 0x07 0x0553 w2 reserved digital pll feedback divider integer part n1, bit 16 0x00 0x0554 dpll_1 fractional feedback divider (24 bits) digital pll _1 fractional feedback divider f rac 1 , bits [7:0] 0x04 0x0555 digital pll _1 fractional feedback divider f rac 1 , bits [15:8] 0x00 0x0556 digital pll _1 fractional feedback divider f rac 1 , bits [23:16] 0x00 0x0557 w2 dpll_1 fractional feedback divider modulus (24 bits) digital pll _1 feedback divider modulus m od 1 , bits [7:0] 0x05 0x0558 w2 digital pll _1 feedback divider modulus m od 1 , bits [15:8] 0x00 0x0559 w2 digital pll _1 feedback divider modulus m od 1 , bits [23:16 ] 0x00 dpll_1 settings for reference input a 0x055a reference priority reserved refa priority , bits [1:0] enable refa 0x00 0x055b w2 dpll_1 loop bw (16 bits) digital pll _ 1 loop bw scaling factor, bits[7:0] (default: 0x01f4 = 50 hz) 0xf4 0x055c w2 d igital pll _ 1 loop bw scaling factor, bits[15:8] 0x01 0x055d w2 reserved base f ilter reserved 0x00 0x055e w2 dpll_1 n1 divider (17 bits) digital pll _ 1 feedback divider integer part n1, bits[7:0] 0xcb 0x055f w2 digital pll _ 1 feedback divider integer par t n1, bits[15:8] 0x07 0x0560 w2 reserved digital pll feedback divider integer part n1 , bit 16 0x00 0x0561 dpll_1 fractional feedback divider (24 bits) digital pll _1 fractional feedback divider f rac 1 , bits [7:0] 0x04 0x0562 digital pll _1 fractional feedback divider f rac 1 , bits [15:8] 0x00 0x0563 digital pll _1 fractional feedback divider f rac 1 , bits [23:16] 0x00 0x0564 w2 dpll_1 fractional feedback divider modulus (24 bits) digital pll _1 feedback divider modulus m od 1 , bits [7:0] 0x05 0x0565 w2 dig ital pll _1 feedback divider modulus m od 1 , bits [15:8] 0x00 0x0566 w2 digital pll _1 feedback divider modulus m od 1 , bits [23:16] 0x00 data sheet ad9559 rev. 0 | page 67 of 120 reg addr (hex) opt name d7 d6 d5 d4 d3 d2 d1 d0 def (hex) dpll_1 settings for reference input b 0x0567 reference priority reserved refb priority [1:0] enable refb 0x00 0x0568 w2 dpll_1 loop bw (16 bits) digital pll _ 1 loop bw scaling factor, bits[7:0] (default: 0x01f4 = 50 hz) 0xf4 0x0569 w2 digital pll _ 1 loop bw scaling factor, bits[15:8] 0x01 0x056a w2 reserved base f ilter reserved 0x00 0x056b w2 dpll_1 n1 divider (17 bit s) digital pll _ 1 feedback divider integer part n1, bits[7:0] 0xcb 0x056c w2 digital pll _ 1 feedback divider integer part n1, bits[15:8] 0x07 0x056d w2 reserved digital pll feedback divider integer part n1 , bit 16 0x00 0x056e dpll_1 fractional feedback divider (24 bits) digital pll _1 fractional feedback divider f rac 1 , bits [7:0] 0x04 0x056f digital pll _1 fractional feedback divider f rac 1 , bits [15:8] 0x00 0x0570 digital pll _1 fractional feedback divider f rac 1 , bits [23:16] 0x00 0x0571 w2 dpll_1 fr actional feedback divider modulus (24 bits) digital pll _1 feedback divider modulus m od 1 , bits [7:0] 0x05 0x0572 w2 digital pll _1 feedback divider modulus m od 1 , bits [15:8] 0x00 0x0573 w2 digital pll _1 feedback divider modulus m od 1 , bits [23:16] 0x00 loo p filters 0x0800 l base loop filter coefficie nt set (normal phase margin of 70 ) npm alpha -0 linear , bits [7:0] 0x24 0x0801 l npm alpha -0 linear , bits [15:8] 0x8c 0x0802 l reserved npm alpha -1 exponent , bits [6:0] 0x49 0x0803 l npm beta -0 linear , bi ts [7:0] 0x55 0x0804 l npm beta -0 linear , bits [15:8] 0xc9 0x0805 l reserved npm beta -1 exponent , bits [6:0] 0x7b 0x0806 l npm gamma -0 linear , bits [7:0] 0x9c 0x0807 l npm gamma -0 linear , bits [15:8] 0xfa 0x0808 l reserved npm gamma -1 exponent , bits [6 :0] 0x55 0x0809 l npm delta -0 linear , bits [7:0] 0xea 0x080a l npm delta -0 linear , bits [15:8] 0xe2 0x080b l reserved npm delta -1 exponent , bits [6:0] 0x57 0x080c l base loop f ilter coefficient set (high phase margin) hpm alpha - 0 linear , bits [7:0] 0x8c 0x080d l hpm alpha -0 linear , bits [15:8] 0xad 0x080e l reserved hpm alpha -1 exponent , bits [6:0] 0x4c 0x080f l hpm beta -0 linear , bits [7:0] 0xf5 0x0810 l hpm beta -0 linear , bits [15:8] 0xcb 0x0811 l reserved hpm beta -1 exponent , bits [6:0] 0x73 0x0812 l hpm gamma -0 linear , bits [7:0] 0x24 0x0813 l hpm gamma -0 linear , bits [15:8] 0xd8 0x0814 l reserved hpm gamma -1 exponent , bits [6:0] 0x59 0x0815 l hpm delta -0 linear , bits [7:0] 0xd2 0x0816 l hpm delta -0 linear , bits [15:8] 0x8d 0x0817 l reserv ed hpm delta - 1 exponent , bits [6:0] 0x5a ad9559 data sheet rev. 0 | page 68 of 120 reg addr (hex) opt name d7 d6 d5 d4 d3 d2 d1 d0 def (hex) common operational controls 0x0a00 l global reserved soft sync all calibrate all power - down all 0x00 0x0a01 reference inputs reserved refd power - down refc power - down refb power - down refa power - down 0x00 0x0a02 a reserved refd timeout refc timeout refb timeout refa timeout 0x00 0x0a03 reserved refd fault refc fault refb fault refa fault 0x00 0x0a04 reserved refd monitor bypass refc monitor bypass refb monitor bypass refa monitor bypass 0x00 0x0a05 a cl ear irq groups clear watchdog timer reserved clear dpll_1 irq s clear dpll_0 irq s clear common irq s clear all irqs 0x00 0x0a06 a clear common irq reserved s ysclk unlocked s ysclk stable s ysclk locked watchdog timer reserved eeprom fault eeprom complete 0x0 0 0x0a07 a reserved refb validated refb fault cleared refb fault reserved refa validated refa fault cleared refa fault 0x00 0x0a08 a reserved refd validated refd fault cleared refd fault reserved refc validated refc fault cleared refc fault 0x00 0x0a0 9 a clear dpll_0 irq frequency unclamped frequency clamped phase slew unlimited phase slew limited frequency unlocked frequency locked phase unlocked phase locked 0x00 0x0a0a a dpll_0 switching dpll_0 free run dpll_0 holdover history updated refd activat ed refc activated refb activated refa activated 0x00 0x0a0b a reserved clock dist syncd apll_0 unlocked apll_0 locked apll_0 cal ended apll_0 cal started 0x00 0x0a0c a clear dpll_1 irq frequency unclamped frequency clamped phase slew unlimited phase slew limited frequency unlocked frequency locked phase unlocked phase locked 0x00 0x0a0d a dpll_1 switching dpll_1 free run dpll_1 holdover history updated refd activated refc activated refb activated refa activated 0x00 0x0a0e a reserved clock dist sy ncd apll_1 unlocked apll_1 locked apll_1 cal ended apll_1 cal started 0x00 pll_0 operational controls 0x0a20 pll_0 sync cal reserved apll_0 soft sync apl l_0 calibrate (no self clear ) pll_0 power - down 0x00 0x0a21 pll_0 output reserved out0 b disable out0 a disable out0 b power - down out0 a power - down 0x00 0x0a22 pll_0 user mode reserved dpll_0 m anual r eference , bits [1:0] dpll_0 s witching m ode , bits [2:0] dpll_0 user holdover dpll_0 user free run 0x00 0x0a23 a pll_0 reset reserved reset dpll_0 lo op filter reset dpll_0 tw history reset dpll_0 auto sync 0x00 0x0a24 a pll_0 phase reserved dpll_0 reset phase offset dpll_0 decrement phase offset dpll_0 increment phase offset 0x00 pll_1 operational controls 0x0a40 pll_1 sync cal reserved apll_1 s oft sync apll_1 calibrate (no self clear ) pll_1 power - down 0x00 0x0a41 pll_1 output reserved out1 b disable out1 a disable out1 b power - down out1 a power - down 0x00 0x0a42 pll_1 user mode reserved dpll_ 1 m anual r eference , bits [1:0] dpll_1 s witching m ode , bits [2:0] dpll_1 user holdover dpll_1 user free run 0x00 0x0a43 a pll_1 reset reserved reset dpll_1 loop filter reset dpll_1 tw history reset dpll_1 auto sync 0x00 0x0a44 a pll_1 phase reserved dpll_1 reset phase offset dpll_1 decrement phase offset dpll_1 increment phase offset 0x00 data sheet ad9559 rev. 0 | page 69 of 120 reg addr (hex) opt name d7 d6 d5 d4 d3 d2 d1 d0 def (hex) read- only status common blocks ( these registers are accessible d uring eeprom t ransactions . to show the latest status, register 0x0d02 to register 0x0d05 require an io_update before being read .) 0x0d00 r, l eeprom res erved eeprom fault detected eeprom load in progress eeprom save in progress n/a 0x0d01 r, l sysclk and pll status reserved pll_1 all locked pll_0 all locked sysclk stable sysclk lock detect n/a 0x0d02 r, l reference status reserved dpll_1 refa active dp ll_0 refa active refa valid refa fault refa fast refa slow n/a 0x0d03 r, l reserved dpll_1 refb active dpll_0 refb active refb valid refb fault refb fast refb slow n/a 0x0d04 r, l reserved dpll_1 refc active dpll_0 refc active refc valid refc fault r efc fast refc slow n/a 0x0d05 r, l reserved dpll_1 refd active dpll_0 refd active refd valid refd fault refd fast refd slow n/a 0x0d06 r, l reserved n/a 0x0d07 r, l reserved n/a irq monitor 0x0d08 r irq, common reserved s ysclk unlocked s ysclk s table s ysclk locked watchdog timer reserved eeprom fault eeprom complete n/a 0x0d09 r reserved refb validated refb fault cleared refb fault reserved refa validated refa fault cleared refa fault n/a 0x0d0a r reserved refd validated refd fault cleared re fd fault reserved refc validated refc fault cleared refc fault n/a 0x0d0b r irq, dpll_0 frequency unclamped frequency clamped phase slew unlimited phase slew limited frequency unlocked frequency locked phase unlocked phase locked n/a 0x0d0c r dpll_0 swi tching dpll_0 free run dpll_0 holdover history updated refd activated refc activated refb activated refa activated n/a 0x0d0d r reserved clock dist syncd apll_0 unlocked apll_0 locked apll_0 cal ended apll_0 cal started n/a 0x0d0e r irq, dpll_1 frequen cy unclamped frequency clamped phase slew unlimited phase slew limited frequency unlocked frequency locked phase unlocked phase locked n/a 0x0d0f r dpll_1 switching dpll_1 free run dpll_1 holdover history updated refd activated refc activated refb activa ted refa activated n/a 0x0d10 r reserved clock dist syncd apll_1 unlocked apll_1 locked apll_1 cal ended apll_1 cal started n/a pll_0 read - only status (to show the latest status , t hese registers require an io_update b efore being read.) 0x0d20 r, l pll_0 lock status reserved apll_0 cal in progress apll_0 locked dpll_0 freq lock dpll_0 phase lock pll_0 all locked n/a 0x0d21 r dpll_0 loop state reserved dpll_0 active ref, bits[1:0] dpll_0 switching dpll_0 holdover dpll_0 free run n/a 0x0d22 r, l res erved dpll_0 phase slew limited dpll_0 frequency clamped dpll_0 history available n/a 0x0d23 r dpll_0 holdover history dpll_0 tuning word readback, bits[7:0] n/a 0x0d24 r dpll_0 tuning word readback, bits[15:8] n/a 0x0d25 r dpll_0 tuning word readback , bits[23:16] n/a 0x0d26 r reserved dpll_0 tuning word readback, bits[29:24] n/a 0x0d27 r dpll_0 phase lock detect bucket dpll_0 phase lock detect bucket level, bits[7:0] n/a 0x0d28 r reserved dpll_0 phase lock detect bucket level, bits[11:8] n/a 0x0 d29 r dpll_0 frequency lock detect bucket dpll_0 frequency lock detect bucket level, bits[7:0] n/a 0x0d2a r reserved dpll_0 frequency lock detect bucket level, bits[11:8] n/a ad9559 data sheet rev. 0 | page 70 of 120 reg addr (hex) opt name d7 d6 d5 d4 d3 d2 d1 d0 def (hex) pll_1 read - only status (to show the latest status , t hese registers require an io_update b efore being read.) 0x0d40 r, l pll_1 lock status reserved apll_1 cal in progress apll_1 locked dpll_1 freq lock dpll_1 phase lock pll_1 all locked n/a 0x0d41 r dpll_1 loop state reserved dpll_1 active ref , bits [1:0] dpll_1 switching dpll_1 holdover dpll_1 free run n/a 0x0d42 r, l reserved dpll_1 phase slew limited dpll_1 frequency clamped dpll_1 history available n/a 0x0d43 r dpll_1 holdover history dpll_1 tuning word readback, bits[7:0] n/a 0x0d44 r dpll_1 tuning word readback, bits[1 5:8] n/a 0x0d45 r dpll_1 tuning word readback, bits[23:16] n/a 0x0d46 r reserved dpll_1 tuning word readback, bits[29:24] n/a 0x0d47 r dpll_1 phase lock detect bucket dpll_1 phase lock detect bucket level, bits[7:0] n/a 0x0d48 r reserved dpll_1 phas e lock detect bucket level, bits[11:8] n/a 0x0d49 r dpll_1 frequency lock detect bucket dpll_1 frequency lock detect bucket level, bits[7:0] n/a 0x0d4a r reserved dpll_1 frequency lock detect bucket level, bits[11:8] n/a nonv olatile memory (eeprom) con trol 0x0e00 e write protect reserved write enable 0x00 0x0e01 e condition reserved conditional value, bits[3:0] 0x00 0x0e02 a, e save reserved save to eeprom 0x00 0x0e03 a, e load reserved load from eeprom 0x00 eeprom storage sequence 0x0e10 user free run command: set user free run mode 0x98 0x0e11 user scratchpad size of transfer: two bytes 0x01 0x0e12 starting a ddress 0x000e 0x00 0x0e13 0x0e 0x0e14 m pins and irq masks size of transfer: 19 bytes 0x12 0x0e15 starting a ddress 0x0100 0x01 0x0e16 0x00 0x0e17 system clock size of transfer: eight bytes 0x07 0x0e18 starting a ddress 0x0200 0x02 0x0e19 0x00 0x0e1a io_update command: io_update 0x80 0x0e1b refa size of transfer: 27 bytes 0x1a 0x0e1c starting a ddress 0x0300 0x03 0x0e1d 0x00 0x0e1e refb size of transfer: 27 bytes 0x1a 0x0e1f starting a ddress 0x0320 0x03 0x0e20 0x20 0x0e21 refc size of transfer: 27 bytes 0x1a 0x0e22 starting a ddress 0x0340 0x03 0x0e23 0x40 0x0e24 refd size of transfer: 2 7 bytes 0x1a 0x0e25 starting a ddress 0x0360 0x03 0x0e26 0x60 0x0e27 dpll_0 general settings size of transfer: 22 bytes 0x15 0x0e28 starting a ddress 0x0400 0x04 0x0e29 0x00 0x0e2a apll_0 config and output drivers size of transfer: 1 5 bytes 0x0e 0x0e2b starting a ddress 0x0420 0x04 0x0e2c 0x20 data sheet ad9559 rev. 0 | page 71 of 120 reg addr (hex) opt name d7 d6 d5 d4 d3 d2 d1 d0 def (hex) 0x0e2d dpll_0 dividers and bw size of transfer: 52 bytes 0x33 0x0e2e starting a ddress 0x0440 0x04 0x0e2f 0x40 0x0e30 dpll_1 general settings size of transfer: 22 bytes 0x15 0x0e31 s tarting a ddress 0x0500 0x 05 0x0e32 0x00 0x0e33 a pll_1 config and output drivers size of transfer: 1 5 bytes 0x0e 0x0e34 starting a ddress 0x0520 0x0 5 0x0e35 0x20 0x0e36 dpll_1 dividers and bw size of transfer: 52 bytes 0x33 0x0e37 starting a ddress 0x0540 0x0 5 0x0e38 0x40 0x0e39 loop filter size of transfer: 24 bytes 0x17 0x0e3a starting a ddress 0x0800 0x08 0x0e3b 0x00 0x0e3c common operational controls size of transfer: 1 5 bytes 0x0e 0x0e3d starting a ddress 0x0a00 0x0a 0x0e3e 0x00 0x0e3f pll_0 o perational controls size of transfer: five bytes 0x04 0x0e40 starting address 0x0a20 0x0a 0x0e41 0x20 0x0e42 pll_1 o perational controls size of transfer: five bytes 0x04 0x0e43 starting address 0x0a40 0x0a 0x0e44 0x40 0x0e45 io_update command: io_update 0x80 0x0e46 calibrate apll s command: c alibrate output plls 0x90 0x0e47 sync outputs command: distribution s ync 0xa0 0x0e48 end of data command: end of data 0xff 0x0e49 to 0x 0 e4f unused unused (a vailable for additional data transfers and/or commands) 0x00 ad9559 data sheet rev. 0 | page 72 of 120 register map bit des criptions serial control port configuration (register 0 x 0000 to register 0x0005) table 35 . serial configuration (note that the c ontents of register 0x0000 are not s tored to the eeprom .) address bits bit name description 0x0000 7 sdo e nable enables spi port sdo p in. 1 = 4 - wire (sdo pin enabled). 0 (default) = 3 - wire . 6 lsb f irst / increment address bit order for spi port. 1 = least significant bit and byte fir st . register a ddresses are automatically incremented in multi byte transfers. 0 (default) = most significant bit and byte first . register a ddresses are autom atically dec remented in multi byte transfers. 5 soft r eset device reset (invokes an eeprom download if eeprom or p in p rogram is enabled. ) see the eeprom and pin configuration and function descriptions sections for detail s. [4:0] reserved default: 0x00 . table 36 . readb ack control address bits bit name description 0x0004 [7:5] reserved default: 0x00 . 4 reset sans r eg map resets the part while maintaining the current register settings . 1 = resets the device . 0 (default) = no action . 3 disa ble auto a ctions d isables the automatic updating of dpll parameters . 1 = disables t he automatic register write detection functions described in table 32 . 0 (default) = t he live registers in th e dpll p rofile registers update immed iately. 2 reserved default: 0x00 . 1 2-w ire spi enables 2 - wire spi mode , in which the a cs e a pin state is ignored. note that the a cs e a stalled high function is not available in this mode and that the correct number of clock edges must be present on the sclk pin during a transfer. 1 = ignores the state of the a cs e a pin , making the m5/ a cs e a pin available as an m pin for control/status of the ad9559 . 0 (default) = normal spi operation . 0 read buffer register for buffe red registers, serial port read back r eads from actual (active) registers instead of the buffer. 1 = reads buffered values that take effect on next assertion of io_update. 0 (default) = reads values currently applied to the devices internal logic . table 37 . soft io_update address bits bit name description 0x0005 [7:1] reserved reserved . 0 io_update writing a 1 to this bit transfers the data in th e serial i/o buffer registers to the devices internal control registers. this is an auto clearing bit. clock part family id (register 0x 000 c and register 0 x000 d) table 38. clock part family id address bits bit name description 0x0 00c [7:0] clock part f amily id , bits [7:0] the value s in this read - only register and r egister 0x000d uniquely identify the ad9559 . this is useful in cases where the users software must determine which device is l ocated at a given i2c address. default : 0x0 2 for the ad9559 . 0x000d [7:0] clock p art f amily id , bits [15:8] default : 0x00 for the ad9559 . data sheet ad9559 rev. 0 | page 73 of 120 user scratchpad (register 0 x000 e and register 0 x000 f) table 39 . user scratchpad address bits bit name description 0x000e [7:0] user scratchpad , bits [7:0] user programmable eeprom id registers. these regis ters enable user s to write a unique code of their choosing to keep track of revisions to the eeprom register loading. it has no effect on part operation. d efault = 0x0000. 0x000f [7:0] user scratchpad , bits [15:8] general configuration (register 0 x 0100 to register 0x0109 ) multifunction pin control (m0 to m 5) and watchdog timer table 40 . multifunction pins (m0 to m5 ) control address bits bit name description 0x0100 [7:6] m3 d river m ode , bits [1:0] 00 (default) = a ctive high cmos. 01 = a ctive low cmos. 10 = o pen - drain pmos (requires an e xternal pull - down resistor) . 11 = o pen - drain nmos (requires an external pull - up resistor) . [5:4] m2 d river m ode , bits [1:0] the settings of these bits are identical to register 0x010 0[7:6]. [3:2] m1 d river m ode , bits [1:0] the settings of these bits are identical to register 0x010 0[7:6]. [1:0] m0 d river m ode , bits [1:0] the settings of these bits are identical to register 0x010 0[7:6]. 0x0101 [7:4] reserved reserved. [3:2] m5 d river m ode , bits [1:0] the settings of these bits are identical to register 0 x0100[7:6]. note that , for this pin to be an m pin , either i 2c or 2 - wire spi mode must be enabled. [1:0] m4 d river m ode , bits [1:0] the settings of these bits are identical to register 0x010 0[7:6]. note that , for this pin to be an m pin , 4- wire spi mode m ust be disabled . 0x0102 7 m0 output/ a input e in put /out put control for m0 pin . 0 (default) = input (control pin) 1 = output ( status pin) [6:0] m0 f unction these bits control the function of the m0 pin. see table 196 and table 197 for details about the input and output functions that are available. default : 0x0 0 = high impedance control pin, no function assigned . 0x0103 7 m1 output/ a input e in put /out put control for m1 pin (same as for the m0 pin ). [6:0] m1 f unction these bits control the function of the m1 pin and are the same as register 0x0102[6:0]. default : 0x00 = high impedance control pin, no function assigned. 0x0104 7 m2 output/ a input e in put /out put control for m2 pin (same as for the m0 pin) . [6:0] m2 f unction these bits control the function of the m 2 pin and are the same as register 0x0102[6:0]. default : 0x00 = high impedance control pin, no function assigned. 0x0105 7 m3 output/ a input e in put /out put control for m3 pin (same as for the m0 pin) . [6:0] m3 f unction these bits control the function of the m 3 pin and are the same as register 0x0102[6:0]. default : 0x00 = high impedance control pin, no function assigned. 0x010 6 7 m4 output/ a input e in put /out put control for m3 pin (same as for the m0 pin) . [6:0] m4 f unction these bits control the function of the m 4 pin and are the same as register 0x0102[6:0]. def ault : 0x00 = high impedance control pin, no function assigned. 0x0107 7 m5 output/ a input e in put /out put control for m3 pin (same as for the m0 pin) . [6:0] m5 f unction these bits control the function of the m 5 pin and are the same as register 0x0102[6:0]. default : 0x00 = high impedance control pin, no function assigned. 0x0108 [7:0] watchdog t imer (in units of ms) watchdog timer , bits[7:0]. the watchdog timer stops when this register is written, and restarts on the next io_update (reg ister 0x0005 = 0x01). default: 0x00 (0x0000 = disabled) . 0x0109 [7:0] watchdog timer , bits[15:8]. the watchdog timer stops when this register is written, and restarts on the next io_update (register 0x0005 = 0x01). default: 0x00 . ad9559 data sheet rev. 0 | page 74 of 120 irq mask (register 0 x 010a to register 0x112) the irq mask register bits form a one - to - one correspondence with the bits of the irq monitor register ( 0x0d08 to 0x0d10). when set to l ogic 1, the irq mask bit s enable the corresponding irq m onitor bits to indicate an irq event. the de fault for all irq m ask bits is l ogic 0, which prevents the irq monitor from detecting any internal interrupts. table 41 . irq mask for sysclk , watchdog timer, and eeprom address bits bit name description 0x010a 7 reserved reserved . 6 sysclk unlocked enables irq for indicating a sysclk pll state transition from locked to unlocked . 5 sysclk stable enables irq for indicating that sysclk stability time has expired and that the sysclk pll is considered to be stable. 4 sysclk loc ked enables irq for indicating a sysclk pll state transition from unlocked to locked . 3 watchdog timer enables irq for indicating expiration of the watchdog timer . 2 reserved reserved . 1 eeprom fault enables irq for indicating a fault during an eeprom load or save operation . 0 eeprom complete enables irq for indicating successful completion of an eeprom load or save operation . table 42 . irq mask for reference inputs address bits bit name description 0x010b 7 reserved reserved . 6 refb validated enables irq for indicating that refb has been validated . 5 refb fault cleared enables irq for indicating that refb has been cleared of a previous fault . 4 refb fault enables irq for indicating that refb has been faulted . 3 rese rved reserved . 2 refa validated enables irq for indicating that refa has been validated . 1 refa fault cleared enables irq for indicating that refa has been cleared of a previous fault . 0 refa fault enables irq for indicating that refa has been faulte d. 0x010c 7 reserved reserved . 6 refd validated enables irq for indicating that refd has been validated . 5 refd fault cleared enables irq for indicating that refd has been cleared of a previous fault . 4 refd fault enables irq for indicating that refd has been faulted . 3 reserved reserved . 2 refc validated enables irq for indicating that refc has been validated . 1 refc fault cleared enables irq for indicating that refc has been cleared of a previous fault . 0 refc fault enables irq for indicating that refc has been faulted . data sheet ad9559 rev. 0 | page 75 of 120 table 43 . irq mask for the digital pll0 (dpll_0) address bits bit name description 0x010d 7 frequency unclamp ed enables irq to indicate that dpll_0 has exited a frequency clamped state 6 frequenc y clamp ed enables irq to indicate that dpll_0 has entered a frequency clamped state 5 phase slew unlimited enables irq to indicate that dpll_0 has exited a phase slew limited state 4 phase slew limited enables irq to indicate that dpll_0 has entered a phase slew limited state 3 frequency unlocked enables irq to indicate that dpll_0 has lost frequency lock 2 frequency locked enables irq to indicate that dpll_0 has acquired frequency lock 1 phase unlocked enables irq to indicate that dpll_0 has lost phase lock 0 phase locked enables irq to indicate that dpll_0 has acquired phase lock 0x010e 7 switching enables irq to indicate that dpll_0 is switching to a new reference 6 free run enables irq to indicate that dp ll_0 has entered free run mode 5 holdover enables irq to indicate that dpll_0 has entered holdover mode 4 history updated enables irq to indicate that dpll_0 has updated its tuning word history 3 refd activated enables irq to indicate that dpll_0 has activated refd 2 refc activated enables irq to indicate that dpll_0 has activated refc 1 refb activated enables irq to indicate that dpll_0 has activated refb 0 refa activated enables irq to indicate that dpll_0 has activated refa 0x010f [7:5] reserved reserved 4 sync clock distri bution enables irq for indicating a distribution sync event 3 apll_0 unlocked enables irq for apll_0 unlocked 2 apll_0 locked enables irq for apll_0 locked 1 apll_0 cal complete enables irq for apll_0 calibration complete 0 apll_0 cal started enabl es irq for apll_0 calibration started table 44 . irq mask for the digital pll1 (dpll_1) address bits bit name description 0x0110 7 frequency unclamp ed enables irq to indicate that dpll_1 has exited a frequency clamped state 6 fre quency clamp ed enables irq to indicate that dpll_1 has entered a frequency clamped state 5 phase slew unlimited enables irq to indicate that dpll_1 has exited a phase slew limited state 4 phase slew limited enables irq to indicate that dpll_1 has enter ed a phase slew limited state 3 frequency unlocked enables irq to indicate that dpll_1 has lost frequency lock 2 frequency locked enables irq to indicate that dpll_1 has acquired frequency lock 1 phase unlocked enables irq to indicate that dpll_1 has lost phase lock 0 phase locked enables irq to indicate that dpll_1 has acquired phase lock 0x0111 7 switching enables irq to indicate that dpll_1 is switching to a new reference 6 free run enables irq to indicate that dpll_1 has entered free run mode 5 holdover enables irq to indicate that dpll_1 has entered holdover mode 4 history updated enables irq to indicate that dpll_1 has updated its tuning word history 3 refd activated enables irq to indicate that dpll_1 has activated refd 2 refc activ ated enables irq to indicate that dpll_1 has activated refc 1 refb activated enables irq to indicate that dpll_1 has activated refb 0 refa activated enables irq to indicate that dpll_1 has activated refa 0x0112 [7:5] reserved reserved 4 sync clock d istribution enables irq for indicating a distribution sync event 3 apll_1 unlocked enables irq for apll_1 unlocked 2 apll_1 locked enables irq for apll_1 locked 1 apll_1 cal complete enables irq for apll_1 calibration complete 0 apll_ 1 cal started enables irq for apll_ 1 calibration started ad9559 data sheet rev. 0 | page 76 of 120 system clock (regist er 0x 02 00 to register 0 x0207 ) table 45 . syste m clock pll feedback divider (k divider) and configuration address bits bit name description 0x02 00 [7:0] system c lock k d ivider system clock p ll feedback divider value = 4 k 255 (default : 0x08) . table 46. s ysclk configuration address bits bit name description 0x0201 [7:4] reserved reserved. 4 sysclk xtal e nable enables the crystal maintaining amplifier for the system clock input . 1 (default ) = c rystal m ode ( c rysta l maintaining amplifier enabled ). 0 = external crystal oscillator or other system clock source . [2:1] sysclk j1 d ivider system clock input divider . 00 (default) = 1 . 01 = 2 . 10 = 4 . 11 = 8 . 0 sysclk d oubler e nable (j0 divider) e nable s the c lock d oubler on s ystem c lock i nput to reduce noise . setting this bit may prevent the sysclk pll from locking if the input duty cycle is not close enough to 50%. see table 4 for the limits on duty cycle. 0 = disable . 1 (default) = enable . table 47 . nominal system clock period address bits bit name description 0x0202 [7:0] nominal s ystem c lock p eriod ( fs ) system clock period , b its[7:0] . this is the period of the system clock. def ault: 0x0 e . [the default of 0x13670e = 1.271566 ns = 16 (1/49.152 mhz) .] 0x0203 [7:0] system clock period , b its [15:8]. default: 0x67. 0x0204 [7:5] reserved default: 0x13 . [4:0] nominal s ystem c lock p eriod (fs) system clock period , b its [20:16]. defau lt: 0x13. table 48 . system clock stability period address bits bit name description 0x0205 [7:0] system clock stability period (ms) system clock period , b its[7:0]. the system clock stability period is the amount of time that the s ystem clock pll must be locked before it is declared stable. the system clock stability timer is reset automatically if the user writes to this register. the system clock stability timer restarts on the next io_update (register 0x0005 = 0x01). default: 0x3 2 (0x000032 = 50 ms) . 0x0206 [7:0] system clock period , bits[15:8]. the system clock stability timer is reset automatically if the user writes to this register. the system clock stability timer restarts on the next io_update (register 0x0005 = 0x01). de fault: 0x00. 0x0207 [7:5] reserved default: 0x0. [3:0] system clock stability period system clock period , bits[19:16]. the system clock stability timer is reset automatically if the user writes to this register. the system clock stability timer restarts on the next io_update (register 0x0005 = 0x01). default: 0x0. data sheet ad9559 rev. 0 | page 77 of 120 reference input a (register 0 x03 00 to register 0 x031a ) table 49 . refa logic type address bits bit name description 0x0300 [7:4] reserved default: 0x0 3 enable ref a divide -by -2 enables the reference input divide -by - 2 for refa 0 = bypass es the divide -by - 2 (default) 1 = enable s the divide -by -2 2 reserved default: 0b [1:0] refa logic type select s logic family for refa input receiver; only the ref a pin is used in cm os mode 00 (default) = differential 01 = 1.2 v to 1.5 v cmos 10 = 1.8 v to 2.5 v cmos 11 = 3.0 v to 3.3 v cmos table 50 . refa 20 -b it dpll r divider address bits bit name description 0x0301 [7:0] r divider dpll integer reference divider (minus 1), bits[7:0] (default: 0xcf) 0x0302 [7:0] dpll integer reference divider (minus 1), bits[15:8] (default: 0x00) 0x0303 [7:4] reserved default: 0x0 [3:0] r divider dpll integer reference divider (minus 1), bits[19:16] (default: 0x0) tab le 51 . nominal period of refa input clock address bits bit name description 0x0304 [7:0] refa n ominal reference period (fs) nominal reference period , b its[7:0] (default: 0xc9) 0x0305 [7:0] nominal reference period , b its[15:8] (de fault: 0xea) 0x0306 [7:0] nominal reference period , b its[23:16] (default: 0x10) 0x0307 [7:0] nominal reference period , b its[31:24] (default: 0x03) 0x0308 [7:0] nominal reference period , b its[39:32] (default: 0x00) default for register 0x0304 to regis ter 0x0308 : 0x000310eac9 = 51.44 ns (1/19.44 mhz ). table 52. refa frequency tolerance address bits bit name description 0x0309 [7:0] inner tolerance input reference frequency monitor inner tolerance , b its [7:0] (default: 0x14) . 0x030a [7:0] input reference frequency monitor inner tolerance , b it s [15:8] (default: 0x00) . 0x030b [7:4] reserved default: 0x0 . [3:0] inner tolerance input reference frequency monitor inner tolerance , bits[19:16]. default for register 0x0309 to register 0x30b: 0x000014 = 20 (5% or 50,000 ppm) . the stratum 3 clock requires inner tolerance of 9.2 ppm and outer tolerance of 12 ppm; an smc clock requires outer tolerance of 48 ppm . the allowable range for the inner tole rance is 0x00a (10%) to 0x8ff ( 2 ppm). 0x030c [7:0] outer tolerance input reference frequency monitor outer tolerance , b its [7:0] (default: 0x0a) . 0x030d [7:0] input reference fre quency monitor outer tolerance, b its[15:8] (default: 0x00) . 0x030e [7:4] reserved default: 0x0 . [3:0] outer to lerance input reference frequency monitor outer tolerance , b its[19: 16] . default for register 0x030c to register 0x30e = 0x00000a = 10 (10% or 100,000 ppm) . the stratum 3 clock requires inner tolerance of 9.2 ppm and outer tolerance of 12 ppm; an smc clo ck requires outer tolerance of 48 ppm. the outer tolerance must be greater than the inner tolerance so that there is hysteresis. ad9559 data sheet rev. 0 | page 78 of 120 table 53. refa validation timer address bits bit name description 0x030f [7:0] validation timer (ms) validation timer , b its[7:0] (default: 0x0a) . this is the amount of time a reference input must be valid before it is declared valid by the reference input monitor (default: 10 ms). 0x0310 [7:0] validation timer , b its[15:8] (default: 0x00) . table 54 . refa lock detectors address bits bit name description 0x0311 [7:0] phase lock threshold phase lock threshold , b its[7:0] (default: 0xbc) ; d efault of 0x02bc = 700 ps 0x0312 [7:0] phase lock threshold , b its[15:8] (default: 0x02) 0x0313 [7:0] phase lock threshold , b its[23:16] (default: 0x00) 0x0314 [7:0] phase lock fill rate phase lock fill rate , b its[7:0] (default: 0x0a = 10 code/pfd cycle) 0x0315 [7:0] phase lock drain rate phase lock drain rate , b its[7:0] (default: 0x0a = 10 cod e/pfd cycle) 0x0316 [7:0] frequency lock threshold freq uency lock threshold , bits[7:0] (default: 0xbc) ; d efault of 0x02bc = 700 ps 0x0317 [7:0] frequ ency lock threshold , bits[15:8] (default: 0x02) 0x0318 [7:0] frequency lock threshold , b its[23:16] (default: 0x00) 0x0319 [7:0] frequency lock fill rate frequency lock fill rate , b its[7:0] (default: 0x0a = 10 code/pfd cycle) 0x031a [7:0] frequency lock drain rate frequency lock drain rate , b its[7:0] (default: 0x0a = 10 code/pfd cycle) reference input b (register 0x 032 0 to register 0x033a) table 55 . refb logic type address bits bit name description 0x0320 [7:4] reserved default: 0x0 3 enable refb divide -by -2 enables the reference input divide -by - 2 for ref b 0 = bypass es the divid e- by - 2 (default) 1 = enable s the divide -by -2 2 reserved default: 0b [1:0] refb logic type select s logic family for ref b input receiver; only the refb pin is used in cmos mode 00 (default) = differential 01 = 1.2 v to 1.5 v cmos 10 = 1.8 v to 2.5 v cm os 11 = 3.0 v to 3.3 v cmos table 56 . refb 20-b it dpll r divider address bits bit name description 0x0321 [7:0] r divider dpll integer reference divider (minus 1), bits[7:0] (default: 0xcf) 0x0322 [7:0] dpll integer reference di vider (minus 1), bits[15:8] (default: 0x00) 0x032 3 [7:4 ] reserved default: 0x0 [3:0] r divider dpll integer reference divider (minus 1), bits[19:16] (default: 0x0) table 57 . nominal period of refb input clock address bits bit na me description 0x0324 [7:0] refb nominal reference period (fs) nominal reference period , bits[7:0] (default: 0xc9) . 0x0325 [7:0] nominal reference period, b its[15:8] (default: 0xea) . 0x0326 [7:0] nominal reference period , bits[23:16] (default: 0x10) . 0x0327 [7:0] nominal reference period , bits[31:24] (default: 0x03) . 0x0328 [7:0] nominal reference period , b its[39:32] (default: 0x00) . d efault for register 0x032 4 to register 0x0328: 0x000310eac9 = 51.44 ns (1/19.44 mhz) . data sheet ad9559 rev. 0 | page 79 of 120 table 58 . refb frequency tolerance address bits bit name description 0x0329 [7:0] inner tolerance input reference frequency monitor inner tolerance , b its [7:0] (default: 0x14) 0x032 a [7:0] input reference frequency monitor inner tolerance , b it s [15:8] (defaul t: 0x00) 0x032b [7:4] reserved default: 0x0 [3:0] inner tolerance input reference frequency monit or inner tolerance , bits[19:16]. default for register 0x0329 to register 0x032 b: 0x000014 = 20 (5% or 50,000 ppm). the stratum 3 clock requires inner tolera nce of 9.2 ppm and outer tolerance of 12 ppm; an smc clock requires outer tolerance of 48 ppm . the allowable range for the inner tole rance is 0x00a (10%) to 0x8ff ( 2 ppm). 0x032c [7:0] outer tolerance input reference frequenc y monitor outer tolerance, bits [7:0] (default: 0x0a). 0x032d [7:0] input reference frequency monitor outer tolerance, bits[15:8] (default: 0x00). 0x032e [7:4] reserved default: 0x0 [3:0] outer tolerance input reference f requency monitor outer tolerance, b its[19:16] . default fo r register 0x032 c to register 0x 032e: 0x00000a = 10 (10% or 100,000 ppm). the stratum 3 clock requires inner tolerance of 9.2 ppm and outer tolerance of 12 ppm; an smc clock requires outer tolerance of 48 ppm. the outer tolerance must be greater than th e inner tolerance so that there is hysteresis. table 59. refb validation timer address bits bit name description 0x032f [7:0] validation timer (ms) validation timer , b its[7:0] (default: 0x0a) . this is the amount of time a reference input must be valid before it is declared valid by the reference input monitor (default: 10 ms). 0x0330 [7:0] validation timer , b its[15:8] (default: 0x00) . table 60 . refb lock detectors address bits bit name description 0x0331 [7:0] phase lock threshold phase lock threshold , b its[7:0] (default: 0xbc) ; d efault of 0x02bc = 700 ps 0x0332 [7:0] phase lock threshold , b its[15:8] (default: 0x02) 0x0333 [7:0] phase lock threshold , b its[23:16] (default: 0x00) 0x0334 [7:0] phase lock fill rate phase lock fill rate , b its[7:0] (default: 0x0a = 10 code/pfd cycle) 0x0335 [7:0] phase lock drain rate phase lock drain rate , b its[7:0] (default: 0x0a=10 code/pfd cycle) 0x0336 [7:0] frequency lock threshold frequency lock threshold , b its[7: 0] (default: 0xbc) ; d efault of 0x02bc = 700 ps 0x0337 [7:0] frequency lock threshold , b its[15:8] (default: 0x02) 0x0338 [7:0] frequency lock threshold , b its[23:16] (default: 0x00) 0x0339 [7:0] frequency lock fill rate frequency lock fill rate , b its[7: 0] (default: 0x0a = 10 code/pfd cycle) 0x033a [7:0] frequency lock drain rate frequency lock drain rate , b its[7:0] (default: 0x0a = 10 code/pfd cycle) reference input c (register 0 x 0340 to register 0x 035a) table 61 . refc logic typ e address bits bit name description 0x0340 [7:4] reserved default: 0x0 3 enable refc divide -by -2 enables the reference input divide -by - 2 for refc 0 = bypass es the divide -by - 2 (default) 1 = enable s the divide -by -2 2 reserved default: 0b [1:0] refc lo gic type select s logic family for refc input receiver; only the refc pin is used in cmos mode 00 (default) = differential 01 = 1.2 v to 1.5 v cmos 10 = 1.8 v to 2.5 v cmos 11 = 3.0 v to 3.3 v cmos ad9559 data sheet rev. 0 | page 80 of 120 table 62 . refc 20 - bit dpll r div ider address bits bit name description 0x0341 [7:0] r divider dpll integer reference divider (minus 1), bits[7:0] (default: 0xcf) 0x0342 [7:0] dpll integer reference divider (minus 1), bits[15:8] (default: 0x00) 0x0343 [7:4] reserved default: 0x0 [3:0] r divider dpll integer reference divider (minus 1), bits[19:16] (default: 0x0) table 63 . nominal period of refc input clock address bits bit name description 0x0344 [7:0] ref c n ominal reference period (fs) nominal reference per iod , b its[7:0] (default: 0xc9) 0x0345 [7:0] nominal reference period , b its[15:8] (default: 0xea) 0x0346 [7:0] nominal reference period , b its[23:16] (default: 0x10) 0x0347 [7:0] nominal reference period , b its[31:24] (default: 0x03) 0x0348 [7:0] nomi nal reference period , bits[39:32] (default: 0x00) default for register 0x0344 to register 0x0348 : 0x000310eac9 = 51.44 ns (1/19.44 mhz) table 64 . refc frequency tolerance address bits bit name description 0x0349 [7:0] inner tolera nce input reference frequency monitor inner tolerance , bits[7:0] (default: 0x14) . 0x034a [7:0] input reference freque ncy monitor inner tolerance, bits [15:8] (default: 0x00) . 0x034b [7:4] reserved default: 0x0 . [3:0] inner tolerance input reference fre quency monitor inner tolerance , b its[19:16]. default for regi ster 0x0349 to register 0x034b: 0x0000 14 = 20 (5% or 50,000 ppm). the stratum 3 clock requires inner tolerance of 9.2 ppm and outer tolerance of 12 ppm; an smc clock requires outer tolerance of 48 ppm . the allowable range for the inner tole rance is 0x00a (10%) to 0x8ff ( 2 ppm). 0x034c [7:0] outer tolerance input reference frequency monitor outer tolerance, bits [7:0] (default: 0x0a). 0x034d [7:0] input reference frequency monitor outer toler ance, bits[15:8] (default: 0x00). 0x034e [7:4] reserved default: 0x0 . [3:0] outer tolerance input reference frequency monitor outer tolerance , bits[19:16]. default for regi ster 0x034c to register 0x034e: 0x00000a = 10 (10% or 100,000 ppm). the stratum 3 clock requires inner tolerance of 9.2 ppm and outer tolerance of 12 ppm ; an smc clock requires outer tolerance of 48 ppm. the outer tolerance must be greater than the inner tolerance so that there is hysteresis. table 65 . refc validation timer address bits bit name description 0x034f [7:0] validation timer (ms) validation timer , b its[7:0] (default: 0x0a) . this is the amount of time a reference input must be valid before it is declared valid by the reference input monitor (defau lt: 10 ms). 0x0350 [7:0] validation timer , b its[15:8] (default: 0x00). table 66 . refc lock detectors address bits bit name description 0x0351 [7:0] phase lock threshold phase lock threshold , b its[7:0] (default: 0xbc) ; d efault of 0x02bc = 700 ps 0x0352 [7:0] phase lock threshold , b its[15:8] (default: 0x02) 0x0353 [7:0] phase lock threshold , b its[23:16] (default: 0x00) 0x0354 [7:0] phase lock fill rate phase lock fill rate , b its[7:0] (default: 0x0a = 10 code/pfd cycle) 0x0355 [7:0] phase lock drain rate phase lock drain rate , b its[7:0] (default: 0x0a = 10 code/pfd cycle) 0x0356 [7:0] frequency lock threshold frequency lock threshold , b its[7:0] (default: 0xbc) ; d efault of 0x02bc = 700 ps 0x0357 [7:0] frequency lock threshol d, b its[15:8] (default: 0x02) 0x0358 [7:0] frequency lock threshold , b its[23:16] (default: 0x00) 0x0359 [7:0] frequency lock fill rate frequency lock fill rate , b its[7:0] (default: 0x0a = 10 code/pfd cycle) 0x035a [7:0] frequency lock drain rate freque ncy lock drain rate , b its[7:0] (default: 0x0a = 10 code/pfd cycle) data sheet ad9559 rev. 0 | page 81 of 120 reference input d (r egister 0 x 0360 to register 0x 037a) table 67 . refd logic type address bits bit name description 0x0360 [7:4] reserved default: 0x0 3 enable r efd div ide -by -2 enables the reference input divide -by - 2 for refd 0 = bypass es the divide -by - 2 (default) 1 = enable s the divide -by -2 2 reserved default: 0b [1:0] refd logic type select s logic family for refd input receiver; only the refd pin is used in cmos mode 00 (default) = differential 01 = 1.2 v to 1.5 v cmos 10 = 1.8 v to 2.5 v cmos 11 = 3.0 v to 3.3 v cmos table 68 . refd 20 -b it dpll r divider address bits bit name description 0x0361 [7:0] r divider dpll integer referenc e divider (minus 1), bits[7:0] (default: 0xcf) 0x0362 [7:0] dpll integer reference divider (minus 1), bits[15:8] (default: 0x00) 0x0363 [7:4] reserved default: 0x0 [3:0] r divider dpll integer reference divider (minus 1), bits[19:16] (default: 0x0) t able 69 . nominal period of refd input clock address bits bit name description 0x0364 [7:0] ref d n ominal reference period (fs) nominal reference period , bits[7:0] (default: 0xc9) 0x0365 [7:0] nominal reference period , bits[15:8] ( default: 0xea) 0x0366 [7:0] nominal reference period , bits[23:16] (default: 0x10) 0x0367 [7:0] nominal reference period , bits[31:24] (default: 0x03) 0x0368 [7:0] nominal reference period b its[39:32] (default: 0x00) default for register 0x0364 to re gi ster 0x0368: 0x000310eac9 = 51.44 ns (1/19.44 mhz) table 70 . refd frequency tolerance address bits bit name description 0x0369 [7:0] inner tolerance input reference frequency monitor inner tolerance , bits[7:0] (default: 0x14) . 0x036a [7:0] input reference freque ncy monitor inner tolerance, bits [15:8] (default: 0x00) . 0x036b [7:4] reserved default: 0x0 . [3:0] inner tolerance input reference frequency monit or inner tolerance , bits[19:16] . default for regi ster 0x0369 to register 0x036b: 0x0000 14 = 20 (5% or 50,000 ppm). the stratum 3 clock requires inner tolerance of 9.2 ppm and outer tolerance of 12 ppm; an smc clock requires an outer tolerance of 48 ppm . the allowable range for the inner tole rance is 0x00a (10%) to 0x8ff (2 p pm). 0x036c [7:0] outer tolerance input reference frequency monitor outer tolerance, bits [7:0] (default: 0x0a). 0x036d [7:0] input reference frequency monitor outer tolerance, bits[15:8] (default: 0x00). 0x036e [7:4] reserved default: 0x0 . [3:0] out er tolerance input reference frequency monitor outer tolerance , bits[19:16]. default for regi ster 0x036c to register 0x036e: 0x00000a = 10 (10% or 100,000 ppm). the stratum 3 clock requires an inner tolerance of 9.2 ppm and outer tolerance of 12 ppm; an smc clock requires outer tolerance of 48 ppm. the outer tolerance must be greater than the inner tolerance so that there is hysteresis. table 71 . refd validation timer address bits bit name description 0x036f [7:0] validation tim er (ms) validation timer , b its[7:0] (default: 0x0a) . this is the amount of time a reference input must be valid before it is declared valid by the reference input monitor (default: 10 ms). 0x0370 [7:0] validation timer , b its[15:8] (default: 0x00). ad9559 data sheet rev. 0 | page 82 of 120 table 72 . refd lock detectors address bits bit name description 0x0371 [7:0] phase lock threshold phase lock threshold , b its[7:0] (default: 0xbc) ; d efault of 0x02bc = 700 ps 0x0372 [7:0] phase lock threshold , b its[15:8] (default: 0x02 ) 0x0373 [7:0] phase lock threshold , b its[23:16] (default: 0x00) 0x0374 [7:0] phase lock fill rate phase lock fill rate , b its[7:0] (default: 0x0a = 10 code/pfd cycle) 0x0375 [7:0] phase lock drain rate phase lock drain rate , b its[7:0] (default: 0x0a=1 0 code/pfd cycle) 0x0376 [7:0] frequency lock threshold frequency lock threshold , b its[7:0] (default: 0xbc) ; d efault of 0x02bc = 700 ps 0x0377 [7:0] frequency lock threshold , b its[15:8] (default: 0x02) 0x0378 [7:0] frequency lock threshold , bits[23:16 ] (default: 0x00) 0x0379 [7:0] frequency lock fill rate frequency lock fill rate , b its[7:0] (default: 0x0a = 10 code/pfd cycle) 0x037a [7:0] frequency lock drain rate frequency lock drain rate , b its[7:0] (default: 0x0a = 10 code/pfd cycle) dpll _0 contro ls (register 0x04 00 to register 0 x0415 ) table 73. dpll_0 free r un frequency tuning word address bits bit name description 0x0400 [7:0] 30- bit free run ning frequency tuning word free run ning frequency tuning word , bits[7:0]; default: 0x12 0x0401 [7:0] free run ning frequency tuning word, b its[15:8]; default: 0x15 0x0402 [7:0] free run ning frequency tuning word, b its[23:16 ]; default: 0x64 0x0403 [7:6] reserved default: 00b [5:0] 30- bit free run ning frequency tuning word free run ning f requency tuning word, b its [29:24]; d efault: 0x1b table 74. dpll_0 digital oscillator control address bits bit name description 0x0404 [7:5] reserved default: 0x0 [4:0] digital oscillator sdm integer p art 0000 to 0011 = inv alid 0100 = divide -by -4 0101 = invalid 0110 = divide -by -6 0111 = divide -by -7 1000 = divide -by - 8 (default) 1001 = divide -by -9 1010 = divide -by -10 1011 = divide -by -11 1100 = divide -by -12 1101 = divide -by -13 1110 = divide -by -14 1111 = divide -by -15 table 75 . dpll _0 frequency clamp address bits bit name description 0x0405 [7:0] lower limit of pull - in range (expressed as a 20 - bit frequency tuning word) lower limit pull -i n range , b its [7:0] default: 0x51 0x0406 [7:0] lowe r limit pull - in range, b its [15:8] default: 0x b8 0x0407 [7:4] reserved default: 0x 0 [3:0] lower limit of pull - in range lower limit pull - in range, b its [19:16] default: 0x 2 0x0408 [7:0] upper limit of pull - in range (expressed as a 20 - bit frequency tuning word) upper limi t pull - in range, b its [7:0] default: 0x 3e 0x0409 [7:0] upper limit pull - in range, b its [15:8] default: 0x 0a 0x040a [7:4] reserved default: 0x 0 [3 :0] upper limit of pull - in range upper l imit pull - in range, b its [19:16] default: 0x b data sheet ad9559 rev. 0 | page 83 of 120 table 76. dpll_0 history accumulation timer address bits bit name description 0x040b [7:0] history accumulation timer (expressed in units of ms) history accumulation timer , b its[7:0]. default: 0x0a. for register 0x040b and register 0x040c, 0x000a = 10 ms. maximum: 65 sec. this register controls the amount of tuning word averaging used to determine the tuning word used in holdover. never program a timer value of 0. d efault value : 0x000a = 10 (10 ms). 0x040c [7:0] history accumulation timer , b its[15:8]. default: 0x00. table 77. dpll_0 history mode address bits bit name description 0x040d [7:5] reserved reserved. 4 single sample fallback controls holdover history. if tuning word history is not available for the reference that w as active just prior to holdover, then: 0 (default) = use s the free running frequency tuning word register value. 1 = use s the last tuning word from the dpll. 3 persistent history controls holdover history initialization. when switching to a new referenc e: 0 (default) = clear s the tuning word history. 1 = retain s the previous tuning word history. [2:0] incremental average history m ode value from 0 to 7 (default: 0) . when set to nonzero, causes the first history accumulation to update prior to the first complete averaging period. after the first full interval, updates occur only at the full period. 0 (default) = update only after the full interval has elapsed. 1 = update at 1/2 the full interval. 2 = update at 1/4 and 1/2 of the full interval. 3 = update at 1/8, 1/4, a nd 1/2 of the full interval. 7 = update at 1/256, 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, and 1/2 of the full interval. table 78. dpll_0 fixed closed loop phase offset address bits bit name description 0x040e [7:0] fixe d phase offset (signed; ps ) fixed phase offset , bits[7:0] default: 0x00 0x040f [7:0] fixed phase offset , bits[15:8] default 0x00 0x0410 [7:0] fixed phase offset , b its [23:16] default: 0x00 0x0411 [7:6] reserved reserved ; d efault: 0x0 [5:0] fixed phas e offset (signed; ps ) fixed phase offset , b its [29:24] default: 0x00 table 79. dpll_0 incremental closed - loop phase offset step size 1 address bits bit name description 0x0412 [7:0] incremental phase o ffset step s ize ( ps ) increment al phase offset ste p size , bits[7:0]. default: 0x00 . this register controls the static phase offset of the dpll while it is locked. 0x0413 [7:0] incremental p hase offset step size , b its[15:8] . default: 0x00 . this register controls the static phase offset of the dpll while it is locked. 1 note that the default incremental closed loop phase lock offset step size value is 0x0000 = 0 (0 ns). table 80. dpll_0 phase slew rate limit address bits bit name description 0x0414 [7:0] phase s lew rate l imit ( s/sec ) phase slew rate limit , bits[7:0]. default: 0x00. this register controls the maximum allowable phase slewing during phase adjustment . (the phase adjustment controls are in register 0x040e to register 0x0411.) d efault phase slew rate limit : 0, or disabled. minimum useful value is 310 s/s ec . 0x0415 [7:0] phase slew rate limit , bits[15:8]. default = 0x00 ad9559 data sheet rev. 0 | page 84 of 120 apll_0 configuration (register 0 x 0420 to register 0x0423 ) table 81 . output pll _0 (apll_0) setting 1 addre ss bits bit name description 0x042 0 [7:0] apll _0 charge pump current lsb : 3.5 a 00000001 = 1 lsb; 00000010 = 2 lsb; 11111111 = 255 lsb default: 0x81 = 451 a cp current 0x042 1 [7:0] apll_0 m0 (feedback) d ivider division : 14 to 255 default: 0x14 = divide -by -20 0x0422 [7:6] apll_0 loop filter control pole 2 resistor , rp2 ; d efault: 0x07 rp2 (?) bit 7 bit 6 500 (default) 0 0 333 0 1 250 1 0 200 1 1 [5:3] zero resistor, rzero rzero (?) bit 5 bit 4 bit 3 1500 (default) 0 0 0 1250 0 0 1 1000 0 1 0 930 0 1 1 1250 1 0 0 1000 1 0 1 750 1 1 0 680 1 1 1 [2:0] pole 1 , cp1 cp1 (pf) bit 2 bit 1 bit 0 0 0 0 0 20 0 0 1 80 0 1 0 100 0 1 1 20 1 0 0 40 1 0 1 100 1 1 0 120 (default) 1 1 1 0x0423 [7: 1 ] reserved default: 0x00 . 0 bypass i nternal rzero 0 (default) = use the internal rzero resistor 1 = bypass the internal rzero resistor (makes rzero = 0 and requires the use of a series external zero resistor in addition to the capacitor to ground on the lf_0 pin ) 1 note that the default apll l oop bw is 240 k hz. data sheet ad9559 rev. 0 | page 85 of 120 pll_0 output sync and clock distribution (register 0 x 0424 to register 0x 042e) table 82 . apll_0 p0 divider settings address bits bit name description 0x0424 [7:4] reserved default: 0x0 [3:0] p0 divider divide ratio 0000/0001 = 3 0010 = 4 0011 = 5 0100 = 6 (default) 0101 = 7 0110 = 8 0111 = 9 1000 = 10 1001 = 11 table 83 . distribution output synchronization settings ad dress bits bit name description 0x0425 [7:3] reserved default: 00000b 2 sync source selection select s the sync source for the clock distribution output channels . 0 (default) = direct . 1 = active reference . [1:0] automatic sync mode auto sync mode . 00 = (default) disabled . 01 = sync on dpll frequency lock . 10 = sync on dpll phase lock . 11 = reserved . 0x0426 [7:3] reserved reserved . 2 apll_0 locked controlled sync disable 0 (default) = t he clock distribution sync function is not enabled until the apll has been calibrated and is locked. after apll calibration and lock, the output clock distribution sync is armed, and the sync function for the clock outputs is unde r the control of register 0x0425 . 1 = override s the lock detector state of the apll ; allow s register 0x0 425 to control the output sync function regardless of the apll lock status. 1 mask out0 b sync mask s the synchronous reset to the out0 b divider . 0 (default) = unmasked . 1 = masked . setting this bit asynchronously rele ases the out0b divider from static sync state, thus allowing the out0 b divider to toggle. out0b ignores all sync events while this bit is set. setting this bit does not enable the output drivers connected to this channel. 0 mask out0 a sync mask s the synchronous reset to the o ut0 a divider . 0 (default) = unmasked . 1 = masked . setting this bit asynchronously releases the out 0a divider from static sync state, thus allowing the out0 a divider to toggle. out0 a ignores all sync events while this bit is set. setting this bit does not e nable the output drivers connected to this channel. ad9559 data sheet rev. 0 | page 86 of 120 table 84. distribution out0a settings address bits bit name description 0x0427 7 reserved default: 0b [6:4] out0a format selects the operating mode of out0a. 000 = power-down, tristate. 001 (default) = hstl. 010 = lvds. 011 = reserved. 100 = cmos, both outputs active. 101 = cmos, p output active, n output power-down. 110 = cmos, n output active, p output power-down. 111 = reserved. [3:2] out0a polarity controls the out0a polarity. 00 (default) = positive, negative. 01 = positive, positive. 10 = negative, positive. 11 = negative, negative. 1 out0a lvds boost controls the output drive capability of out0a. 0 (default) = lvds: 3.5 ma drive strength. 1 = lvds: 4.5 ma drive strength (lvds boost mode). 0 reserved default: 0b. table 85. q0_a divider settings address bits bit name description 0x0428 [7:0] q0_a divider 10-bit channel divider, bits[7:0] (lsb). division equals channel divider, bits[9:0] + 1. ([9:0] = 0 is divide-by-1, [9:0] = 1 is divide-by-2[9:0] = 1023 is divide-by-1024) 0x0429 [7:2] reserved reserved. [1:0] q0_a divider 10-bit channel di vider, bits[9:8] (msb), bits[1:0]. 0x042a [7:6] reserved reserved. [5:0] q0_a divider phase divider initial phase after sync relative to the divider input cl ock (from the p0 divider output). lsb is ? of a period of the divider input clock. phase = 0 is no phase offset. phase = 1 is ? a period offset. table 86. distribution out0b settings address bits bit name description 0x042b 7 enable 3.3 v cmos driver 0 (default) = disables 3.3 v cmos driver. out0 b logic is controlled by register 0x042b[6:4]. 1 = enables 3.3 v cmos driver as operating mode of out0b. this bit should be enabled only if bits[6:4] are in cmos mode. [6:4] out0b format select the operating mode of out0b. 000 = power-down, tristate. 001 = hstl. 010 = lvds. 011 = reserved. 100 = cmos, both outputs active. 101 = cmos, p output active, n output power-down. 110 = cmos, n output active, p output power-down. 111 = reserved. [3:2] out0b polarity configure the out0b polarity in cmos mode. these bits are active in cmos mode only. 00 (default) = positive, negative. 01 = positive, positive. 10 = negative, positive. 11 = negative, negative. 1 out0b lvds boost controls the output drive capability of out0b. 0 (default) = lvds: 3.5 ma drive strength. 1 = lvds: 4.5 ma drive strength (lvds boost mode). 0 reserved default: 0b. data sheet ad9559 rev. 0 | page 87 of 120 table 87. q0b_b divider setting address bits bit name description 0x042c [7:0] q0_b divider 10-bit channel divider, bits[7:0] (lsb). division equals channel divider, bits[9:0] + 1. ([9:0] = 0 is divide-by-1, [9:0] = 1 is divide-by-2[9:0] = 1023 is divide-by-1024). 0x042d [7:2] reserved default: 000000b. [1:0] q0_b divider 10-bit channel di vider, bits[9:8] (msb), bits[1:0]. 0x042e [7:6] reserved default: 00b. [5:0] q0_b divider phase divider initial phase after sync relative to the divider input clock (from the p0 divider output). lsb is ? of a period of the divider input clock. phase = 0 is no phase offset. phase = 1 is ? a period offset. dpll_0 settings for reference input a (refa) (register 0x0440 to register 0x044c) table 88. dpll_0 refa priority setting address bits bit name description 0x0440 [7:3] reserved default: 00000b [2:1] refa priority these bits set the priority level (0 to 3) of refa relative to the other input references. 00 (default) = 0 (highest). 01 = 1. 10 = 2. 11 = 3. 0 enable refa this bit enables dpll_0 to lock to refa. 0 = refa is not enabled for use by dpll_0. 1 (default) = refa is enabled for use by dpll_0. table 89. dpll_0 refa loop bw scaling factor address bits bit name description 0x0441 [7:0] dpll loop bw scaling factor (unit of 0.1 hz) digital pll loop bandwidth scaling fa ctor, bits[7:0] (default: 0xf4). 0x0442 [7:0] digital pll loop bandwidth scaling fa ctor, bits[15:8] (default: 0x01). the default for register 0x0441 and regist er 0x0442 = 0x01f4 = 500 (50 hz loop bw). the loop bandwidth should always be less th an the dpll phase detector frequency divided by 20. the dpll may not lock reliably if the dpll loop bw is <50 hz and a crystal is used for the system clock. see the choosing th e sysclk source section for details. 0x0443 [7:2] reserved default: 0x00. 1 base loop filter selection 0 = base loop filter with normal (70) phase margin (default). 1 = base loop filter with high phase margin. (0.1 db peaking in the closed-loop transfer functi on for loop bw 2 khz. setting this bit is also recommended for loop bw > 2 khz.) 0 reserved default: 0b. table 90. dpll_0 refa integer part of feedback divider address bits bit name description 0x0444 [7:0] integer part n0 dpll integer feedback divider (minus 1), bi ts[7:0] (default: 0xcb) 0x0445 [7:0] dpll integer feedback divi der, bits[15:8] (default: 0x07) 0x0446 [7:1] reserved default: 0x00 0 integer part n0 dpll integer feedback divider, bit 16 (default: 0b) default for register 0x0444 to register 0x0446: 0x007cb (which equals n1 = 1996) table 91. dpll_0 refa fractional part of fractional feedback divider frac0 address bits bit name description 0x0447 [7:0] digital pll fractional feedback divider frac0 the numerator of the fractional-n feedba ck divider, bits[7:0] (default: 0x04) 0x0448 [7:0] the numerator of the fractional-n f eedback divider, bits[15:8] (default: 0x00) 0x0449 [7:0] the numerator of the fractional-n f eedback divider, bits[23:18] (default: 0x00) ad9559 data sheet rev. 0 | page 88 of 120 table 92 . dpll_0 refa modulus of fractional feedback divider m od0 address bit s bit name description 0x044a [7:0] digital pll feedback divider modulu s m od0 the denominator of the fractional - n feedback divider, bits[7:0] (default: 0x05) 0x044b [7:0] the denominator of the fractional - n feedback divider, bits[15:8] (default: 0x00) 0x044c [7:0] the denominator of the fractional - n feedback divider, bits[23:17] (d efault: 0x00) dpll_ 0 settings for reference input b (refb) (register 0 x 044d to register 0x0459) table 93 . dpll_0 refb priority setting address bit s bit name description 0x044d [7:3] reserved default: 00000b . [2:1] refb priority these bits set the priority level (0 to 3) of refb relative to the other input references . 00 (default) = 0 (highest). 01 = 1. 10 = 2 . 11 = 3 . 0 enable refb this bit enables dpll_0 to lock to refb. 0 = refb is not enabled for use by dpll_0 . 1 (default) = re fb is enabled for use by dpll_0. table 94 . dpll_0 refb loop bw scaling factor address bit s bit name description 0x044e [7:0] dpll loop bw scaling factor (unit of 0.1 hz) digital pll loop bandwidth scaling factor, bits[7:0] (def ault: 0xf4). 0x044f [7:0] digital pll loop bandwidth scaling factor, bits[15:8] (default: 0x01). the default for register 0x044 e and register 0x044f = 0x01f4 = 500 (50 hz loop bw ). the loop bandwidth should always be less than the dpll phase detector fre quency divided by 20. the dpll may not lock reliably if the dpll loop bw is <50 hz and a crystal is used for the system clock. see the choosing the sysclk source section for details . 0x0450 [7:2] reserved default: 0x00. 1 base loop filter selection 0 = base loop filter with normal (70 ) phase margin (default). 1 = base loop filter with high phase margin. (0.1 db peaking in the closed - loop transfer function for loop bws 2 khz. setting this bit is also recommended for loop bw > 2 khz.) 0 reserved default: 0b . table 95 . dpll_0 refb integer part of feedback divider address bit s bit name description 0x0451 [7:0] integer part n0 dpll integer feedback divider (minus 1), bits[7:0] (default: 0xcb) 0x0452 [7:0] dpll integer feedback divider, bits[15:8] (default: 0x07) 0x0453 [7:1] reserved default: 0x00 0 integer part n0 dpll integer feedback divider, bit 17 (default: 0b) d efault for register 0x04 51 to register 0x4 53: 0x007cb (which equals n1 = 1996) table 96 . dpll_0 refb fractional part of fractional feedback divider frac 0 address bit s bit name description 0x0454 [7:0] digital pll fractional feedback divider f rac 0 the numerator of the fractional - n feedback divider, bits[7:0] (de fault: 0x04) 0x0455 [7:0] the numerator of the fractional - n feedback divider, bits[15:8] (default: 0x00) 0x0456 [7:0] the numerator of the fractional - n feedback divider, bits[23:18] (default: 0x00) table 97 . dpll_0 refb modulus of fractional feedback divider mod0 address bit s bit name description 0x04 57 [7:0] digital pll feedback divider modulus m od0 the denominator of the fractional - n feedback divider, bits[7:0] (default: 0x05) 0x0458 [7:0] the denominator of the fractional - n feedback divider, bits[15:8] (default: 0x00) 0x0459 [7:0] the denominator of the fractional - n feedback divider, bits[23:17] (default: 0x00) data sheet ad9559 rev. 0 | page 89 of 120 dpll_0 settings for reference input c (refc) (register 0 x045a to register 0 x0466 ) table 98 . dpll_0 refc priority setting address bit s bit name description 0x045a [7:3] reserved default: 00000b . [2:1] refc priority these bits set the priority level (0 to 3) of refc relative to the other input references . 00 (default) = 0 (highest). 01 = 1 . 10 = 2 . 11 = 3 . 0 enable refc this bit enables dpll_0 to lock to refc. 0 (default) = refc is not enabled for use by dpll_0 . 1 = refc is enabled for use by dpll_0 . table 99 . dpll_0 refc loop bw scaling factor address bit s bit n ame description 0x045b [7:0] dpll loop bw scaling factor (unit of 0.1 hz) digital pll loop bandwidth scaling factor, bits[7:0] (default: 0xf4). 0x045c [7:0] digital pll loop bandwidth scaling factor, bits[15:8] (default: 0x01). the default for register 0x045b and register 0x045 c: 0x01f4 = 500 (50 hz loop bw ). the loop bandwidth should always be less than the dpll phase detector frequency divided by 20. the dpll may not lock reliably if the dpll loop bw is <50 hz and a crystal is used for the system clock . see the choosing the sysclk source section for details . 0x045d [7:2] reserved default: 0x00. 1 base loop filter selection 0 = base loop filter with normal (70 ) phase margin (default). 1 = base loop filter with high phase mar gin. (0.1 db peaking in the closed - loo p transfer function for loop bw 2 khz. setting this bit is also recommended for loop bw > 2 khz.) 0 reserved default: 0b . table 100 . dpll_0 refc integer part of feedback divider address b it s bit name description 0x045e [7:0] integer part n0 dpll integer feedback divider (minus 1), bits[7:0] (default: 0xcb) . 0x045f [7:0] dpll integer feedback divider, bits[15:8] (default: 0x07) . 0x0460 [7:1] reserved default: 0x00 . 0 integer part n0 d pll integer feedback divider, bit 16 (default: 0b) . the default for register 0x045e to register 0 x4 60: 0x007cb (which equals n1 = 1996) . table 101 . dpll_0 refc fractional part of fractional feedback divider f rac 0 address bit s bit n ame description 0x0461 [7:0] digital pll fractional feedback divider f rac 0 the numerator of the fractional - n feedback divider, bits[7:0] (default: 0x04) . 0x0462 [7:0] the numerator of the fractional - n feedback divider, bits[15:8] (default: 0x00) . 0x0463 [7:0] the numerator of the fractional - n feedback divider, bits[23:18] (default: 0x00) . table 102 . dpll_0 refc modulus of fractional feedback divider m od0 address bit s bit name description 0x0464 [7:0] digital pll feedback divid er modulus m od0 the denominator of the fractional - n feedback divider, bits[7:0] (default: 0x05) . 0x0465 [7:0] the denominator of the fractional - n feedback divider, bits[15:8] (default: 0x00) . 0x0466 [7:0] the denominator of the fractional - n feedback di vider, bits[23:17] (default: 0x00) . ad9559 data sheet rev. 0 | page 90 of 120 dpll_0 settings for reference input d (refd) (register 0 x0467 to register 0 x0473 ) table 103 . dpll_0 refd priority setting address bit s bit name description 0x0467 [7:3] reserved default: 00000b . [2:1] refd priority these bits set the priority level (0 to 3) of ref d relative to the other input references . 00 (default) = 0 (highest). 01 = 1. 10 = 2 . 11 = 3 . 0 enable refd this bit enables dpll_0 to lock to refd. 0 (default) = refd is not enabled for use by dpll_0 . 1 = refd is enabled for use by dpll_0 . table 104 . dpll_0 refd loop bw scaling factor address bit s bit name description 0x0468 [7:0] dpll loop bw scaling factor (unit of 0.1 hz) digital pll loop bandwidth scali ng factor, bits[7:0] (default: 0xf4). 0x0469 [7:0] digital pll loop bandwidth scaling factor, bits[15:8] (default: 0x01). the default for register 0x04 68 and register 0x0469 = 0x01f4 = 500 (50 hz loop bw ). the loop bandwidth should always be less than th e dpll phase detector frequency divided by 20. the dpll may not lock reliably if the dpll loop bw is <50 hz and a crystal is used for the system clock. see the choosing the sysclk source section for details . 0x046a [7:2] reserved default: 0x00. 1 base loop filter selection 0 = base loop filter with normal (70 ) phase margin (default). 1 = base loop filter with high phase margin. (0.1 db peaking in the closed - loop transfer function for loop bws 2 khz. setting this bit is also recommended for loop bw > 2 khz.) 0 reserved default: 0b . table 105 . dpll_0 refd integer part of feedback divider address bit s bit name description 0x046b [7:0] integer part n0 dpll integer feedback divider (minus 1), bits[7:0] (default: 0xcb) . 0x046c [7:0] dpll integer feedback divider, bits[15:8] (default: 0x07) . 0x046d [7:1] reserved default: 0x00 . 0 integer part n0 dpll integer feedback divider, bit 17 (default: 0b) . the default for register 0x046b to register 0x4 6 d: 0x 007cb (which equals n1 = 1996) . table 106 . dpll_0 refd fractional part of fractional feedback divider f rac 0 address bit s bit name description 0x046e [7:0] digital pll fractional feedback divider f rac 0 the numerator of the fraction al - n feedback divider, bits[7:0] (default: 0x04) 0x046f [7:0] the numerator of the fractional - n feedback divider, bits[15:8] (default: 0x00) 0x0470 [7:0] the numerator of the fractional - n feedback divider, bits[23:18] (default: 0x00) table 107 . dpll_0 refd modulus of fractional feedback divider mod0 address bit s bit name description 0x0471 [7:0] digital pll feedback divider modulus mod0 the denominator of the fractional - n feedback divider, bits[7:0] (default: 0x05) 0x0472 [7:0] the denominator of the fractional - n feedback divider, bits[15:8] (default: 0x00) 0x0473 [7:0] the denominator of the fractional - n feedback divider, bits[23:17] (default: 0x00) data sheet ad9559 rev. 0 | page 91 of 120 dpll_1 controls (register 0 x 0500 to register 0x0515) table 108. dpll_1 free run frequency tuning word address bits bit name description 0x0500 [7:0] 30 - bit free running frequency tuning word free running frequency tuning word , b its[7:0] ( default: 0x12 ) 0x0501 [7:0] free running frequency tuning word , b its[15:8] ( default: 0x15 ) 0x0502 [7:0] free running frequency tuning word , b its[23:9] ( default: 0x64 ) 0x0503 [7:6] reserved default: 00b [5:0] 30- bit free running frequency word free running frequency tuning word , b its[29:24] ( default: 0x1b ) table 109. dpll_1 digital oscillator control address bits bit name description 0x0504 [7:5] reserved default: 0x0 [4:0] digital oscillator sdm integer part 0000 to 0011 = invalid 0100 = divide -by -4 0101 = invalid 0110 = divide -by -6 0111 = divide -by -7 1000 = divide -by - 8 (default) 1001 = divide -by -9 1010 = divide -by -10 1011 = divide -by -11 1100 = divide -by -12 1101 = divide -by -13 1110 = divide -by -14 1111 = divide -by -15 table 110. dpll_1 frequency clamp address bits bi t name description 0x0505 [7:0] lower limit of pull - in range (express ed as a 20 - bit frequency tuning word) lower limit pull - in range , bits[7:0] default: 0x51 0x0506 [7:0] lower limit pull - in range , b its[15:8] default: 0xb8 0x0507 [7:4] reserved defaul t: 0x0 [3:0] lower limit of pull - in range lower limit pull - in range, b its[19:16] default: 0x2 0x0508 [7:0] upper limit of pull - in range (express ed as a 20 - bit frequency tuning word) u pper limit pull- in range, b its[7:0] default: 0x3e 0x0509 [7:0] uppe r limit pull - in range, b its[15:8] default: 0x0a 0x050a [7:4] reserved default: 0x0 [3:0] upper limit of pull - in range upper limit pull - in range , b its[19:16] default: 0xb table 111. dpll_1 history accumulation timer address bit s bit name description 0x050b [7:0] history accumulation timer (expressed in units of ms) history accumulation timer , b its[7:0]. default: 0x0a. for register 0x050b and register 0x050c, 0x000a = 10 ms. maximum: 65 sec . this register controls the amount of tuning word averaging used to determine the tuning word used in holdover. never program a timer value of 0. d efault value : 0x000a = 10 (10 ms). 0x050c [7:0] history accumulation timer , b its[15:8]. default: 0x00. ad9559 data sheet rev. 0 | page 92 of 120 table 112. dpll_1 history mode address bit s bit name description 0x050d [7:5] reserved reserved. 4 single sample fallback controls holdover history. if tuning word history is not available for the reference that was active just prior to holdover, then: 0 (default) = use the free running frequency tuning word register value. 1 = use the last tuning word from the dpll. 3 persistent history controls holdover history initialization. when switching to a new reference: 0 (default) = clear the tuning word history. 1 = retain the previous tuning word history. [2:0] incremental average history mode value from 0 to 7 (default = 0) when set to nonzero, causes the first history accumulation to update prior to the first complete averaging period. after the first full interval, upd ates occur only at the full period. 0 (default) = update only after the full interval has elapsed. 1 = update at 1/2 the full interval. 2 = update at 1/4 and 1/2 of the full interval. 3 = update at 1/8, 1/4, and 1/2 of the full interva l. 7 = update at 1/ 256, 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, and 1/2 of the full interval. table 113. dpll_1 fixed closed loop phase offset address bits bit name description 0x050e [7:0] fixed phase offset (signed; ps) fixed phase offset , b its[7:0] de fault: 0x00 0x050f [7:0] fixed phase offset , bits[15:8] default 0x00 0x0510 [7:0] fixed phase offset , bits[23:16] default: 0x00 0x0511 [7:6] reserved reserved; default: 0x0 [5:0] fixed phase offset (signed; ps) fixed phase offset , bits[29:24] defaul t: 0x00 table 114. dpll_1 incremental closed - loop phase offset step size 1 address bits bit name description 0x0512 [7:0] incremental phase offset step size (ps) increment al phase offset step size, b its[7:0]. default: 0x00. this re gister controls the static phase offset of the dpll while it is locked. 0x0513 [7:0] incremental phase offset step size, b its[15:8]. default: 0x00. this register controls the static phase offset of the dpll while it is locked. 1 note that the default incremental closed loop phase lock offset step size value is 0x0000 = 0 (0 ns). table 115. dpll_1 phase slew rate limit address bits bit name description 0x0514 [7:0] phase slew rate limit (s/sec) phase slew rate limit, b its[7:0]. default: 0x00. this register controls the maximum allowable phase slewing during phase adjustment (the phase adjustment controls are in register 0x050e to register 0x0511.) d efault phase slew rate limit: 0, or disabled. minimum useful value is 310 s/sec . 0x0515 [7:0] phase slew rate limit , bits[15:8]. default = 0x00. data sheet ad9559 rev. 0 | page 93 of 120 a pll_1 configuration (register 0 x 0520 to register 0x0523) table 116 . output pll_1 (a pll_1) setting 1 address bit s bit name description 0x0520 [7:0] apll_1 charge pump current lsb = 3.5 a 00000001 = 1 lsb; 00000010 = 2 lsb; 11111111 = 255 lsb default: 0x81 = 451 a cp current 0x0521 [7:0] apll _1 m1 (feedback) divider division: 14 to 255 default : 0x14 = divide -by -20 0x0522 [7:6] apll_1 loop filter control po le 2 resistor , rp2 ; default: 0x07 rp2 (?) bit 7 bit 6 500 (default) 0 0 333 0 1 250 1 0 200 1 1 [5:3] zero resistor, rzero . rzero (?) bit 5 bit 4 bit 3 1500 (default) 0 0 0 1250 0 0 1 1000 0 1 0 930 0 1 1 1250 1 0 0 1000 1 0 1 750 1 1 0 680 1 1 1 [2:0] pole 1 , cp1 cp 1 (pf) bit 2 bit 1 bit 0 0 0 0 0 20 0 0 1 80 0 1 0 100 0 1 1 20 1 0 0 40 1 0 1 100 1 1 0 120 (default) 1 1 1 0x0523 [7: 1 ] reserved default: 0x00 0 bypass i nternal rzero 0 (default) = use s the internal rzero resistor 1 = bypass es the internal rzero resistor (makes rzero = 0 and requires the use of a series external zero resisto r in addition to the capacitor to ground on the lf_1 pin) 1 note th at the default apll l oop bw is 240 k hz. ad9559 data sheet rev. 0 | page 94 of 120 pll_1 output sync and clock distribution (register 0 x 0524 to register 0x 052e) table 117. apll_1 p1 divider settings address bit s bit name description 0x0524 [7:4] reserved default: 0x0 [3:0] p1 d ivider d ivide ratio 0000/0001 = 3 0010 = 4 0011 = 5 0100 = 6 (default) 0101 = 7 0110 = 8 0111 = 9 1000 = 10 1001 = 11 table 118 . distribution output synchronization settings address bit s bit name description 0x0525 [7:3] reserved default: 00000b . 2 sync source selection select s the sync source for the clock distribution output channels . 0 (default) = direct . 1 = active reference . [1:0] automatic sync mode auto matic sync mode . 00 (default) = disabled . 01 = sync on dpll frequency lock . 10 = sync on dpll phase l ock . 11 = reserved . 0x0526 [7:3] reserved default: 00000b . 2 apll_1 locked controlled sync disable 0 (default) = t he clock distribution sync function is not enabled until apll_1 has been calibrated and is locked. after apll calibration and lock, the out put clock distribution sync is armed, and the sync function for the clock outputs is under the control of register 0x0525. 1 = override s the lock detector state of the apll ; allow s register 0x0525 to control the output sync function regardless of the apll lock status. 1 mask out1 b sync mask s the synchronous reset to the out1 b divider . 0 (default) = unmasked. 1 = masked. setting this bit asynchronously releases the out1 b divider from the static sync state, thus allowing the out1 b divider to toggle. out1 b ignores all sync events while this bit is set. setting this bit does not enable the output drivers connected to this channel. 0 mask out1 a sync mask s the synchronous reset to the out1 a divider . 0 (default) = unmasked . 1 = masked. setting this bit asynchronously releases the out1 a divider from the static sync state, thus allowing the out1 a divider to toggle. out1 a ignores all sync events while this bit is set. setting this bit does not enable the output drivers connected to this channel. data sheet ad9559 rev. 0 | page 95 of 120 table 119. distribution out1a settings address bits bit name description 0x0527 7 reserved default: 0b. [6:4] out1a format select the operating mode of out1a. 000 = power-down, tristate. 001 (default) = hstl. 010 = lvds. 011 = reserved. 100 = cmos, both outputs active. 101 = cmos, p output active, n output power-down. 110 = cmos, n output active, p output power-down. 111 = reserved. [3:2] out1a polarity control the out1a polarity. 00 (default) = positive, negative. 01 = positive, positive. 10 = negative, positive. 11 = negative, negative. 1 out1a lvds boost controls the output drive capability of out1a. 0 (default) = lvds: 3.5 ma drive strength. 1 = lvds: 4.5 ma drive strength (lvds boost mode). 0 reserved default: 0b. table 120. q1_a divider settings address bits bit name description 0x0528 [7:0] q1_a divider 10-bit channel divider, bits[7:0] (lsb). division equals channel divider, bits[9:0] + 1. ([9:0] = 0 is divide-by-1, [9:0] = 1 is divide-by-2[9:0] = 1023 is divide-by-1024). 0x0529 [7:2] reserved reserved. [1:0] q1_a divider 10-bit channel di vider, bits[9:8] (msb), bits[1:0]. 0x052a [7:6] reserved reserved. [5:0] q1_a divider phase divider initial phase after sync relative to the divider input cl ock (from the p1 divider output). lsb is ? of a period of the divider input clock. phase = 0 is no phase offset. phase = 1 is ? a period offset. table 121. distribution out1b settings address bits bit name description 0x052b 7 enable 3.3 v cmos driver 0 (default) = disables 3.3 v cmos driver, an d out1b logic is controlled by 0x052b[6:4]. 1 = enables 3.3 v cmos driver as operating mode of out1. this bit should be enabled only if bits[6:4] are in cmos mode. [6:4] out1b format select the operating mode of out1b. 000 = power-down, tristate. 001 = hstl. 010 = lvds. 011 = reserved. 100 = cmos, both outputs active. 101 = cmos, p output active, n output power-down. 110 = cmos, n output active, p output power-down. 111 = reserved. [3:2] out1b polarity configure the out1b polarity in cmos mode. these bits are active in cmos mode only. 00 (default) = positive, negative. 01 = positive, positive. 10 = negative, positive. 11 = negative, negative. 1 out1b lvds boost controls the output drive capability of out1b. 0 (default) = lvds: 3.5 ma drive strength. 1 = lvds: 4.5 ma drive strength (lvds boost mode). 0 reserved default: 0b. ad9559 data sheet rev. 0 | page 96 of 120 table 122 . out1 b divider setting address bit s bit name description 0x052c [7:0] q1_ b divide r 10- bit channel divider, b its[7:0] (lsb). d ivision equals channel divider, b its[9:0] + 1. ([9:0] = 0 is divide -by - 1, [9:0] = 1 is divide -by - 2[9:0] = 1023 is divide -by -1024). 0x052d [7:2] reserved default: 000000b. [1:0] q1_ b divider 10 - bit channel di vider, b its[9:8] (msb) , bits [1:0]. 0x052e [7:6] reserved default: 00b. [5:0] q1_b divider phase divider initial phase after sync relative to the divider input clock (from the p1 divider output). lsb is ? of a period of the divider input clock. phase = 0 is no phase offset. phase = 1 is ? a period offset. dpll_1 settings for referen ce input c ( refc ) (register 0 x 0540 to register 0x 054c) table 123 . dpll_1 refc priority setting address bit s bit name description 0x0540 [7:3] reserve d reserved. [2:1] refc priority these bits set the priority level (0 to 3) of refd relative to the other input references . 00 (default) = 0 (highest). 01 = 1. 10 = 2 . 11 = 3 . 0 enable refc this bit enables dpll_1 to lock to refc. 0 = refc is not enable d for use by dpll_1 . 1 (default) = refc is enabled for use by dpll_1. table 124 . dpll_1 refc loop bw scaling factor address bit s bit name description 0x0541 [7:0] dpll loop bw scaling factor (unit of 0.1 hz) digital pll loop bandw idth scaling factor, bits[7:0] (default: 0xf4). 0x0542 [7:0] digital pll loop bandwidth scaling factor, bits[15:8] (default: 0x01). d efault for register 0x0541 and register 0x0542 : 0x01f4 = 500 (50 hz loop bw ). the loop bandwidth should always be less th an the dpll phase detector frequency divided by 20. the dpll may not lock reliably if the dpll loop bw is <50 hz and a crystal is used for the system clock. see the choosing the sysclk source section for details . 0x0543 [7:2] reserved default: 0x00. 1 base loop filter selection 0 = base loop filter with normal (70 ) phase margin (default). 1 = base loop filter with high phase margin. (0.1 db peaking in the closed - loo p transfer function for loop bw 2 khz. setting this bit is also recommended for loop bw > 2 khz.) 0 reserved default: 0b . table 125 . dpll_1 refc in teger part of feedback divider address bit s bit name description 0x0544 [7:0] integer part n1 dpll integer feedback divider (minus 1), bits[7:0] (default: 0xcb) . 0x0545 [7:0] dpll integer feedback divider, bits[15:8] (default: 0x07) . 0x0546 [7:1] reser ved default: 0x00 . 0 integer part n1 dpll integer feedback divider, bit 16 (default: 0b) . d efault for register 0x0544 to register 0x0546: 0x007cb (which equals n1 = 1996) . table 126 . dpll_1 refc fractional part of fractional feed back divider frac 1 address bit s bit name description 0x0547 [7:0] digital pll fractional feedback divider f rac 1 the numerator of the fractional - n feedback divider, bits[7:0] (default: 0x04) 0x0548 [7:0] the numerator of the fractional - n feedback divider , bits[15:8] (default: 0x00) 0x0549 [7:0] the numerator of the fractional - n feedback divider, bits[23:18] (default: 0x00) data sheet ad9559 rev. 0 | page 97 of 120 table 127 . dpll_1 refc modulus of fractional feedback divider mod1 address bit s bit name description 0x054a [7:0] digital pll feedback divider modulus mod 1 the denominator of the fractional - n feedback divider, bits[7:0] (default: 0x05) 0x054b [7:0] the denominator of the fractional - n feedback divider, bits[15:8] (default: 0x00) 0x054c [7:0] the denominator of the fractional - n feedback divider, bits[23:17] (default: 0x00) dpll_1 settings for reference input d ( refd ) (register 0 x 054d to register 0x0559) table 128 . dpll_1 refd priority setting address bit s bit name description 0x054d [7:3] reserved default: 00000b . [2:1] refd priority these bits set the priority level (0 to 3) of refd relative to the other input references . 00 (default) = 0 (highest). 01 = 1 10 = 2 11 = 3 0 enable refd this bit enables dpll_1 to lock to refd. 0 = refd is not enabled for use by dpll_1 1 (default) = refd is enabled for use by dpll_1 table 129 . dpll_1 refd loop bw scaling factor address bit s bit name description 0x054e [7:0] dpll loop bw scaling factor (unit of 0.1 hz) digit al pll loop bandwidth scaling factor, bits[7:0] (default: 0xf4). 0x054f [7:0] digital pll loop bandwidth scaling factor, bits[15:8] (default: 0x01). the default for register 0x054 e and register 0x054f = 0x01f4 = 500 (50 hz loop bw ). the loop bandwidth should always be less than the dpll phase detector frequency divided by 20. the dpll may not lock reliably if the dpll loop bw is <50 hz and a crystal is used for the system clock. see the choosing the sysclk source section for deta ils . 0x0550 [7:2] reserved default: 0x00. 1 base loop filter selection 0 = base loop filter with normal (70 ) phase margin (default). 1 = base loop filter with high phase margin. (0.1 db peaking in the closed - loop transfer function for loop bw 2 khz . setting this bit is also recommended for loop bw > 2 khz.) 0 reserved default: 0 b. table 130 . dpll_1 refd integer part of feedback divider address bit s bit name description 0x0551 [7:0] integer part n1 dpll integer feedback di vider (minus 1), bits[7:0] (default: 0xcb) . 0x0552 [7:0] dpll integer feedback divider, bits[15:8] (default: 0x07) . 0x0553 [7:1] reserved default: 0x00 . 0 integer part n1 dpll integer feedback divider, bit 16 (default: 0b) . the default for register 0x 0551 to register 0x0553: 0x007cb (which equals n1 = 1996) . table 131 . dpll_1 refd fractional part of fractional feedback divider f rac 1 address bit s bit name description 0x0554 [7:0] digital pll fractional feedback divider f rac 1 th e numerator of the fractional - n feedback divider, bits[7:0] (default: 0x04) 0x0555 [7:0] the numerator of the fractional - n feedback divider, bits[15:8] (default: 0x00) 0x0556 [7:0] the numerator of the fractional - n feedback divider, bits[23:18] (defaul t: 0x00) table 132 . dpll_1 refd modulus of fractional feedback divider m od 1 address bit s bit name description 0x0557 [7:0] digital pll feedback divider modulus m od 1 the denominator of the fractional - n feedback divider, bits[7:0] ( default: 0x05) 0x0558 [7:0] the denominator of the fractional - n feedback divider, bits[15:8] (default: 0x00) 0x0559 [7:0] the denominator of the fractional - n feedback divider, bits[23:17] (default: 0x00) ad9559 data sheet rev. 0 | page 98 of 120 dpll_1 settings for reference input a ( refa ) (r egister 0 x 055a to register 0x0566) table 133 . dpll_1 refa priority setting address bit s bit name description 0x055a [7:3] reserved default: 0 0000b. [2:1] refa priority these bits set the priority level (0 to 3) of ref a relative t o the other input references . 00 (default) = 0 (highest). 01 = 1 . 10 = 2 . 11 = 3 . 0 enable refa this bit enables dpll_1 to lock to refa . 0 (default) = refa is not enabled for use by dpll_1 . 1 = refa is enabled for use by dpll_1 . table 134 . dpll_1 refa loop bw scaling factor address bit s bit name description 0x055b [7:0] dpll loop bw scaling factor (unit of 0.1 hz) digital pll loop bandwidth scaling factor, bits[7:0] (default: 0xf4). 0x055c [7:0] digital pll loop bandwidth sca ling factor, bits[15:8] (default: 0x01). the default for register 0x05 5b and register 0x0555c = 0x01f4 = 500 (50 hz loop bw ). the loop bandwidth should always be less than the dpll phase detector frequency divided by 20. the dpll may not lock reliably if the dpll loop bw is <50 hz and a crystal is used for the system clock. see the choosing the sysclk source section for details . 0x055d [7:2] reserved default: 0x00. 1 base loop filter selection 0 = base loop filter with normal (7 0 ) phase margin (default). 1 = base loop filter with high phase margin. (0.1 db peaking in the closed - loo p transfer function for loop bw 2 khz. setting this bit is also recommended for loop bw > 2 khz.) 0 reserved default: 0b. table 135 . dpll_1 refa in teger part of feedback divider address bit s bit name description 0x055e [7:0] integer part n1 dpll integer feedback divider (minus 1), bits[7:0] (default: 0xcb) . 0x055f [7:0] dpll integer feedback divider, bits[15:8] (default: 0x07) . 0x0560 [7:1] reser ved default: 0x00 . 0 integer part n1 dpll integer feedback divider, bit 16 (default: 0b) . the default for register 0x055e to register 0x05 60: 0x007cb (which equals n1 = 1996) . table 136 . dpll_1 refa fractional part of fractional feedback divider f rac 1 address bit s bit name description 0x0561 [7:0] digital pll fractional feedback divider frac 1 the numerator of the fractional - n feedback divider, bits[7:0] (default: 0x04) 0x0562 [7:0] the numerator of the fractional - n feedback div ider, bits[15:8] (default: 0x00) 0x0563 [7:0] the numerator of the fractional - n feedback divider, bits[23:18] (default: 0x00) table 137 . dpll_1 refa modulus of fractional feedback divider mod 1 address bit s bit name description 0x0564 [7:0] digital pll feedback divider modulus mod 1 the denominator of the fractional - n feedback divider, bits[7:0] (default: 0x05) 0x0565 [7:0] the denominator of the fractional - n feedback divider, bits[15:8] (default: 0x00) 0x0566 [7:0] the denomin ator of the fractional - n feedback divider, bits[23:17] (default: 0x00) data sheet ad9559 rev. 0 | page 99 of 120 dpll_1 settings for reference input b ( refb ) (register 0 x 0567 to register 0x0573) table 138 . dpll_1 refb priority setting address bit s bit name description 0x 0567 [7:3] reserved default: 0 0000b. [2:1] refb priority these bits set the priority level (0 to 3) of refa relative to the other input references . 00 (default) = 0 (highest). 01 = 1. 10 = 2 . 11 = 3 . 0 enable refb this bit enables dpll_1 to lock to ref b. 0 (default) = refb is not enabled for use by dpll_1 . 1 = refb is enabled for use by dpll_1 . table 139 . dpll_1 refb loop bw scaling factor address bit s bit name description 0x0568 [7:0] dpll loop bw scaling factor (unit of 0.1 hz) digital pll loop bandwidth scaling factor, bits[7:0] (default: 0xf4). 0x0569 [7:0] digital pll loop bandwidth scaling factor, bits[15:8] (default: 0x01). d efault for register 0x05 68 to register 0x05 6a: 0x01f4 = 500 (50 hz loop bw. the loop bandwidth should always be less than the dpll phase detector frequency divided by 20. the dpll may not lock reliably if the dpll loop bw is <50 hz and a crystal oscillator is used for the system clock. see the choosing the sysclk source sec tion for more information . 0x056a [7:2] reserved default: 0x00. 1 base loop filter selection 0 = base loop filter with normal (70 ) phase margin (default). 1 = base loop filter with high phase margin. (0.1 db peaking in the closed - loop transfer function for loop bws 2 khz. setting this bit is also recommended for loop bw > 2khz.) 0 reserved default: 0b . table 140 . dpll_1 refb integer part of feedback divider address bit s bit name description 0x056b [7:0] integer part n1 dp ll integer feedback divider (minus 1), bits[7:0] (default: 0xcb) 0x056c [7:0] dpll integer feedback divider, bits[15:8] (default: 0x07) 0x056d [7:1] reserved default: 0x00 0 integer part n1 dpll integer feedback divider, bit 1 6 (default: 0b) d efault f or register 0x056b to register 0x056d: 0x007cb (which equals n1 = 1996) table 141 . dpll_1 refb fractional part of fractional feedback divider f rac 1 address bit s bit name description 0x056e [7:0] digital pll fractional feedback div ider f rac 1 the numerator of the fractional - n feedback divider, bits[7:0] (default: 0x04) 0x056f [7:0] the numerator of the fractional - n feedback divider, bits[15:8] (default: 0x00) 0x0570 [7:0] the numerator of the fractional - n feedback divider, bits[2 3:18] (default: 0x00) table 142 . dpll_1 refb modulus of fractional feedback divider mod1 address bit s bit name description 0x0571 [7:0] digital pll feedback divider modulus m od 1 the denominator of the fractional - n feedback divider , bits[7:0] (default: 0x05) 0x0572 [7:0] the denominator of the fractional - n feedback divider, bits[15:8] (default: 0x00) 0x0573 [7:0] the denominator of the fractional - n feedback divider, bits[23:17] (default: 0x00) ad9559 data sheet rev. 0 | page 100 of 120 digital loop filter coefficients ( register 0 x 0800 to register 0x0817) table 143 . base digital loop filter with normal phase margin (pm = 70 , bw = 0.1 hz, third pole frequency = 1 hz, n1 = 1) 1 address bit s bit name description 0x0800 [7:0] npm alpha - 0 linear alpha - 0 coefficient linear , bits[7:0]; d efault: 0x24 0x0801 [7:0] alpha - 0 coefficient linear, bits[15:8]; d efault: 0x8c 0x0802 7 reserved default: 0b [6:0] npm alpha - 1 exponent al pha - 1 coefficient exponent, bits[6:0]; d efault: 0x49 0x0803 [7:0] npm beta -0 linear beta - 0 coefficient linear, bits[7:0]; d efault: 0x55 0x0804 [7:0] beta -0 coefficient linear, bits[15:8]; d efault: 0xc9 0x0805 7 reserved default: 0b [6:0] npm beta - 1 exponent beta - 1 coefficient exponent , bits[6:0]; d efault: 0x7b 0x0806 [7:0] np m gamma - 0 linear gamma - 0 coefficient linear , bits[7:0]; d efault: 0x9c 0x0807 [7:0] gamma - 0 coefficient linear , bits [15: 8]; d efault: 0 xfa 0x0808 7 reserved default: 0b [6:0] npm gamma - 1 exponent gamma - 1 coefficient exponent , bits[6:0]; default: 0x55 0x0809 [7:0] npm delta - 0 linear delta - 0 coefficient linear , bits[7:0]; d efault: 0xea 0x080a [7:0] delta - 0 coefficient linear , bits[15:8]; d efault: 0xe2 0x080b 7 reserved default: 0b [6:0] npm delta - 1 exponent delta - 1 coefficient exponent , bits[6:0]; d efault: 0x57 1 note that the digital loop filter base coefficients (, , , and ) have the general form: x(2 y ), where x is the linear component and y is the exponential component of the coefficient. the value of the linear component (x) constitutes a fraction, where 0 x 1. the exponential component (y) is a signed integer. these are live registers ; therefore, an io_update is not needed. however, the updated coefficients do not take effect while the loop is locked. table 144. base digital loop filter with high phase margin (pm = 88.5 , bw = 0.1 hz, third pole frequency = 20 hz, n1 = 1) 1 address bit s bit name description 0x080c [7:0] hpm alpha - 0 linear alpha - 0 coefficient linear , bits[7:0]; d efault = 0x8c 0x080d [7:0] alpha -0 coef ficient linear, bits[15:8]; d efault: 0xad 0x080e 7 reserved default: 0b [6:0] hpm alpha - 1 exponent alpha -1 c oefficient exponent, bits[6:0]; d efault: 0x4c 0x080f [7:0] hpm beta - 0 linear beta -0 coefficient linear, bits[7:0]; d efault: 0xf5 0x0810 [7 :0] beta -0 coefficient linear, bits[15:8]; d efault: 0xcb 0x0811 7 reserved default: 0b [6:0] hpm beta - 1 exponent beta - 1 coefficient exponent , bits[6:0]; d efault: 0x73 0x0812 [7:0] hpm gamma - 0 linear gamma - 0 coefficient linear , bits[7:0]; d efault: 0x24 0x0813 [7:0] gamma - 0 coefficient linear , bits[15:8]; default: 0xd8 0x0814 7 reserved default: 0b [6:0] hpm gamma - 1 exponent gamma - 1 coefficient exponent , bits[6:0]; default: 0x59 0x0815 [7:0] hpm delta - 0 linear delta - 0 coefficient linear , bits[7:0]; d efault: 0xd2 0x0816 [7:0] delta - 0 coefficient linear , bits[15:8]; d efault: 0x8d 0x0817 7 reserved default: 0b [6:0] hpm delta - 1 exponent delta - 1 coefficient exponent , bits[6:0]; d efault: 0x5a 1 note that the base digital loop filter coefficients (, , , and ) have the general form: x(2y), where x is the linear component and y is the exponential component of the coefficient. the value of the linear component (x) constitutes a fraction, where 0 x 1. the exponential component (y) is a signed int eger. these are live registers; therefore, an io_u pdate is not needed. however, the updated coefficients do not take effect while the loop is locked. data sheet ad9559 rev. 0 | page 101 of 120 common operational controls (register 0x 0a00 to register 0 x 0a0e ) table 145. global operational controls address bit s bit name description 0x0a00 [7 :3 ] reserved default: 00000b . 2 soft sync a ll setting this bit initiates synchronization of all clock distribution outputs (default = 0b). non maske d outputs stall when value is 1; restart is initialized on a 1 -to - 0 transition. 1 calibrate a ll calibrates both output pll0 (apll_0) and output pll1 (apll_1) . 0 p ower d own a ll places the entire device in deep sleep mode (default: device is not powered down) . table 146 . reference input power - down address bit s bit name description 0x0a01 [7:4] reserved default: 0x0 3 refd power - down power s down refd input receiver 0 (default) = not powered down 1 = powered down 2 refc power - down power s down refc input receiver 0 (de fault) = not powered down 1 = powered down 1 refb power - down power s down refb input receiver 0 (default) = not powered down 1 = powered down 0 re fa power - down power s down refa input receiver 0 (default) = not powered down 1 = powered down table 147 . reference input validation timeout address bit s bit name description 0x0a02 [7:4] reserved default: 0x0 3 refd t imeout (auto clear) if refd is unfaulted, setting this auto clearing bit forces the reference validation timer for re fd to zero, t hus making it valid immediately (default = 0b). 2 refc t imeout (auto clear) if refc is unfaulted, setting this auto clearing bit forces the reference validation timer for refc to zero, t hus making it valid immediately (default = 0b). 1 refb t imeout (auto clear) if refb is unfaulted, setting this auto clearing bit forces the reference validation timer for refb to zero, t hus making it valid immediately (default = 0b). 0 refa t imeout (auto clear) if refa is unfaulted, setting this auto clearing bit forces the reference validation timer for refa to zero, t hus making it valid immediately (default = 0b). table 148 . force reference input fault address bit s bit name description 0x0a03 [7:4] reserved default: 0x0 3 refd f a ult fault s refd input receiver 0 (default) = not faulted 1 = faulted (refd is not used ) 2 refc f ault fault s refc input receiver 0 (default) = not faulted 1 = faulted (refc is not used ) 1 refb f ault fault s refb input receiver 0 (default) = not faulted 1 = faulted (refb is not used ) 0 refa f ault fault s refa input receiver 0 (default) = not faulted 1 = faulted (refa is not used ) ad9559 data sheet rev. 0 | page 102 of 120 table 149 . reference input monitor bypass address bit s bit name description 0x0a04 [7:4] reserved de fault : 0x0 3 refd monitor b ypass bypass es refd input receiver frequency monitor 0 (default) = refd frequency monitor not bypassed 1 = refd frequency monitor bypassed 2 refc monitor b ypass bypass es refc input receiver frequency monitor 0 (default) = re fc frequency monitor not bypassed 1 = refc frequency monitor bypassed 1 refb monitor b ypass bypass es refb input receiver frequency monitor 0 (default) = refb frequency monitor not bypassed 1 = refb b frequency monitor bypassed 0 refa monitor b ypass bypa sses refa input receiver frequency monitor 0 (default) = refa frequency monitor not bypassed 1 = refa frequency monitor bypassed irq clearing ( register 0x0a05 to register 0x0a0e ) the i rq c learing registers are identical in format to the irq m onitor regis ters ( register 0x0d0 8 to register 0x 0d 10 ). when set to l ogic 1, an irq c learing bit resets the corresponding irq m onitor bit, thereby cancel l ing the interrupt request fo r the indicated event. the irq c learing register s are auto clearing. table 150. irq clearing of groups address bit s bit name description 0x0a05 7 clear w atchdog timer clears watchdog timer alert [6:4] reserved reserved 3 clear dpll_1 irq s clears all irqs associated with dpll_1 2 clear dpll_0 irq s clears all irqs associated with dpll_0 1 clear c ommon irq s c lears all irqs associated with common irq g roup 0 clear a ll irq s clears all irqs table 151 . irq clearing for sysclk and eeprom address bits bit name description 0x0 a06 7 reserved re served 6 sysclk unlocked clears irq indicating a sysclk pll state transition from locked to unlocked 5 sysclk stable clears irq indicating that sysclk stability time has expired and that the sysclk pll is considered to be stable. 4 sysclk locked clea rs irq indicating a sysclk pll state transition from unlocked to locked 3 watchdog timer clears irq indicating expiration of the watchdog timer 2 reserved reserved 1 eeprom fault clears irq indicating a fault during an eeprom load or save operation 0 eeprom complete clears irq indicating successful completion of an eeprom load or save operation data sheet ad9559 rev. 0 | page 103 of 120 table 152 . irq clearing for reference inputs address bits bit name description 0x0a07 7 reserved reserved 6 refb validated clears irq indicating that refb has been validated 5 refb fault cleared clears irq indicating that refb has been cleared of a previous fault 4 refb fault clears irq indicating that refb has been faulted 3 reserved reserved 2 refa validated clears irq indicating that refa has been validated 1 refa fault cleared clears irq indicating that refa has been cleared of a previous fault 0 refa fault clears irq indicating that refa has been faulted 0x0a08 7 reserved reserved 6 refd validated clears irq indicating that refd has been validated 5 refd fault cleared clears irq indicating that refd has been cleared of a previous fault 4 refd fault clears irq indicating that refd has been faulted 3 reserved reserved 2 refc validated clears irq indicating that refc has been validated 1 refc fault cleared clears irq indicating that refc has been cleared of a previous fault 0 refc fault clears irq indicating that refc has been faulted table 153 . irq clearing for digital pll0 (dpll_0) address bits bit name description 0x0a09 7 frequency unclamp ed clears irq indicating that dpll_0 has exited a frequency clamped state 6 frequency clamp ed clears irq indicating that dpll_0 has entered a frequency clamped state 5 phase slew unlimited clears irq indicating that dpll_0 has exited a phase slew limited state 4 phase slew limited clears irq indicating that dpll_0 has entered a phase slew limited state 3 frequency unlocked clears irq indicating that dpll_0 has lost frequency lock 2 fre quency locked clears irq indicating that dpll_0 has acquired frequency lock 1 phase unlocked clears irq indicating that dpll_0 has lost phase lock 0 phase locked clears irq indicating that dpll_0 has acquired phase lock 0x0a0a 7 dpll_0 s witching clear s irq indicating that dpll_0 is switching to a new reference 6 dpll_0 f ree run clears irq indicati ng that dpll_0 has entered free run mode 5 dpll_0 h oldover clears irq indicating that dpll_0 has entered holdover mode 4 h istory updated clears irq indicating that dpll_0 has updated its tuning word history 3 refd activated clears irq indicating that dpll_0 has activated refd 2 refc activated clears irq indicating that dpll_0 has activated refc 1 refb activated clears irq indicating that dpll_0 has activated refb 0 refa activated clears irq indicating that dpll_0 has activated refa 0x0a0b [7:5] reserved reserved 4 sync distribution clears irq indicating a distribution sync event 3 apll_0 unlocked clears irq indicating that apll_0 has been unlocked 2 apll_0 locked clears irq indicating that apll_0 has been locked 1 apll_0 c al complete clears irq indicating that apll_0 calibration complete 0 apll_0 c al started clears irq indicating that apll_0 calibration started ad9559 data sheet rev. 0 | page 104 of 120 table 154 . irq clearing for digital pll1 (dpll_1) address bits bit name description 0x0a0c 7 frequency unclamp clears irq indicating that dpll_1 has exited a frequency clamped state 6 frequency clamp clears irq indicating that dpll_1 has entered a freque ncy clamped state 5 phase slew unlimited clears irq indicating that dpll_1 has exited a phase slew limited state 4 phase slew limited clears irq indicating that dpll_1 has entered a phase slew limited state 3 frequency unlocked clears irq indicating that dpll_1 has lost frequency lock 2 frequency locked clears irq indicating that dpll_1 has acquired frequency lock 1 phase unlocked clears irq indicating that dpll_1 has lost phase lock 0 phase locked clears irq indicating that dpll_1 has acquired phase lock 0x0a0d 7 dpll_1 s witching clears irq indicating that dpll_1 is switching to a new reference 6 dpll_1 f ree run clears irq indicati ng that dpll_1 has entered free run mode 5 dpll_1 h oldover clears irq indicating that dpll_1 has entered holdov er mode 4 history updated clears irq indicating that dpll_1 has updated its tuning word history 3 refd activated clears irq indicating that dpll_1 has activated refd 2 refc activated clears irq indicating that dpll_1 has activated refc 1 refb activ ated clears irq indicating that dpll_1 has activated refb 0 refa activated clears irq indicating that dpll_1 has activated refa 0x0a0e [7:5] reserved reserved 4 sync distribution clears irq indicating a distribution sync event 3 apll_1 unlocked cle ars irq indicating that apll_1 has been unlocked 2 apll_1 locked clears irq indicating that apll_1 has been locked 1 apll_1 c al complete clears irq indicating that apll_1 calibration complete 0 apll_ 1 c al started clears irq indicating that apll_1 cal ibration started pll_ 0 operational controls (register 0x0a20 to register 0 x0a24) table 155 . pll_0 sync and calibration address bit s bit name description 0x0a20 [7:3] reserved default: 0x0 2 apll_0 soft s ync setting this bit ini tiates synchronization o f the clock distribution output . default: 0b . non maske d outputs stall when value is 1; restart is initialized on a 1 -to - 0 transition. 1 apll_0 c alibrate (not self - clearing) 1 = initiat es vco calibration (calibration occurs on a 0 -to -1 transition). 0 (default) = does nothing. this bit is not an auto clearing bit . 0 pll_0 power -d own places dpll_0, apll_0, and pll_0 clock in deep sleep mode . d efault : the device is not powered down . table 156 . pll_0 output di sable address bit s bit name description 0x0a21 [7:4] reserved default 0x0 3 out0 b d isable setting this bit puts the only out0 b driver into power - down. default: 0b . channel synchronization is maintained, but runt pulses may be generated. 2 out0 a d isable setting this bit puts the only out0 a driver into power - down. default: 0b . channel synchronization is maintained, but runt pulses may be generated. 1 out0b c hannel p ower - down setting this bit puts the out0b divider and driver into power - down. default: 0b. this mode saves the most power, but runt pulses may be generated during exit. 0 out0 a c hannel p ower - down setting this bit puts the out0 a divider and driver into power - down. default: 0b . this mode saves the most power, but runt pulses may be generated during exit. data sheet ad9559 rev. 0 | page 105 of 120 table 157. d pll_0 user mode address bit s bit name description 0x0a22 7 reserved default: 0b [6:5] dpll_0 manual r eference input reference when user selection mode = 00, 01, 10, or 11 00 (default) = input refere nce a 01 = input reference b 10 = input reference c 11 = input reference d [4:2] dpll_0 switching m ode select s the operating mode of the re ference switching state machine reference switchover mode, bits[2:0] reference selection mode 000 automati c revertive mode 001 automatic nonrevertive mode 010 manual reference select mode (with automatic fallback) 011 manual reference select mode (with automatic holdover fallback) 100 manual reference select mode (without holdover fallback) 101 not used 110 not used 111 not used 1 dpll_0 user h oldover f orces dpll _0 into holdover mode 0 (default) = normal operation 1 (default) = dpll_0 is forced into holdover mode until this bit is cleared 0 dpll_0 u ser free run f orces dpll _0 into free run mode 0 (default) = normal operation 1 = dpll_0 is forced into free run mode until this bit is cleared table 158. d pll_0 reset address bit s bit name description 0x0a23 [7:3] reserved default: 00000b . 2 reset dpll_0 loop f ilter setting this bit clears the digital loop filter (intended as a debug tool). 1 reset dpll_0 tw h istory setting this bit resets the tuning word history logic (part of holdover functionality). 0 reset dpll_0 auto sync setting this bit resets the automatic synchronization logic (see register 0x0425). table 159. d pll_0 phase address bit s bit name description 0x0a24 [7:3] reserved default: 00000b . 2 dpll_0 r eset phase offset resets the incremental phase offset to zero. thi s is an auto clearing bit. 1 dpll_0 d ecrement phase offset decrements the incremental phase offset by the amount specified in the i ncremental phase lock offset step size register s (register 0x0412 and register 0x0413). this is an auto clearing bit. 0 dpl l_0 i ncrement phase offset increments the incremental phase offset by the amount specified in the i ncremental phase lock offset step size register s (register 0x0412 and register 0x0413). this is an auto clearing bit. ad9559 data sheet rev. 0 | page 106 of 120 pll_1 operational co ntrols (register 0 x 0a40 to register 0x 0a44) table 160 . pll_1 sync and calibration address bit s bit name description 0x0a40 [7:3] reserved default: 0x0 . 2 apll_1 soft sync setting this bit initiates synchronization of the clock distribution output . d efault : 0b . nonmasked outputs stall when value is 1 ; restart is initial ized on a 1 -to - 0 transition. 1 apll_1 calibrate (not self - clearing) 1 = initiates vco calibration (c alibration occurs on a 0- to -1 transition). 0 (default) = does nothing. this bit is not auto clearing. 0 pll_1 power - down places dpll_1, apll_1, and pll_1 clock in deep sleep mode . d efault : the device is not powered down. table 161 . pll_1 output disable address bit s bit name description 0x0a41 [7:4] reserve d default 0x0 . 3 out1 b d isable setting this bit puts th e only out 1 b driver into power - down. default: 0b . channel synchronization is maintained, but runt pulses may be generated. 2 out1 a disable setting this bit puts th e only out1 a driver into power - dow n. default: 0b . channel synchronization is maintained, but runt pulses may be generated. 1 out1 b channel power - down setting this bit puts the out1 b divider and driver into power - down. default: 0b . this mode saves the most power, but runt pulses may be generated during exit. 0 out1 a channel power - down setting this bit puts the out1 a divider and driver into power - down. default: 0b . this mode saves the most power, but runt pulses may be generated during exit. table 162. dpll_1 user mode address bit s bit name description 0x0a42 7 reserved default: 0b . [6:5] dpll_1 manual reference input reference when user selection mode = 00, 01, 10, or 11 . 00 (default) = input reference a . 01 = input reference b . 10 = input reference c . 11 = in put reference d . [4:2] dpll_1 switching mode select s the operating mode of the reference switching state machine. reference switchover mode, bits[2:0] reference selection mode 000 automatic revertive mode 001 automatic nonrevertive mode 010 manual reference select mode (with automatic fallback) 011 manual reference select mode (with automatic holdover fallback) 100 manual reference select mode (without holdover fallback) 101 not used 110 not used 111 not used 1 dpll_ 1 user holdover this bit forces dpll_1 into holdover mode . 0 (default) = normal operation. 1 (default) = dpll_1 is forced into holdover mode until this bit is cleared. 0 dpll_1 user free run this bit forces dpll_1 into free run mode . 0 (default) = normal operation. 1 = dpll_1 is forced into free run mode until this bit is cleared. data sheet ad9559 rev. 0 | page 107 of 120 table 163. dpll_1 reset address bit s bit name description 0x0a43 [7:3] reserved default: 00000b . 2 reset dpll_1 loop f ilter setting this bit clears the digital loop filter (intended as a debug tool). 1 reset dpll_1 tw h istory setting this bit resets the tuning word history logic (part of holdover functionality). 0 reset dpll_1 a uto sync setting this bit resets the automatic synchronization logic (see register 0x0525). table 164. dpll_1 phase address bit s bit name description 0x0a44 [7:3] reserved default: 00000b . 2 dpll_1 r eset phase offset resets the incremental phase offset to zero. this is an auto clearing bit. 1 dp ll_1 d ecrement phase offset decrements the incremental phase offset by the amount specifie d in the incremental phase lock offset step size register (register 0x0512 to register 0x0513). this is an auto clearing bit. 0 dpll_1 i ncrement phase offset increme nts the incremental phase offset by the amount specified in the i ncremental phase lock offset step size register (register 0x0512 and register 0x0513). this is an auto clearing bit. status readback (reg ister 0x 0d00 to register 0 x 0d05 ) all bits in re gister 0x0d0 0 to register 0x0d05 are read only . to report the latest status, these bits require an io_update (register 0x0005 = 0x01) immediately before being read . table 165. eeprom status address bit s bit name description 0x0d00 [7:3 ] r eserved default: 00000b . 2 fault detected an error occurred while saving data to or loading data from the eeprom. 1 load in progress the control logic sets this bit while data is being read from the eeprom. 0 save in progress the control logic sets t his bit while data is being written to the eeprom. table 166. sysclk status address bit s bit name description 0x0d01 [7 :4] reserved default: 0x0 . 3 pll_1 all locked indicate s the status of the system clock, apll_1, and dpll_1. 0 = system clock or apll_1 or dpll_1 is unlocked. 1 = all three plls (system clock, apll_1, and dpll_1) are locked. 2 pll_0 all locked indicate s the status of the system clock, apll_0, and dpll_0. 0 = system clock or apll_0 or dpll_0 is unlocked. 1 = all three plls (system clock, apll_0, and dpll_0) are locked. 1 system clock stable the control logic sets this bit when the device considers the system clock to be stable (see the system clock stability timer sect ion). 0 sysclk lock detect indicates the status of the system clock pll. 0 = unlocked. 1 = locked. ad9559 data sheet rev. 0 | page 108 of 120 table 167 . status of reference inputs address bits bit name description 0x0d02 [7:6] reserved default: 00b . 5 dpll_ 1 refa a ctiv e this bit is 1 if dpll_1 is either locked to or attempting to lock to refa . 4 dpll_0 refa a ctive this bit is 1 if dpll_0 is either locked to or attempting to lock to refa . 3 refa valid this bit is 1 if the refa frequency is within the programmed limit s. 2 refa fault this bit is 1 if the refa frequency is outside of the programmed limits . 1 refa fast this bit is 1 if the refa frequency is higher than allowed by its profile settings. 0 refa slow this bit is 1 if the refa frequency is lower than allowed by its profile settings. 0x0d03 [7:6] reserved default: 00b . 5 dpll_1 refb a ctive this bit is 1 if dpll_1 is either locked to or attempting to lock to refb . 4 dpll_0 refb a ctive this bit is 1 if dpll_0 is either locked to or attempting to lock to refb. 3 refb valid this bit is 1 if the refb frequency is within the programmed limits . 2 refb fault this bit is 1 if the refb frequency is outside of the programmed limits . 1 refb fast this bit is 1 if the refb frequency is higher than allowed by i ts profile settings. 0 refb slow this bit is 1 if the refb frequency is lower than allowed by its profile settings. 0x0d04 [7:6] reserved default: 00b . 5 dpll_1 refc a ctive this bit is 1 if dpll_1 is either locked to or attempting to lock to refc . 4 dpll_0 refc a ctive this bit is 1 if dpll_0 is either locked to or attempting to lock to refc . 3 refc valid this bit is 1 if the refc frequency is within the programmed limits . 2 refc fault this bit is 1 if the refc frequency is outside of the programmed limits . 1 refc fast this bit is 1 if the refc frequency is higher than allowed by its profile settings. 0 refc slow this bit is 1 if the refc frequency is lower than allowed by its profile settings. 0x0d05 [7:6] reserved default: 00b . 5 dpll_1 re fd a ctive this bit is 1 if dpll_1 is either locked to or attempting to lock to refd . 4 dpll_0 refd a ctive this bit is 1 if dpll_0 is either locked to or attempting to lock to refd . 3 refd valid this bit is 1 if the refd frequency is within the programmed limits . 2 refd fault this bit is 1 if the refd frequency is outside of the programmed limits . 1 refd fast this bit is 1 if the refd frequency is higher than allowed by its profile settings. 0 refd slow this bit is 1 if the refd frequency is lower than allowed by its profile settings. irq monitor (registe r 0 x 0d08 to register 0x 0d10) if not masked via the irq mask registers (register 0x010a t o register 0x0112), the appropri ate irq monitor bit is set to logic 1 when the indicated event occurs. these b its can be cleared only by a device reset, o r by setting the clear all irqs bit in register 0x0a05, or by setting the irq clearing registers ( register 0x0a05 to register 0x0a0e ). table 168 . irq for common functions address bits bit name description 0x0d08 7 reserved reserved 6 sysclk unlocked irq indicating a sysclk pll state transition from locked to unlocked 5 sysclk stable irq indicating that sysclk stability time has expired and that the sysclk pll is co nsidered to be stabl e 4 sysclk locked irq indicating a sysclk pll state transition from unlocked to locked 3 watchdog timer irq indicating expiration of the watchdog timer 2 reserved reserved 1 eeprom fault irq indicating a fault during an eeprom load or save operatio n 0 eeprom complete irq indicating successful completion of an eeprom load or save operation data sheet ad9559 rev. 0 | page 109 of 120 address bits bit name description 0x0d09 7 reserved reserved 6 refb validated irq indicating that refb has been validated 5 refb fault cleared irq indicating that refb has been cleared of a previous fault 4 refb fault irq indicating that refb has been faulted 3 reserved reserved 2 refa validated irq indicating that refa has been validated 1 refa fault cleared irq indicating that refa has been cleared of a previous fault 0 refa fault irq indicating that refa has been faulted 0x0d0a 7 reserved reserved 6 refd validated irq indicating that refd has been validated 5 refd fault cleared irq indicating that refd has been cleared of a previous fault 4 refd fault irq indicating that re fd has been faulted 3 reserved reserved 2 refc validated irq indicating that refc has been validated 1 refc fault cleared irq indicating that refc has been cleared of a previous fault 0 refc fault irq indicating that refc has been faulted table 169 . irq monitor for digital pll0 (dpll_0) address bits bit name description 0x0d0b 7 frequency unclamp irq indicating that dpll_0 has exited a frequency clamped state 6 frequency clamp irq indicating that dpll_0 has entered a freq uency clamped state 5 phase slew unlimited irq indicating that dpll_0 has exited a phase slew limited state 4 phase slew limited irq indicating that dpll_0 has entered a phase slew limited state 3 frequency unlocked irq indicating that dpll_0 has los t frequency lock 2 frequency locked irq indicating that dpll_0 has acquired frequency lock 1 phase unlocked irq indicating that dpll_0 has lost phase lock 0 phase locked irq indicating that dpll_0 has acquired phase lock 0x0d0c 7 dpll_0 s witching ir q indicating that dpll_0 is switching to a new reference 6 dpll_0 f ree run irq indicating that dpll_0 has entered free run mode 5 dpll_0 h oldover irq indicating that dpll_0 has entered holdover mode 4 history updated irq indicating that dpll_0 has up dated its tuning word history 3 refd activated irq indicating that dpll_0 has activated refd 2 refc activated irq indicating that dpll_0 has activated refc 1 refb activated irq indicating that dpll_0 has activated refb 0 refa activated irq indicati ng that dpll_0 has activated refa 0x0d0d [7:5] reserved reserved 4 sync distribution irq indicating a distribution sync event 3 apll_0 unlocked irq indicating that apll_0 has been unlocked 2 apll_0 locked irq indicating that apll_0 has been locked 1 apll_0 c al ended irq indicating that apll_0 calibration complete 0 apll_0 c al started irq indicating that apll_0 calibration started ad9559 data sheet rev. 0 | page 110 of 120 table 170 . irq monitor for digital pll1 (dpll_1) address bits bit name description 0x0d0e 7 frequency unclamp ed irq indicating that dpll_1 has exited a frequency clamped state 6 frequency clamp ed irq indicating that dpll_1 has entered a frequency clamped state 5 phase slew unlimited irq indicating that dpll_1 has exited a phase slew limited state 4 phase slew limited irq indicating that dpll_1 has entered a phase slew limited state 3 frequency unlocked irq indicating that dpll_1 has lost frequency lock 2 frequency locked irq indicating that dpll_1 has acquired frequency lock 1 phase u nlocked irq indicating that dpll_1 has lost phase lock 0 phase locked irq indicating that dpll_1 has acquired phase lock 0x0d0f 7 dpll_1 s witching irq indicating that dpll_1 is switching to a new reference 6 dpll_1 f ree run irq indicating that dpll_1 has entered free run mode 5 dpll_1 h oldover irq indicating that dpll_1 has entered holdover mode 4 history updated irq indicating that dpll_1 has updated its tuning word history 3 refd activated irq indicating that dpll_1 has activated refd 2 refc activated irq indicating that dpll_1 has activated refc 1 refb activated irq indicating that dpll_1 has activated refb 0 refa activated irq indicating that dpll_1 has activated refa 0x0d10 [7:5] reserved reserved 4 sync distribution irq indicating a distribution sync event 3 apll_1 unlocked irq indicating that apll_1 has been unlocked 2 apll_1 locked irq indicating that apll_1 has been locked 1 apll_1 c al ended irq indicating that apll_1 calibration complete 0 apll_1 c al started irq indicati ng that apll_ 1 calibration started pll_0 read - only status (registe r 0 x 0d20 to register 0x 0d2a) all bits in register 0x0d20 t o register 0x0d2a are read only. to report the latest status, these bits require an io_update (r egister 0x0005 = 0x01) immediately b efore being read . table 171 . pll_0 lock status address bit s bit name description 0x0d20 [7:5] reserved default: 000b 4 apll_0 c al in progress the control logic holds this bit set while the calibration of the apll_0 vco is in p rogress. 3 apll_0 lock ed indicates the status of apll_0. 0 = unlocked. 1 = locked. 2 dpll_0 frequency lock indicates the frequency lock status of dpll_0. 0 = unlocked. 1 = locked. 1 dpll_0 phase lock indicates the phase lock status of dpll_0. 0 = u nlocked. 1 = locked. 0 pll_0 all locked indicate s t he status of the system clock, apll_0, and dpll_0. 0 = system clock pll or apll_0 or dpll_0 is unlocked. 1 = all three plls (system clock pll, apll_0, and dpll_0) are locked. data sheet ad9559 rev. 0 | page 111 of 120 table 172. dpll_0 loop state address bits bit name description 0x0d21 [7 :5] reserved default: 000b. [4:3 ] dpll_0 active ref indicate s the reference input that dpll_0 is using . 0 0 = dpll_0 has selected refa . 01 = dpll_0 has selected refb . 10 = dpll_0 has se lected refc . 11 = dpll_0 has selected refd . 2 dpll_0 switching indicates that dpll_0 is switching input references. 0 = dpll is not switching. 1 = dpll is switching input references. 1 dpll_0 holdover indicates that dpll_0 is in holdover mode. 0 = not in holdover. 1 = in holdover mode. 0 dpll_0 free run indicates that dpll_0 is in free run mode. 0 = not in free run mode. 1 = in free run mode. 0x0d22 [7:3] reserved default: 00000b. 2 dpll_0 phase slew limited the control logic sets this bit when dpll_0 is phase - slew limited. 1 dpll_0 frequency clamped the control logic sets this bit when dpll_0 is frequency clamped. 0 dpll_0 history available the control logic sets this bit when the tuning word history of dpll_0 is available . (see register 0x0d23 to register 0x0d26 for the tuning word.) table 173. dpll_0 holdover history address bits bit name description 0x0d23 [7:0] dpll_0 tuning word readback dpll_0 tuning word readback bits, bits[7:0]. this group of registers contains the averaged digital pll tuning word used when the dpll enters holdove r. setting the history accumulation timer to its minimal value allows the user to use these registers for a read - back of the most recent dpll tuning word without averaging . 0x0d24 [7:0] dpll_0 t uning word readback , bits [15:8]. 0x0d25 [7:0] dpll_0 tuning word read bac k , bits [23:9]. 0x0d26 [7:6] reserved. [5:0] dpll_0 t uning word re adbac k , bits [29:24]. table 174. dpll_0 phase lock and frequency lock bucket levels address bi ts bit name description 0x0d27 [7:0] dpll_0 p hase lock detect bucket level read - only digital pll lock d etect bucket level, bits[7:0]; see the dpll frequency lock detector section for details. 0x0d28 [7:4] reserved reserved. [3:0] dpll_0 p hase lock detect bucket level read - only digital pll lock de tect bucket level, bits[11:8]; see the dpll frequency lock detector section for details. 0x0d29 [7:0] dpl l_0 f requency lock detect bucket level read - only digital pll lock d etect bucket level, bits[7:0]; see the dpll phase lock detector section for details. 0x0d2a [7:4] reserved reserved. [3:0] dpll_0 f requency lo ck detect bucket level read - only digital pll lock de tect bucket level, bits[11:8]; see the dpll phase lock detector section for details. ad9559 data sheet rev. 0 | page 112 of 120 pll_1 read - only status (registe r 0 x 0d40 to register 0x 0d4a) all bits in register 0x0d4 0 t o register 0x0d4 a are read only. to report the latest status, these bits require an io_update (register 0x0005 = 0x01) immediately before being read . table 175 . pll_ 1 lock status address bits bit name description 0x0d40 [7:5] reserved default: 000b 4 apll_1 cal in progress the control logic holds this bit set while the calibration of the apll_1 vco is in progress. 3 apll_1 locked indicates the status of apll_1 . 0 = unlocked. 1 = locked. 2 dpll_1 frequency loc k indicates the frequency lock status of dpll_1 . 0 = unlocked. 1 = locked. 1 dpll_1 phase lock indicates the phase lock status of dpll_1 . 0 = unlocked. 1 = locked. 0 pll_1 all locked indicates the status of the system clock, apll_1, and dpll_1 . 0 = sys tem clock pll or apll_1 or dpll_1 is unlocked. 1 = all thre e plls (system clock pll, apll_1, and dpll_1 ) are locked. table 176 . dpll_1 loop state address bits bit name description 0x0d41 [7:5] reserved default: 000b. [4:3] dpll_1 active ref indicates the reference input that dpll_0 is using. 0 0 = dpll_1 has selected refa. 01 = dpll_1 has selected refb. 10 = dpll_1 has selected refc. 11 = dpll_1 has selected refd. 2 dpll_1 switching indicates that dpll_1 is switching input refer ences. 0 = dpll is not switching. 1 = dpll is switching input references. 1 dpll_1 holdover indicates that dpll_1 is in holdover mode. 0 = not in holdover mode . 1 = in holdover mode. 0 dpll_1 free run indicates that dpll_1 is in free run mode. 0 = not in free run mode. 1 = in free run mode. 0x0d42 [7:3] reserved default: 00000b. 2 dpll_1 phase slew limited the control logic sets this bit when dpll_1 is phase - slew limited. 1 dpll_1 frequency clamped the control logic sets this bit when dpll_1 is fre quency clamped. 0 dpll_1 history updated the control logic sets this bit when t he tuning word history of dpll_1 is available . (see register 0x0d43 to register 0x0d46 for the tuning word.) table 177. dpll_1 holdover history addres s bits bit name description 0x0d43 [7:0] dpll_0 tuning word readback dpll_1 tuning word readback bits, bits[7:0]. this group of registers contains the averaged digital pll tuning word used when the dpll enters holdover. setting the history accumula tion ti mer to its minimal value allows the user to use these registers for a readback of the most recent dpll tuning word without averaging . 0x0d44 [7:0] dpll_1 tuning word readback, bits[15:8]. 0x0d45 [7:0] dpll_1 tuning word readback, bits[23:9]. 0x0d46 [7 :6] reserved. [5:0] dpll_1 tuning word read back, bits[29:24]. data sheet ad9559 rev. 0 | page 113 of 120 table 178 . dpll_1 phase lock and frequency lock bucket levels address bits bit name description 0x0d47 [7:0] dpll_ 1 phase lock detect bucket read - only d pll _1 lock d etect bucket level, bits[7:0]; see the dpll frequency lock detector section . 0x0d48 [7:4] reserved reserved. [3:0] dpll_ 1 phase lock detect bucket read - only d pll_1 lock de tect bucket level, bits[11:8]; see th e dpll frequency lock detector section. 0x0d49 [7:0] frequency tub read - only dpll_1 frequency lock d etect bucket level, bits[7:0]; see the dpll phase lock detector sec tion. 0x0d4a [7:4] reserved reserved. [3:0] frequency tub read - only dpll_1 frequency lock de tect bucket level, bits[11:8]; see the dpll phase lock detector section. eeprom control (register 0 x 0e00 to register 0x 0e03) table 179. eeprom control address bits bit name description 0x0e00 [ 7:1 ] reserved reserved 0 write e nable eeprom write enable/protect. 0 (default) = eeprom write protected 1 = eeprom write enabled 0x0e01 [7: 4] reserved reserved [3 :0] conditional v alue when set to a non zero value, it establishes the condition for eeprom downloads. the default value is 0. 0x0e02 [7:1] reserved reserved 0 save to eeprom upload s data to the eeprom ( see the eeprom storage sequence (register 0x0e10 to register 0x0e3c) section for more information ). 0x0e03 [7:2] reserved reserved 1 load f rom eprom download s data from the eeprom. 0 reserved reserved ee p rom storage sequence (register 0x 0e10 to register 0 x 0e3 c) t he default settings of register 0x0e10 to register 0x 0e33 contain the default eeprom instruction sequence . the tables in this section provide descriptions of the register defaults, assuming that the controller has been instructed to carr y out an eeprom storage sequence in which all of the registers are stored and loaded by the eeprom . table 180. eeprom storage sequence for m pin settings and irq masks address bit s bit name description 0x0e10 [7:0] user free run th e defaul t value of this register is 0x98 , which the controller interprets as a user f ree run command for both plls . the controller stores 0x 98 in the eeprom and increments the eeprom address pointer. 0x0e11 [7:0] user scratchpad the default value of this register is 0x01, which is a data instruction. its decimal value is 1, which tells the controller to transfer two bytes of data (1 + 1), beginning at the address specified by the next two bytes. the controller stores 0x01 in the eeprom and increments the eeprom address pointer. 0x0e12 [7:0] the default value of these two registers is 0x000e. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x000e). the controller stores 0x000e in the e eprom and increments the eeprom pointer by 2. it then transfers two bytes from the register map (beginning at address 0x000e) to the eeprom and increments the eeprom address pointer by 3 (two data bytes and one checksum byte). the two bytes transferred cor respond to the user scratchpad in the register map. 0x0e13 0x0e14 [7:0] m pins and irq masks the default value of this register is 0x12, which the controller interprets as a data instruction. its decimal value is 18, which tells the controller to tran sfer 19 bytes of data (18 + 1) , beginning at the address specified by the next two bytes. the controller stores 0x12 in the eeprom and increments the eeprom address pointer. 0x0e15 [7:0] the default value of these two registers is 0x0100. because the pre vious register contains a data instruction, these two registers define a starting address (in this case, 0x0100). the controller stores 0x0100 in the eeprom and increments the eeprom pointer by 2. it then transfers 19 bytes from the register map (beginning at address 0x0100) to the eeprom and increments the eeprom address pointer by 20 ( 19 data bytes and one checksum byte). the 19 bytes t ransferred correspond to the m p in and irq settings in the register map. 0x0e16 ad9559 data sheet rev. 0 | page 114 of 120 table 181. e eprom storage sequence for system clock settings address bit s bit name description 0x0e17 [7:0] system clock the default value of this register is 0x07, which is a data instruction. its decimal value is 7, which tells the controller to transfer eight byte s of data (7 + 1), beginning at the address specified by the next two bytes. the controller stores 0x07 in the eeprom and increments the eeprom address pointer. 0x0e18 [7:0] the default value of these two registers is 0x0200. because the previous registe r contains a data instruction, these two registers define a starting address (in this case, 0x0200). the controller stores 0x0200 in the eeprom and increments the eeprom pointer by 2. it then transfers eight bytes from the register map (beginning at a ddres s 0x0200) to the eeprom and increments the eeprom address pointer by 9 ( eight data bytes and one checksum byte). the eight bytes transferred correspond to the system clock settings in the register map. 0x0e19 [7:0] 0x0e1a [7:0] io_update the default va lue of this register is 0x80, which the controller interprets as an io_update instruction. the controller stores 0x80 in the eeprom and increments the eeprom address pointer. table 182. eeprom storage sequence for reference input s ettings address bit s bit name description 0x0e1b [7:0] refa the default value of this register is 0x1a, which is a data instruction. its decimal value is 2 6, which tells the controller to transfer 2 7 bytes of data (2 6 + 1), beginning at the address specified by the next two bytes. the controller stores 0x1a in the eeprom and increments the eeprom address pointer. 0x0e1c [7:0] the default value of these two registers is 0x0300. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0300). the controller stores 0x0300 in the eeprom and increments the eeprom pointer by 2 . it then transfers 2 7 bytes from the register map (beginning at address 0x0300) to the eeprom and increments the eeprom add ress pointer by 2 8 (2 7 data bytes and one checksum byte). the 2 7 bytes transferred correspond to the refa parameters in the register map. 0x0e1d [7:0] 0x0e1e [7:0] refb the default value of this register is 0x1a, which is a data instruction. its decima l value is 2 6, which tells the controller to transfer 2 7 bytes of data (2 6 + 1), beginning at the address specified by the next two bytes. the controller stores 0x1a in the eeprom and increments the eeprom address pointer. 0x0e1f [7:0] the default value of these two registers is 0x0320. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0320). the controller stores 0x0320 in the eeprom and increments the eeprom pointer by 2 . it then tr ansfers 2 7 bytes from the register map (beginning at address 0x0320) to the eeprom and increments the eeprom address pointer by 2 8 (2 7 data bytes and one checksum byte). the 2 7 bytes transferred correspond to the refb parameters in the register map. 0x0e2 0 [7:0] 0x0e21 [7:0] refc the default value of this register is 0x1a, which is a data instruction. its decimal value is 2 6, which tells the controller to transfer 2 7 bytes of data (2 6 + 1), beginning at the address specified by the next two bytes. the controller stores 0x1a in the eeprom and increments the eeprom address pointer . 0x0e22 [7:0] the default value of these two registers is 0x0340. because the previous register contains a data instruction, these two registers define a starting address (in t his case, 0x0340). the controller stores 0x0340 in the eeprom and increments the eeprom pointer by 2 . it then transfers 2 7 bytes from the register map (beginning at address 0x0340) to the eeprom and increments the eeprom address pointer by 2 8 (2 7 data byte s and one checksum byte). the 2 7 bytes transferred correspond to the refc parameters in the register map. 0x0e23 [7:0] 0x0e24 [7:0] refd the default value of this register is 0x1a, which is a data instruction. its decimal value is 2 6, which tells the c ontroller to transfer 2 7 bytes of data (2 6 + 1), beginning at the address specified by the next two bytes. the controller stores 0x1a in the eeprom and increments the eeprom address pointer. 0x0e25 [7:0] the default value of these two registers is 0x0360. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0360). the controller stores 0x0360 in the eeprom and increments the eeprom pointer by 2 . it then transfers 2 7 bytes from the register map (beginning at address 0x0360) to the eeprom and increments the eeprom address pointer by 2 8 (2 7 data bytes and one checksum byte). the 2 7 bytes transferred correspond to the refd parameters in the register map. 0x0e26 [7:0] data sheet ad9559 rev. 0 | page 11 5 of 120 table 183. eeprom storage sequence for dpll_0 general settings address bit s bit name description 0x0e27 [7:0] dpll_0 general settings the default value of this register is 0x15, which the controller interprets as a data instruction. its decimal value is 2 1 , which tells the controller to transfer 2 2 bytes of data (2 1 + 1), beginning at the address specified by the next two bytes. the controller stores 0x15 in the eeprom and increments the eeprom address pointer. 0x0e28 [7:0] th e default value of these two registers is 0x0400. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0400). the controller stores 0x0400 in the eeprom and increments the eeprom pointer by 2. it then transfers 2 2 bytes from the register map (beginning at address 0x0400) to the eeprom and increments the eeprom address pointer by 2 3 (2 2 data bytes and one checksum byte). the 22 bytes transferred correspond to the dpll_0 general settings ( fo r example , free running tuning word) in the register map. 0x0e29 [7:0] table 184. eeprom storage sequence for apll_0 configuration and output drivers address bit s bit name description 0x0e2a [7:0] apll_0 config and output drive rs the default value of this register is 0x0e, which the controller interprets as a data inst ruction. its decimal value is 14 , which tel ls the controller to transfer 15 bytes of data (14 + 1) beginning at the address specified by the next two bytes. the co ntroller stores 0x0e in the eeprom and increments the eeprom address pointer. 0x0e2b [7:0] the default value of these two registers is 0x0420. because the previous register contains a data instruction, these two registers define a starting address (in th is case, 0x0420). the controller stores 0x0420 in the eeprom and increments the eeprom pointer by 2. it then transfers 1 5 bytes from the register map (beginning at address 0x0420) to the eeprom and increments the eeprom address pointer by 1 6 (1 5 data bytes and one checksum byte). the 1 5 bytes transferred correspond to the apll_0 settings as well as the pll_0 output driver settings in the register map. 0x0e2c [7:0] table 185. eeprom storage sequence for pll_0 divider s and bw setti ngs address bit s bit name description 0x0e2d [7:0] dpll_0 dividers and bw the default value of this register is 0x33, which the controller interprets as a data instruction. its decimal value is 5 1 , which tells the controller to transfer 5 2 bytes of data (5 1 + 1), beginning at the address specified by the next two bytes. the controller stores 0x33 in the eeprom and increments the eeprom address pointer. 0x0e2e [7:0] the default value of these two registers is 0x0440. because the previous register contain s a data instruction, these two registers define a starting address (in this case, 0x0440). the controller stores 0x0440 in the eeprom and increments the eeprom pointer by 2. it then transfers 5 2 bytes from the register map (beginning at address 0x0440) to the eeprom and increments the eeprom address pointer by 5 3 (5 2 data bytes and one checksum byte). the 5 2 bytes transferred correspond to the dpll_0 feedback dividers and loop bw settings in the register map. 0x0e2f [7:0] table 186 . eeprom storage sequence for dpll_1 general settings address bit s bit name description 0x0e30 [7:0] dpll_1 general settings the default value of this register is 0x15, which the controller interprets as a data instruction. its decimal value is 2 1 , wh ich tells the controller to transfer 2 2 bytes of data (2 1 + 1), beginning at the address specified by the next two bytes. the controller stores 0x15 in the eeprom and increments the eeprom address pointer. 0x0e31 [7:0] the default value of these two regi sters is 0x0500. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0500). the controller stores 0x0500 in the eeprom and increments the eeprom pointer by 2. it then transfers 2 2 bytes from the register map (beginning at address 0x0500) to the eeprom and increments the eeprom address pointer by 2 3 (2 2 data bytes and one checksum byte). the 22 bytes transferred correspond to the dpll_1 general settings ( for example , free running tuning wo rd) in the register map. 0x0e32 [7:0] ad9559 data sheet rev. 0 | page 116 of 120 table 187. eeprom storage sequence for apll_1 configuration and output drivers address bit s bit name description 0x0e33 [7:0] apll_1 config and output drivers the default value of this register is 0x0e, which the controller interprets as a data instruction. its decimal value is 1 4, which tells the controller to transfer 1 5 bytes of data (1 4 + 1) beginning at the address specified by the next two bytes. the controller stores 0x0e in the eepro m and increments the eeprom address pointer. 0x0e34 [7:0] the default value of these two registers is 0x0520. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0520). the controller stores 0x0520 in the eeprom and increments the eeprom pointer by 2. it then transfers 1 5 bytes from the register map (beginning at address 0x0520) to the eeprom and increments the eeprom address pointer by 1 6 (1 5 data bytes and one checksum byte). the 1 5 b ytes transferred correspond to the apll_1 settings as well as the pll_1 output driver settings in the register map. 0x0e35 [7:0] table 188. eeprom storage sequence for pll_1 divider s and bw settings address bit s bit name description 0x0e36 [7:0] dpll_1 dividers and bw the default value of this register is 0x33, which the controller interprets as a data instruction. its decimal value is 52, which tells the controller to transfer 53 bytes of data (52 + 1), beginning at the address specified by the next two bytes. the controller stores 0x33 in the eeprom and increments the eeprom address pointer. 0x0e37 [7:0] the default value of these two registers is 0x0540. because the previous register contains a data instruction, these two re gisters define a starting address (in this case, 0x0540). the controller stores 0x0540 in the eeprom and increments the eeprom pointer by 2. it then transfers 53 bytes from the register map (beginning at address 0x0540) to the eeprom and increments the eep rom address pointer by 54 (53 data bytes and one checksum byte). the 53 bytes transferred correspond to the dpll_1 feedback dividers and loop bw settings in the register map. 0x0e38 [7:0] table 189. eeprom storage sequence for l oop filter settings address bit s bit name description 0x0e39 [7:0] loop filter the default value of this register is 0x17, which the controller interprets as a data instruction. its decimal value is 23, which tells the controller to transfer 24 bytes of d ata (23 + 1), beginning at the address specified by the next two bytes. the controller stores 0x17 in the eeprom and increments the eeprom address pointer. 0x0e3a [7:0] the default value of these two registers is 0x0800. because the previous register con tains a data instruction, these two registers define a starting address (in this case, 0x0800). the controller stores 0x0800 in the eeprom and increments the eeprom pointer by 2. it then transfers 24 bytes from the register map (beginning at address 0x0800 ) to the eeprom and increments the eeprom address pointer by 25 (24 data bytes and one checksum byte). the 24 bytes transferred are the loop filter settings in the register map. 0x0e3b [7:0] table 190. eeprom storage sequence fo r comm on operational control settings address bit s bit name description 0x0e3c [7:0] common operational controls the default value of this register is 0x0e, which the controller interprets as a data instruction. its decimal value is 1 4 , which tells the co ntroller to transfer 1 5 bytes of data (1 4 + 1), beginning at the address specified by the next two bytes. the controller stores 0x0e in the eeprom and increments the eeprom address pointer. 0x0e3d [7:0] the default value of these two registers is 0x0a00. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0a00). the controller stores 0x0a00 in the eeprom and increments the eeprom pointer by 2. it then transfers 1 5 bytes from the registe r map (beginning at address 0x0a00) to the eeprom and increments the eeprom address pointer by 1 6 (1 5 data bytes and one checksum byte). the 1 5 bytes transferred correspond to the common operational controls in the register map. 0x0e3e [7:0] data sheet ad9559 rev. 0 | page 117 of 120 table 191. eeprom storage sequence for pll_0 operational control settings address bit s bit name description 0x0e3f [7:0] pll_0 o perational controls the default value of this register is 0x04, which the controller interprets as a data instruction. its decimal value is 4, which tells the controller to transfer five bytes of data (4 + 1), beginning at the address specified by the next two bytes. the controller stores 0x04 in the eeprom and increments the eeprom address pointer. 0x0e40 [7:0] th e default value of these two registers is 0x0a20. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0a20). the controller stores 0x0a20 in the eeprom and increments the eeprom pointer by 2. it then transfers five bytes from the register map (beginning at address 0x0a20) to the eeprom and increments the eeprom address pointer by six (five data bytes and one checksum byte). the five bytes transferred correspond to the pll_0 operational co ntrols in the register map. 0x0e41 [7:0] table 192 . eeprom storage sequence for pll_1 operational control settings address bit s bit name description 0x0e42 [7:0] pll_1 o perational controls the default value of this register is 0x04, which the controller interprets as a data instruction. its decimal value is 4, which tells the controller to transfer five bytes of data (4 + 1), beginning at the address specified by the next two bytes. the controller stores 0x04 in the eeprom and i ncrements the eeprom address pointer. 0x0e43 [7:0] the default value of these two registers is 0x0a40. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0a40). the controller stores 0x0a40 in the eeprom and increments the eeprom pointer by 2. it then transfers five bytes from the register map (beginning at address 0x0a40) to the eeprom and increments the eeprom address pointer by six (five data bytes and one checksum byte). the five bytes transferred correspond to the pll_1 operational controls in the register map. 0x0e44 [7:0] table 193 . eeprom storage sequence for apll calibration address bit s bit name description 0x0e45 [7:0] io_update the default value of this register is 0x80, which the controller interprets as an io_update instruction. the controller stores 0x80 in the eeprom and increments the eeprom address pointer. 0x0e46 [7:0] calibrate aplls the default value of this register is 0x90, which the controller interprets as a calibrate instruction for both aplls. the controller stores 0x90 in the eeprom and increments the eeprom address pointer. 0x0e47 [7:0] sync o utputs the default value of this register is 0xa0, which the controller interprets as a distribution sync instruction for all of the output dividers. the controller stores 0xa0 in the eeprom and increments the eeprom address pointer. table 194 . eeprom storage sequence for end of data address bit s bit name descriptio n 0x0e48 [7:0] end of data the default value of this register is 0xff, which the controller interprets as an end instruction. the controller stores this instruction in the eeprom, resets the eeprom address pointer, and enters an idle state. note that if t he user replaces this command with a pause rather than an end instruction, the controller actions are the same except that the controller increments the eeprom address pointer rather than resetting it. this allows the user to store multiple eeprom profiles in the eeprom. table 195 . unused address bit s bit name description 0x0e49 to 0x0e4f [7:0] unused this area is unused in the default configuration and is available for additional eeprom storage s equence commands. note that the eeprom storage s equence sh ould always end with either an end of data or pause c ommand. ad9559 data sheet rev. 0 | page 118 of 120 table 196 . multifunction pin output functions (d7 = 1) bits [ d7 :d0] value output function source proxy 0x8 0 static logic 0 none 0x8 1 static logic 1 none 0x8 2 system clock divided by 32 none 0x8 3 watchdog timer output (40 ns strobe when timer expires) none 0x8 4 eeprom upload (write to eeprom) in progress register 0x0d00, bit 0 0x8 5 eeprom download (read from eeprom) in progress register 0x0d00 , bit 1 0x8 6 eeprom fault detected register 0x0d00, bit 2 0x88 sysclk pll lock detected register 0x0d01, bit 0 0x89 sysclk pll stable register 0x0d01, bit 1 0x8a pll_0 and pll _ 1 all locked (logical and of 0x8b and 0x8c) register 0x0d01, bit 2 and bit 3 0x8b (dpll_0 phase lock) and (apll_0 lock) and (sys pll lock) registe r 0x0d01, bit 2 0x8c (dpll_1 phase lock) and (apll_1 lock) and (sys pll lock) register 0x0d01, bit 3 0x90 (irq_common ) or ( irq_pll_0 ) or ( irq_pll_ 1) none 0x91 irq_common none 0x92 irq_pll_0 none 0x93 irq_pll_1 none 0xa0/0xa1/0xa2/0xa3 refa /refb/refc/refd fault register 0x0d02/0x0d03/0x0d04/0x0d05, bit 2 0xa8/0xa9/0xaa / 0xab refa /refb/refc/refd valid register 0x0d02/0x0d03/0x0d04/0x0d05, bit 3 0xb0 (dpll_0 refa active) or (dpll_1 refa active) register 0x0d0 2, bit 4 || bit 5 0xb1 (dpll_0 refb active) or (dpll_1 refb active) register 0x0d03, bit 4 || bit 5 0xb2 (dpll_0 refc active) or (dpll_1 refc active) register 0x0d04, bit 4 || bit 5 0xb3 (dpll_0 refd active) or (dpll_1 refd a ctive) register 0x0d05, bit 4 || bit 5 0xc0 dpll_0 phase locked register 0x0d20, bit 1 0xc1 dpll_0 frequency locked register 0x0d20, bit 2 0xc2 apll _0 lock detect register 0x0d 20 , bit 3 0xc3 apll_0 cal in process register 0x0d 20 , bit 4 0xc4 dpll_0 act ive register 0x0d0c, bit 4 || bit 3 || bit 2 || bit 1 0xc5 dpll_0 in free run mode register 0x0d21, bit 0 0xc6 dpll_0 in holdover register 0x0d21, bit 1 0xc7 dpll_0 in reference switchover register 0x0d21, bit 2 0xc8 dpll_0 tuning word history availab le register 0x0d22, bit 0 0xc9 dpll_0 tuning word history updated register 0x0d 0c , bit 4 0xca dpll_0 tuning word clamp activated register 0x0d22, bit 1 0xcb dpll _0 phase slew limited register 0x0d22, bit 2 0 xcc pll_0 clock distribution sync pulse regis ter 0x0d0d, bit 4 0xd0 dpll_1 phase locked register 0x0d40, bit 1 0xd1 dpll_1 frequency locked register 0x0d40, bit 2 0xd2 apll _1 lock detect register 0x0d40, bit 3 0xd3 apll_1 cal in process register 0x0d40, bit 4 0xd4 dpll_1 active register 0x0d0f, bit 4 || bit 3 || bit 2 || bit 1 0xd5 dpll_1 in free run mode register 0x0d41, bit 0 0xd6 dpll_1 in holdover register 0x0d41, bit 1 0xd7 dpll_1 in reference switchover register 0x0d41, bit 2 0xd8 dpll_1 tuning word history available register 0x0d42, bi t 0 0xd9 dpll_1 tuning word history updated register 0x0d0f, bit 4 0xda dpl l_1 tuning word clamp activated register 0x0d42, bit 1 0xdb dpll _1 phase slew limited register 0x0d42, bit 2 0xdc pll_ 1 clock distribution sync pulse register 0x0d10, bit 4 0xd d to 0xff reserved data sheet ad9559 rev. 0 | page 119 of 120 table 197 . multifunction pin input functions (d7 = 0) bits [ d7 :d0] value output function destination proxy 0x00 reserved high - z input none 0x01 io_update register 0x0005, bit 0 0x02 full power - down register 0x 0a00, bit 0 0x03 clear watchdog timer register 0x0 a05, bit 7 0x04 sync all channel dividers register 0x0 a00, bit 2 0x10 clear all irqs register 0x0 a05, bit 0 0x11 clear c ommon irqs register 0x0 a05, bit 1 0x12 clear d pll_ 0 irqs register 0x0 a05, bit 2 0x13 clear d pll_ 1 irqs register 0x0 a05, bit 3 0x20/0x21/0x22/ 0x23 force fault refa/refb / refc/ refd register 0x0 a03, bits[3:0] 0x28/0x29/0x2a/0x2b force validation timeout refa/refb/refc/ refd register 0x0 a02, bits[3:0] 0x40 pll_0 power - down register 0x0 a2 0, bit 0 0x41 dpll_0 u ser free run register 0x0 a22, bit 0 0x42 dpll_0 u ser holdover register 0x0 a22, bit 1 0x43 dpll_0 t uning word history reset register 0x0 a23, bit 1 0x44 dpll_0 i ncrement incremental phase offset register 0x0 a24, bit 0 0x45 dpll_0 d ecrement incremental phase offset register 0x0 a24, bit 1 0x46 dpll_0 r eset incremental phase offset register 0x0 a24, bit 2 0x48 a pll_0 s ync clock distribution outputs register 0x0 a20, bit 2 0x49 pll_0 d isable all output drivers register 0x0 a21, bits[3:2 ] 0x4a pll_0 disable out0a register 0x0 a21, bit 2 0x4b pll_0 d isable out0b register 0x0 a21, bit 3 0x4c pll_0 m an ual reference input selection, bit 0 register 0x0 a22, bit 5 0x4d pll_0 m an ual reference input selection, bit 1 register 0x0 a22, bit 6 0x50 pll_1 power - down register 0x0 a40, bit 0 0x51 dpll_1 u ser free run register 0x0 a42, bit 0 0x52 dpll_1 u ser holdover register 0x0 a42, bit 1 0x53 dpll_1 t uning word history reset register 0x0 a43, bit 1 0x54 d pll_1 i ncrement incremental phase offset regist er 0x0a44, bit 0 0x55 dpll_1 d ecrement incremental phase offset register 0x0 a44, bit 1 0x56 dpll_1 r eset incremental phase offset register 0x0 a44, bit 2 0x58 a pll_1 s ync clock distribution outputs register 0x0 a40, bit 2 0x59 pll_1 d isable all output dr ivers register 0x0 a41, bits[3:2] 0x5a pll_1 disable out1a register 0x0 a41, bit 2 0x5b pll_1 disable out1b register 0x0 a41, bit 3 0x5c pll_1 m an ual reference input selection, bit 0 register 0x0 a42, bit 5 0x5d pll_1 m anual referen ce input selection, b it 1 register 0x0 a42, bit 6 0x5e to 0x7f reserved ad9559 data sheet rev. 0 | page 120 of 120 outline dimensions compliant to jedec standards mo-220-vnnd-4 073108- a 0.20 ref 0.80 max 0.65 ty p 1.00 0.85 0.80 0.05 max 0.02 nom 1 18 54 37 19 36 72 55 0.50 0.40 0.30 8.50 ref 7.10 bsc sq exposedp ad (bot t om view) top view 9.75 bsc sq 10.00 bsc sq pin 1 indic at or sea ting plane 12 max 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 0.50 bsc pin 1 indic at or coplanarit y 0.08 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 57 . 72- lead lead frame chip sc ale package [lfcsp_vq] 10 mm 10 mm body, very thin quad (cp - 72 -4 ) dimensions shown in millimeters ordering guide mo del 3f 1 temperature range package description package option ad9559 bcpz ?40 c to +85c 72-l ead lead frame chip scale package [ lfcsp_vq] cp-72-4 ad9559 bcpz - reel7 ? 40c to +85c 72- lead lead frame chip scale package [lfcsp _vq] cp-72-4 ad9559 /pcbz ? 40c to +8 5c evaluation board cp-72-4 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2012 analog devices, inc. all rights reserved. trade marks and registered trademarks are the property of their respective owners. d10644 -0- 7/12(0) |
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