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page 1 of 29 09/26/05 ir3094pbf 3 phase pwm controller for point of load description the ir3094 control ic provides a full featured, cos t effective, single chip solution to offers a compa ct, efficient solution for high current pol converters. control and 3 phase gate drive functions are integ rated into a single space-saving ic. features x 0.85v reference voltage x 3a gatelx pull down drive capability x programmable 100khz to 540khz oscillator x programmable voltage positioning (can be disabled) x programmable softstart x programmable hiccup over-current protection with d elay to prevent false triggering x simplified powergood provides indication of proper operation and avoids false triggering x operates up to 16v converter input with 7.5v under -voltage lockout x 4.36v under-voltage lockout threshold for gate dri ver voltage x adjustable voltage, 150ma bias regulator provides mosfet drive voltage x enable input x ovp flag output detects high side fet short at pow erup x separate ovp sense line to sense the output voltag e and latched ovp with protection x inductor dcr sensing for current sensing will supp ort up to 5.1v output applications x available 48l mlpq package ordering information device order quantity ir3094mtrpbf 3000 per reel IR3094MPBF 100 piece strips package information 48l mlpq (7 x 7 mm body) ja = 27 o c/w biasout csinm1 nc csinp1 csinp2 eaout enable fb gateh1 gateh2 gatel1 gatel2 lgnd ocset ovp pgnd1 pgnd2 pwrgd rosc scomp2 setbias ss/del vcc vcch1 vcch2 vccl1_2 5vuvl vref vdrp nc nc nc nc nc vosns- nc gatel3 pgnd3 gateh3 vcch3 vccl3 csinp3 scomp3 5vref ovpsns csinm2 csinm3 nc 48ld mlpq ir3094 d ata sheet no. pd 94716 downloaded from: http:///
ir3094pbf page 2 of 29 09/26/05 pin description pin# pin symbol pin description 1 nc not connected 2 nc not connected 3 rosc connect a resistor to vosns- to program osci llator frequency, ocset and stbias bias currents. 4 vosns- remote sense input. connect to ground at t he load. 5 ocset programs the hiccup over-current threshold through an external resistor tied to vref and an internal c urrent source. the bias current is a function of rosc. 6 vref 0.85v reference voltage. current sensing and over c urrent protection are referenced to this pin. an external rc network tied to vosns- is needed for th e compensation. 7 vdrp buffered average current information. connect an ex ternal resistor to fb to program converter output. . impedance 8 fb inverting input to the error amplifier. 9 eaout output of the error amplifier. 10 ss/del controls converter softstart, power good, and over- current timing. connect an external capacitor to lgnd to program the timing. 11 scomp2 compensation for the current share control loop. c onnect a capacitor to ground to set the control loo ps bandwidth. phase 2 is forced to match phase 1s cu rrent. 12 scomp3 compensation for the current share control loop. c onnect a capacitor to ground to set the control loo ps bandwidth. phase 3 is forced to match phase 1s cu rrent. 13 lgnd local ground and ic substrate connection. 14 setbias external resistor to ground sets voltage at biasout pin. bias current is a function of ros c. 15 vcc power for internal circuitry and source for biasout regulator. 16 csinp3 non-inverting input to the phase 3 curren t sense amplifier. 17 csinm3 inverting input to the phase 3 current se nse amplifier. 18 biasout 150ma open-looped regulated voltage set by setbias for gate drive bias. 19 pwrgd open collector output that drives low duri ng softstart or any fault condition. connect extern al pull-up. 20 csinp2 non-inverting input to the phase 2 curren t sense amplifier. 21 csinm2 inverting input to the phase 2 current se nse amplifier. 22 nc not connected 23 vccl3 power for phase 3 low-side gate driver. 24 gatel3 phase 3 low-side gate driver output and i nput to gateh3 non-overlap comparator. 25 pgnd3 return for phase 3 gate drivers. 26 gateh3 phase 3 high-side gate driver output and input to gatel3 non-overlap comparator. 27 vcch3 power for phase 3 high-side gate driver. 28 vcch2 power for phase 2 high-side gate driver. 29 gateh2 phase 2 high-side gate driver output and input to gatel2 non-overlap comparator. 30 pgnd2 return for phase 2 gate drivers. 31 gatel2 phase 2 low-side gate driver output and i nput to gateh2 non-overlap comparator. 32 5vuvl can be used to monitor the driver supply voltage or 5v supply voltage when converting from 5v. an und er voltage condition initiates soft start. 33 vccl1_2 power for phase 1 and 2 low-side gate dr ivers. 34 gatel1 phase 1 low-side gate driver output and i nput to gateh1 non-overlap comparator. 35 pgnd1 return for phase 1 gate drivers. 36 gateh1 phase 1 high-side gate driver output and input to gatel1 non-overlap comparator. 37 vcch1 power for phase 1 high-side gate driver. 38 nc not connected 39 csinm1 inverting input to the phase 1 current se nse amplifier. 40 csinp1 non-inverting input to the current sense amplifier. 41 ovp output that drives high during an over-volta ge condition. 42 enable enable input. a logic low applied to this pin puts the ic into fault mode. 43 ovpsns dedicated output voltage sense pin for ov er voltage protection. 44 5vref decoupling for internal voltage reference rail. 45 nc not connected 46 nc not connected 47 nc not connected 48 nc not connected downloaded from: http:///
ir3094pbf page 3 of 29 09/26/05 absolute maximum ratings operating junction temperature..0 o c to 150 o c storage temperature range.-65 o c to 150 o c pin name vmax vmin isource isink 3 rosc 20v -0.3v 1ma 1ma 4 vosns- 0.5v -0.5v 10ma 1ma 5 ocset 20v -0.3v 1ma 1ma 6 vdac 20v -0.3v 1ma 1ma 7 vdrp 20v -0.3v 25ma 5ma 8 fb 20v -0.3v 1ma 1ma 9 eaout 10v -0.3v 5ma 10ma 10 ss/del 20v -0.3v 1ma 1ma 11 scomp2 20v -0.3v 1ma 1ma 12 scomp3 20v -0.3v 1ma 1ma 13 lgnd n/a n/a 50ma 1ma 14 setbias 20v -0.3v 1ma 1ma 15 vcc 20v -0.3v 1ma 500ma 16 csinp3 20v -0.3v 1ma 1ma 17 csinm3 20v -0.3v 1ma 1ma 18 biasout 20v -0.3v 450ma 1ma 19 pwrgd 20v -0.3v 1ma 20ma 20 csinp2 20v -0.3v 1ma 1ma 21 csinm2 20v -0.3v 1ma 1ma 22 nc n/a n/a n/a n/a 23 vccl3 20v -0.3v n/a 3a for 100ns, 200ma dc 24 gatel3 20v -0.3v dc, -2v for 100ns 3a for 100ns, 200ma dc 3a for 100ns, 200ma dc 25 pgnd3 0.3v -0.3v 3a for 100ns, 200ma dc n/a 26 gateh3 30v -0.3v dc, -2v for 100ns 3a for 100ns, 200ma dc 3a for 100ns, 200ma dc 27 vcch3 30v -0.3v n/a 3a for 100ns, 200ma dc 28 vcch2 30v -0.3v n/a 3a for 100ns, 200ma dc 29 gateh2 30v -0.3v dc, -2v for 100ns 3a for 100ns, 200ma dc 3a for 100ns, 200ma dc 30 pgnd2 0.3v -0.3v 3a for 100ns, 200ma dc n/a 31 gatel2 20v -0.3v dc, -2v for 100ns 3a for 100ns, 200ma dc 3a for 100ns, 200ma dc 32 5vuvl 20v -0.3v 1ma 1ma 33 vccl1_2 20v -0.3v n/a 3a for 100ns, 200ma dc 34 gatel1 20v -0.3v dc, -2v for 100ns 3a for 100ns, 200ma dc 3a for 100ns, 200ma dc 35 pgnd1 0.3v -0.3v 3a for 100ns, 200ma dc n/a 36 gateh1 30v -0.3v dc, -2v for 100ns 3a for 100ns, 200ma dc 3a for 100ns, 200ma dc 37 vcch1 30v -0.3v n/a 3a for 100ns, 200ma dc 38 nc n/a n/a n/a n/a 39 csinm1 20v -0.3v 1ma 1ma 40 csinp1 20v -0.3v 1ma 1ma 41 ovp 20v -0.3v 1ma 1ma 42 enable 20v -0.3v 1ma 1ma 43 ovpsns 20v -0.3v 1ma 1ma 44 5vref 10v -0.3v 10ma 20ma downloaded from: http:///
ir3094pbf page 4 of 29 09/26/05 electrical specifications unless otherwise specified, these specifications ap ply over: 8.0 ? v cc ? 16v, 4v ? v cclx ? 14v, 4v ? v cchx ? 28v, c gatehx =3.3nf, c gatelx =6.8nf, 0 o c ? t j ? 125 o c parameter test condition min typ max unit vref reference sink current r rosc = 47k ?95() =ocset 45 53 61 p a source current r rosc = 47k ?95() =ocset 48 56 64 p a system reference voltage connect fb to eaout, measure v(eaout)-v(vosns-). applies to -0.3v ir3094pbf page 5 of 29 09/26/05 parameter test condition min typ max unit biasout regulator setbias bias current r rosc = 47k ? 94 103 117.5 p a set point accuracy v(setbias)-v(biasout) @ 100ma 0 0.25 0.55 v biasout dropout voltage i(biasout)=100ma,threshold when v(setbias)-v(biasout)=0.45v 1.2 1.8 2.5 v biasout current limit 150 250 500 ma soft start and delay ss/del to fb input offset voltage with fb = 0v, adjust v(ss/del) until eaout drives high 0.8 1.1 1.8 v charge current 30 60 90 p a hiccup discharge current 3.5 6 9 p a oc discharge current 25 55 70 p a charge/discharge current ratio 9 10 13 p a/ p a charge voltage 3.8 4.0 4.2 v delay comparator threshold relative to charge volta ge 180 245 310 mv discharge comparator threshold 170 265 350 mv over-current comparator input offset voltage v(ocset)-v(vref), csinm=csinp1=csinp2=csinp3, note 1. -125 0 125 mv ocset bias current r rosc = 47k ? 23.5 27 29.4 p a max ocset set point 3.9 v under-voltage lockout vcc start threshold 7.0 7.5 8.0 v vcc stop threshold 6.5 7.0 7.5 v vcc hysteresis start C stop 400 500 700 mv 5vuvl start threshold 4.05 4.36 4.60 v 5vuvl stop threshold 3.92 4.17 4.40 v 5vuvl hysteresis start C stop 100 200 250 mv pwrgd output output voltage i(pwrgd) = 4ma 150 400 mv leakage current v(pwrgd) = 5.5v 0 10 p a downloaded from: http:///
ir3094pbf page 6 of 29 09/26/05 parameter test condition min typ max unit enable input threshold referenced to vosns- 1.3 1.5 1.7 v input resistance 5 10 20 k ? pull-up voltage 2.4 3.0 3.7 v gate drivers gateh rise time vcchx = 8v, measure 1v to 7v transi tion time. note 1. 25 50 ns gateh fall time vcchx = 8v, measure 7v to 1v transi tion time. note 1. 25 50 ns gatel rise time vcclx= 8v, measure 1v to 7v transit ion time. note 1. 50 90 ns gatel fall time vcclx= 8v, measure 7v to 1v transit ion time. note 1. 30 60 ns high voltage (ac) measure vcclxC gatelx or vcchx C gatehx, note 1 0 0.5v v low voltage (ac) measure gatelx or gatehx, note 1 0 0.5v v gatel low to gateh high delay vcchx = vcclx= 8v, measure the time from gatelx falling to 1v to gatehx rising to 1v. note 1. 10 25 50 ns gateh low to gatel high delay vcchx = vcclx= 8v, measure the time from gatehx falling to 1v to gatelx rising to 1v. note 1. 10 25 50 ns disable pull-down current gathx or gatelx=2v with v cc = 0v. measure gate pull-down current 20 35 50 p a pwm comparator propagation delay note1 100 150 ns common mode input range 4 v internal ramp start voltage 0.44 0.6 0.9 v internal ramp amplitude 35 50 65 mv / %dtc current sense amplifier csinpx bias current -1 0 1 p a csinm2,3 bias current -1 0 1 p a csinm1 bias current -2 -0.5 1 p a phase 2 and 3 input current offset ratio 1 p a/ p a phase 1 input current offset ratio 0.5 1.7 4 p a/ p a average input offset voltage (vdrp-vref)/gain with csinx=0. note1 -5 0 5 mv offset voltage mismatch monitor i(scompx), note1. - 5 0 5 mv gain at t j = 25 o c 22.5 24 25.5 v/v gain at t j = 125 o c 19 20.9 22 v/v gain mismatch note 1. -1 0 1 v/v differential input range -25 75 mv common mode input range -0.2 5.5 v downloaded from: http:///
ir3094pbf page 7 of 29 09/26/05 note 1: guaranteed by design, but not tested in productio n note 2 : vref output is trimmed to compensate for error a mp input offsets errors parameter test condition min typ max unit share adjust error amplifier input offset voltage note 1 -5 0 5 mv max duty cycle adjust ratio compare duty cycle to g ateh1 1.5 2.0 min duty cycle adjust ratio compare duty cycle to g ateh1 0.6 0.5 transconductance note 1 100 200 300 p a/v scompx source/sink current 16 22 28 p a scompx precondition and gatelx release threshold v(fb) 0.6 0.67 0.74 v scomp precondition current 160 360 560 p a duty cycle match at startup compare duty cycle to gatehx -7 -1 7 % 0% duty cycle comparator threshold voltage below internal ramp1 start voltag e -25 25 75 mv propagation delay vcclx= 8v. step eaout from .8v to .3v and measure time to gatelx transition to < 7v. 200 400 ns ovp comparator threshold compare to v(vref) 120 150 20 0 mv power-up headroom for ovp flag vcc=ovpsns where v(ovp)>0.5v. same for 5vuvl=ovpsns. 0.8 1.1 1.8 v ovpsns threshold at power- up vcc=2v, v(ovp) >0.5v. same for v(5vuvl)=2v. 0.3 0.48 0.85 v ss/del power-up clear threshold vcc=12v, v(ovpsns)=1v, vref=1.6v, where ovp<0.5v 0.35 0.60 0.95 v propagation delay vcclx= 8v. v(eaout)=0v. step ovpsns 540mv + v(vref). measure time to gatelx transition to >1v. note 1. 150 350 650 ns ovp source current v(ovp)=0.5v, vcc=1.8v, 5vuvl=0v 10 75 p a ovp pull down resistance ovp to lgnd 30 60 100 k ? ovp high voltage i(ovp)=10ua, v(vcc) or v(5vuvl)- v(ovp), vcc=1.8v 0.4 0.70 1.1 v ovpsns bias current -6.0 -3.0 1.5 ua 5vref short circuit current 20 45 60 ma supply voltage i(5vref)=0a 4.5 5 5.5 v general vcc supply current v(vcc)=16v 28.5 35 40.5 ma vosns- current -0.3v ? vosns- ? 0.3v 0.6 0.8 1.2 ma vcchx and vccl3 current v(vcchx)=28v, v(vccl3)=14v 3 5 7 ma vccl1_2 supply current v(vccl1_2)=14v 6 10 17 ma 5vuvl supply current v(5vuvl)=5v, no ovp condition 100 200 400 ua non_sync to sync threshold 70.6 77.7 87 %vre f downloaded from: http:///
ir3094pbf page 8 of 29 09/26/05 typical operating characteristics i(vdac) sink and source currents vs. rosc 0 20 40 60 80 100 120 140 160 180 10 20 30 40 50 60 70 80 90 100 110 120 130 rosc in kohms ua i(vdac) source current i(vdac) sink current i(ocset) current vs. rosc 0 10 20 30 40 50 60 70 80 90 10 20 30 40 50 60 70 80 90 100 110 120 rosc (kohm) ua i(ocset) oscillator freq vs. rosc 0 50 100 150 200 250 300 350 400 450 500 10 20 30 40 50 60 70 80 90 100 110 120 rosc (kohm) frequency (khz) i(setbias) vs. rosc 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 10 20 30 40 50 60 70 80 90 100 110 120 rosc (kohm) ua frequency and bias current accuracy vs. rosc (inclu des temperature) 1 2 3 4 5 6 10 20 30 40 50 60 70 80 90 100 rosc (kohm) +/-3 sigm a variation (% ) frequency vref sink vref source ocset setbias peak high side gate drive current vs. laod capacitance 1.000 1.100 1.200 1.300 1.400 1.500 1.600 1.700 1.800 1.900 2.000 1 2 3 4 5 6 7 8 9 10 c(gatehx) in nf i(gatehx) in amps i(rise) i(fall) ref ref ref oa d downloaded from: http:///
ir3094pbf page 9 of 29 09/26/05 peak low side gate drive current vs. laod capacitance 1.000 1.250 1.500 1.750 2.000 2.250 2.500 2.750 3.000 3.250 1 2 3 4 5 6 7 8 9 10 c(gatelx) in nf i(gatelx) in amps i(rise) i(fall) error amplifier frequency response frequency 1.0hz 10hz 100hz 1.0khz 10khz 100khz 1.0mhz 10mhz 100mhz db(v(comp)) -100 0 100 -180 180 93db dc gain 88 phase margin 3.1mhz crossover p(v(comp)) oad downloaded from: http:///
ir3094pbf page 10 of 29 09/26/05 ir3094 theory of operation figure 1 ? ir3094 block diagram 0.85v vcc pgnd1 clk3 clk3 -+ pwm comparator v o s n s - vdrp eaout scomp3 csinm1 - + - + startup ovp comparator 0.48v clk1 clk1 pgnd2 -+ pwm comparator gatel2 gatehi pgnd ol_out drive ol_in in gatehi s q qb r rsff vcch2 irosc/2 0.6v gateh2 gatelo pgnd drive ol_in in ol_out gatelo 9p 150mv pgnd3 -+ pwm comparator 9p reset dominant gatel3 gatehi pgnd ol_out drive ol_in in gatehi s q qb r rsff vcch3 irosc vccl3 0.6v gateh3 gatelo pgnd drive ol_in in ol_out gatelo csinm2 csinm3 6u 9p reset dominant clk2 -+ + - preset share adjust error amp gatel1 5vref s q qb r sy nc latch fb ovpsns 0.6v 10k set dominant -+ uvl pwrgd gatehi pgnd ol_out drive ol_in in gatehi + - irosc ref buffer -+ discharge comparator setbias s q qb r rsff ss 0 to irosc*3/4 60k 3v biasout + - + - 1.1v sof tstart_clamp u37 or4 set dominant on internal reference -+ over current 4v 55u 1.243 iave vcch1 vcc 0.575v 4.36v start 4.17v stop 7.5v start 7.0v stop h forces irosc/2 off 60u -+ irosc/2 vccl1_2 245mv irosc vdac lgnd 1.5v 0.6v vosns- rosc scomp2 on reset dominant set dominant -+ uvl + - preset share adjust error amp enable 0 to irosc*3/4 - ++ error_amp i r o s c 5vuvl gateh1 vref s q r fault latch 0.265v 4 x irosc ocset gatelo pgnd drive ol_in in ol_out gatelo ovp clk1 clk2 irosc clk3 oscillator - + delay v o s n s - - + ovp comparator -+ x23.5 csinp1 -+ x23.5 summer csinp2 summer v d a c - + 0% duty cy cle 75u 5vuvl -+ x23.5 csinp3 v d a c summer v d a c co3 75u co1 co2 disable iave co3 co1 co1 co2 v o s n s - 0.75*vdac - + clk2 s q qb r ovp latch downloaded from: http:///
ir3094pbf page 11 of 29 09/26/05 pwm operation the ir3094 is a fully integrated 3 phase interleave d pwm control ic which uses voltage mode control wi th trailing edge modulation. a high-gain wide-bandwidth voltage type error amplifier in the control ic is used for the voltage control loop. the pwm block diagram of the ir3094 i s shown in figure 2. s q qb r ovp latch csinm2 csinm1 9p 9p vdrp buffer reset dominant reset dominant 0.575v irosc -+ pwm comparator 0 to irosc*3/4 + - share adjust error amp irosc - + error amplifier 0.6v rcs2 s q qb r rsff csc2 -+ irosc/2 ccs1 1 2 -+ pwm comparator ccs2 rsc2 rcs1 ccomp cdac vdac - + 0% duty cycle rfb clk2 s q qb r rsff rdrp rcomp rdac 0.6v cout 1 2 vref vdrp eaout scomp2 gatel1 gateh1 gateh2 csinp1 gatel2 csinp2 csinm3 fb vosns- vout sense+ vout sense- vout- vout+ vdac - + x23.5 csinp3 reset dominant 9p irosc -+ pwm comparator 0 to irosc*3/4 + - share adjust error amp s q qb r rsff 0.6v rcs3 ccs3 1 2 gateh3 gatel3 vin csc3 scomp3 rsc3 vin vin vdac - + x23.5 vdac - + x23.5 clk3 clk2 eaout clk1 clk2 irosc clk3 u30 oscblock clk3 ovp set ovp reset figure 2 ? pwm block diagram refer to figure 3. upon receiving a clock pulse, t he rsff is set, the internal pwm ramp voltage begin s to increase, the low side driver is turned off, and th e high side driver is then turned on. for phase 1, an internal 9pf capacitor is charged by a current source that propo rtional to the switching frequency resulting in a r amp rate of 50mv per percent duty cycle. for example, if the s teady-state operating switch node duty cycle is 10% , then the internal ramp amplitude is typically 500mv from the starting point (or floor) to the crossing of the e aout control voltage. when the pwm ramp voltage exceeds the err or amplifiers output voltage, the rsff is reset. t his turns off the high side driver, turns on the low side dri ver, and discharges the pwm ramp to 0.6v until the next clock pulse. downloaded from: http:///
ir3094pbf page 12 of 29 09/26/05 figure 3 ? 3 phase oscillator and pwm waveforms the rsff is reset dominant allowing both phases to go to zero duty cycle within a few tens of nanoseco nds in response to a load step decrease. phases can overla p and go to 100% duty cycle in response to a load s tep increase with turn-on gated by the clock pulses. an error amplifier output voltage greater than the co mmon mode input range of the pwm comparator results in 100% d uty cycle regardless of the voltage of the pwm ramp . this arrangement guarantees the error amplifier is alway s in control and can demand 0 to 100% duty cycle as required. it also favors response to a load step decrease whi ch is appropriate given the low output to input vol tage ratio of most systems. the inductor current will increase mu ch more rapidly than decrease in response to load t ransients. this control method is designed to provide single cycle transient response where the inductor curren t changes in response to load transients within a single switchi ng cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. body braking tm in a conventional synchronous buck converter, the m inimum time required to reduce the current in the i nductor in response to a load step decrease is; t slew = [l x (i max - i min )] / vout (1) the slew rate of the inductor current can be signif icantly increased by turning off the synchronous re ctifier in response to a load step decrease. the switch node v oltage is then forced to decrease until conduction of the synchronous rectifiers body diode occurs. this inc reases the voltage across the inductor from vout to vout + v body diode . the minimum time required to reduce the current in the inductor in response to a load transient dec rease is now; t slew = [l x (i max - i min )] / (vout + v body diode ) (2) clk1 clk3 50% internal oscillator ramp duty cycle ra mp1 slope = 50mv / % dc 0.6v fixed ramp1 eaout ramp3 ramp3 min duty cycle adjust ramp3 max duty cycle adjust the share adjust error amplifier can change the pulse width of ramps 2 & 3 from 0.5 x ramp1 to 2.0 x ramp1 to force current sharing. clk2 ramp 2 downloaded from: http:///
ir3094pbf page 13 of 29 09/26/05 since the voltage drop in the body diode is often h igher than output voltage, the inductor current sle w rate can be increased by 2x or more. this patent pending techni que is referred to as body braking and is accompl ished through the 0% duty cycle comparator. if the erro r amplifiers output voltage drops below 0.575v, th is comparator turns off the low side gate driver. figure 4 depicts pwm operating waveforms under vari ous conditions figure 4 ? pwm operating waveforms current sense amplifier a high speed differential current sense amplifier i s shown in figure 5. its gain decreases with increa sing temperature and is nominally 24 at 25oc and 20.9 at 125oc (-1400 ppm/oc). this reduction of gain tends to compensate the 3850 ppm/oc increase in inductor dcr . since in most designs the ir3094 ic junction is h otter than the inductors these two effects tend to cancel such that no additional temperature compensation of the load line is required. the current sense amplifier can accept positive dif ferential input up to 75mv and negative up to -25mv before clipping. the output of the current sense amplifier is summed with the vref voltage which is used for over current protection, voltage positioning and current sharing . figure 5 ? inductor curren t sensing and current sense amplifier clk1 pulse eaout 0.6v pwm ramp1 gateh1 gatel1 steady - state operation duty cycle increase due to load increase duty cycle decrease due to load decrease (body braking) or fault steady - state operation 0.575v c o l r l r s c s v o csa co i l v l v c downloaded from: http:///
ir3094pbf page 14 of 29 09/26/05 power-up in non-synchronous mode the sync latch is set by either a uvlo or a low ena ble fault at the beginning of the power-up cycle, k eeping all three low side gate drivers low. the sync latch is then reset once the fb pin exceeds 78% of vref to r elease the low side gate drive control to the error-amp. s comp preconditioning is also released at this time. non- synchronous startup helps preventing negative induc tor current until current sharing is stabilized. vcc under voltage lockout (uvlo) the vcc uvlo function monitors the ir3094s vcc sup ply pin and ensures enough voltage is available to power the internal circuitry. during power-up the fault l atch is reset when vcc exceeds 7.5v and all other f aults are cleared. the fault latch is set when vcc drops bel ow 7.0v and ss/del is below 3.75v. 5vuvl under voltage lockout (5vuvl) the 5vuvl function is provided for converters using a separate voltage supply other than vcc for gate driver bias. the 5vuvl comparator prevents operation by discharg ing ss/del below 3.75v to force eaout low. the 5vu vl comparator has an ok threshold of 4.36v ensuring ad equate gate drive voltage is present and a fault th reshold of 4.17v. power good output the pwrgd pin is an open-collector output and shoul d be pulled up to a voltage source through a resist or. during soft start, the pwrgd remains low until the output voltage is in regulation and ss/del is above 3.75v. the pwrgd pin becomes low if the fault latch is set. a high level at the pwrgd pin indicates that the conv erter is in operation and has no fault, but does not ensure the output voltage is within the specification. output voltage regulation within the design limits can logically b e assured however, assuming no component failure in the system. tri-state gate drivers the gatelx drivers can pull down up to 3.5a peak cu rrent and source up to 1.5a. the gatehx drivers ca n source and sink up to 1.5a peak current. an adaptiv e non-overlap circuit monitors the voltage on the g atehx and gatelx pins to prevent mosfet shoot-through current while minimizing body diode conduction. the error amplifier output of the control ic drives low in response to any fault condition such as vcc input under voltage or output overload. the 0% duty cycle compa rator detects this and drives both gate outputs low . this tri- state operation prevents negative inductor current and negative output voltage during power-down. the gate drivers revert to a high impedance off s tate at vcclx and vcchx supply voltages below the n ormal operating range. an 80k ?uhvlvwrulvfrqqhfwhgdfurvvwkh*$7(;dqg3*1'; slqvwrsuhyhqwwkh*$7(;yrowdjh from rising due to leakage or other cause under the se conditions. over voltage protection (ovp) the output over-voltage protection comparator monit ors the output voltage through the ovpsns pin, the positive remote sense point. if ovpsns exceeds vref plus 15 0mv, the ovp latch will be set. this will set the f ault latch immediately pulling the error amplifiers out put low, reset the pwm latch to fully turn-off the high side mosfets and turn-on the low side mosfets within app roximately 350ns. the low side mosfets will remain on until the ovp latch is reset by recycling vcc. ovps ns exceeding vref by 150mv also activates 75ua sour ces on the ovp pin. the lower mosfets alone can not cla mp the output voltage however an scr or mosfet coul d be triggered with the ovp pin to prevent processor damage. if powering up with a high side mosfet short, the o vp flag is activated and the ovp latch is set with as little vcc supply voltage as possible. the ovpsns pin is compared against both vcc and 5vuvl for ovp conditi ons at power-up. vcc is monitored for conversion off 1 2v, 5vuvl is monitored for conversion off 5v. the ovp pin flags a voltage greater than 0.48v with supply volt ages as low as 1.0v. this headroom voltage varies inversely with temperature. an external comparator can be used to disable the silver box, activate a crowbar, or sup ply source. downloaded from: http:///
ir3094pbf page 15 of 29 09/26/05 applications information vin cvin rset csc3 rsc3 enable cosns- rdrp csc2 cref rfb rref rcomp rocset rsc2 ccomp rrosc css vout+ vout sense+ vout sense- biasout csinm1 nc csinp1 csinp2 eaout enable fb gateh1 gateh2 gatel1 gatel2 lgnd ocset ovp pgnd1 pgnd2 pwrgd rosc scomp2 setbias ss/del vcc vcch1 vcch2 vccl1_2 5vuvl vref vdrp nc nc nc nc nc vosns- nc gatel3 pgnd3 gateh3 vcch3 vccl3 csinp3 scomp3 5vref ovpsns csinm2 csinm3 nc 48ld mlpq ir3094 pgood gnd cbias cbst1 1 2 l1 ccs1 ccs2 rcs1 rcs2 1 2 l2 cbst2 cout vout+ vin vin gnd vin c5vref ccs3 rcs3 1 2 l3 cbst3 vin cvcc ovp figure 6 ? system diagram oscillator resistor r rosc the oscillator frequency is programmable from 100kh z to 540khz with an external resistor r rosc as shown in figure 6. the oscillator generates an internal 50% duty cycle sawtooth signal (figure 3.) that is used to generate 120 out-of-phase timing pulses to set phase 1,2 an d 3 rs flip-flops. once the switching frequency is chosen, r rosc can be determined from the curve in the typical op erating characteristics section. soft start, over-current fault delay, and hiccup mo de the ir3094 has a programmable soft-start function t o limit the surge current during converter power-up . a capacitor connected between the ss/del and lgnd pins controls soft start timing as well as over-current protecti on delay and hiccup mode timing. figure 8 depicts the various operating modes of the ss/del function. under a no fault condition, the s s/del capacitor will charge. the ss/del charge soft-start duration is controlled by a 60ua charge current wh ich charges css up to 4.0v. the error amplifier output is clam ped low until ss/del reaches 1.1v. the error amplif ier will then regulate the converters output voltage to match th e ss/del voltage less the 1.1v offset until it reac hes the level determined by the vref voltage. the pwrgd signal is asserted once the ss/del voltage exceeds 3.75v. four different faults will immediately cause ss/del to begin discharging and set the fault latch once ss/del is below 3.75v; downloaded from: http:///
ir3094pbf page 16 of 29 09/26/05 1. vcc under voltage lock out 2. 5vuvl under voltage lock out 3. low enable pin 4. over current condition. a delay is included if any of the four fault condit ions occurs after a successful soft start sequence. this is required since momentary faults can occur as part of normal operation due to load transients such as exciting a n over- current condition. if any fault occurs during norma l operation, the ss/del capacitor will discharge th rough a 55ua current sink but will not set the fault latch immed iately. if the fault condition persists long enough for the ss/del capacitor to discharge below the 3.75v threshold of the delay comparator, the fault latch will be set pulling the error amplifiers output low, inhibiting switching and de -asserting the pwrgd signal. the ss/del capacitor is then discharged through a 6ua discharge current resultin g in a long hiccup duration. the ss/del capacitor will continue to discharge unt il it reaches 0.265v where the fault latch is reset allowing a normal soft start to occur. if a fault condition i s again encountered during the soft start cycle, th e fault latch will be set without any delay and hiccup mode will begin. d uring hiccup mode the 10 to 1 charge to discharge r atio results in a 9.1% hiccup mode duty cycle regardless of at w hat point a fault condition occurs. ovp fault immediately sets the fault latch causing ss/del to begin to discharge and this fault can onl y be cleared by cycling power to the ir3094 on and off. if ss/del pin is pulled below 0.8v, the converter c an be disabled. figure 7 ? operating waveforms soft-start delay time t ssdel is the time ss/del charged up to 1.1v. after that the error amp lifier output is released to allow the soft start. the soft start time t ss represents the time during which converter output voltage rises from zero to v o. t ss can be programmed by c ss using equation (3). o ss o ss chg ss v t v t i c * 10 * 60 * 6 (3) vcc start - up normal operation hiccup over - current protection re - start after ocp clears power - down 7.0v uvlo (12v) 5vuvl 4.36v ss/del 3.75v pwrgd vout iout (5vuvl gates fau lt mode) (vcc gates fault mode) 1.1v (vout changes due to load and vid changes) ocp delay ocp threshold downloaded from: http:///
ir3094pbf page 17 of 29 09/26/05 once c ss is chosen, the soft start delay time t ssdel, the over-current fault latch delay time t ocdel , and the delay time t vccpg from output voltage (v o ) in regulation to power good are fixed and shown i n equation (4), (5) and (6) respectively. 6 10 * 60 1.1* * ? ' ss chg ss ssdel c i v c t (4) 6 10 * 61 25.0* * ? ' ss dischg ss ocdel c i v c t (5) 6 10 * 60 )1.1 75.3(* * ? ' o ss chg ss vccpg v c i v c t (6) vref compensation network r ref and c ref a rc network tied between vref pin and vosens- is n eeded to compensate vref circuit. vref should come up earlier than ss/del pin charged up to 3.75v. for sa ve estimation, use half of the soft start time that is 0.5* t ss as the vref voltage establishing time. use equation ( 7) and (8) to determine r ref and c ref where vref source current i source is determained by r rosc and can be found using the curve in the typical ope rating characteristics section. ref ss source ref v t i c *5.0* (7) 2 15 10 2.3 5.0 ref ref c r ? (8) over current protection (ocp) the current limit threshold is set by a resistor co nnected between the ocset and vref pins. if the ave rage current sense amplifier output plus vref voltage ex ceeds the ocset voltage, the over-current protectio n is triggered. a delay is included if an over-current condition oc curs after a successful soft-start sequence. this i s required since over-current conditions can occur as part of normal operation due to load transients. if an over-curre nt fault occurs during normal operation, the over current comparato r will initiate the discharge of the capacitor at s s/del but will not set the fault latch immediately. if the over-cu rrent condition persists long enough for the ss/del capacitor to discharge below the 245mv offset of the delay compa rator, the fault latch will be set pulling the erro r amplifiers output low inhibiting switching in the phase ics an d de-asserting the pwrgd signal. the hiccup mode du ty cycle of over current protection is determined by the fixed 10:1 ratio of the charge to discharge current. the inductor dc resistance r l is utilized to sense the inductor current. the cur rent limit threshold is set by a resistor r ocset connected between the ocset and vref pins, as show n in fig6. i limit is the required over current limit. i ocset, the bias current of ocset pin, is set by r rosc and is determined by the curve in the typical operating characteristics section. ocp need to sati sfy the high temperature condition. r l_max and r l_room are the inductor dcr at maximum temperature t l_max and room temperature t_ room respectively, the maximum inductor dcr can be calculated from equation (9) downloaded from: http:///
ir3094pbf page 18 of 29 09/26/05 )] ( 10 * 3850 1[ _ 6 _ _ room max l room l max l t t r r ? (9) the current sense amplifier gain of ir3094 decrease s with temperature at the rate of 1400 ppm, which compensates part of the inductor dcr increase. the minimum current sense amplifier gain at the maximum ic temperature t ic_max is calculated from equation (10). )] ( 10 * 1400 1[ _ 6 _ _ room max ic room cs min cs t t g g ? (10) r ocset can be calculated by the following equation (11). ocset min cs max l limit ocset i g r i r / ) 3 ( _ _ (11) output voltage droop in some of the applications, output voltage droop i s needed to minimize output voltage deviations duri ng load transients and reduce power dissipation of the load when it is drawing maximum current. the voltage at the vdrp pin is an average of three phase current sense amplifiers and represents the s um of the vref voltage and the average inductor current of al l the phases. the vdrp pin is connected to the fb p in through the r drp resistor, see figure 6. the error amplifier force s the voltage on the fb pin to equal vref through t he power supply loop therefore the current through rdr p is equal to (vdrp-vref) / r drp. as the load current increases, the vdrp voltage increases accordingly w hich results in an increase in r fb current, positioning the output regulated voltage lower thus making the outp ut voltage reduction proportional to an increase in load current. the droop impedance or output impedance of the conv erter can thus be programmed by the resistor r drp. the offset and slope of the converter output impedance are independent of the vref voltage. the vdrp pin voltage represents the average current of the converter plus the 0.84v reference voltage. the load current can be retrieved by subtracting the vref vo ltage from the vdrp voltage. the converter voltage will be lowered by r o *i o, where r o is the required output impedance of the converter. r drp is determined by equation (12) o min cs max l fb drp r n g r r r _ _ (12) lossless average inductor current sensing inductor current can be sensed by connecting a seri es resistor and a capacitor network in parallel wit h the inductor and measuring the voltage across the capacitor. the equation of the sensing network is, s s l l s s l c c sr sl r s i c sr s v s v 1 )( 1 1 )( )( (13) usually the resistor rcs and capacitor ccs are chos en so that the time constant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr. if the two time constants ma tch, the voltage across ccs is proportional to the current t hrough l, and the sense circuit can be treated as i f only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component o f the inductor current. downloaded from: http:///
ir3094pbf page 19 of 29 09/26/05 the advantage of sensing the inductor current versu s high side or low side sensing is that actual outp ut current being delivered to the load is obtained rather than peak or sampled information about the switch curre nts. the output voltage can be positioned to meet a load lin e based on real time information. except for a sens e resistor in series with the inductor, this is the only sense me thod that can support a single cycle transient resp onse. other methods provide no information during either load i ncrease (low side sensing) or load decrease (high s ide sensing). an additional problem associated with peak or valle y current mode control for voltage positioning is t hat they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of freq uency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope compensa tion, input voltage, and output voltage are all add itional sources of peak-to-average errors. measure the inductance l and the inductor dc resist ance r l . pre-select the capacitor c cs and calculate r cs as follows. cs l cs c r l r (14) inductor dcr temperature correction if the current sense amplifier temperature dependen t gain is not adequate to compensate the inductor d cr tc, a negative temperature coefficient (ntc) thermistor c an be added. the thermistor should be placed close to the inductor and connected in parallel with the feedbac k resistor, as shown in figure 8. the resistor in s eries with the thermistor is used to reduce the nonlinearity of th e thermistor. figure 8 - temperature compensation of inductor dcr remote voltage sensing to compensate for impedance in the ground plane, th e vosns- pin is used for remote sensing and connect s directly to the load. the vref voltage is reference d to vosns- to avoid additional error terms or dela y related to a separate differential amplifier. the capacitor conn ecting the vref and vosns- pins ensure that high sp eed transients are fed directly into the error amplifie r without delay. downloaded from: http:///
ir3094pbf page 20 of 29 09/26/05 master-slave current share loop current sharing between phases of the converter is achieved by a master-slave current share loop topol ogy. the output of the phase 1 current sense amplifier sets the reference for the share adjust error amplifiers . each share adjust error amplifier adjusts the duty cycle of it s respective pwm ramp and to force its input error to zero compared to the master phase 1, resulting in accura te current sharing. the maximum and minimum duty cycle adjust range of ramps 2 & 3 compared to ramp1 has been limited to a minimum of 0.5x and a maximum of 2.0x typical (see figure 3.). the crossover frequency of the current share loop can be programmed with a capacitor at the scompx pi n so that the share loop does not interact with the output voltage loop. the scompx capacitor is driven by a trans-conductan ce stage capable of sourcing and sinking 22ua. the duty cycle of ramps 2 & 3 inversely tracks the voltage o n their scompx pin; if v(scomp2) increases, ramp2s slope will increase and the effective duty cycle will dec rease resulting in a reduction in phase 2s output current. due to the limited 22ua source current, an scompx pre-cond iton circuit has been included to pre-condition v(s compx) so that the duty cycle of ramps 2 & 3 are equal to ramp1 prior to any gatehx high pulses. the pre-co ndition circuit can source/sink 360ua. the sync latch (see figure 1) releases the pre-condition circuit once fb reaches 78% of vref. set biasout voltage biasout pin provides a 150ma open-loop regulated vo ltage for gate drive bias. the voltage is set by se tbias through an external resistor rset connecting betwee n setbias pin and ground. bias current i setbias is a function of rosc. rset is chosen by equation (15). v fd in the equation is the forward voltage drop across the bootstrap diode. setbias fd biasout set i v v r (15) compensation of the current share loop the crossover frequency of the current share loop s hould be at least one decade lower than that of the voltage loop in order to eliminate the interaction between the t wo loops. a 22nf capacitor from scomp to lgnd is go od for most of the applications. if necessary have a resistor in series with the csc to make the current loop a little bit faster. compensation of voltage loop the selection of compensation types depends on the output capacitors used in the converter. for the ap plications using electrolytic, polymer or al-polymer capacitor s and running at lower frequency, type ii compensat ion shown in figure 9(a) is usually enough. while for the applic ations using only ceramic capacitors and running at higher frequency, type iii compensation shown in figure 9( b) is preferred. for applications without voltage droop, the compens ation is the same as for the regular voltage mode c ontrol. for converter using polymer, al-polymer, and ceramic ca pacitors, which have much higher esr zero frequency , type iii compensation is required as shown in figure 9(b ) with r drp and c drp removed. downloaded from: http:///
ir3094pbf page 21 of 29 09/26/05 rcp ccp1 eaout ccp rfb rdrp vo+ vdrp vdac + - eaout fbfb cfb cdrp rcp eaout ccp1 ccp rfb rdrp vo+ vdrp vdac fb + - eaout rfb1 ( a) type ii compensation (b) type iii compensation figure 9. voltage loop compensation networks type ii compensation for voltage droop applications determine the compensation at no load, the worst ca se condition. choose the crossover frequency fc bet ween 1/10 and 1/5 of the switching frequency per phase. assum e the time constant of the resistor and capacitor a cross the output inductors matches that of the inductor, and determine r cp and c cp from (16) and (17), where l e and c e are the equivalent inductance of output inductors and t he equivalent capacitance of output capacitors resp ectively. 2 2 ) * * * 2( 1 * 5 ) 2( c c i fb e e c cp r c f v r c l f r s s (16) cp e e cp r c l c 10 (17) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usually enough. type iii compensation for voltage droop application s determine the compensation at no load, the worst ca se condition. assume the time constant of the resis tor and capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of the voltage loop can be estimated by (18) and (19), whe re r le is the equivalent resistance of inductor dcr. le fb cs e drp c r r g c r f * * 2 1 s (18) s t 180 )5.0 tan( 90 1 a c (19) choose the desired crossover frequency fc around fc 1 estimated by (18) or choose fc between 1/10 and 1 /5 of the switching frequency per phase, and select the compo nents to ensure the slope of close loop gain is -20 db /dec around the crossover frequency. choose resistor r fb1 according to (20), and determine c fb and c drp from (21) and (22). vref vref downloaded from: http:///
ir3094pbf page 22 of 29 09/26/05 fb fb r r 2 1 1 to fb fb r r 3 2 1 (20) 1 4 1 fb c fb r f c s (21) drp fb fb fb drp r c r r c ) ( 1 (22) r cp and c cp have limited effect on the crossover frequency, an d are used only to fine tune the crossover frequenc y and transient load response. determine r cp and c cp from (23) and (24). i fb e e c cp v r c l f r 5 ) 2( 2 s (23) cp e e cp r c l c 10 (24) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usually enough. type iii compensation for no droop applications resistor r drp and capacitor c drp are not needed. choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase and select the desire d phas hpdujlq f&dofxodwh.idfwruiurp 25), and determine the component values based on (26) to (30), )]5.1 180 ( 4 tan[ c k t s (25) k v f c l r r i c e e fb cp 5 ) 2( 2 s (26) cp c cp r f k c s 2 (27) cp c cp r k f c s 2 1 1 (28) fb c fb r f k c s 2 (29) fb c fb c k f r s 2 1 1 (30) downloaded from: http:///
ir3094pbf page 23 of 29 09/26/05 mathcad file to estimate the power dissipation of t he ic the full featured control ic ir3094 contain both control and 3 phase gate drive functions. it also has theadjustable voltage bias regulator inside to provide mosfet drive voltage. for the thermal consideration, this mathcad file step by step shows how to estimate the power dissipation of ir3094 . initial conditions: no.of phases: n 3 ic supply voltage: vcc 12 v( ) , ic supply current(quiescent): icq 35 ma ( ) total high side driver vcch supply current(quiescent): iqh 5 n ? ma ( ) total low side driver vccl supply current(quiescent): iql 5 n ? ma ( ) biasout voltage: vbias 7.5 v( ) switching frequency per phase: fsw 450 khz ( ) thermal impedance of ic: t ja 27 ( o c/w) the data from the selected mosfets: controi fet ir6637, number of control fet per phase: nc 1 control fet total gate charge: qgc 15 nc( ) synchronous fet ir6612, number of sync. fet per phase: ns 1 sync fet total gate charge: qgs 45 nc( ) power dissipation: the ic will have less power dissipation if using external gate driver supply. for the worst case estimation, assuming using the bias regulator for all the gate drive supply voltage. 1. quiescent power dissipation total quiescent power dissipation: pq icq iqh iql ( ) vcc ? 10 3 ? pq w( ) 2. the power loss to drive the gate of the mosfets with the assumption of the low mosfet gate resistances, most gate drive losses are dissipated in the driver circuit. pdrv vbias fsw ? 10 3 ? n ? nc qgc ? ns qgs ? ( ) 10 9 ? a ? o ? ? pdrv w( ) where the ig fsw 10 3 ? n ? nc qgc ? ns qgs ? ( ) ? 10 9 ? term in the equation gives the total average bias current required to drive all the mosfets. 3. the bias regulator power loss to supply driving the mosfets preg vcc vbias ( ) ig ? preg w( ) 4. total power dissipation of the ic: pdiss pq pdrv preg pdiss w( ) and the total junction temperature rising is: pdiss t ja ? ( o c) downloaded from: http:///
ir3094pbf page 24 of 29 09/26/05 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of t he pcb layout, therefore minimizing the noise coupled to t he ic. refer to the schematic in figure 6 C system diagram. x dedicate at least one inner layer of the pcb as po wer ground plane (pgnd). x the center pad of ic must be connected to ground p lane (pgnd) using the recommended via pattern shown in package dimensions. x the ics pgnd1, 2, 3 and lgnd should connect to th e center pad under ic. x the following components must be grounded directly to the lgnd pin on the ic using a ground plane on the component side of pcb: css, rsc2, rsc3, rset, cvcc and c5vref. the lgnd should only be connected to ground plan on the center pad under ic x place the decoupling capacitors cvcc and cbias as close as possible to the vcc and vccl1_2, vccl3 pins. the ground side of cbias should not be connec ted to lgnd and it should directly ground through v ias. x the following components should be placed as close as possible to the respective pins on the ic: rros c, rocset, cref, rref, css, csc2, rsc2, csc3, rsc3, rs et. x place current sense capacitors ccs1, 2, 3 and resi stors rcs1, 2, 3 as close as possible to csinp1, 2, 3 pins of ic and route the two current sense signals in pa irs connecting to the ic. the current sense signals should be located away from gate drive signals and switch nod es. x use kelvin connections to route the current sense traces to each individual phase inductor, in order to achieve good current share between phases. x place the input decoupling capacitors closer to th e drain of top mosfet and the source of the bottom mosfet. if possible, use multiple smaller value cer amic caps instead of one big cap, or use low induct ance type of ceramic cap, to reduce the parasitic inductance. x route the high current paths using wide and short traces or polygons. use multiple vias for connectio ns between layers. x the symmetry of the following connections from pha se to phase is important for proper operation: - the kelvin connections of the current sense signa ls to inductors. - the gate drive signals from the ic to the mosfets . - the polygon shape of switching nodes. downloaded from: http:///
ir3094pbf page 25 of 29 09/26/05 pcb and stencil design methodology x 7x7 x 48 lead x 0.5mm pitch mlpq see figures 10-12. pcb metal design (0.5mm pitch leads) 1. lead land width should be equal to nominal part lead width. the minimum lead to lead spacing should be ?ppwrplqlpl]hvkruwlqj 2. lead land length should be equal to maximum part lead length + 0.2 mm outboard extension + 0.05mm inboard extension. the outboard extension e nsures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalig nment and ensure a fillet. 3. center pad land length and width should be = max imum part pad length and width. however, the minimum metal to metal spacing should be ?ppr]&rsshu?ppirur]&rsshu and ?ppirur]&rsshu 4. sixteen 0.30mm diameter vias shall be placed in the pad land spaced at 1.2mm, and connected to ground to minimize the noise effect on the ic, and to transfer heat to the pcb. pcb solder resist design (0.5mm pitch leads) 1. lead lands. the solder resist should be pulled away from the metal lead lands by a minimum of 0.060mm. the solder resist mis-alignment is a m aximum of 0.050mm and it is recommended that the lead lands are all nsmd. therefore pulling the s/r 0.060mm will always ensure nsmd pads. 2. the minimum solder resist width is 0.13mm, there fore it is recommended that the solder resist is completely removed from between the lead lands f orming a single opening for each group of lead lands. 3. at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of ?ppuhpdlqv 4. land pad. the land pad should be smd, with a mi nimum overlap of the solder resist onto the copper of 0.060mm to accommodate solder resist mis- alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. 5. ensure that the solder resist in-between the lea d lands and the pad land is ?ppgxhwr the high aspect ratio of the solder resist strip se parating the lead lands from the pad land. 6. the single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than the diameter of the via. stencil design (0.5mm pitch leads) 1. the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited wil l minimize the occurrence of lead shorts. since fo r 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are di fficult to maintain repeatable solder release. 2. the stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. 3. the center land pad aperture should be striped w ith 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the cen ter pad. if too much solder is deposited on the center land pad the part will float and the lead la nds will be open. 4. the maximum length and width of the center land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull b ack to decrease the incidence of shorting the center land to the lead lands when the part is push ed into the solder paste. downloaded from: http:///
ir3094pbf page 26 of 29 09/26/05 figure 10. pcb metal and solder resist. downloaded from: http:///
ir3094pbf page 27 of 29 09/26/05 figure 11. pcb metal and component placement. downloaded from: http:///
ir3094pbf page 28 of 29 09/26/05 figure 12. stencil design. downloaded from: http:///
ir3094pbf page 29 of 29 09/26/05 package dimensions data and specifications subject to change without n otice. this product has been designed and qualified for th e consumer market. qualification standards can be found on irs web si te. ir world headquarters: 233 kansas st., el segundo, california 90245, usa t el: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact informati on www.irf.com downloaded from: http:///

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