View AD8390AACPZ-R7_8931966.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low power, high output current differential amplifier data sheet ad8390a rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2013 analog devices, inc. all rights reserved. features voltage feedback amplifier ideal for adsl and adsl2+ central office (co) and customer premises equipment (cpe) applications enables high current differential applications low power operation single- or dual-supply operation from 10 v ( 5 v) up to 24 v ( 12 v) 5.5 ma total quiescent supply current for full power adsl and adsl2+ co applications adjustable supply current to minimize power consumption high output voltage and current drive 400 ma peak output drive current 44 v p-p differential output voltage low distortion ?70 dbc mtpr, 26 khz to 1.1 mhz ?65 dbc mtpr, 1.1 mhz to 2.2 mhz high speed: 260 v/s differential slew rate applications adsl/adsl2+ co and cpe line drivers xdsl line drivers high current differential amplifiers functional block diagram 56k ? 56k ? 56k ? 56k ? v c c vcc vcom outp ad8390a outn inp inn vee vee 07094-002 figure 1. general description the ad8390a is a high output current, low power consumption differential amplifier. it is particularly well suited for the central office (co) driver interface in digital subscriber line systems such as adsl and adsl2+. in full bias operation, the driver delivers 20.4 dbm output power into low resistance loads while compensating for hybrid and transformer insertion losses and back termination resistors. the ad8390a is available in a thermally enhanced lfcsp package (16-lead lfcsp). significant control and flexibility in bias current have been designed into the ad8390a. four power modes are selectable via two digital inputs, pd0 and pd1, providing three levels of driver bias and one power-down state. in addition, the i adj pin is available for fine quiescent current trimming to tailor the performance of the ad8390a. the low power consumption, high output current, high output voltage swing, and robust thermal packaging enable the ad8390a to be used as the central office line driver in adsl, adsl2+, and proprietary xdsl systems, as well as in other high current applications requiring a differential amplifier.
ad8390a data sheet rev. b | page 2 of 12 table of contents feature s .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general descriptio n ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 thermal resistance ...................................................................... 4 maximum power dissipation ..................................................... 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 test circuits ........................................................................................8 theory of operation .........................................................................9 applications information .............................................................. 10 supplies, grounding, and layout ............................................. 10 vcom pin .................................................................................. 10 power management .................................................................... 10 adsl and adsl2+ applications ............................................. 11 lightning and ac power fault ................................................. 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 12 revision history 2 / 13 rev ision b: initial version
data sheet ad8390a rev. b | page 3 of 12 specifications v s = 12 v or v s = 24 v, r l = 100 ? , g = 10, pd(1:0) = ( 1 ,1 ), i adj = nc, v com = nc (bypas sed with 0.1 f capacitor), t a = 25c, unless otherwise noted. refer to the basic test circuit in figure 14. table 1 . parameter conditions min typ max unit dynamic performance ? 3 db small signal bandwidth v out = 0.2 v p - p, r f = 10 k ? 38 45 mhz large signal bandwidth v out = 4 v p -p 3 5 38 mhz peaking v out = 0.2 v p -p 0.1 db slew rate v out = 4 v p -p 260 v/s noise/distortion performance multitone power ratio (26 khz to 1. 1 mhz) z line = 100 ? , p line = 20.4 dbm, crest factor (cf) = 5.4 C 70 dbc multitone power ratio (1.1 mhz to 2.2 mhz) z line = 100 ? , p line = 20.4 dbm, crest factor (cf) = 5.4 C 65 dbc voltage noise (rti) f = 10 khz 5 nv/ hz input characteristics rti offset voltage (v os,dm(rti) ) v inp ? v inn , vcom = midsupply C 3.0 1.0 +3.0 mv v inp C v inn , vcom = nc C 3.0 1.0 +3.0 mv input bias current C 4.0 C 7.0 a input offset current C 0.35 0.05 +0.35 a input resistance 400 k ? input capacitance 2 pf common - mode rejection ratio ( ?v os,dm(rti) )/( ?v in,cm ) 58 69 db output characteristics differential output voltage swing ?v out 42.8 44 44.6 v output balance error ( ?v os,cm )/ ?v out 60 db linear output current r l = 10 ?, f c = 100 khz 400 m a output impedance f c = 2 mhz 0.1 ? output common - mode offset (v outp + v outn )/2, vcom = midsupply C 75 35 +75 mv (v outp + v outn )/2, vcom = nc C 75 35 +75 mv power supply operating range (dual supply) 5 12 v operating range (single supply) 10 24 v total quiescent current, i adj = vee pd(1:0) = (1,1) 5. 5 6.5 ma pd(1:0) = (1,0) 4.0 5.0 ma pd(1:0) = (0,1) 2.6 3.5 ma pd(1:0) = (0,0) 0.5 6 1.0 ma total quiescent current , i adj = nc pd(1:0) = (1,1) 10.0 11.0 ma pd(1:0) = (1,0) 6.7 8.0 ma pd(1:0) = (0,1) 3.8 5.0 ma pd(1:0) = (0,0) 0.67 1.0 ma power supply rejection ratio (psrr) ?v os,dm / ?v s , ?v s = 1 v, vcom = midsupply 72 94 db pd(1:0) = 0 (low logic state) 0 .8 v pd(1:0) = 1 (high logic state) 1.6 v vcom input voltage range ? 11.0 + 10.0 v input resistance 28 k ? vcom accuracy ?v out,cm / ?v com 0.99 5 1.0 1.00 5 v/ v
ad8390a data sheet rev. b | page 4 of 12 absolute maximum rat ings table 2 . parameter rating supply voltage (vcc ? vee) 26 v vcom vee < vcom < vcc package power dissipation see figure 2 maximum junction temperature (t j max ) 150c operating temperature range (t a ) C 40c to +85c storage temperature range C 65c to +150c lead temperature (soldering , 10 s ec ) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a st ress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect devi ce reliability. thermal resistance ja is specified in still air with exposed pad soldered to 4 - layer jedec test board. jc is specified at the exposed pad. table 3 . thermal resistance package type ja jc unit 16- lead lfcsp (cp -16-4 ) 30.4 16 c/w maximum power dissip ation the maximum safe power dissipation for the ad839 0a is limited by its junction temperature on the die. the maximum safe junction temperature of plastic encapsu - lated devices, as determined by the glass transition temperature of the plastic, is 150 c. exceeding this limit temporarily may cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. exceeding this limit for an extended period can result in device fail ure. figure 2 shows the maximum safe power dissipation in the package v s. the ambient temperature. ja values are approximations. ambient temperature ( c) maximum power dissipation (w) 0 0.5 1.0 1.5 2.0 2.5 3.0 ?25 ?15 ?5 5 15 25 35 45 55 65 75 85 3.5 t j = 150c 07094-003 figure 2 . maximum power dissipation vs. temperature the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). assuming that the load r l is referenced to midsupply, the total drive power is v s /2 i out , part of which is dissipated in the package and part in the load (v out i out ). rms output voltages should be considered. if r l is referenced to vee as in single - supply operation, the total power is v s i out . in single - supply operation with r l referenced to vee, the worst case is v out = v s /2. airflow increases heat dissipation, effectively reducing ja . in addition, more copper in direct contact with the package leads from pcb traces, through holes, ground, and power planes reduces ja . esd c aution
data sheet ad8390a rev. b | page 5 of 12 pin configuration and fu nction descriptions 07094-004 pin 1 indicator 1 inp 2 pd1 3 pd0 4 inn 11 vee 12 outn 10 vcc 9outp 5 n c 6 d g n d 7 i a d j 8 n c 1 5 v c o m 1 6 n c 1 4 n c 1 3 n c top view (not to scale) ad8390a notes 1. nc = no connect. 2 . no electrical connection. connect the exposed pad to a solid exte rnal plane with low thermal resistance. figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 inp amplifier noninverting input. 2 pd1 power mode control. 3 pd0 power mode control. 4 inn amplifier inverting input. 5 nc no connection. 6 dgnd ground. 7 i adj bias current adjustment. 8 nc no connection. 9 outp amplifier noninverting output. 10 vcc positive power supply. 11 vee negative power supply. 12 outn amplifier inverting output. 13 nc no connection. 14 nc no connection. 15 vcom common-mode voltage. 16 nc no connection. epad exposed pad. no electrical connection. connect the ex posed pad to a solid external plane with low thermal resistance.
ad8390a data sheet rev. b | page 6 of 12 typical performance characteristics v s = 12 v, r l = 100 , g = 10, pd(1:0) = (1,1), i adj = nc, vcom = nc (bypassed with 0.1 f capacitor), t a = 25c, unless otherwise noted. refer to the basic test circuit in figure 14. pd(1:0) = (1,0) i adj = nc pd(1:0) = (1,1) i adj = nc pd(1:0) = (0,1) i adj = nc pd(1:0) = (1,1) i adj = v ee pd(1:0) = (1,0) i adj = v ee pd(1:0) = (0,1) i adj = v ee gain (db) 1 0.1 10 100 frequency (mhz) 07094-006 ?5 0 5 10 15 20 25 figure 4. differential small signal frequency response; v s = 12 v, gain = 10, v out = 200 mv p-p pd(1:0) = (1,0) i adj = nc pd(1:0) = (1,1) i adj = nc pd(1:0) = (0,1) i adj = nc pd(1:0) = (0,1) i adj = v ee pd(1:0) = (1,1) i adj = v ee pd(1:0) = (1,0) i adj = v ee ?5 0 5 10 gain (db) 15 20 25 1 0.1 10 100 frequency (mhz) 07094-007 figure 5. differential large signal frequency response; v s = 12 v, gain = 10, v out = 4 v p-p internal power dissipation (mw) output power (dbm) 0 7094-008 0 200 400 600 800 1000 12 14 16 18 20 22 pd(1:0) = (0,1) pd(1:0) = (1,1) pd(1:0) = (1,0) figure 6. internal power dissipation vs. output power; transformer turns ratio = 1:1.4 34 36 38 40 42 44 20 30 40 50 60 70 80 90 100 110 load ( ? ) differential dc output swing (v p-p) 0 7094-009 figure 7. differential dc output swing vs. r l ; v s = 12 v, pd(1:0) = (1,1), r iadj = nc 0.01 0.1 1 10 100 1000 r adj (k ? ) quiescent current (ma) 0 2 4 6 8 10 pd(1:0) = (1,0) pd(1:0) = (0,1) pd(1:0) = (1,1) 0 7094-010 figure 8. quiescent current vs. i adj resistor; v s = 12 v 012345678910 time (s) v pd (v) ?6 ?4 ?2 0 4 2 6 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 v out (v) output pd pulse 07094-011 figure 9. power-down to power-up time; pd(1:0) = (1,1) to pd(1:0) = (0,0) to pd(1:0) = (1,1)
data sheet ad8390a rev. b | page 7 of 12 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 1 10 100 frequency (mhz) feedthrough (db) v s = 12v g = 10 r l = 100 pd(1:0) = (0,0) 07094-019 figure 10 . signal feed thr ough 0 ?20 ?40 ?60 ?80 psrr (db) ?100 ?120 0.1 0.01 1 10 frequenc y (mhz) 07094-013 100 psr? psr+ figure 11 . psrr vs. frequency; pd(1:0) = (1,1) 0 ?20 ?10 ?30 ?40 ?50 cmrr (db) ?60 ?70 0.1 0.01 1 10 100 frequenc y (mhz) 07094-014 figure 12 . cmrr vs. frequency; v in = 200 mv p - p, gain = 10, i adj = nc 7 ?3 frequenc y (mhz) 07094-015 ?2 ?1 0 1 2 3 4 5 6 0.01 0.1 1 10 100 gain (db) figure 13 . gain with vcom driven vs. frequenc y; vcom = 200 mv p - p
ad8390a data sheet rev. b | page 8 of 12 test circuit s r f = 10k ? r g = 1k ? 52.3 ? 52.3 ? r g = 1k ? v in r l, dm = 100 ? r f = 10k ? ad8390 a v ou t , dm 07094-005 figure 14 . basic test circuit
data sheet ad8390a rev. b | page 9 of 12 theory of operation 56k ? 56k ? v c c vcc vcom outp ad8390a outn inp inn vee vee c a b 07094-016 56k ? 56k ? figure 15. functional block diagram the ad8390a is a true differential amplifier with common- mode feedback. the ad8390a is fu nctionally equivalent to three amplifiers, as shown in figure 15. amplifier a and amplifier b form a standard dual amplifier in an inverting configuration. amplifier c maintains the common-mode voltage vcom at the output. with vcom left unconnected, the outputs are internally biased to midsupply. vcom can be driven externally to set the dc output common-mode voltage. r f outn outp inp inn r g vcom r g r l, dm v out, dm + ? v in, dm ? + r f 07094-017 figure 16. basic application circuit the high open-loop gain of the ad8390a and the negative feedback minimize the differential and common-mode error voltages. with the differential and common-mode error voltages assumed to be 0, the differential-mode gain and input impedance of the basic application circuit shown in figure 16 are as follows: g f dmin dmout r r v v ? , , g dmin r r ? ? 2 ,
ad8390a data sheet rev. b | page 10 of 12 applications information supplies, grounding, and layo ut the ad8390a can be powered from either single or dual supplies, with the total supply voltage ranging from 10 v to 24 v. for optimum performance, use well - regulated low ripple supplies. as with all high speed amplifiers, pay close attention to supply d ecoupling, grounding, and overall board layout. provide low frequency supply decoupling with 10 f tantalum capacitors from each supply to ground. in addition, decouple all supply pins with 0.1 f quality ceramic chip capacitors placed as close as possible to the driver. use an internal low impedance ground plane to provide a common ground point for all driver and decoupling capacitor ground requirements. whenever possible, use separate ground planes for analog and digital circuitry. follow high speed layou t techniques to minimize parasitic capacitance around the inverting inputs. some practical examples of these techniques are keeping feedback traces as short as possible and clearing away ground plane in th e area of the inverting inputs. keep input and outp ut traces as short as possible and as far apart from each other as practical to minimize crosstalk. keep all differential signal traces as symmetrical as possible. vcom pin by design, the v com pin is internally biased at midsupply, eliminating the need for external resistors. however, the designer may set vcom to other voltage levels with an external low impedance source. when the vcom pin is left unconnected, decouple it with a 0.1 f capacitor to ground, placed in close proximity to the ad8390a. with dual equal supplies, connect the vcom pin directly to ground to bias the outputs at midsupply , e limina ting the need for the external decoupling capacitor. power management the ad8390a offers significant versatility for maxi mizing efficiency while maintaining optimal levels of performance. optimizing driver efficiency while delivering the required signal level is accomplished with two on - chip power management features: two pd pins t o select one of four bias modes and an i adj pin for fine bias adjustments. pd (1:0) pins two cmos - compatible logic pins, pd1 and pd0, select one of three active power levels and a power - down mode. the digital ground pin (dgnd) is the logic ground reference for the pd(1:0) pins. pd(1:0) = (0,0) is the power - down mode. the pd pins are internally connected to dgnd via termination resistors. when the pd pins are left unconnected, the ad8390a is in power - down mode. the ad8390a exhibits a low output impedance in the three active modes. the output impedance in the power - down mode is high bu t undefined and may not be suitable for systems that rely on a high impedance off state, such as multiplexing. i adj pin the i adj pin provides bias current fine - tuning . with the i adj pin unconnected, the bias currents are internally set to 10 ma, 6.7 ma, an d 3.8 ma for the three active modes. with the i adj pin connected to the negative supply (vee) , the bias currents ar e reduced by approximately 50%. a resistor , r adj , connected between the i adj pin and the negative supply, provides fine bias adjustment as s hown i n figure 8 . table 5 . pd and i adj selection guide pd1 pd0 r adj ( ? ) i q (ma) 1 1 10.0 1 0 6.7 0 1 3.8 0 0 0.67 1 1 0 5. 5 1 0 0 4.0 0 1 0 2.6 0 0 0 0.5 6
data sheet ad8390a rev. b | page 11 of 12 adsl and adsl2+ appl ications in a typical adsl/adsl2+ application, a differential line driver drives the signal from the analog front end (afe) onto the twisted pair telephone line. referring to the typical circuit representation in figure 17 , the differential input appears at v in+ and v in? from the afe. the dif ferential output is transformer - cou pled to the telephone line at tip and ring. the common - mode operating point, generally midway between the supplies, is set through vcom. in adsl/adsl2+ applications, it is common practice to conserve power by using positive feedback ( r3 in figure 17) to synthesize the output resistance, lowering the required value of the line matching resistors, r m . pd1 pd0 r m r l v ou t , dm + ? ?out +out r m r3 r2 r1 r1 r3 0.1f i adj r adj r2 1:n 10f 0.1f vcc +in vcom ?in 10f 0.1f 0.1f vee 07094-018 figure 17 . adsl/adsl2+ application circuit the differential input impedance to the circuit is 2 r1. r1 is chosen by the designer to match system requirements . the synthesized value of the back term ination resistor is given by the following equation . 2 2 n r k r l m = where r l is the line impedance , and n is the turns ratio of the trans former. the factor k defines the relationship between the negative and positive feedback resistors and is given by 2 1 r r3 k ? = commonly used values for k are between 0.1 and 0.25. values less than 0.1 can lead to instability and are not recommended. assuming low values for back term ination resistor r m , r3 is approximated as v a k r1 r3 ? 2 where a v is the voltage gain. r2 is given by k r3 r2 ? = 1 with r m , r3, and r2 calculated, the closest 1% resistors are chosen and the gain rechecked with the following equation: ( ) [ ] r3 k r2 r r1 r3 r2 a m v ? + + = 1 table 6 c ompar es the results of th e exact values, the simplified approximation, and the closest 1% resistor value calculation s. in this example, r1 = 1.0 k ? , a v = 10 , and k = 0.1. note that decreasing the value of the back term ination resistors attenuates the receive signal by approximately 1/k. advances in low noise receive amplifiers permit the use of k value s as small as 0.1. the line impedance, turns ratio, and k factor specify the output voltage and current required from the ad8390a. to accom - modate higher crest factors or lower supply rails, the turns ratio, n, may need to be increased. because higher turn s ratios and smaller k factors both attenuate the receive signal, a large increase in n may require an increase in k to maintain the desired noise performance. any particular design process requires that these trade - offs be address ed. table 6 . resistor selection component exact value approximate calculation standard 1% resistor value r1 (?) 1000 1000 1000 r2 (?) 2246.95 2222.22 2210 r3 (?) 2022.25 2000 2000 r m (?) 5 5 4.99 actual a v 10.000 9.889 10.138 actual k 0.1 0.1 0.095 l ightning and ac powe r fault when the ad8390a is an adsl/adsl2+ line driver, it is transformer - coupled to the twisted pair telephone line. in this environment, the ad8390a is subject to large line transients resulting from events such as lightning strikes o r downed power lines. additional circuitry is required to protect the ad8390a from damage due to these events.
ad8390a data sheet rev. b | page 12 of 12 outline dimensions 2.25 2.10 sq 1.95 compliant to jedec standards mo-220-vggc 02-26-2013-b 1 0.65 bsc pin 1 indic a t or 1.95 ref 0.75 0.60 0.50 t o p view 12 max 0.80 max 0.65 ty p se a ting plane coplanarit y 0.08 1.00 0.85 0.80 0.35 0.30 0.25 0.05 max 0.02 nom 0.20 ref 16 5 1 3 8 9 1 2 4 0.60 max 0.60 max pin 1 indic a t or 4.10 4.00 sq 3.90 exposed pad for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.25 min bot t om view 3.75 bsc sq figure 18 . 16 - lead lead frame chip scale package [lfcsp _vq ] 4 mm 4 mm body, very thin quad (cp - 16 - 4) dimensions shown in millimeters ordering guide model 1 temperature range package description package o ption ad8390aacp z - r2 ?40c to +85c 16 - lead lfcsp _vq, 250 piece reel cp - 16 - 4 ad839 0a acp z -rl ?40c to +85c 16- lead lfcsp _vq, 13 tape and reel c p -16-4 ad839 0a acp z -r 7 ?40c to +85c 16- lead lfcsp _vq, 7 tape and reel cp -16-4 1 z = rohs compliant part. ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07094 - 0- 2/13(b)

▲Up To Search▲

Price & Availability of AD8390AACPZ-R7

	To Download AD8390AACPZ-R7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .