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73s8024c smart card interface simplifying system integration? data sheet april 2009 rev. 1.3 ? 2009 teridian semiconductor corporation 1 description the teridian 73s8024c is a single smart card interface ic. it provides full electrical comp liance with iso - 7816 - 3, emv 4.0 and nds specifications 1 . interfacing with the system controller is done through the control bus, composed of digital inputs to control the interface, and one interrupt output to inform the system controller of the card presence and faults. data exchange with the card is managed from the system controller using the i/o line (and eventually the auxiliary i/o line s). hardware support for auxiliary i/o lines, c4 / c8 contacts, is provided. the card clock signal can be generated by an on - chip oscillator using an external crystal or by connection to a clock signal coming from the system controller. the teridian 73 s8024c device incorporates an iso - 7816 - 3 activation/deactivation sequencer that controls the card signals. level shifters drive the card signals with the selected card voltage (3 v or 5 v), coming from an internal dc - dc converter. with its high - efficien cy dc - dc converter, the teridian 73s8024c is a cost - effective solution for any smart card reader application to be powered from a single 2.7 v to 3.6 v power supply. emergency card deactivation is initiated upon card extraction or upon any fault generated by the protection circuitry. the fault can be a v dd (digital power supply) or a v cc (card power supply) failure , a card over - current , or ? the only smart card interface ic firmware compatible with the tda8004 operating with a single 2.7 v to 3.6 v power supply (allows removal of 5 v from the system) an over - heating fault. advantages ? the inductor - based dc - dc converter provides higher current and efficiency than the usual charge - pump capacitor - based converters ? ideal for battery - powered applications ? suita ble for high curren t cards and sams: (100 ma max) ? power down mode: 2 a typical features ? card interface: ? complies with iso - 7816 - 3, emv 4.0 and nds 1 ? a dc - dc converter provides 3v / 5v to the card from an external power supply input ? high - efficiency converter: > 80% @ v dd =3.3 v, v cc =5 v and i cc ? up to 100 ma supplied to the card = 65 ma ? iso - 7816 - 3 activation / deactivation sequencer with emergency automated deactivation on card removal or fault detected by the protection circuitry ? protection includes 2 voltage supervisors which detect voltage drops on card v cc and on v dd ? the v powe r supplies dd ? true over - current detection ( 150 ma max. ) voltage supervisor threshold value can be externally adjusted ? 2 card detection inputs, 1 for each possible user polarity ? auxiliary i/o lines, for c4/c8 contact signals ? card clock up to 20 mhz ? sys tem controller interface: ? 3 digital inputs control the card activation / deactivation, card reset and card voltage ? 4 digital inputs control the card clock (division rate and card clock stop modes) ? 1 digital output, interrupt to the system controller, allows the system controller to monitor the card presence and faults. ? crystal oscillator or host clock, up to 27 mhz ? power supply: v dd ? power d own mode 2.7 v to 3.6 v ? 6 kv esd protection on the card interface ? package: so28 applications ? set -top- boxes , dvd / hdd recorders ? point of sales and transaction terminals ? control access and identification 1 pending nds approval. downloaded from: http:///
73s8024c data sheet ds_8024c_ 023 2 rev. 1.3 functional diagram pin number reference to so28 package figure 1 : 73s8024c block diagram icc i/o buffers vdd voltage supervisor voltage reference xtal osc clock generation digital circuitry & fault logic v dd fault v cc fault int_clk vdd vdd vccrst clk pres pres xtalin xtalout clkdiv1clkdiv2 gnd temp fault nc 12 3 5 6 7 9 10 11 12 13 14 15 17 16 21 20 19 18 26 25 24 2328 27 iso-7816-3 sequencer r-c osc. dc-dc converter icc reset buffer icc clock buffer over temp pwrdn i/o aux1 aux2 iouc aux1uc aux2uc vddf_adj rstin cmdvcc 5v/ # v off 8 gnd 4 6 lin 6 22 gnd i cc fault downloaded from: http:///
ds_8024c_ 023 73s8024c data sheet rev. 1.3 3 table of contents 1 pin description ................................................... ................................................... .............................. 4 1.1 card interface ................................................... ................................................... ......................... 4 1.2 miscellaneous inputs and outputs ................................................... ............................................. 4 1.3 power supply and ground ................................................... ................................................... ....... 4 1.4 microcontroller interface ................................................... ................................................... ......... 5 2 system controller i nterface ................................................... ................................................... ......... 6 3 oscillator ................................................... ................................................... ........................................ 6 4 dc - dc converter C card power supply ................................................... ........................................ 7 5 over - temperature monitor ................................................... ................................................... ............ 7 6 voltage supervision ................................................... ................................................... ..................... 8 7 power down ................................................... ................................................... ................................... 8 8 activation sequence ................................................... ................................................... ..................... 9 9 deactivation sequence ................................................... ................................................... ............... 10 10 off and fault detection ................................................... ................................................... ............ 11 11 i/o circuitry and timing ................................................... ................................................... ............. 12 12 typical application schematic ................................................... ................................................... .. 13 13 electrical specification ................................................... ................................................... ............... 14 13.1 absolute maximum ratings ................................................... ................................................... .. 14 13.2 recommended operating conditions ................................................... ...................................... 14 13.3 card interface characteristics ................................................... ................................................. 15 13.4 digital signals ................................................... ................................................... ....................... 18 13.5 dc characteristics ................................................... ................................................... ................ 18 13.6 voltage / temperature fault detection circuits ................................................... ....................... 18 14 mechanical drawings (28 - so) ................................................... ................................................... .... 19 15 package pin designation (28 - so) ................................................... ................................................ 20 16 ordering information ................................................... ................................................... .................. 21 17 related documentation ................................................... ................................................... .............. 21 18 contact information ................................................... ................................................... .................... 21 revision history ................................................... ................................................... .................................. 22 figures figure 1: 73s8024c block dia gram ................................................... ................................................... ....... 2 figure 2: power down mode operation ................................................... ................................................... .. 9 figure 3: activation sequence C rstin low when cmdvcc goes low ................................................... .... 9 figure 4: activation sequence C rstin high when cmdvcc goes low ................................................... 10 figure 5: deactivation sequence ................................................... ................................................... ......... 11 figure 6: timing diagram C management of the interrupt line off ................................................... ....... 11 figure 7: i/o and i/ouc state diagram ................................................... ................................................... 12 figure 8: i/o C i/ouc delays: timing diagram ................................................... ........................................ 12 figure 9: 73s8024c typical application schematic ................................................... ................................ 13 figure 10: dc C dc converte r efficiency (v cc = 5 v) ................................................... ............................. 16 figure 11: dc C dc converter efficiency (v cc = 3 v) ................................................... ............................. 16 figure 12: 28 lead so ................................................... ................................................... .......................... 19 table table 1: choice of vcc pin capacitor ................................................... ................................................... .... 7 downloaded from: http:///
73s8024c data sheet ds_8024c_ 023 4 rev. 1.3 1 p in description 1.1 c ard interface name pin (so) description io 11 card i/o: data signal to/from card. includes a pull - up resistor to v cc. aux1 13 aux1: auxiliary data signal to/from card. includes a pull - up resistor to v cc. aux2 12 aux2: auxiliary data signal to/from card. includes a pull - up resistor to v cc. rst 16 card reset: provides reset (rst) signal to card. clk 15 card clock: provides clock (clk) signal to card. the rate of this c lock is determined by crystal oscillator frequency and clkdiv selections. pres 10 card presence switch: active high indicates card is present. includes a pull - down current source. pres 9 card presence switch: active low indicates card is present. includes a pull - up current source. vcc 17 card power supply: logically controlled by the sequencer, output of dc - dc converter. requires an external filter capacitor to the car d gnd. gnd 14 card ground. 1.2 miscellaneous i nputs and o utputs name pin (so) description xtalin 24 crystal oscillator input: can either be connected to crystal or driven as a source for the card clock. xtalout 25 crystal oscillator output: connected to crystal. left open if xtalin is being used as an external clock input. vddf_adj 18 v dd fault threshold adjustment input: this pin can be used to adjust the v ddf value (that controls deactivation of the card). must be left open if unused. nc 7 non - connec ted pin. 1.3 power supply and ground name pin (so) description vdd 6, 21 system controller interface supply voltage, supply voltage for internal power supply and dc - dc converter power supply source. gnd 4 dc - dc converter ground. gnd 22 digital ground. li n 5 external inductor. connect external inductor from pin 5 to v dd . keep the inductor close to pin 5. downloaded from: http:///
ds_8024c_ 023 73s8024c data sheet rev. 1.3 5 1.4 microcontroller interface name pin (so) description cmdvcc 19 command v cc (negative assertion): logic low on this pin causes the dc - dc converter to ramp the v cc supply to the card and initiates a card activation sequence . 5v/ #v 3 5 volt / 3 volt card selection: logic one selects 5 volts for v cc and card interface, logic low selects 3 volt operation. when the part is to be used with a single card vol tage, this pin should be tied to either gnd or v dd . however, it includes a high impedance pull - up resistor to default this pin high (selection of 5 v card) when unconnected . pwrdn 8 power down control input (active h igh ): when power down (pd) mode is activated; all internal analog functions are disabled to place the 73s8024c in its lowest power consumption mode. the pd mode is allowed only out of a card session (= pwrdn high is not taken into account when cmdvcc = 0). must be tied to ground when the pow er down function is not used. clkdiv1 clkdiv2 1 2 sets the divide ratio from the xtalin oscillator (or external clock i nput) to the card clock. these pins include pull - down resistors. clkdiv1 clkdiv2 clock rate 0 0 xtalin/8 0 1 xtalin/4 1 1 xtalin/2 1 0 xtalin off 23 in terrupt signal to the processor (active l ow ): multi - function indicating fault conditions and card presence. op en drain output configuration; it includes an internal 20 k pull - up to v dd. rstin 20 reset input: this signal is the reset command to the card . i/ouc 26 system controller data i/o to/from the card. includes internal pull - up resistor to v dd. aux1uc 27 system controller auxiliary data i/o to/from the card . includes internal pull - up resistor to v dd. aux2uc 28 system controller auxiliary data i/o to/from the card . includes internal pull - up resistor to v dd. downloaded from: http:///
73s8024c data sheet ds_8024c_ 023 6 rev. 1.3 2 system controller interface ? 2 digital inputs allow direct control of the card interface from the host as follows: ? pin cmdvcc : when low, starts an activation sequence if a card is present . ? pin 5v/ #v : defines the card voltage . ? the card i/o and reset signals have their corresponding controller i/os to be connected directly to the host: ? pin rstin: controls t he card reset signal (when enabled by the sequencer) . ? pin i/ouc: data transfer to card i/o contact . ? pins aux1uc and aux2uc (auxiliary i/o lines associated to the auxili ary i/o lines to be connected to the c4 and c8 card connector contacts) . ? 2 digital inputs control the card clock frequency division rate: clkdiv1 and clkdiv2 define the card clock frequency, from the input clock frequen cy (crystal or external clock). the division rate is defined as follows: clkdiv2 clkdiv1 clk 0 0 ? xtal 0 1 xtal 1 0 ? xtal 1 1 ? xtal when the division rate is equal to 1 (clkdiv2 = 0 and clkdiv1 = 1 ), the duty - cycle of the card clock depends on the duty - cycle and waveform of the signal applied on the pin xtalin . when other division rates are used, the 73s8024c circuitry guarantees a duty - cycle in the range 45% to 55%, conforming to iso - 7816 - 3, emv 4.0 and nds specifications. ? interrupt output to the host: as long as the card is not activated, the off pin informs the host about the card presence only ( l ow = n o card in the reader). when cmdvcc is set low (card activation sequence requested from the host), a low level on off means a fault has been detected ( e.g. card removed during a card session, or voltage fault, or thermal / over - current fault) that automatically initiates a deactivation sequence. ? power down: the pwrdn pin is a digital input that allows the host controller to put the 73s8024c in its power down state. this pin can only be activated out of a card session. 3 o scillator the 73s8024c device has an on - chip oscillator that can generate the smart card clock using an external crystal (connected between the pins xtalin and xtalout) to set the oscil lator frequency. when the card clock signal is available from another source, it can be connected to the pin xtalin, and the pin xtalout should be left unconnected. downloaded from: http:///
ds_8024c_ 023 73s8024c data sheet rev. 1.3 7 4 dc - dc converter C card power supply an internal dc - dc converter provides the card power supply. this converter is able to provide either 3 v or 5 v card voltage from the power supply applied on the v dd pin. the digital iso - 7816 - 3 sequencer controls the converter. card voltage selection is carried out by the digital i nput 5v/ #v . the circuit is an inductive step - up converter/regulator. the external components required are 2 filt er capacitors on the power - supply input v dd (next to the lin pin, 100 nf + 10 f), an inductor, and an output filter capacitor on the card power supply v cc . the circuit performs regulation by activating the step - up operation when v cc is below a set point of 5.0 or 3.0 volts minus a comparator hysteresis volt age and the input supply v dd is less than the set point for v cc . when v dd is greater than the set point for v cc (v dd = 3.6 v, v cc =3 v) the circuit operates as a linear regulator. depending on the inductor values, the voltage converter can provide current on v cc as high as 100 ma. the circuit provides over - current protection and limits i cc to 150 ma. when an over - current condition is sen sed, the circuit initiates a deactivation sequence from the control logic and reports back to the host controller a fault on the interrupt output off . choice of the inductor the nominal inductor value is 10 h, rated for 400 ma. the inductor is connected between lin (pin 5 in the so package, pin 2 in the qfn package) and the v dd voltage. the inductor value can be optimized to meet a particular configuration (i cc_max ). the inductor should be located on the pcb as close as possible to the lin pin of the ic. choice of the v cc depending on the applications, the requirements in terms of both the v capacitor cc table 1 minimum voltage and the transient currents that the interface must provide to the card are different. shows the recommended capacitors for each v cc table 1 : choice of vcc pin capacitor power supply configuration and applicable specification. specification requirement application specification min v cc max transient current c harge voltage a llowed during t ransient current capacitor type capaci tor value emv 4.0 4.6 v 30 na s x5r/x7r w/ esr < 100 m ? 3.3 f iso - 7816 -3 4.5 v 20 na s 1 f t ab l e 1: c h o i c e o f v c c p in c ap ac i t o r 5 over - temperature monitor a built - in detector monitors die temperature . when an over - temperature condition occurs , a card deactivation sequence is initiated, and an error or fault condition is reported t o the system controller. downloaded from: http:///
73s8024c data sheet ds_8024c_ 023 8 rev. 1.3 6 v oltage supervision two voltage supervisors constantly check the level of the voltages v dd and v cc . a c ard deactivation sequence is triggered upon a fault of any of these voltage supervisors. the d igit al circuitry is powered by the power supply applied on the vdd pin. v dd also defines the voltage range for the interface with the system controller. the v dd voltage supervisor is also used to initialize the iso - 7816 - 3 sequencer at power - on, and also to deactivate the card at power - off or upon a fault. the voltage threshold of the v dd voltage supervisor is internally set by default to 2.3 v nominal. however, it may be desirable, in some applications, to modify this threshold value. the pin vddf_adj (pin 18 in the so package, pin 17 in the qfn package) is used to connect an external resis tor r ext to ground to raise the v dd fault voltage to another value, v ddf . the resistor value is defined as follows: r ext = 180 k / (v ddf an alternative (more accurate) method of adjusting the v - 2.33) dd figure 9 fault voltage is to use a resistive network of r3 from the pin to supply and r1 from the pin to ground (see ). in order to set the new threshold voltage, the equivalent resistance must be determined. this resistance value w ill be designated kx. kx is defined as r1/(r1+r3) and is calculated as: kx = (2.649 / v th ) - 0.6042 where v th is the desired new threshold voltage. to determine the values of r1 and r3, use the following formulas: r3 = 72000 / kx r1 = r3*(kx / (1 C kx)) taking the example above, where a v dd 7 p ower down fault threshold voltage of 2.7 v is d esired, solving for kx gives: ? kx = (2.649 / 2.7) - 0.6042 = 0.377. solv ing for r3 gives: ? r3 = 72000 / 0.377 = 191 k ? . solving for r1 gives: ? r1 = 191000 *(0.377 / (1 C 0.377)) = 115.6 k ? . using standard 1% resistor values gives r3 = 191 k ? and r1 = 115 k ?. these values give an equivalent resistance of kx = 0.376, a 0.3% error. if the 2.3 v default threshold is used, this pin must be left unconnected. a power down function is provided via the pwrdn pin (a ctive h igh). when activated, the power down (pd) mode disables all the internal analog functions, including the card analog interf ace, the oscillators and the dc - dc converter, to put the 73s802 4 c in its lowest power consumption mode. pd mode is only allowed in the deactivated condition (out of a card session, when the cmdvcc signal is driven h igh from t he host controller). the host controller invokes the power down state when it is desirable to save power. the signals pres and pres remain functional in pd mode such that a card insertion sets off high. the micro - controller must then set pwrdn low and wait for the internal stabilization time prior to starting any card sessi on (prior to turning cmdvcc low). resumption of the normal mode occurs at approximately 10 ms (stabilization of the internal oscillators and reset of the circuitry) after pwrdn is set low. no card activation should be invoked during this 10 ms time period. if a card is present, off can be used as an indication that the circuit has completed its recovery from the power down state. off will go high at the end of the stabilization period. should cmdvcc go low during pwrdn = 1, or within the 10 ms internal stabilization / reset time, it will not be taken into account and the card interface will remain inactive. since cmdvcc is taken into account on its edges, it should be toggled high and low again after the 10 ms to activate a card. figure 2 illustrates the sequencing of the pd and normal modes. pwrdn must be conn ected to gnd if the power down function is not used. downloaded from: http:///
ds_8024c_ 023 73s8024c data sheet rev. 1.3 9 figure 2 : power down mode operation 8 a ctivation sequence the 73s8024c smart card interface ic has an internal 10 ms delay at power - on reset or upon application of v dd > v ddf the following steps and or upon exit of power - down mode. the card interface may only be activated when off is high which indicates a card is present. no activation is allowed at this time. cmdvcc (edge triggered) must then be set low to activate the card. figure 3 show the activation sequence and the timing of the card control signals when the system controller sets cmdvcc low while the rstin is low: 1. cmdvcc is set low. 2. next, the internal v cc control circuit checks the presence of v cc at the end of t 1 . in normal operation, the voltage v cc to the card becomes valid during t 1 . if v cc does not become valid, then off goes low to report a fault to the system controller, and the power v cc 3. turn i/o (aux1, aux2) t o reception mode at the end o f t to the card is shut down. 2 4. due to the fall of rstin, clk is app lied to the card at the end of t . 3 5. rst is a copy of rstin after t . 4 . rstin may be set high before t 4 , however the sequencer wont set rst high until 42000 clock cycles after the start of clk. figure 3: activation sequence C rstin low when c m d v c c goes low t 1 = 0.510 ms (timing by 1.5 mhz internal oscillator) t 2 = 1.5 s, i/o goes to reception state t 3 = >0.5 s, clk starts t 4 42000 card clock cycles (time for rst to become the copy of rstin) cmdvcc vcc io clk rstin t 1 t 2 t 3 t 4 rst pres o ff pwrdn internal rc osc cm dv cc off follows pres regardless of pwrdn pwrdn during a card session has no effect after setting pwrdn = 0, the controller must wait at least 10ms before setting cmdvcc =0 emv / iso deactivation time ~= 100 us ~10ms pwrdn has effect when the cardi s deactivated downloaded from: http:///
73s8024c data sheet ds_8024c_ 023 10 rev. 1.3 the following steps and figure 4 show the activation sequence and the timing of the card control signals when the system controller pulls cmdvcc low while rstin is high: 1. cmdvcc is set low. 2. next, the internal v cc control circuit checks the presence of v cc at the end of t 1 . in normal operation, the voltage v cc to the card becomes valid during this time. if not, off goe s low to report a fault to the system controller and the v cc 3. after the fall of rstin at t power to the card is shut down. 2 4. clk is applied to the card at the end of t , turn i/o (aux1, aux2) to reception mode. 3 5. rst is a copy of rstin after t after i/o is in reception mode. 4 . rstin may be set high before t 4 , however the sequencer will not set rst high until 42 , 000 clock cycles after the start of clk. figure 4: activation sequence C rstin high when c m d v c c goes low 9 d eactivation sequence deactivation is initiated either by the system controller by setting the cmdvcc high, or automatically in the event of hardware faults. hardware faults are over - current, overheating, v dd fault, v cc the following steps and fault, and card extract ion during the session. figure 5 show the deactivation sequence and the timing of the card control signals when the system controller sets the cmdvcc high or off goes low due to a fault or card removal: 1. rst goes low at the end of time t 1 2. clk is set low at the end of time t . 2 3. i/o goes low at the end of time t . 3 4. v . out of reception mode. cc is turned off at the end of time t 4 . after a delay t 5 (discharge of the v cc capacitor), v cc is low. t 1 = 0.510 ms (timing by 1.5mhz internal oscillator) t 2 = 1.5 s, i/o goes to reception state t 3 0.5 s, clk active t 4 42000 card clock cycles (time for rst to become the copy of rstin ). cmdvcc vcc io clk rstin t 1 t 2 t 3 t 4 rst downloaded from: http:///
ds_8024c_ 023 73s8024c data sheet rev. 1.3 11 figure 5 : deactivation sequence 10 off and f ault d etection there are two cases for which the system controller can monitor the off signal: to query regarding the card presence outside card sessions, or for fault detection during card ses sions. m oni t or i ng o ut s i d e a c a r d s e s s i on in this condition, cmdvcc is always high, off is low if the card is not present, and high if the card is present. because it is outside a card session, any fault detection will not act upon the off signal. no deactivation is required during this time. m oni t or i ng d ur i ng a c a r d s e s s i on cmdvcc is always low, and off falls low if the card is extracted or if any fault is detected. at the same time that off is set low, the sequencer starts the deactivation pro cess. figure 6 shows the timing diagram for the cmdvcc , pres, and off signals during a card session and outside the card session. pres off cmdvcc vcc outside card session within card session off is low by card extracted off is low by any fault within card session figure 6: timing diagram C management of the interrupt line off t 1 0.5 s, timing by 1.5 mhz internal oscillator t 2 7.5 s t 3 0.5 s t 4 0.5 s t 5 = depends on v cc filter capacitor for nds application, c f = 1 f making t 1 + t 2 + t 3 + t 4 + t 5 < 100 s rst clk i/o vcc t 1 t 2 t 3 t 4 t 5 cmdvcc -- or -- off downloaded from: http:///
73s8024c data sheet ds_8024c_ 023 12 rev. 1.3 11 i/o c ircuitry and t iming the i/o, aux1, and aux2 pins are in the low state after power on reset and they are in the high state when the activation sequencer turns on the i/o reception state. see section 8 activation sequence for more details on when the i/o reception is on. the state of the i/ouc, aux1uc, and aux2uc is high after power on reset. within a card session and when the i/o reception state is on, the first i/o line on which a falling edge is detected becomes the input i/o line and the other becomes the output i/o line. when the input i/o line rising edge is detected , both i/o lines return to their neutral state. figure 7 shows the state diagram of how the i/o and i/ouc lines are managed to bec ome input or output . the delay between the i/o signals is shown in figure 8 . neutral state i/ ouc in i/ o reception i/ oicc in no yes no no no yes no yes i/ o & not i / ouc i/ ouc & not i / o i/ ouc i/o yes yes figure 7 : i/o and i/ouc state diagram figure 8 : i/o C i/ouc delays : timing diagram delay from i/o to i/ouc: t io_hl = 100 ns t io_lh = 25 ns delay from i/ouc to i/o: t i/ouc_hl = 100 ns t i/ouc_lh = 25 ns io iouc t io _ hl t io _ lh t iouc _ hl t iouc _ lh downloaded from: http:///
ds_8024c_ 023 73s8024c data sheet rev. 1.3 13 12 t ypical application schematic c2 22pf c3 22pf see note 5 rstin_f rom_uc cmdvcc_f rom_uc c6 100nf 5v/3v_select_f rom_uc aux1uc_to.f rom_uc aux2uc_to/f rom_uc so28 see note 1 see note 4 clk track should be routed far from rst, i/o, c4 and c8 . l o w e sr (< 1 0 0 mo hms) c1 should be placed near the sc connecter contact see note 2 external_clock_f rom uc see note 3 - or - vdd r2 20k see note 6 card detection switch is normally closed. c1 nds & iso7816=1uf, emv=3.3uf l1 10uh r1 rext1 see note 7 clkdiv2_f rom_uc clkdiv1_f rom_uc see note 8 vdd see note 1 r3 rext2 vdd notes: 1) vdd supply must be =2.7v to 3.6v dc. 2) opti onal , can be l eft open 3) requi red i f external cl ock from up i s used. 4) required if crystal is used. y1, c2 and c3 must be removed i f external cl ock i s used. 5) pin can not float. must be driven or connected to gnd if power down function is not used. 6)internal pull-up allows it to be left open if unused. 7) rext1 and rext2 are external resi stors to ground and vdd to modi fy the vddfaul t vol tage. can be l eft open 8) keep l1 cl ose to pi n 5 off_interrupt_to_uc vdd iouc_to/f rom_uc pwrdn_f rom_uc y1 cry stal smart card connector vcc 1 rst 2 clk 3 c4 4 gnd 5 vpp 6 i/o 7 c8 8 sw-1 9 sw-2 10 u5 73s8024c clkdiv1 1 clkdiv2 2 5v3v_ 3 gnd 4 lin 5 vdd 6 nc 7 a u x2 12 pwrdn 8 presb 9 pres 10 i/o 11 a u x1 13 gnd 14 clk 15 rst 16 vcc 17 vdd_adj 18 cmdvcc_ 19 rstin 20 vdd 21 gnd 22 off_ 23 aux2uc 28 aux1uc 27 xtalout 25 xta l i n 24 i/ouc 26 c4 100nf c5 10uf figure 9 : 73 s8024c typical application schematic downloaded from: http:///
73s8024c data sheet ds_8024c_ 023 14 rev. 1.3 13 e lectrical specification 13.1 absolute maximum ratings operation outside these rating limits may cause permanent damage to the device. parameter r ating supply voltage v - 0.5 to 4.0 vdc dd input voltage for digital inpu ts - 0.3 to (v dd +0.5) vdc storage temperature - 60 c to 150 c pin voltage (except lin and card interface) - 0.3 to (v dd +0.5) vdc pin voltage (lin) - 0.3 to 6.0 vdc pin voltage (card interface) - 0.3 to ( v cc + 0.5) vdc esd tolerance C card interface pin s +/ - 6 kv esd tolerance C other pins +/ - 2 kv esd testing on card pins uses the hbm condition, 3 pulses, each polarity referenced to ground. 13.2 recommended operating conditions parameter rating supply voltage v dd 2.7 to 3.6 vdc ambient operating tem perature - 40 c to +85 c input voltage for digital inputs 0 v to v dd + 0.3 v downloaded from: http:///
ds_8024c_ 023 73s8024c data sheet rev. 1.3 15 13.3 card interface characteristics symbol parameter condition min. typ. max. unit card power supply (v cc ) dc - dc converter general conditions, - 40 c < t < 85 c, 2.7 v < v dd < 3 .6 v v card supply voltage including ripple and noise cc inactive mode - 0.1 0.1 v inactive mode i cc - 0.1 =1 ma 0.4 v active mode i cc 4.75 < 65 ma; 5 v 5.25 v active mode i cc 2.8 < 65 ma; 3 v 3.2 v active mode single pulse of 100 ma for 2 s; 5 v , fixed load = 25 ma 4.6 5.25 v active mode single pulse of 100 ma for 2 s; 3 v , fixed load = 25 ma 2.76 3.2 v active mode current pulses of 40 nas with peak |i cc 4.6 | < 200 ma, t < 400 ns; 5 v 5.25 v active mode current pulses of 40 nas with peak |i cc 2.76 | < 200 ma, t < 400 ns; 3 v 3.2 v i maximum supply current to the card ccmax static load current, v cc 100 > 4.6 or 2.7 volts as selected, l=10 h ma i i ccf cc fault current 100 125 180 ma v v sr cc c slew rate C rise rate on activate f on v cc 0.05 = 1 f 0.15 0.25 v/ s v v sf cc c slew rate C fall rate on deactivate f on v cc 0.1 = 1 f 0.3 0.5 v/ s c external filter capacitor (v f cc to gnd) 0.47 1 3.3 f l inductor (lin to v dd ) 10 h limax imax in inductor v cc = 5 v, i cc = 65 ma, v dd = 2.7 v 400 ma efficiency v cc = 5 v, i cc = 65 ma, v dd = 3.3 v 80 % downloaded from: http:///
73s8024c data sheet ds_8024c_ 023 16 rev. 1.3 1011b01 converter efficiency (vcc 5v) 50 55 60 65 70 75 80 85 90 95 100 0 20 40 60 80 100 icc [ma] efficiency [%] 2.7v 3.0v 3.3v 3.6v figure 10 : dc C dc converter efficiency (v cc = 5 v) output current on v cc at 5 v . input voltage on v dd 1011b01 converter efficiency (vcc 3v) 50 55 60 65 70 75 80 85 90 95 100 0 20 40 60 80 100 icc [ma] efficiency [%] 2.7v 3.0v 3.3v (linear) 3.6v (linear) at 2.7, 3.0, 3.3 and 3.6 volts . figure 11 : dc C dc converter efficiency (v cc = 3 v) output current on v cc at 3 v. input voltage on v dd at 2.7, 3.0, 3.3 and 3.6 volts . converter efficiency (v cc 5 v) converter efficiency (v cc 3 v) downloaded from: http:///
ds_8024c_ 023 73s8024c data sheet rev. 1.3 17 symbol parameter condition min. typ. max. unit interface requirements C data signals: i/o, aux1, aux2, and host interfaces: i/ ouc, aux1uc, aux2uc. i shortl , i shorth , and v inact requirements do not pertain to i//ouc, aux1uc, and aux2uc. i il requirements only pertain to i//ouc, aux1uc, and aux2uc. v output level, high (i/o, aux1, aux2) oh i oh 0.9 v = 0 cc v cc v + 0.1 i oh 0.75 v = - 40 a cc v cc v + 0.1 v output level, high (i/ouc, aux1uc, aux2uc) oh i oh 0.9 v = 0 dd v dd v + 0.1 i oh 0.75 v = - 40 a dd v dd v + 0.1 v output level, low ol i ol = 1 ma 0.3 v v input level, high (i/o, aux1, aux2) ih 1.8 v cc v + 0.30 v input level, high (i/ouc, aux1uc, aux2uc) ih 1.8 v dd v + 0.30 v input level, low il - 0.3 0.8 v v output voltage when outside of session inact i ol = 0 0.1 v i ol = 1 ma 0.3 v i input leakage leak v ih = v cc 10 a i inp ut current, low il v il = 0, cs = 1 0.65 ma v il = 0, cs = 0 5 a i short circuit output current shortl for output low, shorted to v cc through 33 ? 15 ma i short circuit output current shorth for output high, shorted to ground through 33 ? 15 ma t r , t output rise time, fall times f c l = 80 pf, 10% to 90%. for i/ouc, aux1uc, aux2uc, cl = 50 pf 100 ns t ir , t input rise, fall times if 1 s r internal pull - up resistor pu output stable for > 200ns 8 11 14 k ? fd maximum data rate max 1 mhz t delay, i/o to i/ouc, i/ouc to i/o (falling edge to falling edge) fdio 100 ns c input capacitance in 10 pf reset and clock for card interface, rst, clk v output level, high oh i oh 0.9 v = - 200 a cc v v cc v output level, low ol i ol 0 = 200 a 0.3 v v output voltage when outside of a session inact i ol = 0 0.1 v i ol = 1 ma 0.3 v i output current limit, rst rst_lim 30 ma i output current limit, clk clk_lim 70 ma t r , t output rise time, fall time f c l = 35 pf for clk, 10% to 90% 8 ns c l = 200 pf for rst, 10% to 90% 100 ns duty cycle for clk, except for f = f c xtal l =35 pf, f clk 45 20 mhz 55 % downloaded from: http:///
73s8024c data sheet ds_8024c_ 023 18 rev. 1.3 13.4 digital signals symbol parameter condition min. typ. max. unit digital i/o except for osc i/o vil input low voltage - 0.3 0.8 v vih input high voltage 1.8 vdd + 0.3 v vol output low voltage iol = 2 ma 0.45 v voh output high vo ltage ioh = -1 ma vdd - 0.45 v rout pull - up resistor, off 20 k ? |iil1| input leakage current gnd < vin < vdd -5 5 a oscillator (xtalin) i/o parameters v input low voltage - xtalin ilxtal - 0.3 0.3 v v dd v input high voltage - xtalin ihxtal 0.7 v dd v dd v + 0.3 i input current - xtalin ilxtal gnd < v in < v - 30 dd 30 a f max freq. osc or external clock max 27 mhz in external input duty cycle limit t r/f < 10% f in , 45% < clk 48 < 55% 52 % 13.5 dc characteristics symbol parameter condition min. typ. max. unit i supply current on v pc linear mode, icc = 0 i/o, aux1, aux2 = high dd 4.9 ma step up mode, icc = 0 i/o, aux1, aux2 = high 4.7 ma i supply current on v dd_pd dd pwrdn=1, start/stop bit = 0 all digital inputs drive n with a true logical 0 or 1 in power down mode 0.11 2.5 a 13.6 voltage / temperature fault detection circuits symbol parameter condition min. typ. max. unit v v ddf dd fault (v dd no external resistor on vddf_adj voltage supervisor threshold) 2.15 2.4 v v v ccf cc fault (v cc v voltage supervisor threshold) cc 4.20 = 5 v 4.6 v v cc 2.5 = 3 v 2.7 v t die over temperature fault f 115 145 c i card over current fault ccf 90 150 ma downloaded from: http:///
ds_8024c_ 023 73s8024c data sheet rev. 1.3 19 14 mechanical drawings (28 - so) figure 12 : 28 lead so .335 (8.509) .320 (8.128) .420 (10.668) .390 (9.906) .050 typ. (1.270) .305 (7.747) .285 (7.239) .715 (18.161) .695 (17.653) .0115 (0.29) .003 (0.076) .016 nom (0.40) .110 (2.790) .092 (2.336) pin no. 1 bevel downloaded from: http:///
73s8024c data sheet ds_8024c_ 023 20 rev. 1.3 15 package pin designation (28 - so) use handling proc edures necessary for a static sensitive component. (top view) figure 11: 73s8024c 28 - so pin out 73s8024c 1 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 19 20 28 27 26 25 24 23 22 21 clkdiv 1 clkdiv 2 5v/ # v gnd vdd pr es pres i/o aux 2 aux 1 gnd aux 2 uc aux 1 uc i/ouc xtalin xtalout o ff vdd rstin cmdv cc vcc rst clk nc lin pwrdn vddf _ adj gnd downloaded from: http:///
ds_8024c_ 023 73s8024c data sheet rev. 1.3 21 16 o rdering information part description order n umber packaging mark 73s8024c - so 28 - pin lead - free so 73s8024c - il/f 73s8024c - il 73s8024c - so 28 - pin l ead - free so tape / reel 73s8024c - ilr/f 73s8024c - il 17 related documentation the following 73s8024c documents are available from teridian semiconductor corporation: 73s8024c data sheet (this document) 73s8024c demo board users guide 18 contact information f or more information about teridian semiconductor products or to check the availability of the 73s8024c, contact us at: 6440 oak canyon road suite 100 irvine, ca 92618 - 5201 telephone: (714) 508 - 8800 fax: (714) 508 - 8878 email: scr.support@teridian.com for a complete list of worldwide sales offices, go to http://www.teridian.com . downloaded from: http:///
73s8024c data sheet ds_8024c_ 023 22 rev. 1.3 revision history revision date description 1.0 6/21/2005 first publication. 1.1 7/15/2005 removed qfn package information. 1.2 12/5/200 7 add iso and emv logos, remove leaded package option, update 28so package dimension . 1.3 4/3 /2009 remove all references to vpc as vpc must be tied to vdd. ? 2009 teridian semiconductor corporation. all rights reserved. teridian semiconductor corporation is a registered trademark of teridian semic onductor corporation. simplifying system integration is a trademark of teridian semiconductor co rporation. all other trademarks are the property of their respective owners. ter idian semiconductor corporation makes no warranty for the use of its products , other than expressly contained in the companys warranty detailed in the teridian semiconductor corporati on standard terms and conditions. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed he rein at any time without notice and does not make any commitment to update the information contained herein. ac cordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative. teridian semiconductor corp., 6440 oak canyon rd., suite 100, irvine, ca 92618 tel (714) 508 - 88 00, fax (714) 508 - 8877, http://www.teridian.com downloaded from: http:///

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