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general description the max96705 is a compact serializer with features especially suited for automotive camera applications. it is function and pin compatible with the max9271. in high- bandwidth mode, the parallel-clock maximum is 116mhz for 12-bit linear or combined hdr data types. the embedded control channel operates at 9.6kbps to 1mbps in uart, i 2 c, and mixed uart/i 2 c modes, allow - ing programming of serializer, deserializer, and camera registers independent of video timing. for driving longer cables, the ic has programmable pre/deemphasis. programmable spread spectrum is available on the serial output. the serial output meets iso 10605 and iec 61000-4-2 esd standards. the core supply range is 1.7v to 1.9v, and the i/o supply range is 1.7v to 3.6v. the max96705 is available in a 32-pin (5mm x 5mm) tqfn package with 0.5mm lead pitch, and operates over the -40 c to +115 c temperature range. applications automotive camera applications beneits and features ideal for safety camera applications ? works with low-cost 50 coax (100 stp) cables ? error detection of video/control data ? high-immunity mode for robust control-channel emc tolerance ? retransmission of control data upon error detection ? best-in-class supply current: 93ma (max) ? pre/deemphasis allows 15m cable at full speed ? 32-pin (5mm x 5mm) tqfn package with 0.5mm lead pitch high-speed data serialization for megapixel cameras ? up to 1.74gbps serial-bit rate ? 12.5mhz to 87mhz x 14 bit + h/v data ? 36.66mhz to 116mhz x 12-bit + h/v data (through internal encoding) multiple modes for system flexibility ? 9.6kbps to 1mbps control channel in uart, i 2 c (with clock stretch), or uart-to-i 2 c modes ? crosspoint switch accepts any input bitmap ? modes for encoded vsync and hsync reduces emi and shielding requirements ? programmable output spread spectrum ? tracks spread spectrum applied at the parallel input ? 1.7v to 3.6v i/o supply peripheral features for camera power-up and verification ? built-in prbs generator for ber testing ? dedicated gpo for camera frame-sync trigger and other uses ? remote/local wake-up from sleep mode meets aec-q100 automotive specification ? -40c to +115c operating temperature ? 8kv contact and 15kv air iec 61000-4-2 and iso 10605 esd protection ordering information appears at end of data sheet. 19-8434; rev 0; 12/15 cam max96705 max96706 video i 2 c gpu video i 2 c simpliied block diagram max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive evaluation kit available downloaded from: http:///
general description ............................................................................ 1 applications .................................................................................. 1 benefits and features .......................................................................... 1 simplified block diagram ........................................................................ 1 absolute maximum ratings ...................................................................... 6 package information ........................................................................... 6 32-pin tqfn-ep ................................................... .......................... 6 dc electrical characteristics ..................................................................... 7 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 typical operating characteristics ................................................................ 13 pin configuration ............................................................................. 15 pin description ............................................................................... 15 functional block diagram ...................................................................... 18 detailed description ........................................................................... 23 serial link signaling and data format ................................................... ........ 23 operating modes ................................................... ...................... 23 video/configuration link .................................................. ................. 23 single/double mode ................................................... .................... 24 hs/vs encoding ................................................... ...................... 24 error detection ................................................... ........................ 24 bus widths ................................................... ........................... 24 control channel and register programming .................................................. .... 28 forward control channel ................................................... ................ 28 reverse control channel ................................................... ................ 28 uart interface ................................................... ....................... 28 i 2 c interface ................................................... .......................... 28 remote-end operation ................................................... ................. 28 clock-stretch timing ................................................... ................... 28 packet-based i 2 c ................................................... ........................ 28 packet protocol summary ................................................... ............... 29 control-channel error detection and packet retransmission ...................................... 29 gpo/gpi control ................................................... ........................ 29 spread spectrum ................................................... ........................ 29 cable type configuration ................................................... .................. 29 crossbar switch ................................................... ......................... 29 video timing generator ................................................... ................... 29 shutdown/sleep modes .................................................. .................... 31 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 2 table of contents downloaded from: http:///
configuration link ................................................... ..................... 31 serialization disable ................................................... ................... 31 sleep mode ................................................... .......................... 31 power-down mode ................................................... ..................... 32 link startup procedure ................................................... .................... 32 register map ................................................................................ 33 gmsl register map ................................................... ...................... 33 applications information ........................................................................ 69 parallel interface ................................................... ......................... 69 bus data width .................................................. ........................ 69 bus data rates ................................................... ....................... 69 crossbar-switch programming ................................................... ........... 70 recommended crossbar-switch program procedure ............................................ 70 timing-generator programming ................................................... ............. 73 double-mode alignment ................................................... ................... 73 external high/low signal ................................................... ............... 73 align from hs or de .................................................. .................... 73 control-channel interfaces ................................................... ................. 73 i 2 c ................................................... ................................. 73 i 2 c bit rate ................................................... .......................... 73 software programming of device addresses ................................................... 74 i 2 c address translation ................................................... ................. 74 configuration blocking ................................................... .................. 74 cascaded/parallel devices .................................................. ............... 74 uart .................................................. ................................ 74 base mode ................................................... ........................... 74 uart timing ................................................... ......................... 74 uart-to-i 2 c conversion ................................................... ................ 76 uart bypass mode ................................................... ................... 77 device address ................................................... ....................... 77 spread spectrum ................................................... ........................ 77 manual programming of the spread-spectrum divider .............................................. 77 equation: .................................................. ............................. 77 board layout ................................................... ............................ 78 power-supply circuits and bypassing ................................................... ...... 78 high-frequency signals ................................................... ................. 78 esd protection ................................................... .......................... 78 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 3 table of contents (continued) downloaded from: http:///
compatibility with other gmsl devices .................................................. ....... 79 device configuration and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 internal input pulldowns ................................................... ................. 79 three-level configuration inputs ................................................... ......... 79 i 2 c/uart pullup resistors .................................................. ............... 80 ac-coupling capacitors ................................................... ................ 80 cables and connectors ................................................... ................. 80 prbs ................................................... .................................. 80 gpi/gpo ................................................... ............................... 80 fast detection of loss-of-lock ................................................... ........... 81 providing a frame sync (camera applications) ................................................. 81 entering/exiting sleep mode ................................................... ............... 81 typical application circuits ..................................................................... 82 ordering information .......................................................................... 82 revision history .............................................................................. 83 figure 1. serial-output parameters ............................................................... 18 figure 2. output waveforms at out+, out- ........................................................ 19 figure 3. single-ended output template .......................................................... 19 figure 4. worst-case pattern input ............................................................... 19 figure 5. parallel clock input requirements ........................................................ 19 figure 6. i 2 c timing parameters ................................................................. 20 figure 7. differential output template ............................................................. 20 figure 8. input setup and hold times ............................................................. 21 figure 9. gpi-to-gpo delay .................................................................... 21 figure 10. serializer delay ...................................................................... 22 figure 11. link startup time .................................................................... 22 figure 12. power-up delay ..................................................................... 23 figure 13. 24-bit mode serial-data format ......................................................... 25 figure 14. 27-bit high-bandwidth mode serial-data format ........................................... 26 figure 15. 32-bit mode serial-data format ......................................................... 27 figure 16. coax connection .................................................................... 29 figure 17. crossbar switch dataflow .............................................................. 30 figure 18. sync-signal format for video-timing generation .......................................... 30 figure 19. state diagram ....................................................................... 31 figure 20. crossbar-switch default mapping ....................................................... 72 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 4 list of figures table of contents (continued) downloaded from: http:///
figure 21. gmsl-uart data format for base mode ................................................. 75 figure 22. gmsl-uart protocol for base mode .................................................... 75 figure 23. sync byte (0x79) .................................................................... 75 figure 24. ack byte (0xc3) ..................................................................... 75 figure 25. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) ........ 76 figure 26. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 1) ........ 76 figure 27. human body model esd test circuit ..................................................... 78 figure 28. iec 61000-4-2 contact discharge esd test circuit ......................................... 78 figure 29. iso 10605 contact discharge esd test circuit ............................................ 78 table 1. reverse control-channel modes .......................................................... 28 table 2. link-startup procedure ................................................................. 31 table 3. input data-width selection .............................................................. 68 table 4. data-rate selection .................................................................... 68 table 5. crossbar output to serial link map (d23:0) ................................................. 69 table 6. crossbar output to serial link map (d31:24 and speci al packets) ............................... 70 table 7. legend .............................................................................. 71 table 8. timing-generator parameter restrictions ................................................... 72 table 9. output spread ........................................................................ 76 table 10. spread limitations .................................................................... 76 table 11. modulation coefficients and maximum sdiv setting s ........................................ 77 table 12. feature compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 13. three-level configuration input map ..................................................... 79 table 14. suggested connectors and cables for gmsl ............................................... 79 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 5 list of tables list of figures (continued) downloaded from: http:///
avdd to ep* ........................................................ -0.5v to +1.9v dvdd to ep* ........................................................ -0.5v to +1.9v iovdd to ep* ....................................................... -0.5v to +3.9v out+, out- to ep* .............................................. -0.5v to +1.9v all other pins to ep* ............................ -0.5v to (iovdd + 0.5v) out+, out- short circuit to ground or supply ........continuous continuous power dissipation, t a = +70c tqfn (derate 34.5 mw/c above +70c) ............. 2758.6mw operating temperature range .......................... -40c to +115c junction temperature ...................................................... +125c storage temperature range ............................ -40c to +150c soldering temperature (reflow) ....................................... +260c *ep connected to ic ground. 32-pin tqfn-ep package code t3255+8 outline number 21-0140 land pattern number 90-0013 single-layer board: junction-to-ambient thermal resistance ( ja ) 47 junction-to-case thermal resistance ( jc ) 1.7 four-layer board: junction-to-ambient thermal resistance ( ja ) 29 junction-to-case thermal resistance ( jc ) 1.7 package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 6 downloaded from: http:///
(v dvdd = v avdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), t a = -40c to +115c, ep connected to pcb ground, typical values are at v dvdd = v avdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units single-ended inputs (lccen, din_, pclkin, hs, vs, de, bws, dbl, him, ms, hven, pwdnb) high-level input voltage v ih 0.65 x v iovdd v low-level input voltage v il 0.35 x v iovdd v input current i in v in = 0 to v iovdd -20 +20 a three-level inputs (conf0, conf1) high-level input voltage v ih 0.7 x v iovdd v low-level input voltage v il 0.3 x v iovdd v mid-level input current i inm open or connected to a driver with output in high impedance (note 2) -10 +10 a input current i in high or low, pwdnb high or low -220 +220 a single-ended output (gpo) high-level output voltage v oh i oh = -2ma v iovdd - 0.2 v low-level output voltage v ol i ol = 2ma 0.2 v output short-circuit current i os v o = 0v, v iovdd = 3.0v to 3.6v -16 -35 -64 ma v o = 0v, v iovdd = 1.7v to 1.9v -3 -12 -21 uart/i 2 c and general-purpose i/os (rx/sda, tx/scl, gpio_) with open-drain outputs high-level input voltage v ih 0.7 x v iovdd v low-level input voltage v il 0.3 x v iovdd v input current i in v in = 0 to v iovdd (note 3), rx/sda, tx/scl -110 +5 a v in = 0 to v iovdd (note 3), gpio_ -80 +5 low-level open-drain output voltage v ol i ol = 3ma, v iovdd = 1.7v to 1.9v 0.4 v i ol = 3ma, v iovdd = 3.0v to 3.6v 0.3 input capacitance c in each pin (note 4) 10 pf dc electrical characteristics max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 7 downloaded from: http:///
(v dvdd = v avdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), t a = -40c to +115c, ep connected to pcb ground, typical values are at, v dvdd = v avdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units differential outputs (out+, out-) differential output voltage v od preemphasis off, high drive ( figure 1 ) 300 400 500 mv 3.3db preemphasis, high drive ( figure 2 ) 350 610 3.3db deemphasis, high drive ( figure 2 ) 240 425 change in v od between complementary output states v od 25 mv output offset voltage (v out+ + v out- )/2 = v os v os preemphasis off 1.1 1.4 1.56 v change in v os between complementary output states v os 25 mv output short-circuit current i os v out+ or v out- = 0v -60 ma v out+ or v out- = 1.9v 25 magnitude of differential output short-circuit current i osd v od = 0v 25 ma output-termination resistance (internal) r o from out+ or out- to avdd 45 54 63 reverse control-channel receiver outputs (out+, out-) high-switching threshold v chr legacy 27 mv high immunity 40 low-switching threshold v clr legacy -27 mv high immunity -40 single-ended serial outputs (out+ or out-) single-ended output voltage v o preemphasis off, high drive ( figure 3 ) 375 500 625 mv 3.3db preemphasis, high drive ( figure 2 ) 435 765 3.3db deemphasis, high drive ( figure 2 ) 300 535 output short-circuit current i os v out+ or v out- = 0v -69 ma v out+ or v out- = 1.9v 32 output-termination resistance (internal) r o from out+ or out- to avdd 45 54 63 dc electrical characteristics (continued) max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 8 downloaded from: http:///
(v dvdd = v avdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), t a = -40c to +115c, ep connected to pcb ground, typical values are at, v dvdd = v avdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units power supply supply current, worst-case pattern ( figure 4 ) i wcs f pclkin = 116mhz, hibw = 0, bws = 0, default register values, avdd + dvdd (1.9v) 64 90 ma f pclkin = 116mhz, hibw = 0, bws = 0, default register values, iovdd (3.6v) 1.8 2.7 f pclkin = 116mhz, hibw = 0, bws = 0, default register values, iovdd (1.9v) (note 4) 0.45 0.69 f pclkin = 116mhz, hibw = 1, bws = 0, default register values, avdd + dvdd (1.9v) 62 83 f pclkin = 116mhz, hibw = 1, bws = 0, default register values, iovdd (3.6v) 1.8 2.7 f pclkin = 116mhz, hibw = 1, bws = 0, default register values, iovdd (1.9v) (note 4) 0.45 0.69 f pclkin = 87mhz, bws = 1, default register values, avdd + dvdd (1.9v) 61 85 f pclkin = 87mhz, bws = 1, default register values, iovdd (3.6v) 1.4 2.0 f pclkin = 87mhz, bws = 1, default register values, iovdd (1.9v) (note 4) 0.37 0.61 sleep-mode supply current i ccs wake-up receiver enabled 40 100 a power-down supply current i ccz pwdnb = low 15 70 a esd protection out+, out- (note 5) v esd human body model, r d = 1.5k, c s = 100pf 8 kv iec 61000-4-2, r d = 330, c s = 150pf, contact discharge 8 iec 61000-4-2, r d = 330, c s = 150pf, air discharge 15 iso 10605, r d = 2k, c s = 330pf, contact discharge 8 iso 10605, r d = 2k, c s = 330pf, air discharge 15 all other pins (note 6) v esd human body model, r d = 1.5k, c s = 100pf 4 kv dc electrical characteristics (continued) max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 9 downloaded from: http:///
(v dvdd = v avdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), t a = -40c to +115c, ep connected to pcb ground, typical values are at, v dvdd = v avdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units parallel clock input (pclkin) clock frequency f pclkin bws = 0, hibw = 0, single input 16.66 58 mhz bws = 0, hibw = 1, single input 36.66 58 bws = 1, single input 12.5 43.5 bws = 0, hibw = 0, double input 33.32 116 bws = 0, hibw = 1, double input 73.33 116 bws = 1, double input 25 87 clock duty cycle dc t high /t t or t low /t t (note 4, figure 5 ) 35 50 65 % clock transition time t r, t f (note 4, figure 5 ) 4 ns clock jitter t j 1.74gbps bit rate, 300khz sinusoidal jitter (note 4) 800 ps i 2 c/uart port timing i 2 c/uart bit rate 9.6 1000 kbps output rise time t r 30% to 70%, c l = 10pf to 100pf, 1k pullup to iovdd 20 150 ns output fall time t f 70% to 30%, c l = 10pf to 100pf, 1k pullup to iovdd 20 150 ns i 2 c timing ( figure 6 ) scl clock frequency f scl low f scl range: (i2cmstbt = 010, i2cslvsh = 10) 9.6 100 khz mid f scl range: (i2cmstbt 101, i2cslvsh = 01) > 100 400 high f scl range: (i2cmstbt = 111, i2cslvsh = 00) > 400 1000 start condition hold time t hd:sta f scl range, low 4 s f scl range, mid 0.6 f scl range, high 0.26 low period of scl clock t low f scl range, low 4.7 s f scl range, mid 1.3 f scl range, high 0.5 high period of scl clock t high f scl range, low 4 s f scl range, mid 0.6 f scl range, high 0.26 repeated start condition setup time t su:sta f scl range, low 4.7 s f scl range, mid 0.6 f scl range, high 0.26 ac electrical characteristics max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 10 downloaded from: http:///
(v dvdd = v avdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), t a = -40c to +115c, ep connected to pcb ground, typical values are at, v dvdd = v avdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units data hold time t hd:dat f scl range, low 0 ns f scl range, mid 0 f scl range, high 0 data setup time t su:dat f scl range, low 250 ns f scl range, mid 100 f scl range, high 50 setup time for stop condition t su:sto f scl range, low 4 s f scl range, mid 0.6 f scl range, high 0.26 bus-free time t buf f scl range, low 4.7 s f scl range, mid 1.3 f scl range, high 0.5 data valid time t vd:dat f scl range, low 3.45 s f scl range, mid 0.9 f scl range, high 0.45 data valid-acknowledge time t vd:ack f scl range, low 3.45 s f scl range, mid 0.9 f scl range, high 0.45 pulse width of spikes suppressed t sp f scl range, low 50 ns f scl range, mid 50 f scl range, high 50 capacitive load of each bus line c b note 4 100 pf switching characteristics (note 4) differential/single-ended output rise/fall time t r, t f 20% to 80%, v od , 400mv differential r l = 100, 500mv single-ended r l = 50, serial bit rate = 1.74gbps 250 ps total serial-output jitter (differential output) t tsoj1 1.74gbps prbs, measured at v od = 0v differential, preemphasis disabled ( figure 7 ) 0.25 ui deterministic serial-output jitter (differential output) t dsoj2 1.74gbps prbs, measured at v od = 0v differential, preemphasis disabled ( figure 7 ) 0.15 ui total serial-output jitter (single-ended output) t tsoj1 1.74gbps prbs, measured at v o /2, preemphasis disabled ( figure 3 ) 0.25 ui deterministic serial-output jitter (single-ended output) t dsoj2 1.74gbps prbs, measured at v o /2, preemphasis disabled ( figure 3 ) 0.15 ui parallel data-input setup time t set ( figure 8 ) 2 ns ac electrical characteristics (continued) max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 11 downloaded from: http:///
note 1: limits are 100% production tested at t a = +115c. limits over the operating temperature range are guaranteed by design and characterization, unless otherwise noted. note 2: to provide a mid-level voltage, leave the input open; or, if driven, put the driver in high-impedance state. high-impedance leakage current must be less than 10a. note 3: i in min is due to voltage drop across the internal pullup resistor. note 4: not production tested. guaranteed by design. note 5: specified pin to ground . note 6: specified pin to all supply/ground . note 7: measured in serial link bit times. bit time = 1/(30 x f pclkin ) for bws = 0; bit time = 1/(40 x f pclkin ) for bws = 1. (v dvdd = v avdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 1% (differential), t a = -40c to +115c, ep connected to pcb ground, typical values are at, v dvdd = v avdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units parallel data input hold time t hold ( figure 8 ) (note 4) 1 ns gpi-to-gpo delay t gpio deserializer gpi to serializer gpo ( figure 9 ) 350 s serializer delay t sd spread spectrum enabled ( figure 10 ) (notes 4, 7) 2065 bits spread spectrum disabled ( figure 10 ) (notes 4, 7) 1095 link start time t lock ( figure 11 ) 2 ms power-up time t pu ( figure 12 ) 7 ms ac electrical characteristics (continued) max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 12 downloaded from: http:///
(v avdd = v dvdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) 40 45 50 55 60 65 70 75 15 35 55 75 95 115 supply current (ma) pixel clock frequency (mhz) supply current vs. pixel clock frequency (bws = 0, hibw = 1) toc02 prbs on, coax mode, ss off pe off pe = 0xb to 0xf pe = 0x1 to 0x4 dbl = 1 dbl = 0 40 45 50 55 60 65 70 75 15 35 55 75 95 115 supply current (ma) pixel clock frequency (mhz) supply current vs. pixel clock frequency (bws = 0, hibw = 0) toc01 prbs on, coax mode, ss off pe off pe = 0xb to 0xf pe = 0x1 to 0x4 dbl = 1 dbl = 0 40 45 50 55 60 65 70 10 30 50 70 90 supply current (ma) pixel clock frequency (mhz) supply current vs. pixel clock frequency (bws = 1, hibw = 0) toc03 prbs on, coax mode, ss off pe off pe = 0xb to 0xf pe = 0x1 to 0x4 dbl = 1 dbl = 0 40 45 50 55 60 65 15 35 55 75 95 115 supply current (ma) pixel clock frequency (mhz) supply current vs. pixel clock frequency (bws = 0, hibw = 0) toc04 prbs on, coax mode, pe off all spread values dbl = 1 dbl = 0 40 45 50 55 60 65 15 35 55 75 95 115 supply current (ma) pixel clock frequency (mhz) supply current vs. pixel clock frequency (bws = 0, hibw = 1) toc05 prbs on, coax mode, pe off all spread values dbl = 1 dbl = 0 40 45 50 55 60 65 10 30 50 70 90 supply current (ma) pixel clock frequency (mhz) supply current vs. pixel clock frequency (bws = 1, hibw = 0) toc06 prbs on, coax mode, pe off all spread values dbl = 1 dbl = 0 typical operating characteristics maxim integrated 13 www.maximintegrated.com max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
(v avdd = v dvdd = v iovdd = 1.8v, t a = +25c, unless otherwise noted.) -80 -70 -60 -50 -40 -30 -20 -10 0 10 18.5 19.0 19.5 20.0 20.5 21.0 21.5 supply current (ma) pixel clock frequency (mhz) output power spectrum vs. pclk frequency (various spread) toc07 f pclkin = 20mhz 4% spread 2% spread 1% spread 0.5% spread no spread -80 -70 -60 -50 -40 -30 -20 -10 0 10 47 48 49 50 51 52 53 supply current (ma) pixel clock frequency (mhz) output power spectrum vs. pclk frequency (various spread) toc08 f pclkin = 50mhz 4% spread 2% spread 1% spread 0.5% spread no spread 0 10 20 30 40 50 60 70 0 5 10 15 20 25 pixel clock frequency (mhz) stp cable length (m) maximum pixel clock frequency vs. stp cable length (ber < 10 - 10 ) toc09 ber can be as low as 10 - 12 for cable lengths less than 15m aeq no eq 4.3db eq 9.7db eq no pe, dbl = 0 0 10 20 30 40 50 60 70 0 10 20 30 40 pixel clock frequency (mhz) coax cable length (m) maximum pixel clock frequency vs. coax cable length (ber < 10 - 10 ) toc10 ber can be as low as 10 - 12 for cable lengths less than 15m aeq no eq 4.3db eq no pe, dbl = 0 100mv/div toc11 200ps/div serial link switching pattern with 4.4db preemphasis (1.5gbps, 10m stp cable) 50mv/div toc12 200ps/div serial link switching pattern with 3.3db preemphasis (1.5gbps, 20m coax cable) typical operating characteristics (continued) maxim integrated 14 www.maximintegrated.com max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
pin name function ref supply type power 5, 22 avdd 1.8v analog power supply. bypass avdd to ep with 0.1f, and 0.001f capacitors as close as possible to the device with the smaller value capacitor closest to avdd. power 12 iovdd i/o supply voltage. 1.8v to 3.3v logic i/o power supply. bypass iovdd to ep with 0.1f and 0.001f capacitors as close as possible to the device with the smaller value capacitor closest to iovdd. power 29 dvdd 1.8v digital power supply. bypass dvdd to ep with 0.1f, and 0.001f capacitors as close as possible to the device with the smaller value capacitor closest to dvdd. power ep exposed pad. ep is internally connected to device ground. must connect ep to the pcb ground plane through a via array for proper thermal and electrical performance. power max96705 tqfn (5 mm x 5 mm ) top view din7 din9 avdd din10/gpio2 din11/gpio3 din6 rx/sda out+ out- tx/scl/dbl conf1 conf0 1 2 din2 4 5 6 7 dvdd din3 gpio1/bws gpo/him iovdd din15/vs din8 avdd 3 din4 din14/hs din5 din13/gpio5/de + din1 ms/hven din0 pwdnb din12/gpio4 lccen 8 pclkin 16 15 14 13 12 11 10 9 17 18 19 20 21 22 23 24 26 25 27 28 29 30 31 32 pin conigurationpin description max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 15 downloaded from: http:///
pin name function ref supply type high-speed digital single function 1 din6 parallel data input. internal pulldown to ep. iovdd digital 2 din7 parallel data input. internal pulldown to ep. iovdd digital 3 din8 parallel data input. internal pulldown to ep. iovdd digital 4 din9 parallel data input. internal pulldown to ep. iovdd digital 25 pclkin parallel clock input with internal pulldown to ep. latches parallel data inputs and provides the pll reference clock. iovdd digital 26 din0 parallel data input. internal pulldown to ep. iovdd digital 27 din1 parallel data input. internal pulldown to ep. iovdd digital 28 din2 parallel data input. internal pulldown to ep. iovdd digital 30 din3 parallel data input. internal pulldown to ep. iovdd digital 31 din4 parallel data input. internal pulldown to ep. iovdd digital 32 din5 parallel data input. internal pulldown to ep. iovdd digital multifunction 6 din10/gpio2 parallel data input/gpio. defaults to parallel data input on power- up. parallel data input has internal pulldown to ep. gpio2 has an open-drain input/output with internal 60k pullup to iovdd. iovdd digital 7 din11/gpio3 parallel data input/gpio. defaults to parallel data input on power- up. parallel data input has internal pulldown to ep. gpio3 has an open-drain input/output with internal 60k pullup to iovdd. iovdd digital 8 din12/gpio4 parallel data input/gpio. defaults to parallel data input on power- up. parallel data input has internal pulldown to ep. gpio4 has an open-drain input/output with internal 60k pullup to iovdd. iovdd digital 9 din13/ gpio5/de parallel data input/gpio/data enable with internal pulldown to ep. defaults to parallel data input on power-up. gpio5 has an open- drain input/output with internal 60k pullup to iovdd. data enable input in high-bandwidth mode. iovdd digital 10 din14/hs parallel data input/horizontal sync with internal pulldown to ep. defaults to parallel data input on power-up. defaults to horizontal- sync input when hs/vs encoding is enabled, or when in high- bandwidth mode. iovdd digital 11 din15/vs parallel data input/vertical sync with internal pulldown to ep. defaults to parallel data input on power-up. defaults to vertical- sync input when hs/vs encoding is enabled, or when in high- bandwidth mode. iovdd digital multifunction coniguration (from lccen) 14 gpio1/bws gpio1/bus-width select input. function is determined by the state of lccen. gpio1 (lccen = high): open-drain, general-purpose input/output with internal 60k? pullup to iovdd. bws (lccen = low): input with internal pulldown to ep. set bws = low for 22-bit input latch. set bws = high for 30-bit input latch. iovdd digital pin description (continued) max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 16 downloaded from: http:///
pin name function ref supply type 15 ms/hven mode-select/hs and vs encoding enable input with internal pulldown to ep. function is determined by the state of lccen. ms (lccen high): set ms low to select base mode. set ms high to select bypass mode. hven: (lccen low): set hven = high to enable hs/vs encoding. set hven = low to disable hs/vs encoding. iovdd digital 17 lccen local control-channel enable input with internal pulldown to ep. lccen = high enables the control-channel interface pins. lccen = low disables the control-channel interface pins and selects an alternate function on the indicated pins. iovdd digital 24 tx/scl/dbl transmit/serial clock/double mode. function is determined by the state of lccen. tx/scl (lccen = high): input/output with internal 30k? pullup to iovdd. in uart mode, tx/scl is the tx output of the serializer's uart. in i 2 c mode, tx/scl is the scl input/output of the serializer's i 2 c master/slave. tx/scl has an open-drain driver and requires a pullup resistor. dbl (lccen = low): input with internal pulldown to ep. set dbl = high to use double-input mode. set dbl = low to use single-input mode. iovdd digital coniguration and interface 13 gpo/him general-purpose output/high-immunity mode input with internal pulldown to ep. him is latched at power-up or when resuming from power-down mode (pwdnb = low), and switches to gpo output automatically after power-up. connect him to iovdd with a 30k? resistor to set high, or leave open to set low. highimm can be programmed to a different value after power-up. highimm in the deserializer must be set to the same value. gpo output follows the state of the gpi (or int) input on the gmsl deserializer. gpo is low upon power-up or when pwdnb is low. iovdd digital 16 pwdnb active-low, power-down input with internal pulldown to ep. to reduce power consumption, set pwdnb low to enter power- down mode. iovdd digital 18 conf0 coniguration 0. three-level coniguration input ( table 13 ). conf0 pin value is latched at power-up, or when resuming from power-down mode. iovdd 3-level 19 conf1 coniguration 1. three-level coniguration input ( table 13 ). conf1 pin value is latched at power up or when resuming from power-down mode. iovdd 3-level 20 out- inverting coax/twisted-pair serial output. digital 21 out+ noninverting coax/twisted-pair serial output digital 23 rx/sda receive/serial data. input/output with internal 30k? pullup to iovdd. in uart mode, rx/sda is the rx input of the serializer's uart. in i 2 c mode, rx/sda is the sda input/output of the serializer's i 2 c master/slave. rx/sda has an open-drain driver and requires a pullup resistor. iovdd digital pin description (continued) max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 17 downloaded from: http:///
figure 1. serial-output parameters parallel to serial sspll scramble/ hven/crc/ parity/ encode fifo control vs hs fcc pclkin din14/hs reverse control channel video max96705 out+ out- clkdiv din15/vs din[9:0] cml tx sync uart/i 2 c tx/ scl/ dbl rx/ sda gpo/him pwdnb ms/hven conf[1:0] crosspoint switch any 32 inputs to any 22/24/30 outputs 16 x 1 latch (single) or 16 x 2 latch (dbl) lccen gpio din13/gpio5/de din12/gpio4 din11/gpio3 din10/gpio2 4 4 timing generator gpio1/bws dbl him bws rx functional block diagram out- v od v os gnd r l /2 r l /2 out+ out- out+ (out+) - (out-) v os(-) v os(+) ((out+) + (out-))/2 v os(-) v od(-) v od(-) v od = 0v dv os = | v os(+) - v os(-) | dv od = | v od(+) - v od(-) | v od (+) max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 18 downloaded from: http:///
figure 2. output waveforms at out+, out- figure 3. single-ended output template figure 4. worst-case pattern input figure 5. parallel clock input requirements out+out- v os v od(p) v od(d) serial-bit time out+ or out- v o /2 v o /2 v o v o pclkin note: pclkin programmed for rising latch edge. din_ v il max t high t low t t t r t f v ih min pclkin max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 19 downloaded from: http:///
figure 6. i 2 c timing parameters figure 7. differential output template protocol scl sda start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) t su;sta v iovdd x 0.7 v iovdd x 0.7 v iovdd x 0.3 v iovdd x 0.3 t low t high t buf t hd;sta t r t sp t f t su;dat t hd;dat t vd;dat t vd;ack t su;sto 1/f scl 800mv p-p t tsoj1 2 t tsoj1 2 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 20 downloaded from: http:///
figure 8. input setup and hold times figure 9. gpi-to-gpo delay v ih min v ih min v ih min v il max v il max v il max pclkin din_ t hold t set note: pclkin programmed for rising latching edge. t gpio t gpio v oh_min v ol_max v ih_min v il_max deserializer gpi serializer gpo max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 21 downloaded from: http:///
figure 10. serializer delay figure 11. link startup time t sd first bit last bit n n+3 expanded time scale n+4 n n+1 n+2 n-1 din_ pclkin out+/- serial link inactive serial link active channel disabled reverse control channel enabled t lock 500 f s pclkin reverse control channel available pwdnb must be high max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 22 downloaded from: http:///
detailed description the max96705 is a compact device with features especially suited for automotive camera applications. the device operates at a variety of input widths and word rates up to a total serial-data rate up to 1.74gbps. high- bandwidth mode offers a 116mhz parallel clock rate with 12 bits of video data and 2 bits of sync (hs/vs) data. an embedded 9.6kbps to 1mbps control channel programs the serializer, deserializer, and any attached uart or i 2 c peripherals. to promote safety applications, the device features crc protection of video and control data. in addition, control-channel retransmission and high-immunity modes reduce the effects of bit errors corrupting communica - tion. preemphasis and a prbs tester allow for in-system evaluation and optimization of the link quality. this max96705 operates over the -40c to +115c automotive temperature range.serial link signaling and data format the serializer scrambles the input parallel data and combines this with the forward control data. the data is then encoded for transmission and output as a single- serialized bitstream at several times the input word rate (depending on bus width). the deserializer receives the serial data and recovers the clock signal. the data is then deserialized, decoded, and descrambled into parallel out - put data and forward control data. operating modes the gmsl devices are configurable to operate in many modes depending on the application. these modes allow for a more efficient use of serial bandwidth. most of these settings are set during system design, and are configured using the external configuration pins or through register bits. video/coniguration link in normal operation, the serializer runs in video link mode (serializer seren = 1) with video data and control data sent across the serial link. set seren = 0 in the serializer to turn off serialization. the serializer powers up in video link mode and requires a valid pclk for operation. a configuration link is available to set up the serializer, deserializer, and peripherals when pclk is not available. set seren = 0 and clink = 1 in the serializer to enable the configuration link (seren = 1 forces the serializer into video link mode). once pclk has been established, turn on the video link (seren = 1). by default, video link mode requires a valid pclk for operation. set auto_clink bit = 1 and seren = 1 in the serializer to have the device automatically switch between the video link and configuration link whenever pclk is not present. figure 12. power-up delay pwdnb powered down v ih1 t pu reverse control channel disabled 500s pclkin powered up, serial link inactive powered up, serial link active reverse control channel enabled www.maximintegrated.com maxim integrated 23 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
single/double mode single-/double-mode operation configures the available 1.74gbps bandwidth into a variety of widths and word rates. single-mode operation is compatible with all gmsl devices and serializers, yielding one parallel word for each serial word. double mode serializes two half-width parallel words for each serial word, resulting in a 2x increase in the parallel word rate range (compared to single mode). set dbl = 0 for single-mode operation and dbl = 1 for double-mode operation. hs/vs encoding by default, gmsl assigns a video bit slot to hsync, vsync, and de (if used). with hs/vs encoding, the device instead encodes special packets to sync signals to free up additional video bit slots. hs/vs encoding is on by default when the device is in high-bandwidth mode (hibw = 1). de is encoded only when hibw = 1 and de_en = 1. set hven = 1 to turn on hs/vs encoding when hibw = 0 (de, if enabled, uses up a video bit). hs/vs encoding requires that hsync, vsync, and de (if used) remain high during the active video and low during the blanking period. use hs/vs inversion when using reverse-polarity sync signals. error detection the serial link's 8b/10b encoding/decoding and 1-bit parity detect bit errors that occur on the serial link. an optional 6-bit crc check is available at the expense of 6 video bits (when hibw = 0). to activate 6-bit crc mode, set pxl_crc = 1 in the remote-side device first, then in the local-side device. when using 6-bit crc mode, the available internal bus width is reduced by 6 bits in single- input mode (dbl = 0) and 3 bits in double-input mode (dbl = 1). note that the input bus width may already have been reduced due to pin availability of the serializer or deserializer; thus, the reduction of bandwidth from crc may not be visible (see table 3 ). an additional 32-bit video line crc is available by setting line_crc_en = 1. when enabled, the serializer calculates the 32-bit crc of the video line and sends this information during the blanking period. the deserializer compares the received crc with the video line data. the deserializer's line_crc_err bit latches when a crc error is detected. line_crc_err clears when read. bus widths the serial link has multiple bus-width settings that determine the parallel bus width and the resulting parallel word rate. the serial link operates to a maximum serial bit rate of 1.74gbps. the bws bit determines if each serial packet is 30 or 40 bits long, which translates to a maximum serial packet rate (and resulting maximum parallel word rate) of 58mhz or 43.5mhz when bws = 0 or 1 respectively. encoding translates the 24, 27, or 32 parallel bits into 30- or 40-bit serial packets. one bit is used for parity, while a second is reserved for the control channel. an additional 6 bits are used during optional 6-bit crc. in addition, double mode splits the remaining word size in half, if used. the remaining bits can be used for video bits (minus any sync bits if h/v encoding is not used) the following modes list the internal bus widths. the number of available input and output pins may limit the actual bus width available. 24-bit mode ( figure 13 ) when bws = 0 and hibw = 0, the 30-bit serial packet corresponds with three 8b/10b symbols representing 24 bits (24-bit mode). after the parity and control channel, this leaves 16/22 bits of video data if crc is/or is not used (single mode), or 8/11 bits of video data if crc is/or is not used (double mode). 27-bit high-bandwidth mode ( figure 14 ) when bws = 0 and hibw = 1 (high-bandwidth mode), the 30-bit serial packet represents three 9b/10b symbols representing 27 bits. after the parity and control channel, this leaves 19/25 bits of video data if crc is/or is not used (single mode), or 9/12 bits of video data if crc is/or is not used (double mode). 32-bit mode ( figure 15 ) when bws = 1, the 40-bit serial packet corresponds with four 8b/10b symbols representing 32 bits (32-bit mode). after parity and control channel, this leaves 24/30 bits of video data if crc is/or is not used (single mode), or 12/15 bits of video data if crc is/or is not used (double mode). www.maximintegrated.com maxim integrated 24 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
figure 13. 24-bit mode serial-data format 24-bit mode packet parity- check bit fcc pcb d0 d1 d21 d20 d19 d18 d17 serial data no pxl_crc rx/ sda tx/ scl uart/i 2 c forward control-channel bit d0 d1 d21 d0 d1 d15 d21 d20 d19 d18 d17 2 bits 16 video bits d16 d15 22 bits 22 video bits d16 6 pxl_crc bits pxl_crc on pxl_crc dbl = 0 d0 d1 d21 22 video bits* dbl = 1 d0 d1 d10 d11 d12 d21 11 x 2 video bits* d0 d1 d15 16 video bits* d0 d1 d7 d8 d9 d15 8 x 2 video bits* dbl = 0 dbl = 1 no pxl_crc, dbl = 0 58mhz (max) no pxl_crc, dbl = 1 116mhz (max) pxl_crc on, dbl = 0 58mhz (max) pxl_crc on, dbl = 1 116mhz (max) *internal bits. input/output pin availability may limit the external bus width. max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 25 downloaded from: http:///
figure 14. 27-bit high-bandwidth mode serial-data format 27-bit mode packet parity- check bit fcc pcb d0 d1 d21 d20 d19 d18 d17 serial data no pxl_crc rx/ sda tx/ scl uart/i 2 c forward control-channel bit d0 d1 d24 d0 d1 d15 d24 d23 d22 d18 d17 2 bits 19 video bits d16 d15 25 bits 25 video bits d16 6 pxl_crc bits pxl_crc on pxl_crc dbl = 0 d0 d1 d24 25 video bits* dbl = 1 d0 d1 d11 d12 d13 d23 12 x 2 video bits* d0 d1 d18 19 video bits* d0 d1 d8 d9 d10 d17 9 x 2 video bits* dbl = 0 dbl = 1 no pxl_crc, dbl = 0 58mhz (max) no pxl_crc, dbl = 1 116mhz (max) pxl_crc on, dbl = 0 58mhz (max) pxl_crc on, dbl = 1 116mhz (max) d24 d23 d22 d18 d24 *internal bits. input/output pin availability may limit the external bus width. max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 26 downloaded from: http:///
figure 15. 32-bit mode serial-data format 32-bit mode packet parity- check bit fcc pcb d0 d1 d24 d23 d29 d28 d27 serial data no pxl_crc rx/ sda tx/ scl uart/i 2 c forward control-channel bit d0 d2 d29 d0 d2 d23 d29 d28 d27 d26 d25 2 bits 24 video bits d26 d25 30 bits 30 video bits d24 6 pxl_crc bits pxl_crc on pxl_crc d0 d1 d29 30 video bits* d0 d1 d14 d15 d16 d29 15 x 2 video bits* d0 d1 d23 24 video bits* d0 d1 d11 d12 d13 d23 12 x 2 video bits* dbl = 0 dbl = 1 dbl = 0 dbl = 1 no pxl_crc, dbl = 0 43.5mhz (max) no pxl_crc, dbl = 1 87mhz (max) pxl_crc on, dbl = 0 43.5mhz (max) pxl_crc on, dbl = 1 87mhz (max) *internal bits. input/output pin availability may limit the external bus width. max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 27 downloaded from: http:///
x = dont care. control channel and register programming the control channel sends information across the serial link for control of the serializer, deserializer, and any attached peripherals. the control channel is multiplexed onto the serial link and is available with or without the video channel. forward control channel control data sent from the serializer to the deserializer is sent on the forward control channel. the data is encoded as one of the serial bits in the forward high-speed link. after deserialization, the forward control-channel data is extract - ed from the serial link. the forward control-channel band - width exceeds the maximum external control data rate, and all data sent on the forward control channel appears on the remote side after transmission delay of a few bit times. reverse control channel control data sent from the deserializer to the serial - izer is sent on the reverse control channel. the data is encoded as a series of 1s pulses, with a maximum raw data rate of 1mbps. high-immunity mode is available to increase the robustness of the reverse control channel at a reduced raw bit rate of 500kbps. in table 1 , setting the rev_fast bit = 1 increases this rate back to 1mbps. in i 2 c mode, when the input data rate (after encoding) exceeds the reverse data rate, the input clock is held through clock stretching to slow the external clock to match the internal bit rate. uart interface the uart interface, compatible with all gmsl devices, sends commands from device to device through several uart packets. two modes are available: base mode and bypass mode. base mode is used to communicate with the serializer, deserializer, and to i 2 c peripherals using uart-to-i 2 c translation. bypass mode allows for full-duplex uart communication to peripherals using any uart protocol. i 2 c interface the serial link connects the serializer and deserializer i 2 c interfaces together through the control channel. when an i 2 c master sends a command to one side of the link (local side) the control channel forwards this information to and from the other side of the link (remote side), allow - ing a single microcontroller to configure the serializer, deserializer, and peripherals. the microcontroller can be located on the serializer side (display applications) and the deserializer side (camera applications). dual micro - controller operations are supported as long as a software- arbitration method is used. the serial link assumes that only one microcontroller is talking at any given time. remote-end operation when an i 2 c master initiates communication on the local slave device (the serializer/deserializer directly connected to the master), the remote-side device acts as a master device that sends data forwarded from the local-side device, and forwards any data received from peripher - als attached to the remote-side device. this remote- side master device operates according to the timing settings in the i 2 c master setting register. set the master settings to match the timing settings used by the external microcontroller. clock-stretch timing the i 2 c interface uses clock stretching to allow time for data to be forwarded across the serial link. the master microcontroller, along with any attached peripherals, must accept clock stretching of the gmsl devices. packet-based i 2 c a packet-based control channel is available for enhanced error handling of the control channel. this control- channel method handles simultaneous gpi/gpo and i 2 c transmission, along with error detection and retrans - mission. him pin setting revfast bit reverse control-channel mode maximum uart/i 2 c bit rate (kbps) low x legacy reverse control-channel mode (compatible with all gmsl devices) 1000 high 0 high-immunity mode 500 1 fast high-immunity mode (requires hibw = 0, serial-data rate > 1.25gbps) 1000 table 1. reverse control-channel modes www.maximintegrated.com maxim integrated 28 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
packet protocol summarythe packet-based control channel uses a synchronous, symbol-based system to send data across the control channel. data to be sent across the control channel is split into symbols and stored in a transmit queue and then sent across the link. if both gpi and i 2 c data needs to be sent (e.g., when gpi transitions during an i 2 c transmis - sion), the symbols from both commands are combined in the queue. if the transmit queue is empty, idle pack - ets are sent across the link to maintain control-channel lock. received i 2 c packets are output as determined by the microcontroller scl rate (local device) or the pro - grammed master bit rate (remote device). the device holds scl low (clock stretch) until data has been received from the remote-side device. control-channel error detection and packet retransmission when the packet-based control channel is used, all pack - ets are checked for errors through crc. using 1, 5, or 8 bits, crc detects 1, 3, or 4 random bit errors in a packet. the transmitter retransmits packets whenever an error is detected. the transmitter sets a flag if a number of retries exceed a programmed threshold. the receiver filters out packets with errors. gpo/gpi control gpo on the serializer follows gpi transitions on the dese - rializer. this gpo/gpi function can be used to transmit signals such as a frame sync in a surround-view cam - era system (see the providing a frame sync (camera applications) section). optionally, gpo can be set directly by register bits.spread spectrum the serializer contains a programmable spread-spectrum output to lower emission levels by spreading the clock- frequency peaks across a frequency spectrum. in addition, the serializer and deserializer can track a spread input clock, eliminating the need for multiple spread clocks. cable type coniguration the driver output is programmable for two kinds of cable,100 twisted pair and 50 coax (contact the factory for devices compatible with 75 cables). in coax mode, connect out+ to in+ of the deserializer. leave the unused in_ pin unconnected, or connect it to ground through 50, and a capacitor for increased power-supply rejection. connect out- to v dd through a 50 resistor ( figure 16 ). crossbar switch the crossbar switch routes data between the parallel input/output and the serdes. the anything-to-anything routing assures the mapping between the video source and destination. for each crossbar output (xbo_) an input multiplexer selects from the available crossbar inputs (xbi_) using the crossbar_ register bits ( figure 17 ). multiple crossbar outputs can use the same crossbar input. by default, the sync signals share the same inputs as the msbs of the video data. video timing generator the serializer includes a programmable video timing generator to generate/retime the input sync signals. the timing generator can be used to modify a camera's input timing, filter out glitches in the sync signals, or to reduce the number of required input sync signals. each sync signal can be individually retimed or left unmodified. several registers determine the length of the timing parameters (in pclk cycles) shown in figure 18 . timing parameters include high/low period length, line count, and delay from the input vs signal. the timing generator uses three different trigger modes, tracking, single trigger, and autorun. tracking mode looks at the input vsync and locks once it receives three consecutive identical vsync signals. the tracker then continues to output the same identical signal, erasing any glitches that may appear on vsync. the tracker attempts to relock to a new signal if three consecutive input wave - forms do not match the locked signal. single trigger gen - erates one generated frame for each input vsync edge. autorun generates a new frame at the rate determined by the vsync high/low period. if a new vsync signal appears before a frame is complete in either single trig - ger or autorun modes, a new frame immediately starts, cutting the previous frame short. figure 16. coax connection out+ out- in+ optional componentsfor increased power-supply rejection in- avdd 50 ? gmsl deserializer gmsl serializer www.maximintegrated.com maxim integrated 29 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
figure 18. sync-signal format for video-timing generation figure 17. crossbar switch dataflow de out de_h de_cnt (pulse count) de_l hs out hs_h hs_cnt (pulse count) hs_l vs_h vs_out vs_in vs_dly hs_dly de_dly vs_l low input xbi0 : din14/hs din15/vs din9 din13 din12 din11 din10 din0 din1 xbi1 xbi9 xbi10 xbi11 xbi12 xbi13 xbi14 xbi15 xbi16 : din14/hs din9 din13 din12 din11 din10 din0 din1 xbi17 xbi25 xbi26 xbi27 xbi28 xbi29 xbi30 high input (dbl = 1 only) :: xbi0 xbi1 xb30 xb31 : : crossbar_ 5 force_mux_ 0 1 0 invert_mux_ 0 1 xbo_ 34 switches xbo0 xbo1 d0 d1 : : xbo29 xbo30 d29 d30 xbohs hs xbovs vs xbode de data sync pclk din15/vs xbi15 hs/de* hs/de hs/de hi_lo* *register settings decide if hs, de, or hi_lo determines the high/low input timing. din14/hs xbi30 xbi14 xbi15 xbi30 xbi14 din13 xbi29 xbi13 din1 xbi17 xbi1 din0 xbi16 xbi0 xbi29 xbi13 xbi17 xbi1 xbi16 xbi0 ... ... : : xbi31 xbi31 www.maximintegrated.com maxim integrated 30 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
shutdown/sleep modes several sleep and shutdown modes are available when full operation is not needed. coniguration link when the high-speed video link is not needed, or unavail - able, a configuration link can be used in its place. in configuration link mode, the parallel digital input/output is disabled, the lock pin remains low, and the serial link internally generates its own clock to allow full operation of the control channel (uart/i 2 c and gpio). serialization disablewhen the serial link is not needed, such as when down - stream devices are powered off, the user can disable serialization. in this mode, all forward communication is shut down. the user can reenable serialization either locally, or through the reverse channel. sleep mode to reduce power consumption further, the devices can be put into sleep mode. in this mode, all registers keep their programmed values, and all functions in the device are powered down except for the wake-up detectors on the local control interface, and the serial link. any activity seen by the wake-up detectors temporarily turns on the control-channel interface. during this time, a microcon - troller can command the device to exit sleep mode. see the shutdown/sleep modes section . figure 19. state diagram all states power down or power off power on idle config link started config link operating program registers video link locking video link operating video link prbs test pwdnb = low or power off clinken = 1 clinken = 0 or seren = 1 clinken = 0 or seren = 1 pwdnb = high, power on config link locked config link unlocked video link unlocked video link locked prbsen = 1 prbsen = 0 seren = 0 or no pclkin seren = 0 or no pclkin seren = 1, pclkin running wakeup sleep sleep = 1 for > 8ms link wakeup signal sleep = 1 sleep = 0, seren = 1 sleep = 0, seren = 0 www.maximintegrated.com maxim integrated 31 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
power-down modethe lowest power consumption mode is power-down mode. in this mode, all functions are powered down, and all register values are lost. link startup procedure table 2 lists the startup procedure for image-sensing applications. the control channel is available after the video link or the configuration link is established. if the deserializer powers up after the serializer, the control channel becomes unavailable until 2ms after power-up. no. c serializer deserializer c connected to deserializer set coniguration inputs set coniguration inputs 1 powers up (wait t pu ). powers up and loads default settings. establishes video link when valid pclk is available. powers up and loads default settings. locks to video link signal if available. 1a if no pclk, programs clinken, seren, and/or autoclink bits. wait 5ms after each command. establishes coniguration link. locks to coniguration link if available. 1b if not locked, sets any additional coniguration bits that are mismatched between the serializer and deserializer (e.g., bws, cx/tp). wait 5ms for lock after each command. coniguration changed. reestablishes coniguration/video link if needed. coniguration changed. locks to coniguration/video link. 2 sets register 0x07 coniguration bits in the serializer (dbl, bws, hibw, edc, etc.). wait 2ms. coniguration changed. reestablishes coniguration/video link if needed. loss-of-lock may occur. 3 sets register 0x07 coniguration bits in the deserializer (dbl, bws, hibw, edc, etc.). wait 5ms for lock to reestablish. coniguration changed. locks to coniguration/video link. 4 writes rest of serializer/deserializer coniguration bits. coniguration changed. coniguration changed. 5 writes camera/peripheral coniguration bits. forwards commands from c to serializer. forwards commands to camera/peripherals. 5a if in coniguration link, when pclk is available, set seren = 1. wait 5ms for lock. enables video link. locks to video link. table 2. link-startup procedure www.maximintegrated.com maxim integrated 32 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
register map offset name msb lsb 0x00 seraddr[7:0] seraddr[6:0] cfg- block 0x01 desaddr[7:0] desaddr[6:0] rsvd 0x02 ss[7:0] ss[2:0] rsvd prng[1:0] srng[1:0] 0x03 sdiv[7:0] autofm[1:0] sdiv[5:0] 0x04 main_control[7:0] seren clinken prbsen sleep inttype[1:0] revccen fwdccen 0x05 prbs_len[7:0] i2c- method rsvd prbs_len[1:0] rsvd rsvd rsvd rsvd 0x06 cmllvl_preemp[7:0] cmllvl[3:0] preemp[3:0] 0x07 conig[7:0] dbl hibw bws es rsvd hven rsvd pxl_crc 0x08 rsvd_8[7:0] rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x09 i2c_source a[7:0] i2c_src_a[6:0] rsvd 0x0a i2c_dest a[7:0] i2c_dst_a[6:0] rsvd 0x0b i2c_source b[7:0] i2c_src_b[6:0] rsvd 0x0c i2c_dest b[7:0] i2c_dst_b[6:0] rsvd 0x0d i2c_conig[7:0] i2c_loc_ ack i2c_slv_sh[1:0] i2c_mst_bt[2:0] i2c_slv_to[1:0] 0x0e gpio_en[7:0] rsvd rsvd gpio_ en_5 gpio_ en_4 gpio_ en_3 gpio_ en_2 gpio_ en_1 rsvd 0x0f gpio_out[7:0] en_set_ gpo rsvd gpio_ out_5 gpio_ out_4 gpio_ out_3 gpio_ out_2 gpio_ out_1 set_gpo 0x10 gpio_in[7:0] rsvd rsvd gpio_ in_5 gpio_ in_4 gpio_ in_3 gpio_ in_2 gpio_ in_1 gpo_l 0x11 errg[7:0] errg_rate[1:0] errg_type[1:0] errg_cnt[1:0] errg_ per errg_en 0x12 rsvd_12[7:0] rsvd rsvd rsvd rsvd[4:0] 0x13 pd[7:0] soft_pd rsvd rsvd rsvd rsvd rsvd rsvd[1:0] 0x14 pktcc_lock[7:0] rsvd[1:0] rsvd rsvd rsvd rsvd cc_ wblock rem_ cclock 0x15 input_status[7:0] cx_tp rsvd lccen rsvd rsvd rsvd out- puten pclkdet 0x16 max_rt_err[7:0] rsvd max_rt_ err rsvd[5:0] 0x17 rsvd_17[7:0] rsvd[7:0] 0x18 crc 0[7:0] crc_value_0[7:0] 0x19 crc 1[7:0] crc_value_1[7:0] 0x1a crc 2[7:0] crc_value_2[7:0] 0x1b crc 3[7:0] crc_value_3[7:0] 0x1c cc_crc_errcnt[7:0] cc_crc_errcnt[7:0] 0x1d rsvd_1d[7:0] rsvd[7:0] gmsl register map max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 33 downloaded from: http:///
offset name msb lsb 0x1e id[7:0] id[7:0] 0x1f revision[7:0] rsvd rsvd rsvd hdcpcap revision[3:0] 0x20 crossbar 0[7:0] rsvd force_ mux_0 invert_ mux_0 crossbar_0[4:0] 0x21 crossbar 1[7:0] rsvd force_ mux_1 invert_ mux_1 crossbar_1[4:0] 0x22 crossbar 2[7:0] rsvd force_ mux_2 invert_ mux_2 crossbar_2[4:0] 0x23 crossbar 3[7:0] rsvd force_ mux_3 invert_ mux_3 crossbar_3[4:0] 0x24 crossbar 4[7:0] rsvd force_ mux_4 invert_ mux_4 crossbar_4[4:0] 0x25 crossbar 5[7:0] rsvd force_ mux_5 invert_ mux_5 crossbar_5[4:0] 0x26 crossbar 6[7:0] rsvd force_ mux_6 invert_ mux_6 crossbar_6[4:0] 0x27 crossbar 7[7:0] rsvd force_ mux_7 invert_ mux_7 crossbar_7[4:0] 0x28 crossbar 8[7:0] rsvd force_ mux_8 invert_ mux_8 crossbar_8[4:0] 0x29 crossbar 9[7:0] rsvd force_ mux_9 invert_ mux_9 crossbar_9[4:0] 0x2a crossbar 10[7:0] rsvd force_ mux_10 invert_ mux_10 crossbar_10[4:0] 0x2b crossbar 11[7:0] rsvd force_ mux_11 invert_ mux_11 crossbar_11[4:0] 0x2c crossbar 12[7:0] rsvd force_ mux_12 invert_ mux_12 crossbar_12[4:0] 0x2d crossbar 13[7:0] rsvd force_ mux_13 invert_ mux_13 crossbar_13[4:0] 0x2e crossbar 14[7:0] rsvd force_ mux_14 invert_ mux_14 crossbar_14[4:0] 0x2f crossbar 15[7:0] rsvd force_ mux_15 invert_ mux_15 crossbar_15[4:0] 0x30 crossbar 16[7:0] rsvd force_ mux_16 invert_ mux_16 crossbar_16[4:0] 0x31 crossbar 17[7:0] rsvd force_ mux_17 invert_ mux_17 crossbar_17[4:0] 0x32 crossbar 18[7:0] rsvd force_ mux_18 invert_ mux_18 crossbar_18[4:0] 0x33 crossbar 19[7:0] rsvd force_ mux_19 invert_ mux_19 crossbar_19[4:0] 0x34 crossbar 20[7:0] rsvd force_ mux_20 invert_ mux_20 crossbar_20[4:0] gmsl register map (continued) max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 34 downloaded from: http:///
offset name msb lsb 0x35 crossbar 21[7:0] rsvd force_ mux_21 invert_ mux_21 crossbar_21[4:0] 0x36 crossbar 22[7:0] rsvd force_ mux_22 invert_ mux_22 crossbar_22[4:0] 0x37 crossbar 23[7:0] rsvd force_ mux_23 invert_ mux_23 crossbar_23[4:0] 0x38 crossbar 24[7:0] rsvd force_ mux_24 invert_ mux_24 crossbar_24[4:0] 0x39 crossbar 25[7:0] rsvd force_ mux_25 invert_ mux_25 crossbar_25[4:0] 0x3a crossbar 26[7:0] rsvd force_ mux_26 invert_ mux_26 crossbar_26[4:0] 0x3b crossbar 27[7:0] rsvd force_ mux_27 invert_ mux_27 crossbar_27[4:0] 0x3c crossbar 28[7:0] rsvd force_ mux_28 invert_ mux_28 crossbar_28[4:0] 0x3d crossbar 29[7:0] rsvd force_ mux_29 invert_ mux_29 crossbar_29[4:0] 0x3e crossbar 30[7:0] rsvd force_ mux_30 invert_ mux_30 crossbar_30[4:0] 0x3f crossbar_hs[7:0] rsvd force_ mux_hs invert_ mux_hs crossbarhs[4:0] 0x40 crossbar_vs[7:0] rsvd force_ mux_vs invert_ mux_vs crossbarvs[4:0] 0x41 crossbar_de[7:0] rsvd force_ mux_de invert_ mux_de crossbarde[4:0] 0x42 link_conig[7:0] line_crc_ loc[1:0] line_ crc_en max_ rt_en rsvd gpi_ comp_ en gpi_rt_ en gpo_en 0x43 sync_gen_conig[7:0] rsvd rsvd gen_vs gen_hs gen_de vs_ trig vtg_mode[1:0] 0x44 vs_dly 2[7:0] vs_dly[7:0] 0x45 vs_dly 1[7:0] vs_dly[7:0] 0x46 vs_dly 0[7:0] vs_dly[7:0] 0x47 vs_h 2[7:0] vs_h[7:0] 0x48 vs_h 1[7:0] vs_h[7:0] 0x49 vs_h 0[7:0] vs_h[7:0] 0x4a vs_l 2[7:0] vs_l[7:0] 0x4b vs_l 1[7:0] vs_l[7:0] 0x4c vs_l 0[7:0] vs_l[7:0] 0x4d cxtp[7:0] rsvd cxtp rsvd rsvd vsync_ inv hsync_ inv de_inv rsvd 0x4e hs_dly 2[7:0] hs_dly[7:0] gmsl register map (continued) max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 35 downloaded from: http:///
offset name msb lsb 0x4f hs_dly 1[7:0] hs_dly[7:0] 0x50 hs_dly 0[7:0] hs_dly[7:0] 0x51 rsvd[7:0] rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x52 rsvd[7:0] rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x53 rsvd[7:0] rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x54 hs_h 1[7:0] hs_h[7:0] 0x55 hs_h 0[7:0] hs_h[7:0] 0x56 hs_l 1[7:0] hs_l[7:0] 0x57 hs_l 0[7:0] hs_l[7:0] 0x58 hs_cnt 1[7:0] hs_cnt[7:0] 0x59 hs_cnt 0[7:0] hs_cnt[7:0] 0x5a de_dly 2[7:0] de_dly[7:0] 0x5b de_dly 1[7:0] de_dly[7:0] 0x5c de_dly 0[7:0] de_dly[7:0] 0x5d rsvd[7:0] rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x5e rsvd[7:0] rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x5f rsvd[7:0] rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x60 de_h 1[7:0] de_h[7:0] 0x61 de_h 0[7:0] de_h[7:0] 0x62 de_l 1[7:0] de_l[7:0] 0x63 de_l 0[7:0] de_l[7:0] 0x64 de_cnt 1[7:0] de_cnt_1[7:0] 0x65 de_cnt 0[7:0] de_cnt_0[7:0] 0x66 prbs_type[7:0] rsvd[1:0] prbs_ type rev_ fast de_en dis_ rwake rsvd cxsel 0x67 dbl_align_to[7:0] rsvd[1:0] auto_ clink rsvd rsvd dbl_align_to[2:0] 0x68 cc_crc_length[7:0] rsvd rsvd[2:0] rsvd[1:0] cc_crc_ length[1:0] 0x69 hi_lo[7:0] rsvd en_hi_ lo invert_ hi_lo crossbar_hi_lo[4:0] 0x96 rsvd_96[7:0] rsvd rsvd rsvd rsvd rsvd rsvd rsvd[1:0] 0x97 rsvd_97[7:0] rsvd rsvd rsvd rsvd rsvd rsvd[2:0] 0x98 rsvd_98[7:0] rsvd[1:0] rsvd[2:0] rsvd[2:0] 0x99 rsvd_99[7:0] rsvd rsvd rsvd rsvd rsvd rsvd rsvd[1:0] 0x9a pktcc_en[7:0] rsvd[1:0] rsvd[1:0] pktcc_ en rsvd[1:0] rsvd gmsl register map (continued) max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 36 downloaded from: http:///
seraddr (0x00) bit 7 6 5 4 3 2 1 0 field seraddr[6:0] cfgblock reset 1000000 0b access type write, read write, read bitfield bits description decode seraddr 7:1 serializer address: serializer device address 0000000: write/read device address is 0x00/0x01 0000001: write/read device address is 0x02/0x03 1111111: write/read device address is 0xfe/0xff cfg- block 0 coniguration block: set to 1 to make all registers read-only. set pwdnb low, or a power-on reset to clear this bit. 0: make all registers read/write1: make all registers read-only desaddr (0x01) bit 7 6 5 4 3 2 1 0 field desaddr[6:0] rsvd reset 1001000b 0b access type write, read write, read bitfield bits description decode desaddr 7:1 deserializer address: deserializer device address 0000000: write/read device address is 0x00/0x01 0000001: write/read device address is 0x02/0x03 1111111: write/read device address is 0xfe/0xff rsvd 0 reserved: do not change from default value 0: reserved offset name msb lsb 0xc8 rsvd_c8[7:0] rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0xc9 rsvd_c9[7:0] rsvd[7:0] 0xfc rsvd_fc[7:0] rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0xfd rsvd_fd[7:0] rsvd[7:0] 0xfe rsvd_fe[7:0] rsvd[3:0] rsvd[3:0] 0xff rsvd_ff[7:0] rsvd rsvd rsvd rsvd rsvd[3:0] gmsl register map (continued) max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 37 downloaded from: http:///
ss (0x02) bit 7 6 5 4 3 2 1 0 field ss[2:0] rsvd prng[1:0] srng[1:0] reset 000b 1b 11b 11b access type write, read write, read write, read write, read bitfield bits description decode ss 7:5 spread spectrum: spread-spectrum setting 000: spread is off 001: 0.5% spread setting 010: 1.5% spread setting 011: 2% spread setting 100: spread is off 101: 1% spread setting 110: 3% spread setting 111: 4% spread setting rsvd 4 reserved: do not change from default value 1: reserved prng 3:2 pixel clock range: pixel clock-range selection stated ranges depend on dbl = setting 00: select 12.5mhz to 25mhz (dbl = 0) or 25mhz to 50mhz (dbl = 1) pixel clock range 01: select 25mhz to 58mhz (dbl = 0) or 50mhz to 116mhz (dbl = 1) pixel clock range 10: automatically detect pixel clock range 11: automatically detect pixel clock range. srng 1:0 serial-data rate range 00: 0.5gbps to 1gbps serial-data range01: 1gbps to 1.74gbps serial-data range 10: automatically detect serial-data range 11: automatically detect serial-data range sdiv (0x03) bit 7 6 5 4 3 2 1 0 field autofm[1:0] sdiv[5:0] reset 00b 000000b access type write, read write, read bitfield bits description decode autofm 7:6 automatic frequency modulation: modulation- rate calibration interval 00: calibration occurs once01: calibration occurs every 2ms 10: calibration occurs every 16ms 11: calibration occurs every 256ms sdiv 5:0 sawtooth divider: sawtooth divider value 0x00 sets the sawtooth divider to autocalibrate mode 000000: sawtooth divider automatically calibrates the divider value 000001: sawtooth divider set to 1 111111: sawtooth divider set to 63 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 38 downloaded from: http:///
main_control (0x04) bit 7 6 5 4 3 2 1 0 field seren clinken prbsen sleep inttype[1:0] revccen fwdccen reset 1b 0b 0b 0b 1b 1b 1b access type write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode seren 7 serialization enable: requires a valid pclk for serialization 0: disable serialization1: enable serialization clinken 6 coniguration link enable: coniguration link enabled only when the video link is not enabled (seren = 1) 0: disable coniguration link1: enable coniguration link prbsen 5 prbs test enable: see the prbs test section for more details 0: disable prbs test1: enable prbs test sleep 4 sleep mode enable: activates sleep mode (see the shutdown/sleep modes section for more information) 0: disable sleep mode1: enable sleep mode inttype 3:2 uart/i 2 c interface type: local control-channel interface when in uart/uart or uart/i 2 c mode (i2csel = 0) 00: device performs uart-to-i 2 c conversion when functioning as the remote device 01: device outputs uart packets when functioning as the remote device 10: tx/rx input/outputs disabled when functioning as the remote device 11: tx/rx input/outputs disabled when functioning as the remote device revccen 1 reverse control-channel enable: enable reverse control-channel receiver (data from deserializer) 0: disable reverse control-channel receiver1: enable reverse control-channel receiver fwdccen 0 forward control channel enable: enable forward control channel receiver (data to deserializer) 0: disable forward control channel transmitter1: enable forward control channel transmitter max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 39 downloaded from: http:///
prbs_len (0x05) bit 7 6 5 4 3 2 1 0 field i2c- method rsvd prbs_len[1:0] rsvd rsvd rsvd rsvd reset 0b 0b 00b 0b 0b 0b 0b access type write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode i2cmethod 7 uart-to-i 2 c method: when set, skip the sending of the register address when converting uart to i 2 c (i2csel = 0). 0: do not skip the sending of the register address1: skip the sending of the register address rsvd 6 reserved: do not change from default value. 0: reserved prbs_len 5:4 prbs length: prbs test pattern length 00: continuous bit pattern (ininite length)01: 9.8mbit length 10: 167.1mbit length 11: 1341.5mbit length rsvd 3 reserved: do not change from default value 0: reserved rsvd 2 reserved: do not change from default value. 0: reserved rsvd 1 reserved: do not change from default value. 0: reserved rsvd 0 reserved: do not change from default value. 0: reserved max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 40 downloaded from: http:///
cmllvl_preemp (0x06) bit 7 6 5 4 3 2 1 0 field cmllvl[3:0] preemp[3:0] reset 10x0b 0000b access type write, read write, read bitfield bits description decode cmllvl 7:4 cml level: output cml signal level = (register value) x 50mvdefault level depends on cable type (cxtp) 0000: do not use0001: do not use 0010: 100mv output 0011: 150mv output 0100: 200mv output 0101: 250mv output 0110: 300mv output 0111: 350mv output 1000: 400mv output (stp default) 1001: 450mv output 1010: 500mv output (coax default) 1011: do not use 1100: do not use 1101: do not use 111x: do not use preemp 3:0 preemphasis level: preemphasis setting negative preemphasis levels denote deemphasis 0000: preemphasis off 0001: 1.2db deemphasis 0010: 2.5db deemphasis 0011: 4.1db deemphasis 0100: 6.0db deemphasis 0101: do not use 011x: do not use 1000: 1.1db preemphasis 1001: 2.2db preemphasis 1010: 3.3db preemphasis 1011: 4.4db preemphasis 1100: 6.0db preemphasis 1101: 8.0db preemphasis 1110: 10.5db preemphasis 1111: 14.0db preemphasis max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 41 downloaded from: http:///
conig (0x07) bit 7 6 5 4 3 2 1 0 field dbl hibw bws es rsvd hven rsvd pxl_crc reset 0b 0b xb xb 0b 0b 0b 0b access type write, read write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode dbl 7 double-input mode enable: set high to enable double-input mode. default setting is determined by lccen and tx/scl/dbl pin setting at power-up. 0: single-input mode1: double-input mode hibw 6 high-bandwidth mode enable: high-bandwidth mode select (effective only when bws = 0) 0: use 24-bit mode when bws = 01: use high-bandwidth mode when bws = 0 bws 5 bus-width select: default value is determined by lccen and gpio1/bws pin setting at power-up. 0: 24-bit and high-bandwidth mode1: 32-bit mode es 4 edge select: default value is determined by conf[1:0] pins at power-up 0: parallel data clocked in on rising edge1: parallel data clocked in on falling edge rsvd 3 reserved: do not change from default value. 0: reserved hven 2 hsync/vsync encoding enable: default value is determined by lccen and ms/hven pin setting at powerup 0: disable hs/vs encoding1: enable hs/vs encoding rsvd 1 reserved: do not change from default value. 0: reserved pxl_crc 0 pixel crc type: pixel error-detection type effective only when hibw = 0 0: serial data uses 1-bit parity1: serial data uses 6-bit crc rsvd_8 (0x08) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd reset 0b 0b 0b 0b 0b 0b 0b 0b access type write, read write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value. 0: reserved rsvd 6 reserved: do not change from default value. 0: reserved rsvd 5 reserved: do not change from default value. 0: reserved rsvd 4 reserved: do not change from default value. 0: reserved rsvd 3 reserved: do not change from default value. 0: reserved rsvd 2 reserved: do not change from default value. 0: reserved rsvd 1 reserved: do not change from default value. 0: reserved rsvd 0 reserved: do not change from default value. 0: reserved max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 42 downloaded from: http:///
i2c_source (0x09, 0x0b) bit 7 6 5 4 3 2 1 0 field i2c_src[6:0] rsvd reset 0000000b 0b access type write, read write, read bitfield bits description decode i2c_src 7:1 i 2 c source: i 2 c address translator source 0000000: write/read device address is 0x00/0x01 0000001: write/read device address is 0x02/0x03 1111111: write/read device address is 0xfe/0xff rsvd 0 reserved: do not change from default value. 0: reserved i2c_dest (0x0a, 0x0c) bit 7 6 5 4 3 2 1 0 field i2c_dst[6:0] rsvd reset 0000000b 0b access type write, read write, read bitfield bits description decode i2c_dst 7:1 i 2 c destination: i 2 c address translator destination 0000000: write/read device address is 0x00/0x01 0000001: write/read device address is 0x02/0x03 1111111: write/read device address is 0xfe/0xff rsvd 0 reserved: do not change from default value. 0: reserved max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 43 downloaded from: http:///
i2c_conig (0x0d) bit 7 6 5 4 3 2 1 0 field i2c_loc_ ack i2c_slv_sh[1:0] i2c_mst_bt[2:0] i2c_slv_to[1:0] reset 1b 01b 101b 10b access type write, read write, read write, read write, read bitfield bits description decode i2c_loc_ack 7 i 2 c local acknowledge: i 2 c-to-i 2 c slave generates local acknowledge when forward channel is not available 0: do not send local autoacknowledge when control channel is absent 1: send local autoacknowledge when control channel is absent i2c_slv_ sh 6:5 i 2 c slave setup/hold time: i 2 c-to-i 2 c slave setup and hold-time setting (setup, hold) (typ) 00: (352ns, 117ns) setup/hold time 01: (469ns, 234ns) setup/hold time 10: (938ns, 352ns) setup/hold time 11: (1406ns, 469ns) setup/hold time i2c_mst_bt 4:2 i 2 c master bit rate: i 2 c-to-i 2 c master bit-rate setting (min, typ, max) 000: (6.61, 8.47, 9.92) kbps001: (22.1, 28.3, 33.2) kbps 010: (66.1, 84.7, 99.2) kbps 011: (82, 105, 123) kbps 100: (136, 173, 203) kbps 101: (265, 339, 397) kbps 110: (417, 533, 625) kbps 111: (654, 837, 980) kbps i2c_slv_ to 1:0 i 2 c slave timeout: i 2 c-to-i 2 c slave remote-side timeout setting (typ). 00: 64 s slave timeout 01: 256 s slave timeout 10: 1024 s slave timeout 11: slave timeout disabled max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 44 downloaded from: http:///
gpio_en (0x0e) bit 7 6 5 4 3 2 1 0 field rsvd rsvd gpio_en_5 gpio_en_4 gpio_en_3 gpio_en_2 gpio_en_1 rsvd reset 0b 0b 0b 0b 0b 0b 1b 0b access type write, read write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value. 0: reserved rsvd 6 reserved: do not change from default value. 0: reserved gpio_en_5 5 gpio enable: disabled by default 0: pin functions as a parallel input1: pin functions as a gpio gpio_en_4 4 gpio enable: disabled by default. 0: pin functions as a parallel input1: pin functions as a gpio gpio_en_3 3 gpio enable: disabled by default. 0: pin functions as a parallel input1: pin functions as a gpio gpio_en_2 2 gpio enable: disabled by default 0: pin functions as a parallel input1: pin functions as a gpio gpio_en_1 1 gpio enable: disabled by default 0: pin functions as parallel input1: pin functions as gpio rsvd 0 reserved: do not change from default value 0: reserved gpio_out (0x0f) bit 7 6 5 4 3 2 1 0 field en_set_ gpo rsvd gpio_ out_5 gpio_ out_4 gpio_ out_3 gpio_ out_2 gpio_ out_1 set_gpo reset 1b 0b 1b 1b 1b 1b 1b 0b access type write, read write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode en_set_gpo 7 enable set gpo: set to 1 to enable setting of gpo from set_gpo 0: disable setting of gpo through set_gpo1: enable setting of gpo through set_gpo rsvd 6 reserved: do not change from default value 0: reserved gpio_out_5 5 gpio output level: pull down gpio when 0 0: set gpio output level low1: set gpio output level high gpio_out_4 4 gpio output level: pull down gpio when 0 0: set gpio output level lo1: set gpio output level high gpio_out_3 3 gpio output level: pull down gpio when 0 0: set gpio output leve1: set gpio output level high gpio_out_2 2 gpio output level: pull down gpio when 0 0: set gpio output level low1: set gpio output level high gpio_out_1 1 gpio output level: pull down gpio when 0 0: set gpio output level low1: set gpio output level high set_gpo 0 set gpo level: set gpo output high or low (when en_set_gpo = 1) 0: set gpo output low1: set gpo output high max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 45 downloaded from: http:///
gpio_in (0x10) bit 7 6 5 4 3 2 1 0 field rsvd rsvd gpio_in_5 gpio_in_4 gpio_in_3 gpio_in_2 gpio_in_1 gpo_l reset 0b 0b xb xb xb xb xb xb access type read only read only read only read only read only read only read only read only bitfield bits description decode rsvd 7 reserved 0: reserved rsvd 6 reserved 0: reserved gpio_in_5 5 gpio input level: input pin level of gpio 0: gpio input is low1: gpio input is high gpio_in_4 4 gpio input level: input pin level of gpio 0: gpio input is low1: gpio input is high gpio_in_3 3 gpio input level: input pin level of gpio 0: gpio input is low1: gpio input is high gpio_in_2 2 gpio input level: input pin level of gpio 0: gpio input is low1: gpio input is high gpio_in_1 1 gpio input level: input pin level of gpio 0: gpio input is low1: gpio input is high gpo_l 0 gpo output level 0: gpi output level is low1: gpo output level is high max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 46 downloaded from: http:///
errg (0x11) bit 7 6 5 4 3 2 1 0 field errg_rate[1:0] errg_type[1:0] errg_cnt[1:0] errg_per errg_en reset 0b 0b 0b 0b 0b access type write, read write, read write, read write, read write, read bitfield bits description decode errg_rate 7:6 error-generation rate: error-generation rate, on average 00: generate errors every 2560 bits01: generate errors every 40,960 bits 10: generate errors every 655,360 bits 11: generate errors every 10,485,760 bits errg_type 5:4 error-generation type: type of generated errors 00: single-bit errors01: 2 8b/10b symbols 10: 3 8b/10b symbols 11: 4 8b/10b symbols errg_cnt 3:2 error-generation count: number of generated errors 00: generate errors continuously01: generate16 errors 10: generate 128 errors 11: generate 1024 errors errg_per 1 periodic error generation enable 0: generator creates errors randomly (based on error rate) 1: generator creates errors periodically (based on error rate) errg_en 0 error generator enable 0: disable error generator1: enable error generator rsvd_12 (0x12) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd[4:0] reset 0b 1b 0b 00000b access type write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 1: reserved rsvd 5 reserved: do not change from default value 0: reserved rsvd 4:0 reserved: do not change from default value 00000: reserved max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 47 downloaded from: http:///
pd (0x13) bit 7 6 5 4 3 2 1 0 field soft_pd rsvd rsvd rsvd rsvd rsvd rsvd[1:0] reset 0b 0b 0b 0b 0b 0b 10b access type write 1 to set, read write, read write, read write, read write, read write, read write, read bitfield bits description decode soft_pd 7 soft power down: set this bit to 1 to reset the device; this bit is cleared after the device resets 0: normal operation1: reset the device (bit clears itself) rsvd 6 reserved: do not change from default value 0: reserved rsvd 5 reserved: do not change from default value 0: reserved rsvd 4 reserved: do not change from default value 0: reserved rsvd 3 reserved: do not change from default value 0: reserved rsvd 2 reserved: do not change from default value 0: reserved rsvd 1:0 reserved: do not change from default value 10: reserved pktcc_lock (0x14) bit 7 6 5 4 3 2 1 0 field rsvd[1:0] rsvd rsvd rsvd rsvd cc_ wblock rem_ cclock reset xxb xb xb xb xb xb xb access type read only read only read only read clears all read only read only read only bitfield bits description decode rsvd 7:6 reserved: do not change from default value xx: reserved rsvd 5 reserved: do not change from default value x: reserved rsvd 4 reserved: do not change from default value x: reserved rsvd 3 reserved: do not change from default value x: reserved rsvd 2 reserved: do not change from default value x: reserved cc_wblock 1 control-channel word boundary locked 0: control-channel word boundary is not locked1: control-channel word boundary is locked rem_cclock 0 remote-side control channel locked 0: remote side control channel is not locked1: remote side control channel is locked max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 48 downloaded from: http:///
input_status (0x15) bit 7 6 5 4 3 2 1 0 field cx_tp rsvd lccen rsvd rsvd rsvd outputen pclkdet reset xb xb xb 0b 0b 0b xb xb access type read only read only write, read read only read only read only read only read only bitfield bits description decode cx_tp 7 coax/twisted pair level: cx_tp pin level 0: cx/tp input is low 1: cx/tp input is high rsvd 6 reserved: do not change from default value x: reserved lccen 5 detected lccen pin level 0: pin is input low1: pin is input high rsvd 4 reserved 0: reserved rsvd 3 reserved 0: reserved rsvd 2 reserved 0: reserved out- puten 1 output enabled 0: output disabled1: output enabled pclkdet 0 pclk detected: valid pclk detected 0: no valid pclk detected 1: valid pclk detected max_rt_err (0x16) bit 7 6 5 4 3 2 1 0 field rsvd max_rt_ err rsvd[5:0] reset 0b xb xxxxxxb access type read only read clears all read only bitfield bits description decode rsvd 7 reserved 0: reserved max_rt_err 6 maximum retransmission error: maximum retransmission error bit goes high if packet control channel hits maximum retransmission limit. cleared when read. 0: device has not reached maximum retransmis- sion limit. 1: device has reached maximum retransmission limit. rsvd 5:0 reserved: do not change from default value. xxxxxx: reserved max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 49 downloaded from: http:///
rsvd_17 (0x17) bit 7 6 5 4 3 2 1 0 field rsvd[7:0] reset xxxxxxxxb access type read only bitfield bits description decode rsvd 7:0 reserved: do not change from default value xxxxxxxx: reserved crc (0x18 to 0x1b) bit 7 6 5 4 3 2 1 0 field crc_value[7:0] reset xxxxxxxxb access type read only bitfield bits description decode crc_value 7:0 crc value: crc output for latest line crc_value_3 to crc_value_0 represents crc[31:0] 00000000: value is 0 00000001: value is 1 11111111: value is 255 cc_crc_errcnt (0x1c) bit 7 6 5 4 3 2 1 0 field cc_crc_errcnt[7:0] reset xxxxxxxxb access type read only bitfield bits description decode cc_crc_errcnt 7:0 control-channel crc error count: packet- based control-channel crc error counter 00000000: value is 0 00000001: value is 1 11111111: value is 255 rsvd_1d (0x1d) bit 7 6 5 4 3 2 1 0 field rsvd[7:0] reset xxxxxxxxb access type read only bitfield bits description decode rsvd 7:0 reserved: do not change from default value xxxxxxxx: reserved max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 50 downloaded from: http:///
id (0x1e) bit 7 6 5 4 3 2 1 0 field id[7:0] reset xxxxxxxxb access type read only bitfield bits description decode id 7:0 device id: 8-bit value depends on the gmsl device attached 01000001 device is a max96705 revision (0x1f) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd hdcpcap revision[3:0] reset 0b 0b 0b xb xxxxb access type read only read only read only read only read only bitfield bits description decode rsvd 7 reserved 0: reserved rsvd 6 reserved 0: reserved rsvd 5 reserved 0: reserved hdcpcap 4 hdcp capability: 1 = hdcp capable 0: device does not have hdcp 1: device is hdcp capable revision 3:0 device revision 0000: value is 0 0001: value is 1 1111: value is 15 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 51 downloaded from: http:///
crossbar (0x20 to 0x3e) bit 7 6 5 4 3 2 1 0 field rsvd force_ mux invert_ mux crossbar[4:0] reset 0b 0b 0b xxxxxb access type write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved force_mux 6 force mux output 0: input mapped to mux output1: force mux output low invert_ mux 5 invert mux output 0: do not invert mux output1: invert mux output cross- bar 4:0 crossbar settingselect 1 of 32 input signals. default values connect mux n with input n for low-through routing (i.e., din_ mapped to dout_). 00000: mux outputs data from input 000001: mux outputs data from input 1 11111: mux outputs data from input 31 crossbar_hs (0x3f) bit 7 6 5 4 3 2 1 0 field rsvd force_ mux_hs invert_ mux_hs crossbarhs[4:0] reset 0b 0b 0b 01110b access type write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved force_mux_hs 6 force mux output 0: input mapped to mux output1: force mux output low invert_ mux_hs 5 invert mux output 0: do not invert mux output1: invert mux output cross- barhs 4:0 crossbar setting hs: select 1 of 16 input pins for hs. default values connect hs with the corresponding named input pin. 00000: mux sync signal from din000001: mux sync signal from din1 01111: mux sync signal from din15 1xxxx: do not use max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 52 downloaded from: http:///
crossbar (0x40) bit 7 6 5 4 3 2 1 0 field rsvd force_ mux_vs invert_ mux_vs crossbarvs[4:0] reset 0b 0b 0b 01111b access type write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved force_mux_vs 6 force mux output 0: input mapped to mux output1: force mux output low invert_ mux_vs 5 invert mux output 0: do not invert mux output1: invert mux output cross- barvs 4:0 crossbar setting vs: select 1 of 16 input pins for vs. default values connect vs with the correspond- ing named input pin. 00000: mux sync signal from din000001: mux sync signal from din1 01111: mux sync signal from din15 1xxxx: do not use crossbar_de (0x41) bit 7 6 5 4 3 2 1 0 field rsvd force_ mux_de invert_ mux_de crossbarde[4:0] reset 0b 0b 0b 01101b access type write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved force_mux_de 6 force mux output 0: input mapped to mux output. 1: force mux output low. invert_ mux_de 5 invert mux output 0: do not invert mux output.1: invert mux output. cross- barde 4:0 crossbar setting de: select 1 of 16 input pins for de. default values connect de with din13. 00000: mux sync signal from din000001: mux sync signal from din1 01111: mux sync signal from din15 1xxxx: do not use max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 53 downloaded from: http:///
link_conig (0x42) bit 7 6 5 4 3 2 1 0 field line_crc_loc[1:0] line_crc_ en max_rt_ en rsvd gpi_ comp_en gpi_rt_en gpo_en reset 01b 0b 1b 1b 0b 1b 1b access type write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode line_crc_loc 7:6 line crc location: video line crc insertion location 00: crc insertion at [1...4]01: crc insertion at [5...8] 10: crc insertion at [9...12] 11: crc insertion at [13...16] line_crc_en 5 line crc enable: video line crc enable 0: disable crc1: enable crc max_rt_en 4 maximum retransmission limit enable 0: disable maximum retransmission limit1: enable maximum retransmission limit rsvd 3 reserved: do not change from default value 1: reserved gpi_comp_en 2 gpi compensation enable 0: disable gpi compensation1: enable gpi compensation gpi_rt_en 1 gpi retransmission enable 0: disable gpi retransmission1: enable gpi retransmission gpo_en 0 gpo enable: enable gpo pin 0: disable gpo pin1: enable gpo pin max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 54 downloaded from: http:///
sync_gen_conig (0x43) bit 7 6 5 4 3 2 1 0 field rsvd rsvd gen_vs gen_hs gen_de vs_trig vtg_mode[1:0] reset 0b 0b 0b 0b 0b 1b 01b access type write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved gen_vs 5 vsync generation: enable to generate vs output according to the timing deinition 0: disable vs output generation (vs used from input) 1: enable vs output generation (vs internally generated) gen_hs 4 hsync generation: enable to generate hs utput according to the timing deinition 0: disable hs output generation (hs used from input) 1: enable hs output generation (hs internally generated) gen_de 3 de generation: enable to generate de output according to the timing deinition 0: disable de output generation (de used from input) 1: enable de output generation (de internally generated) vs_trig 2 vsync trigger edge select 0: vs trigger uses falling edge1: vs trigger uses rising edge vtg_mode 1:0 video timing generator mode 00: vs input is tracked and then locked after three consecutive matches (three consecutive mismatch- es unlock tracking) 01: vs edge triggers one vs frame (current frame is extended/cut short to adjust timing to next trigger) 10: vs edge triggers vs generation (current frame is extended/cut short to adjust timing to next trigger) 11: same as above max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 55 downloaded from: http:///
vs_dly (0x44 to 0x46) bit 7 6 5 4 3 2 1 0 field vs_dly[7:0] reset 00000000b access type write, read bitfield bits description decode vs_dly 7:0 vsync delay: vs delay in terms of pclk cycles; the output vs delay by vs_delay cycles from the input vs. 00000000: value is 0 00000001: value is 1 11111111: value is 255 vs_h (0x47 to 0x49) bit 7 6 5 4 3 2 1 0 field vs_h[7:0] reset 00000000b access type write, read bitfield bits description decode vs_h 7:0 vsync high: vs high period in terms of pclk cycles. 00000000: value is 0 00000001: value is 1 11111111: value is 255 vs_l (0x4a to 0x4c) bit 7 6 5 4 3 2 1 0 field vs_l[7:0] reset 00000000b access type write, read bitfield bits description decode vs_l 7:0 vsync low: vs low period in terms of pclk cycles 00000000: value is 0 00000001: value is 1 11111111: value is 255 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 56 downloaded from: http:///
cxtp (0x4d) bit 7 6 5 4 3 2 1 0 field rsvd cxtp rsvd rsvd vsync_ inv hsync_ inv de_inv rsvd reset xb 0b 0b 0b 0b 0b 0b 0b access type write, read write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value x: reserved cxtp 6 coax/twisted pair select default value depends on the state of the conf0, conf1 inputs 0: use differential output (stp mode) 1: use dual single ended outputs (coax) rsvd 5 reserved: do not change from default value 0: reserved rsvd 4 reserved: do not change from default value 0: reserved vsync_inv 3 vsync inversion: invert output vsync in timing gen 0: do not invert vs in timing generator1: invert vs in timing generator hsync_inv 2 hsync inversion: invert output hsync in timing gen 00: value is zero 01: value is two 10 11 de_inv 1 de inversion: invert output de in timing gen 00: value is zero 01: value is two 10 11 rsvd 0 reserved: do not change from default value 0: reserved max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 57 downloaded from: http:///
hs_dly (0x4e to 0x50) bit 7 6 5 4 3 2 1 0 field hs_dly[7:0] reset 00000000b access type write, read bitfield bits description decode hs_dly 7:0 vsync to hsync delay: vs edge to the rising edge of the irst hs in terms of pclk cycles (bits [15:8]) 00000000: value is 0 00000001: value is 1 11111111: value is 255 rsvd (0x51 to 0x53, 0x5d to 0x5f) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd reset 0b 0b 0b 0b 0b 0b 0b 0b access type write, read write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5 reserved: do not change from default value 0: reserved rsvd 4 reserved: do not change from default value 0: reserved rsvd 3 reserved: do not change from default value 0: reserved rsvd 2 reserved: do not change from default value. 0: reserved rsvd 1 reserved: do not change from default value 0: reserved rsvd 0 reserved: do not change from default value 0: reserved max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 58 downloaded from: http:///
hs_h (0x54, 0x55) bit 7 6 5 4 3 2 1 0 field hs_h[7:0] reset 00000000b access type write, read bitfield bits description decode hs_h 7:0 hsync high period: hs high period in terms of pclk cycles 00000000: value is 0 00000001: value is 1 11111111: value is 255 hs_l (0x56, 0x57) bit 7 6 5 4 3 2 1 0 field hs_l[7:0] reset 00000000b access type write, read bitfield bits description decode hs_l 7:0 hsync low period: hs low period in terms of pclk cycles. 00000000: value is 0 00000001: value is 1 11111111: value is 255 hs_cnt (0x58, 0x59) bit 7 6 5 4 3 2 1 0 field hs_cnt[7:0] reset 00000000b access type write, read bitfield bits description decode hs_cnt 7:0 hsync count: lines per panel (bits [7:0]). 00000000: value is 0 00000001: value is 1 11111111: value is 255 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 59 downloaded from: http:///
de_dly (0x5a to 0x5c) bit 7 6 5 4 3 2 1 0 field de_dly[7:0] reset 00000000b access type write, read bitfield bits description decode de_dly 7:0 vsync to devs falling edge to the rising edge of the irst de in terms of pclk cycles. 00000000: value is 0. 00000001: value is 1. 11111111: value is 255. de_h (0x60, 0x61) bit 7 6 5 4 3 2 1 0 field de_h[7:0] reset 00000000b access type write, read bitfield bits description decode de_h 7:0 de high period: de high period in terms of pclk cycles. 00000000: value is 0 00000001: value is 1 11111111: value is 255 de_l (0x62, 0x63) bit 7 6 5 4 3 2 1 0 field de_l[7:0] reset 00000000b access type write, read bitfield bits description decode de_l 7:0 de low period: de low period in terms of pclk cycles 00000000: value is 0 00000001: value is 1 11111111: value is 255 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 60 downloaded from: http:///
de_cnt (0x64, 0x65) bit 7 6 5 4 3 2 1 0 field de_cnt[7:0] reset 00000000b access type write, read bitfield bits description decode de_cnt 7:0 de count: active lines per panel 00000000: value is 0 00000001: value is 1 11111111: value is 255 prbs_type (0x66) bit 7 6 5 4 3 2 1 0 field rsvd[1:0] prbs_ type rev_fast de_en dis_ rwake rsvd cxsel reset 01b 1b 0b 0b 0b 0b 1b access type write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7:6 reserved: do not change from default value 01: reserved prbs_type 5 prbs type: prbs type select 0: select legacy prbs mode 1: select max9271Cmax9273 prbs mode rev_ fast 4 reverse channel fast-mode enable 0: disable reverse channel fast mode1: enable reverse channel fast mode de_en 3 de enable: enable processing separate hs and de signals 0: disable separate processing of hs and de signals 1: enable separate processing of hs and de signals dis_ rwake 2 disable remote wake-up: disable wake-up receiver 0: do not disable remote wake-up receiver1: disable remote wake-up receiver rsvd 1 reserved: do not change from default value 0: reserved cxsel 0 coax select 0: coax cable connected to inverting output1: coax cable connected to noninverting output max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 61 downloaded from: http:///
dbl_align_to (0x67) bit 7 6 5 4 3 2 1 0 field rsvd[1:0] auto_ clink rsvd rsvd dbl_align_to[2:0] reset 11b 0b 0b 0b 111b access type write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7:6 reserved: do not change from default value 11: reserved auto_ clink 5 auto coniguration link: automatic control of coniguration link 0: enable coniguration link only when clinken = 1 and seren = 0 1: automatically enable coniguration link when seren = 1 and pclkdet = 0 rsvd 4 reserved: do not change from default value 0: reserved rsvd 3 reserved: do not change from default value 0: reserved dbl_ align_to 2:0 double alignment mode: sets the alignment mode when dbl = 1 in the serializer and dbl = 0 in the deserializer. set dbl_align_to = 000 when an external high-low signal is used (en_hi_lo =1). 000: align at each rising edge of hs. turn off alignment after hs is low (max9286). use this setting when an external high/low signal is used. 001: do not use 010: force align 011: do not use 100: align at each rising edge of hs 101: align at each rising edge of de 110: force align 111: no alignment done while in dbl mode cc_crc_length (0x68) bit 7 6 5 4 3 2 1 0 field rsvd rsvd[2:0] rsvd[1:0] cc_crc_length[1:0] reset 0b 001b 10b 01b access type write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6:4 reserved: do not change from default value 001: reserved rsvd 3:2 reserved: do not change from default value 10: reserved cc_crc_length 1:0 control-channel crc length 00: 1-bit cc crc length01: 5-bit cc crc length 10: 8-bit cc crc length 11: do not use max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 62 downloaded from: http:///
hi_lo (0x69) bit 7 6 5 4 3 2 1 0 field rsvd en_hi_lo invert_ hi_lo crossbar_hi_lo[4:0] reset 0b 0b 0b 01111b access type write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved en_hi_lo 6 enable high/low signal alignment 0: do not align using a hi-lo signal1: use a hi-lo signal to align input data invert_ hi_lo 5 invert high/low signal alignment 0: do not invert hi-lo signal1: invert hi-lo signal cross- bar_hi_ lo 4:0 crossbar high low: select 1 of 16 input pins for the hi-lo signal. default values connect the hi-lo signal to the vs input pin (effective when dbl_align_to = 000). 00000: mux hi-lo signal from din000001: mux hi-lo signal from din1 01111: mux hi-lo signal from din15 1xxxx: do not use rsvd_96 (0x96) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd rsvd rsvd rsvd[1:0] reset 0b 0b 0b 0b 0b 0b 10b access type write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5 reserved: do not change from default value 0: reserved rsvd 4 reserved: do not change from default value 0: reserved rsvd 3 reserved: do not change from default value 0: reserved rsvd 2 reserved: do not change from default value 0: reserved rsvd 1:0 reserved: do not change from default value 10: reserved max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 63 downloaded from: http:///
rsvd_97 (0x97) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd rsvd rsvd[2:0] reset 0b 0b 0b 1b 1b 111b access type write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5 reserved: do not change from default value 0: reserved rsvd 4 reserved: do not change from default value 1: reserved rsvd 3 reserved: do not change from default value 1: reserved rsvd 2:0 reserved: do not change from default value 111: reserved rsvd_98 (0x98) bit 7 6 5 4 3 2 1 0 field rsvd[1:0] rsvd[2:0] rsvd[2:0] reset 01b 001b 010b access type write, read write, read write, read bitfield bits description decode rsvd 7:6 reserved: do not change from default value 01: reserved rsvd 5:3 reserved: do not change from default value 001: reserved rsvd 2:0 reserved: do not change from default value 010: reserved max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 64 downloaded from: http:///
rsvd_99 (0x99) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd rsvd rsvd rsvd[1:0] reset 0b 0b 0b 0b 1b 1b 01b access type write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5 reserved: do not change from default value 0: reserved rsvd 4 reserved: do not change from default value 0: reserved rsvd 3 reserved: do not change from default value 1: reserved rsvd 2 reserved: do not change from default value 1: reserved rsvd 1:0 reserved: do not change from default value 01: reserved pktcc_en (0x9a) bit 7 6 5 4 3 2 1 0 field rsvd[1:0] rsvd[1:0] pktcc_en rsvd[1:0] rsvd reset 00b 01b 0b 00b 0b access type write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7:6 reserved: do not change from default value 00: reserved rsvd 5:4 reserved: do not change from default value 01: reserved pktcc_en 3 packet-based control-channel-mode enable 0: disable packet-based control-channel mode1: enable packet-based control-channel mode rsvd 2:1 reserved: do not change from default value 00: reserved rsvd 0 reserved: do not change from default value 0: reserved max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 65 downloaded from: http:///
rsvd_c8 (0xc8) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd reset 0b xb xb xb 0b 0b 0b 0b access type write, read read only read only read only write, read read only write, read read only bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value x: reserved rsvd 5 reserved: do not change from default value x: reserved rsvd 4 reserved: do not change from default value x: reserved rsvd 3 reserved: do not change from default va 0: reserved rsvd 2 reserved 0: reserved rsvd 1 reserved: do not change from default value 0: reserved rsvd 0 reserved 0: reserved rsvd_c9 (0xc9) bit 7 6 5 4 3 2 1 0 field rsvd[7:0] reset xxxxxxxxb access type read only bitfield bits description decode rsvd 7:0 reserved: do not change from default value xxxxxxxx: reserved max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 66 downloaded from: http:///
rsvd_fc (0xfc) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd reset 0b 0b 0b 0b 0b 0b 0b 0b access type write, read write, read write, read write, read write, read write, read write, read write, read bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5 reserved: do not change from default value 0: reserved rsvd 4 reserved: do not change from default value 0: reserved rsvd 3 reserved: do not change from default value 0: reserved rsvd 2 reserved: do not change from default value 0: reserved rsvd 1 reserved: do not change from default value 0: reserved rsvd 0 reserved: do not change from default value 0: reserved rsvd_fd (0xfd) bit 7 6 5 4 3 2 1 0 field rsvd[7:0] reset 00000000b access type write, read bitfield bits description decode rsvd 7:0 reserved: do not change from default value 00000000: reserved max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 67 downloaded from: http:///
bitfield bits description decode rsvd 7 reserved: do not change from default value 0: reserved rsvd 6 reserved: do not change from default value 0: reserved rsvd 5 reserved: do not change from default value 0: reserved rsvd 4 reserved: do not change from default value 0: reserved rsvd 3:0 reserved: do not change from default value xxxx: reserved rsvd_fe (0xfe) bit 7 6 5 4 3 2 1 0 field rsvd[3:0] rsvd[3:0] reset 0000b 0000b access type write, read write, read bitfield bits description decode rsvd 7:4 reserved: do not change from default value 0000: reserved rsvd 3:0 reserved: do not change from default value 0000: reserved rsvd_ff (0xff) bit 7 6 5 4 3 2 1 0 field rsvd rsvd rsvd rsvd rsvd[3:0] reset 0b 0b 0b 0b xxxxb access type write, read write, read write, read write, read read only max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 68 downloaded from: http:///
* the input bit width is limited by the number of available inputs. ** the input bit width is limited by the number of available outputs on the deserializer. applications information parallel interface the cmos parallel interface-data width is programmable and depends on the application. using a larger width (bws = 1) results in a lower-pixel clock rate, while a smaller width (bws = 0) allows a higher-pixel clock rate. bus data width the bus data width depends on the selected modes. the available bus width is less when using error detection or when in double mode (dbl = 1). table 3 shows the avail - able bit widths and default mapping for various modes. bus data rates the bus data rate depends on the settings for bws and dbl. table 4 lists the available pclk rates available for different bus-width settings. for lower pclk rates, set dbl = 0 (if dbl = 1 in both the serializer and deserializer). register bit settings input mapping (with 96706) input mapping (with other) dbl bws hibw pxl_crc hven 1 1 1 1 din11:0, hs, vs din11:0, hs, vs 1 1 1 0 din11:0 din11:0 1 1 0 1 din11:0 ** , hs, vs din13:0*, hs, vs 1 1 0 0 din13:0** din14:0 1 0 1 1 din8:0, hs, vs din8:0, hs, vs 1 0 1 0 din11:0, hs, vs din11:0, hs, vs 1 0 0 1 1 din7:0, hs, vs din7:0, hs, vs 1 0 0 1 0 din7:0 din7:0 1 0 0 0 1 din10:0, hs, vs din10:0, hs, vs 1 0 0 0 0 din10:0 din10:0 0 1 1 1 din11:0**, hs, vs din13:0*, hs, vs 0 1 1 0 din13:0** din15:0* 0 1 0 1 din11:0**, hs, vs din13:0*, hs, vs 0 1 0 0 din13:0* din15:0* 0 0 1 - din11:0**, hs, vs din13:0*, hs, vs 0 0 0 1 1 din11:0**, hs, vs din13:0*, hs, vs 0 0 0 1 0 din13:0** din15:0* 0 0 0 0 1 din11:0**, hs, vs din13:0*, hs, vs 0 0 0 0 0 din13:0** din15:0* dbl bws hibw pclk range (mh z ) 1 1 0 25 to 87 1 0 0 33.3 to 116 1 0 1 73.3 to 116 0 1 0 12.5 to 43.5 0 0 0 16.7 to 58 0 0 1 36.6 to 58 table 3. input data-width selection table 4. data-rate selection www.maximintegrated.com maxim integrated 69 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
crossbar switch by default, the crossbar switch connects the serializer input pins din_ and hs/vs (when hv encoding is used) to the corresponding deserializer output pins dout_ and hs/vs. reprogram the crossbar switch when changing the input or output pin assignments, or when connecting to devices that do not have a dbl = 1 mode. crossbar-switch programming each crossbar-switch output can select any of the 16 din_ inputs for either high or low words (when dbl = 1) for a total of 32 possible inputs. multiple outputs can share the same input. hs, vs, and de remain the same for both word halves, and should be programmed to use the low-word input of the corresponding pin. to invert an input data bit, set the respective invert_mux_ = 1. to force an output low, (and ignore the input) set the force_mux_ bit = 1. to force an output high set both invert_mux_ and force_mux_ = 1. recommended crossbar-switch program procedure the procedure to program the crossbar switch depends on the dbl settings on the serializer and deserializer. devices without double mode can be assumed to have dbl = 0. both devices' dbl set to the same value 1. for the crossbar-output equivalent of din0 (xbo0, xbo16) select which pin to map (e.g., din4 ? xbi4, xbi20). 2. set the low- and high-input crossbar bits (crossbar0, crossbar 16) to the desired selected mapped input (e.g., crossbar0 = 00100, crossbar16 = 10100). 3. repeat for the other crossbar outputs, making sure the set of high and low crossbar outputs are assigned to the same crossbar input set. in general, xbo[i] and xbo[i+16] should be assigned to xbi[j] and xbi[j+16]. 4. for xbohs, xbovs, and xbode, set crossbar to use the low-input pins (crossbar_ = 00000 to 01111). note that hs, vs, and de use both the low and high input. both devices' dbl do not match 1. table 5 , table 6 , and table 7 list which crossbar output (xbo_) maps to each serial bit. 2. for each crossbar output, select which pin and high/ low clock cycle (if needed) to map (e.g., din4 low input). 3. set the crossbar bits (crossbar_) to select the desired selected mapped input (e.g., crossbar0 = 00100 maps din4 low input to xbo0). 4. repeat for the other crossbar outputs; any unused serial bits should have a force low mapped to the respective crossbar output. 5. for xbohs, xbovs, and xbode, set crossbar to use the low-input pins (crossbar_ = 00000 to 01111). note that hs, vs, and de use both the low and high input. bit setting serial bits db hv bw hb cr de 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 0 0 0 0 x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 z z z z z z f p 0 0 0 0 1 x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 f e e e e e e p 0 0 0 1 0 x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 z z z z z z f p 0 0 0 1 1 x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 z z z f e e e p 0 0 1 0 0 x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 z z z z z z z z 0 0 1 0 1 x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 z z z z z z z z 0 1 0 0 0 x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 z z z z z z f p 0 1 0 0 1 x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 f e e e e e e p 0 1 1 0 0 x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 z z z z z z z z 0 1 1 0 1 x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 z z z z z z z z 1 0 0 0 0 x 16 17 18 19 20 21 22 23 24 25 26 0 1 2 3 4 5 6 7 8 9 10 f p 1 0 0 0 1 x 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7 f e e e e e e p 1 0 0 1 0 x 16 17 18 19 20 21 22 23 24 25 26 27 0 1 2 3 4 5 6 7 8 z f p table 5. crossbar output to serial link map (d23:0) www.maximintegrated.com maxim integrated 70 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
table 5. crossbar output to serial link map (d23:0) (continued) bit setting serial bits db hv bw hb cr de 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 0 0 1 1 x 16 17 18 19 20 21 22 23 24 0 1 2 3 4 5 6 7 8 z f e e e p 1 0 1 0 0 x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0 1 2 3 4 5 6 7 8 1 0 1 0 1 1 16 17 18 19 20 21 22 23 24 25 26 dh 0 1 2 3 4 5 6 7 8 9 10 dl 1 0 1 0 1 0 16 17 18 19 20 21 22 23 24 25 26 27 0 1 2 3 4 5 6 7 8 9 10 11 1 1 0 0 0 1 16 17 18 19 20 21 22 23 24 25 dh 0 1 2 3 4 5 6 7 8 9 dl f p 1 1 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 0 1 2 3 4 5 6 7 8 9 10 f p 1 1 0 0 1 1 16 17 18 19 20 21 22 dh 0 1 2 3 4 5 6 dl f e e e e e e p 1 1 0 0 1 0 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7 f e e e e e e p 1 1 1 0 0 x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0 1 2 3 4 5 6 7 8 1 1 1 0 1 1 16 17 18 19 20 21 22 23 24 25 26 dh 0 1 2 3 4 5 6 7 8 9 10 dl 1 1 1 0 1 0 16 17 18 19 20 21 22 23 24 25 26 27 0 1 2 3 4 5 6 7 8 9 10 11 table 6. crossbar output to serial link map (d31:24 and special packets) bit setting special packets db hv bw hb cr de 24 25 26 27 28 29 30 31 c0 c1 c2 c3 hs vs de 0 0 0 0 0 x 0 0 0 0 1 x 0 0 0 1 0 x z z z z z z z h v d 0 0 0 1 1 x e e e z z z z h v d 0 0 1 0 0 x z z z z z z f p 0 0 1 0 1 x f e e e e e e p 0 1 0 0 0 x h v 0 1 0 0 1 x h v 0 1 1 0 0 x z z z z z z f p h v 0 1 1 0 1 x f e e e e e e p h v 1 0 0 0 0 x 1 0 0 0 1 x 1 0 0 1 0 x 9 10 11 a z a a h v d 1 0 0 1 1 x e e e a z a a h v d 1 0 1 0 0 x 9 10 11 12 13 14 f p 1 0 1 0 1 1 f e e e e e e p 1 0 1 0 1 0 f e e e e e e p 1 1 0 0 0 1 hh/l vh/l 1 1 0 0 0 0 hh/l vh/l 1 1 0 0 1 1 hh/l vh/l 1 1 0 0 1 0 hh/l vh/l 1 1 1 0 0 x 9 10 11 12 13 14 f p hh/l vh/l 1 1 1 0 1 1 f e e e e e e p hh/l vh/l 1 1 1 0 1 0 f e e e e e e p - - - - hh/l vh/l - max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 71 downloaded from: http:///
table 7. legend bit settings map inputs db double-mode bit dbl h hsync ( when dbl = 0 or hibw = 1) hv h/v encoding bit hven v vsync ( when dbl = 0 or hibw = 1) bw bws bit d de ( when dbl = 0 or hibw = 1) hb hibw bit hh hsync (high word, dbl = 1) cr pxl_crc bit vh vsync (high word, dbl = 1) de de = 1 when deen = 1 and not processed in rgb888 mode dh de (high word, dbl = 1) x 1 or 0 hl hsync (low word, dbl = 1) special packets vl vsync (low word, dbl = 1) c0 cnt_0 dl de (low word, dbl = 1) c1 cnt_1 # xbo output from crossbar switch c2 cnt_2 f internal forward control-channel bit c3 cnt_3 e internal pixel crc bit bit color p internal pixel parity bit output bits from crossbar serial bit not sent internal bits z zero other output bits a internal alignment bit (used when hibw=1) output bits from sync figure 20. crossbar-switch default mapping xbi15 xbi30 xbi14 xbi29 xbi13 xbi28 xbi12 xbi27 xbi11 xbi26 xbi10 xbi25 xbi9 xbi24 xbi8 xbi23 xbi7 xbi22 xbi6 xbi21 xbi5 xbi20 xbi4 xbi19 xbi3 xbi18 xbi2 xbi17 xbi1 xbi16 xbi0 din15/vs input pin din14/hs din13 din12 din11 din10 din9 din8 din7 din6 din5 din4 din3 din2 din1 din0 alignment hs* hs hs hi_lo* pclk xbi15 xbi30 xbi14 xbi29 xbi13 xbi28 xbi12 xbi27 xbi11 xbi26 xbi10 xbi25 xbi9 xbi24 xbi8 xbi23 xbi7 xbi22 xbi6 xbi21 xbi5 xbi20 xbi4 xbi19 xbi3 xbi18 xbi2 xbi17 xbi1 xbi16 xbi0 pixel n n+1 de* de de xbi31 xbi31 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 72 downloaded from: http:///
timing-generator programming timing-generator parameters are stored in the registers as unsigned integers as pclk periods. to prevent out - put glitches, program all timing-generator parameters while the device is in configuration-link mode, or when pclk is not applied. by default, the timing generator is set to single trigger, and is disabled. figure 18 show the timing waveforms under the default conditions with rising-edge trigger, and noninverted signals. do not pro - gram the hsync or de signals such that the total length exceeds the length of a vsync period ( table 8 ). all delay parameters are positive. to implement a negative delay, set the delay value subtracted from the vsync period (e.g., a delay value of vs_high + vs_low - n creates a delay of -n pclk cycles). do not set any delay lengths larger than the vsync period. double-mode alignment when dbl = 1 in both the serializer and deserializer, gmsl automatically keeps the pixels in order. use double-mode alignment when dbl = 1 in the serializer and dbl = 0 (or is not supported) in the deserializer. two different methods are available for double-mode alignment. external high/low signal to use an external alignment signal, set en_hi_lo = 1, dbl_align_to = 000, and select which input din_ pin to use by setting the crossbar_hi_lo bits. the external signal designates whether the clocked word is the high or low word (e.g., for pixels [1h, 1l, 2h, 2l...] the high/low signal would be [1, 0, 1, 0...]). align from hs or de to align from a sync signal, set the dbl_align_to to select the input signal. when using this mode, ensure that the signal used for alignment uses the same value for both the high and low word (e.g., for pixels [1h, 1l, 2h, 2l...], aligning on de requires values of [de1, de1, de2, de2...]). control-channel interfaces i 2 c set i2csel = 1 to configure the control channel for i 2 c to i 2 c. in this mode, the control channel forwards i 2 c commands from the microcontroller side to the other side of the gmsl link. the remote device acts as an i 2 c master to the other peripherals connected to the remote- side device. i 2 c-to-i 2 c mode uses clock stretching to hold the microcontroller until the data and an acknowledge or not acknowledge have been sent across the link. i 2 c bit rate the i 2 c interface accepts bit rates from 9.6kbps to 1mbps. the local i 2 c rate is set by the microcontroller. the remote i 2 c rate is set by the remote device. by default, the control channel is set up for a 400kbps i 2 c bit rate. program the i2c_mstbt and slv_sh bits (register 0x0d) to match the desired microcontroller i 2 c rate. signal size (bits) min value (hex) maximum value restriction (hex) vs_high 24 1 vs_high + vs_low < 0xffffff vs_low 24 1 vs_high + vs_low < 0xffffff vs_dly 24 0 vs_dly < vs_high + vs_low hs_high 16 1 (hs_high + hs_low) x hs_cnt < vs_high + vs_low hs_low 16 1 (hs_high + hs_low) x hs_cnt < vs_high + vs_low hs_cnt 16 1 (hs_high + hs_low) x hs_cnt < vs_high + vs_low hs_dly 24 0 hs_dly < vs_high + vs_low de_high 16 1 (de_high + de_low) x de_cnt < vs_high + vs_low de_low 16 1 (de_high + de_low) x de_cnt < vs_high + vs_low de_cnt 16 1 (de_high + de_low) x de_cnt < vs_high + vs_low de_dly 24 0 de_dly < vs_high + vs_low table 8. timing-generator parameter restrictions www.maximintegrated.com maxim integrated 73 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
software programming of device addresses the serializer and deserializer have programmable device addresses. this allows multiple gmsl devices, along with i 2 c peripherals, to coexist on the same control channel. the serializer device address is in register 0x00 of each device, while the deserializer device address is in register 0x01 of each device. to change a device address, first write to the device whose address changes (register 0x00 of the serializer for serializer device address change, or register 0x01 of the deserializer for deserializer device address change). then, write the same address into the corresponding register on the other device (register 0x00 of the deserializer for serializer device address change, or register 0x01 of the serializer for deserializer device address change). i 2 c address translation the device supports i 2 c address translation for up to two device addresses. use address translation to assign unique device addresses to peripherals with limited i 2 c addresses. source addresses (address to translate from) are stored in registers 0x09 and 0x0b. destination addresses (address to translate to) are stored in registers 0x0a and 0x0c. coniguration blocking the device can block changes to its registers. set cfgblock to make all registers read-only. once set, the registers remain blocked until the supplies are removed or until pwdnb is low. cascaded/parallel devices gmsl supports both cascaded and parallel devices connected through i 2 c. when cascading or using parallel links, all i 2 c commands are forwarded to all links. each link attempts to hold the control channel until it receives an acknowledge/not acknowledge from the remote-side device. it is important to keep the control channel active between links to prevent timeout. if a link is unused, keep the control channel clear by turning on the configuration link, disconnecting the i 2 c lines, or powering down the unused device. dual c control most systems use a single microcontroller; however cs can reside on each side simultaneously and trade off in running the control channel. contention occurs if both cs attempt to use the control channel at the same time. it is up to the user to prevent this contention by imple - menting a higher level protocol. in addition, the control channel does not provide arbitration between i 2 c masters on both sides of the link. an acknowledge frame is not generated when communication fails due to contention. if communication across the serial link is not required, the cs can disable the forward and reverse control channel using the fwdccen and revccen bits (0x04, d[1:0]) in the serializer/deserializer. communication across the serial link is stopped and contention between cs cannot occur. uart set i2csel = 0 to configure the control channel for uart or uart-to-i 2 c mode. in this mode, the control channel forwards uart commands from the microcontroller side to the other side of the gmsl link. when inttype = 00, the remote device acts as an i 2 c master to the other peripherals connected to the remote-side device. uart- to-i 2 c mode does not support devices that use clock stretching.base mode in base mode, uart packets control the serializer, deserializer, and attached peripherals. uart timing in base mode, the uart idles high (through a pullup resistor). each gmsl uart byte consists of a start bit, 8 data bits, an even-parity bit, and a stop bit ( figure 21 ). keep the idle time between bytes of the same uart packet to less than 4 bit times. the gmsl-uart protocol is listed in figure 22 . a write packet consists of a sync byte ( figure 23 ), device address byte, starting register address byte, number of bytes to write, and the data bytes. the slave device responds with an ack byte ( figure 24 ) if the write was successful. a read packet consists of a sync byte, device address byte, starting register address byte, and number of bytes to read. the slave device responds with an ack byte, and the read data bytes. www.maximintegrated.com maxim integrated 74 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
figure 23. sync byte (0x79) figure 24. ack byte (0xc3) figure 21. gmsl-uart data format for base mode figure 22. gmsl-uart protocol for base mode write data format sync reg addr number of bytes sync dev addr + r/w reg addr number of bytes byte 1 byte n ack byte n byte 1 ack master reads from slave read data format master writes to slave master writes to slave master reads from slave dev addr + r/w start d0 d1 d2 d3 d4 d5 d6 d7 parity* stop 1 uart frame frame 1 frame 2 frame 3 *base mode uses even parity start stop start stop start d0 1 0 0 1 1 1 1 0 d1 d2 d3 d4 d5 d6 d7 parity stop start d0 1 1 0 0 0 0 1 1 d1 d2 d3 d4 d5 d6 d7 parity stop max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 75 downloaded from: http:///
uart-to-i 2 c conversion when using the uart control channel, the remote-side device can communicate to i 2 c peripherals through uart-to-i 2 c conversion. set the inttype bits in the remote-side device to 00 to activate uart-to-i 2 c conversion. the converted i 2 c bit rate is the same as the incoming uart bit rate. i 2 c peripherals must not use clock stretching in order to be compatible with uart-to- i 2 c conversion. there are two possible methods the devices use to convert uart to i 2 c. in the first method (i2cmethod = 0), the register address is sent with the i 2 c communica - tion ( figure 25 ). for devices that do not use a register address (such as the max7324), set i2cmethod = 1 and send a dummy byte in place of the register address ( figure 26 ). in this method, the remote device omits send - ing the register address. figure 25. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) figure 26. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 1) 11 sync frame register address number of bytes device id + wr data 0 dev id a 11 11 11 11 data n 11 11 s 1 1 1 ack frame 7 : master to slave 8 serializer/deserializer peripheral w 1 reg addr 8 a 1 1 8 1 11 sync frame register address number of bytes device id + rd 11 11 11 11 ack frame data 0 11 data n 11 uart-to-i 2 c conversion of write packet (i2cmethod = 0) uart-to-i 2 c conversion of read packet (i2cmethod = 0) s: start p: stop a: acknowledge : slave to master data 0 a data n a p dev id a s 1 1 7 w 1 dev id a s 1 1 7 r 1 data n p 1 8 a 1 data 0 8 a 1 reg addr 8 a 1 c serializer/deserializer c serializer/deserializer serializer/deserializer peripheral master to slave serializer/deserializer serializer/deserializer serializer/deserializer uart-to-i 2 c conversion of read packet (i2cmethod = 1) uart-to-i 2 c conversion of write packet (i2cmethod = 1) c serializer/deserializer c sync frame 11 11 11 11 11 11 11 11 11 11 11 11 11 11 device id + rd register address number of bytes sync frame device id + wr register address number of bytes data 0 data n ack frame ack frame data 0 data n data n a data 0 w a dev id s a p peripheralperipheral s 1 1 1 8 8 8 1 11 1 7 1 1 8 1 1 1 7 dev id r a a a p data 0 data n slave to master s: start p: stop a: acknowledge www.maximintegrated.com maxim integrated 76 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
uart bypass mode in uart bypass mode, the control channel acts as a full-duplex 9.6kbps to 1mbps link that forwards uart commands across the serial link without responding to the packets themselves. set ms high to enter bypass mode (wait 1ms after setting bypass mode if the c is connected on the deserializer side). bypass uses bit rates from 9.6kbps to 1mbps. do not send a logic-low value longer than 100s when using the gpi/gpo functionality. device address the serializer/deserializer both have a 7-bit-long slave address stored in registers 0x00 and 0x01. the bit follow - ing a 7-bit slave address is the r/w bit, which is low for a write command and high for a read command. the default slave address is 0x80. after startup, a microcontroller can reprogram the slave address as needed. spread spectrum program the ss bits in the serializer to turn on spread spectrum in the serializer ( table 9 ). if the deserializer driven by the serializer has programmable spread spectrum, do not enable spread for both at the same time or their interaction cancels benefits. the deserializer tracks the serializers spread and passes the spread to the deserializer output. some spread-spectrum ampli - tudes can only be used at lower pclkin frequencies ( table 10 ). when the spread spectrum is turned on or off, the serial link stops for several microseconds and then restarts in order for the deserializer to lose and relock to the new serial-data stream. changing the spread- spectrum amplitude does not cause a loss of lock. manual programming of the spread-spectrum divider by default, autodetection of the pclkin operation range guarantees a spread-spectrum modulation frequency within 20khz to 40khz. additionally, manual configura - tion of the sawtooth divider (sdiv: 0x03,d[5:0]) allows the user to set a modulation frequency (typically 20khz) according to the pclkin frequency. equation: relation of modulation rate to the pclkin frequency: f m = f pclkin /(mod x sdiv) where:f m = modulation frequency f pclkin = pclkin frequency mod = modulation coefficient given in table 11 sdiv = 6-bit sdiv setting, manually programmed by the c bws = 0 mode, pclkin frequency (mh z ) bws = 1 mode, pclkin frequency (mh z ) serial link bit rate (mbps) available spread rates < 33.3 (dbl = 0) < 25 (dbl = 0) < 1000 all rates available < 66.6 (dbl = 1) < 50 (dbl = 1) 33.3 to 58 (dbl = 0) 25 to 43.5 (dbl = 0) 1000 1.5%, 1%, 0.5% 66.6 to 116 (dbl = 1) 50 to 87 (dbl = 1) table 10. spread limitations table 9. output spread ss spread (%) 000 power-up default (no spread spectrum) 001 0.5% spread spectrum 010 1.5% spread spectrum 011 2% spread spectrum 100 no spread spectrum 101 1% spread spectrum 110 3% spread spectrum 111 4% spread spectrum www.maximintegrated.com maxim integrated 77 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
to program the sdiv setting, first look up the modulation coefficient according to the desired bus-width and spread- spectrum settings. solve the above equation for sdiv using the desired pixel clock and modulation frequencies. if the calculated sdiv value is larger than the maximum allowed sdiv value in table 11 , set sdiv to the maximum value. board layoutpower-supply circuits and bypassing the serializer uses an avdd and dvdd of 1.7v to 1.9v. all inputs and outputs, except for the serial output, derive power from an iovdd of 1.7v to 3.6v that scales with iovdd. proper voltage-supply bypassing is essential for high-frequency circuit stability. high-frequency signals separate the lvcmos logic signals and cml/coax high - speed signals to prevent crosstalk. use a four-layer pcb with separate layers for power, ground, cml/coax, and lvcmos logic signals. layout stp-pcb traces close to each other for a 100 differential characteristic imped - ance. the trace dimensions depend on the type of trace used (microstrip or stripline). note: two 50 pcb traces do not have 100 differential impedance when brought close together; the impedance goes down when the traces are brought closer. use a 50 trace for the single-ended output when driving coax. route the pcb traces for differential cml in parallel to maintain the differential characteristic impedance. avoid via arrays. keep pcb traces that make up a differential pair equal in length to avoid skew within the differential pair. esd protection esd tolerance is rated for human body model, iec 61000-4-2, and iso 10605. the iso 10605 and iec 61000-4-2 standards specify esd tolerance for electronic systems. the serial outputs are rated for iso 10605 esd protection and iec 61000-4-2 esd protection. all pins are tested for the human body model. the human body model discharge components are cs = 100pf and rd = 1.5k ( figure 27 ). the iec 61000-4-2 discharge compo - nents are cs = 150pf and rd = 330 ( figure 28 ). the iso 10605 discharge components are cs = 330pf and rd = 2k ( figure 29 ). table 11. modulation coefficients and maximum sdiv settings bws spread- spectrum setting (%) modulation coefficient (dec) sdiv upper limit (dec) 1 1 104 40 0.5 104 63 3 152 27 1.5 152 54 4 204 15 2 204 30 0 1 80 52 0.5 80 63 3 112 37 1.5 112 63 4 152 21 2 152 42 figure 29. iso 10605 contact discharge esd test circuit figure 27. human body model esd test circuit figure 28. iec 61000-4-2 contact discharge esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1m ? r d 1.5k ? c s 100pf c s 150pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 330 ? storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 2k ? c s 330pf www.maximintegrated.com maxim integrated 78 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
compatibility with other gmsl devices the device is designed to pair with the max96705C max96711 family of devices, but interoperates with any gmsl device. see table 12 for operating limitations. device coniguration and component selectioninternal input pulldowns the control and configuration inputs (except three-level inputs) include a pulldown resistor to gnd; external pull - down resistors are not needed. three-level coniguration inputs conf1 and conf0 are three-level inputs that control the serial interface configuration and power-up defaults ( table 13 ). connect conf1 or conf0 to iovdd to set a high level, to gnd to set a low level, or open to set a mid level. for digital control, use three-state logic to drive the three-level logic inputs. conf pin values are latched at power-up or resuming from power-down mode. multifunction inputs the device has several inputs/outputs that serve multiple functions. gpo/him functions as the gpo output, and as a configuration pin. on power-up, or when reverting from a power-down state, the pins act as the him input. after latching the input state, the pin becomes the gpo output. connect a configuration input through a 30k resistor to iovdd to set a high level. leave the configuration input open to set a low level. in addition, several multifunction pins are controlled by the lccen input. when lccen = 1, the local control channel (rx/sda, tx/scl) is active, and the gpio1/ bws and ms/hven pins behave as gpio1 and the ms input respectively. when lccen = 0, the local control channel is disabled, and these pins operate as their alter - nate function (dbl, bws, hven inputs). serializer feature gmsl deserializer hsync/vsync encoding if feature not supported in the deserializer, turn off in the serializer. i 2 c to i 2 c if feature not supported in the deserializer, use uart to i 2 c or uart to uart. packet control channel if feature not supported in the deserializer, use legacy control channel. crc error detection if feature not supported in the deserializer, turn off in the serializer. double input if feature not supported in the deserializer, data is output as a single word at half the input frequency. use crossbar switch to correct input mapping. coax if feature not supported in the deserializer, connect unused serial input through 200nf and 50 in series to avdd, and set the reverse control-channel amplitude to 100mv. i 2 s encoding if supported in the deserializer, disable i 2 s in the deserializer. high-bandwidth mode if feature not supported in the deserializer, turn off in the serializer. high-immunity mode if feature not supported in the deserializer, turn off in the serializer. low-speed mode if supported in the deserializer, set drs to 0 in the deserializer. table 12. feature compatibility table 13. three-level configuration input map conf1 conf0 cxtp (out+/out- output type) es (pclkin latch edge) i2csel (control-channel type) low low 1 (coax) 1 (falling) 1 (i 2 c o i 2 c) low mid 1 (coax) 1 (falling) 0 (uart to i 2 c/uart) low high 1 (coax) 0 (rising) 1 (i 2 c to i 2 c) mid low 1 (coax) 0 (rising) 0 (uart to i 2 c/uart) mid mid 0 (stp) 1 (falling) 1 (i 2 c to i 2 c) mid high 0 (stp) 1 (falling) 0 (uart to i 2 c/uart) high low 0 (stp) 0 (rising) 1 (i 2 c to i 2 c) high mid 0 (stp) 0 (rising) 0 (uart to i 2 c/uart) high high do not use do not use do not use www.maximintegrated.com maxim integrated 79 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
i 2 c/uart pullup resistors the i 2 c and uart open-drain lines require a pullup resistor to provide a logic-high level. there are tradeoffs between power dissipation and speed, and a compro - mise may be required when choosing pullup resistor values. every device connected to the bus introduces some capacitance even when the device is not in opera - tion. i 2 c specifies 300ns rise times (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the i 2 c/uart port timing section in the ac electrical characteristics table for details). to meet the fast-mode rise-time requirement, choose the pullup resistors so that rise time t r = 0.85 x r pullup x c bus < 300ns. the waveforms are not recognized if the transition time becomes too slow. gmsl supports i 2 c/uart rates up to 1mbps (uart-to-i 2 c mode) and 400kbps (i 2 c-to-i 2 c mode).ac-coupling capacitors voltage droop and the digital-sum variation (dsv) of transmitted symbols cause signal transitions to start from different voltage levels. because the transition time is fixed, starting the signal transition from different voltage levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the cml/coax receiver termination resistor (r tr ), the cml/coax-driver termi - nation resistor (r td ), and the series ac-coupling capacitors (c). the rc time constant for four equal-value series capacitors is (c x (r td + r tr ))/4. r td and r tr are required to match the transmission-line impedance (usually 100 differential, 50 single-ended). this leaves the capacitor selection to change the system time constant. use 0.2f or larger high-frequency, surface-mount ceramic capacitors with sufficient voltage rating to withstand a short to battery, to pass the lower speed reverse control-channel signal. use capacitors with a case size less than 3.2mm x 1.6mm to have lower-parasitic effects to the high-speed signal. cables and connectors interconnect for cml typically has a differential imped - ance of 100. use cables and connectors that have matched differential impedance to minimize impedance discontinuities. coax cables typically have a characteristic impedance of 50; contact the factory for 75 operation). table 14 lists the suggested cables and connectors used in the gmsl link. prbs the serializer includes a prbs pattern generator that works with bit-error verification in the deserializer. to run the prbs test, set prbsen = 1 (0x04, d5) in the deserializer, then in the serializer. to exit the prbs test, set prbsen = 0 (0x04, d5) in the serializer. the deserializer automatically ends prbs checking and sets the prbs_ok bit high. during prbs mode, the forward control channel is not available except to exit prbs mode if autoacknowledge is enabled in the deserializer; other - wise, the remote control channel is not available at all. to run the prbs with a 3gbps serdes, or when hibw = 1, first set the prbs_type bit = 0 in the max967xx. then set prbsen = 1 (0x04, d5) in the serializer and then in the deserializer. to exit the prbs test, set prbsen = 0 (0x04, d5) in the deserializer, then in the serializer. during prbs test, errb function changes to reflect prbs errors only. errb goes low when any prbs errors occur. errb goes high when the prbs error counter is reset when prbs_err is read. normal errb function resumes when exiting the prbs test. gpi/gpo gpo on the serializer follows gpi transitions on the deserializer. by default, the gpi-to-gpo delay is 0.35ms (max). keep the time between gpi transitions to a minimum 0.35ms. gpi_in the deserializer stores the gpi input state. gpo is low after power-up. the c can set gpo by writing to the set_gpo register bit. do not send a logic-low value on the deserializer rx/sda input (uart mode) longer than 100s in either base or bypass mode to ensure proper gpo/gpi functionality. vendor connector cable type rosenberger 59s2ax-400a5-y dacar 302 coax rosenberger d4s10a-40ml5-z dacar 538 stp nissei gt11l-2s f-2wme awg28 stp jae mx38-ff a-bw-lxxxxx stp table 14. suggested connectors and cables for gmsl www.maximintegrated.com maxim integrated 80 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
fast detection of loss-of-lock a measure of link quality is the recovery time from loss- of-synchronization. the host can be quickly notified of loss-of-lock by connecting the deserializers lock output to the gpi input (when pktcc_en = 0). if other sources use the gpi input, such as a touch-screen controller, the c can implement a routine to distinguish between inter - rupts from loss-of-sync and normal interrupts. reverse control-channel communication does not require an active forward link to operate and accurately tracks the lock status of the gmsl link. lock asserts for video link only and not for the configuration link. providing a frame sync (camera applications) the gpi and gpo provide a simple solution for camera applications that require a frame-sync signal from the ecu (e.g., surround-view systems). connect the ecu frame-sync signal to the gpi input and connect the gpo output to the camera frame-sync input. gpi/gpo have a typical delay of 275s in legacy mode and 21s in packet mode (with 5-bit crc). skew between multiple gpi/ gpo channels is 115s (max) in legacy mode and 21s (max) in packet mode. if a lower skew signal is required in legacy mode, connect the cameras frame-sync input to one of the serializers gpios and use an i 2 c broad - cast-write command to change the gpio output state. this has a maximum skew of 1.5s, independent from the used i 2 c bit rate. in packet-based control-channel mode, set gpi_comp_en = 1 in both the serializer and deserializer to turn on gpi/gpo compensation. this reduces the device-to-device skew to 0.35s. entering/exiting sleep mode the procedure for entering and exiting sleep mode depends on the location of the microcontroller, and the type of control-channel interface used. if wake up from a remote (deserializer) side microcontroller is not needed or desired, set the dis_rwake bit = 1 to shut down remote wake-up for further power savings. legacy control channel: to enter sleep mode, set sleep = 1. the device sleeps after 8ms. to wake up the device, send an arbitrary control-channel command to the serializer (the serializer does not send an acknowledge), wait for 5ms for the chip to power up and then set sleep = 0 to make the wake- up permanent. packet-based control channel: when c is on the deserializer side, set sleep = 1 in serializer. next set revccen = 0 in the deserializer to stop reverse-control transmission to the serializer. the device sleeps after 8ms. to wake up the serializer, first set revccen = 1, wait 8ms for the device to wake up and then set sleep = 0 to exit sleep mode permanently. when c is on the serializer side, first set sleep = 1 in the deserializer. if the deserializer must remain awake, switch to legacy control-channel mode. next, set sleep = 1 in the serializer. the device sleeps after 8ms. to wake up the device, send an arbitrary control- channel command to the serializer (the serializer does not send an acknowledge). wait for 5ms for the chip to power up and then set sleep = 0 to make the wake- up permanent. the deserializer wakes up and clears its sleep bit when serialization is enabled and it locks to the serializer. www.maximintegrated.com maxim integrated 81 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive downloaded from: http:///
/v denotes an automotive qualified product. +denotes a lead(pb)-free/rohs-compliant package. *ep = exposed pad. part number temp range pin-package max96705gtj/v+ -40c to +115c 32 tqfn-ep* conf1 conf0 rx/sda tx/scl/dbl out+ lccen dout[11:0] pclkout in+ in- gpi max96706 rx/sda tx/scl camera application lock max96705 din[11:0] pclkin note: not all pullup/pulldown resistors are shown. see pin description for details. sdascl gpu ecu din[11:0] pclk din14/hs pclk din[11:0] camera hs i 2 c din15/vs vs sdascl ms/hven fsynclock out- 49.9 49.9 k 49.9 45.3k 4.99k lmn0 errb err dout12/hs hs dout13/vs vs lfltb lflt i2csel = 1, cx/tp = 1 typical application circuits ordering information max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive www.maximintegrated.com maxim integrated 82 downloaded from: http:///
revision history revision number revision date description pages changed 0 12/15 initial release maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. ? 2015 maxim integrated products, inc. 83 max96705 16-bit gmsl serializer with high-immunity/ bandwidth mode and coax/stp cable drive for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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