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? semiconductor components industries, llc, 2013 1 publication order number: march 2017 - rev. p0 FAN604 FAN604 offline quasi - resonant pwm controller the FAN604 is an advanced pwm controller aimed at achieving power density of 10w/in 3 in universal input range ac/dc flyback isolated power supplies. it incorporates quasi - resonant (qr) control with proprietary valley switching with a limited frequency variation. qr switching provides high efficiency by reducing switching losses while valley switching with a limited frequency v ariation bounds the frequency band to overcome the inherent limitation of qr switchin g . FAN604 features mwsaver? burst mode operation with extremely low operating current (300 a) and significantly reduces standby power consumption to meet the most stringe nt efficiency regulations such as energy stars 5 - star level and coc tier ii specifications . FAN604 includes several user configurable features aimed at optimizing efficiency, emi and protections. FAN604 has a wide blanking frequency range that improves light load efficiency and eliminating audio noise for adaptive application . it incorporates user - configurable constant current reference , which allows controlling the maximum output current from primary - side , thereby optimizing transformer design to improv e the overall efficiency . it also includes several rich programmable protection features such as over - voltage protection (ovp), p recise constant o utput current regulation (cc) . features ? higher average efficiency by quasi - resonant switching operation with wide blanking time range ? wide input and output conditions achieve high power density power supply ? optimization transformer design for adaptive charger application ? user configurable constant current reference (ccr) to limit the maximum output current ? precise constant output current regulation w ith programmable line compensation ? mws aver? t echnology for ultra low standby power consumption (<20 mw) ? forced and inherent frequency modulation of valley switching for low emi emissions and common mode noise ? bui lt - in and user configurable over - voltage protection (ovp), under - voltage protection (uvp) and over - temperature protection (otp) ? programmable over - temperature - protection through external ntc resistor ? fully programmable brown - in and browno ut protection ? built - in high - voltage s tartup to reduce external components typical applications ? battery charges for smart phones, feature phones, and tablet pcs ? ac - dc adapters for portable devices or battery chargers that require cv/cc contro l www. onsemi.com marking diagram z : assembly p lant c ode x: year c ode y : week c ode tt : die r un c ode t: package type (m=soic ) m : m anufacture flow code pin connections (top view) ordering information see detailed ordering and shipping information in the package dimensions section on page 20 of this data sheet. z x y t t 6 0 4 t m 1 1 0 h v n c c s g n d f b s d 1 3 2 7 6 8 f a n 6 0 4 m x v d d 4 v s 5 9 1 0 g a t e c c r
FAN604 www. onsemi.com 2 figure 1 FAN604 typical application v o d r c o c s n p n p d s n p r s n p c b l k 2 n s n a r v s 1 r v s 2 c v s l f c b l k 1 a c i n b r i d g e h v g a t e c s v d d v s g n d f b c s n p r s n s r f 1 r f 2 c v d d c c s f r c s _ c o m p r c s r g f r g r d g p h o t o c o u p l e r p h o t o c o u p l e r s h u n t r e g u l a t o r r b i a s 2 r b i a s 1 r c o m p c c o m p 1 c c o m p 2 r h v 1 c c r s d c f b t x c h o k e f u s e r c c r c c c r r h v 2 d a u x x c f a n 6 0 4 r s d n t c
FAN604 www. onsemi.com 3 pin function description pin no. pin name description 1 hv high voltage. this pin connects to d c bus for high - voltage startup. 2 nc no connect. 3 cs current sense. this pin connects to a current - sense resistor to sense the mosfet current for peak - current - mode control for output regulation. the current sense information is also used to estimate the output current for cc regulation. 4 gate pwm signal ou tput . this pin has an internal totem - pole output driver to drive the power mosfet. the gate driving voltage is internally clamped at 7.5 v . 5 vdd p ower s upply. ic operating current and mosfet driving current are supplied through this pin. this pin is typically connected to an external vdd capacitor. 6 vs voltage sense. the vs voltage is used to detect resonant valleys for quasi - resonant switching. this pin detects the o utput voltage information and diode current discharge time based on the auxiliary winding voltage. it also senses input voltage for brown - out protection. 7 ccr constant current reference. this pin connects to external resistor to program the reference voltage of constant output current. 8 sd shut down. this pin is implemented for external over - temperature - protect by connecting ntc thermistor. 9 fb feedback. typically opto - coupler is connected to this pin to provide feedback information to the internal pwm comparator. this feedback is used to control the duty cycle in cv regulation. 10 gnd ground. figure 2 FAN604 block diagram 5 . 2 5 v z f b f b c s l e b v d d h v s t a r t - u p h v v s 7 c c r 1 s / h s / h = s a m p l i n g a n d h o l d v a l l e y d e t e c t i o n f o r c e d f r e q u e n c y m o d u l a t i o n v c s - l i m i o e s t i m a t o r v s o v p f a u l t o s c v s u v p f a u l t 3 t d i s t d i s 6 9 v f b v d d o v p f a u l t v v d d - o v p v d d u v l o 1 7 . 2 v / 5 . 5 v 5 d e b o u n c e v d v s _ s h d c q q c l k v d d d r i v e r c o n t r o l g a t e m a x i m u m o n t i m e 4 v s u v p f a u l t b u r s t / g r e e n m o d e v f b v d d o v p f a u l t 1 0 g n d p e a k c u r r e n t a u t o - r e s t a r t p r o t e c t i o n o t p f a u l t v s o v p f a u l t b r o w n o u t v d d u v l o v d d u v l o v c s v c s i c o m p v c c r i c c r 5 v b r o w n i n h v v n v s v n v s i s d 5 v s d f a u l t v s d - t h 8 s d v c s f a u l t s d f a u l t v s p r o t e c t i o n 5 v a v c s p r o t e c t i o n v c s f a u l t v c s a v - c c
FAN604 www. onsemi.com 4 maximum ratings 1. all voltage values, except differential voltages, are given with respect to gnd pin. 2. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device . 3. es d ratings including hv pin: hbm= 2 .0 kv, cdm= 0.75 kv . recommended operating ranges 4. the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditio ns are specified to ensure optimal performance. on does not recommend exceeding them or designing to absolute maximum ratings. rating symbol value unit maximum voltage on hv pin v hv 500 v dc supply voltag e v v dd 30 v maximum voltage on gate pin v gete - 0.3 to 30 v maximum voltage on low power pins (except pin 1, pin 4, pin 5) v max - 0.3 to 6 v power dissipation (t a =25 ? c ) p d 850 mw thermal resistance (junction - to - a mbient ) ja 1 40 ? c/w thermal resistance (junction - to - top ) jt 1 3 ? c/w operating junction temperature t j - 40 to + 150 ? c storage temperature range t stg - 40 to + 150 ? c human body model, jedec:jesd22_a114 (except hv p in ) esd 2 .0 kv charged device model, jedec:jesd22_c101 (except hv p in ) 0 .75 rating symbol min max unit hv pin supply voltage v hv 50 400 v vdd pin supply voltag e v v dd 6 25 v vs pin supply voltage v vs 0 .65 2.3 v cs pin supply voltage v cs 0 0.9 v fb pin supply voltage v fb 0 5.25 v ccr pin supply voltage v ccr 0.2 1 .7 v sd pin supply voltage v sd 0 5 v operating temperature t a - 40 +85 ? c
FAN604 www. onsemi.com 5 electrical characteristics f or typical values t j = 25 c, for min/max values t j = - 40 c to 125 c , v dd = 15 v ; unless otherwise noted. parameter test conditions symbol min typ max unit hv section supply current drawn from hv p in v hv =120 v, v dd =0 v i hv 1.2 2.0 10 ma leakage current drawn from hv pin v hv = 5 00 v, v dd =v dd - off +1 v i hv - lc 0 0.8 10 a brown - in threshold voltage r hv = 150 k , v in =80v ac v brown - in 100 110 120 v v dd section turn - o n threshold voltage v dd rising v dd - on 15. 3 1 7.2 18. 7 v turn - o ff threshold voltage v dd falling v dd - off 5.0 5.5 5.7 v threshold voltage for hv startup t j = 25 ? c v dd - hv - on 4.1 4 .7 5.4 v startup current v dd =v dd - on - 0.16 v i dd - st - 300 4 50 a operating supply current v cs =5.0 v, v v s =3 v, v fb =3 v c gate =1nf i dd - op - 2 3 ma burst - mode operating supply current v cs =0.3 v, v v s =0 v, v fb =0 v; v dd =v dd - on ? v dd - ovp ? 10 v, c gate =1nf i dd - b urst - 300 600 a v dd over - voltage - protection level t j = 25 ? c v vdd - ovp 27.5 29.0 29.5 v v dd over - voltage - protection debounce time t d - vddovp - 70 105 s oscillator section maximum blanking frequency v fb > v fb - bnk - h f bnk - max 1 25 1 3 0 1 35 khz minimum blanking frequency v fb < v fb - bnk - l f bnk - min 16.5 18.5 20.5 khz minimum frequency v vs = 1v f osc - min 15 17 19 khz forced frequency modulation range v fb> vfb - burst -- h t fm - range 2 10 265 3 10 ns forced frequency modulation period t fm - period 2 .1 2.5 2.9 m s feedback input section fb p in input impedance z fb 39 42 45 k internal voltage attenuator of fb p in ( note 5 ) a v 1/3 1/ 3.5 1/4 v/v fb p in pull - u p voltage fb pin open v fb - o pen 4. 55 5. 25 5. 90 v frequency foldback starting/stopping v fb t j = 25 ? c v fb - bnk - h 2.1 0 2.2 5 2.40 v t j = 25 ? c v fb - bnk - l 1.1 0 1.2 5 1.40 v fb threshold to en able/disable gate drive in burst mode v fb rising v fb - burst - h 0.65 0.75 0.85 v v fb falling v fb - burst - l 0.60 0.70 0.80 v
FAN604 www. onsemi.com 6 electrical characteristics (continued) f or typical values t j = 25 c, for min/max values t j = - 40 c to 125 c , v dd = 15 v ; unless otherwise noted. parameter test conditions symbol min typ max unit voltage - sense section maximum vs source current capability i vs - max - - 3 ma vs sampling blanking time 1 after gate pin pull - low v fb falling and v fb < 2.0v t vs - bnk 1 0. 8 4 1. 0 1. 23 s vs sampling blanking time 2 after gate pin pull - low v fb rising and v fb > 2.2v t vs - bnk 2 1. 4 5 1.8 2.1 5 s delay from vs voltage zero crossing to pwm on ( note 5 ) v vs =0v, c gate =1nf t zcd - to pwm 175 ns vs s ource current threshold to enable brown - out i vs - brown - out 3 6 0 450 5 3 0 a brown - out debounce time t d - brown - out 12.5 16.5 21 ms output over - v oltage - protection with vs sampling voltage v vs - ovp 2.2 2.3 2.4 v output over - v oltage - protection debounce pulse counts n vs - ovp - 2 - pulse output under - v oltage - protection with vs sampling voltage t j = 25 ? c v vs - uvp 0.6 25 0.65 0 0.675 v output over - v oltage - protection debounce pulse counts n vs - uvp - 2 - pulse output under - voltage protection blanking time at start - up t vs - uvp - blank 25 40 55 ms a uto - r estart cycle counts when extend auto - restart mode is triggered v v s < v vs - uvp n vdd - hiccup - 2 - cycle over - t emperature p rotection section threshold temperature for over - temperature - protection ( note 5 ) t otp - 1 4 0 - ? c current - sense section current limit threshold voltage fb pin open v cs - lim 0.8 65 0. 8 9 0 0 . 9 15 v high threshold voltage of current sense v fb > v fb - bnk - l v cs - imin - h 0. 39 0.4 4 0.5 1 v middle threshold voltage of current sense v fb = 1v , t j = 25 ? c v cs - imin - m 0.30 0.35 0.40 v low threshold voltage of current sense v fb < v fb - burst - h , t j = 25 ? c v cs - imin - l 0.2 1 0. 25 0.2 9 v gate output turn - off delay ( note 5 ) t pd - 50 100 ns leading - e dge b lanking t ime ( note 5 ) t leb - 150 200 ns
FAN604 www. onsemi.com 7 5. design guaranteed. electrical characteristics (continued) f or typical values t j = 25 c, for min/max values t j = - 40 c to 125 c , v dd = 15 v ; unless otherwise noted. parameter test conditions symbol min typ max unit shut - down function section sd pin source current i sd 90 103 110 a threshold voltage for shut - down function enable v sd - th 0.95 1.0 0 1.05 v debounce time for shut - down function t d - sd 200 400 600 s r atio between threshold voltage and source current z sd - th 8.5 10 11 k hysteresis of threshold voltage for shut - down function enable v sd - th - st 1.30 1.35 1.40 v duration of v sd - th - st at startup t sd - st 0. 4 1. 0 1. 6 ms constant current correction section high line compensation current v in = 264 v rms i comp - h 90 100 110 a low line compensation current v in = 90 v rms i comp - l 3 2 36 40 a constant current estimator section ccr pin source current i ccr 1 8.2 20 21 .8 a constant current control reference offset voltage ( note 5 ) v ref_cc_offset 0.8 v peak value amplifying gain ( note 5 ) a pk 3.6 v/v fb cc pull - u p voltage cc ( note 5 ) v fb - cc - o pen 4.0 v internal voltage attenuator of fb cc ( note 5 ) a v - cc 0.444 v/v gate section gate output voltage low v gate - l 0 - 1.5 v internal gate pmos driver on v dd falling v dd - pmos - on 7.0 7.5 8.0 v internal gate pmos driver off v dd rising v dd - pmos - off 9.0 9.5 10.0 v rising time v cs =0 v, v s =0 v, c gate =1nf t r 100 135 180 ns falling time v cs =0 v, v s =0 v, c gate =1nf t j = 25 ? c t f 30 50 70 ns gate output clamping voltage v dd =25 v v gate - clamp 6.8 7.5 8.2 v maximum on time v fb =3v , v cs =0.3v t on - max 20 22 25 s
FAN604 www. onsemi.com 8 typical characteristics figure 3 turn - o n threshold voltage (v dd - on ) vs. temperature figure 4 turn - off threshold voltage (v dd - off ) vs. temperature figure 5 v dd over voltage - protection level ( v v dd - o v p ) vs. temperature figure 6 brown - in threshold voltage ( v brown - in ) vs. temperature figure 7 maximum blanking frequency (f bnk - max ) vs. temperature figure 8 m inimum blanking frequency (f bnk - min ) vs. temperature 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c)
FAN604 www. onsemi.com 9 figure 9 frequency foldback starting vfb ( v fb - bnk - h ) vs. temperature figure 10 frequency foldback stopping vfb ( v fb - bnk - l ) vs. temperature figure 11 vs sampling blanking time 1 ( t vs - bn k1 ) vs. temperature figure 12 vs sampling blanking time 2 ( t vs - bn k2 ) vs. temperature figure 13 output over - v oltage - protection ( v vs - ovp ) vs. temperature figure 14 output u nder - v oltage protection ( v vs - uvp ) vs. temperature 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c)
FAN604 www. onsemi.com 10 figure 15 current limit threshold voltage ( v cs - lim ) vs. temperature figure 16 high threshold voltage of current sense ( v cs - imin - h ) vs. temperature figure 17 ratio between threshold voltage and source current ( z sd - th ) vs. temperature figure 18 during of v sd - th - st at startup ( t sd - st ) vs. temperature figure 19 ccr pin source current (i ccr ) vs. temperature figure 20 maximum on time ( t on - max ) vs. temperature 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c) 0.9 0.95 1 1.05 1.1 - 40 - 30 - 15 0 25 50 75 85 100 125 normalized temperature ( c)
FAN604 www. onsemi.com 11 applications information fan60 4 is an offline pwm controller which operates in a quasi - resonant (qr) mode and significantly enhances sys tem efficiency and power density. its control method is based on the load condition (valley switching with fixed blanking time at heavy load and valley switching with variable blanking time at medium load) to maximize the efficiency. it offers constant output voltage (cv) regulation through opto - coupler feedback circuitry. line voltage compensation gain can be programmed by using an external resistor to minimize the effect of line voltage variation on output current regulation due to turn - off delay of the gate drive circuit. fan60 4 incorporates hv startup and accurate brown - in through hv pin. the brown - in voltage is programmed by using an external hv pin resistor. the constant current regulation ( ccr ), which sets the maximum output cu rrent level , is programmable via an external resistor connected to the ccr pin. protections such as v dd over - voltage protection (v dd ovp), v s over - voltage protection (v s ovp), v s under - voltage protection (v s uvp), internal over - temperature protection (otp), brownout protection and e xternally triggered shut - down (sd) function im prove reliability. basic operation principle quasi - resonant switching is a method to reduce primary mosfet switching losses low line is more effective . in order to perform qr turn - on of the primary mosfet, the valley of the resonance occurring between transformer magnetizing inductance (l m ) and mosfet effective output capacitance (c oss - eff ) must be detected. (eq. 1 ) (eq. 2 ) for heavy load condition (50%~100% of full load), the blanking time for the valley detection is fixed such that the switching time is between 1/f bnk - m ax and 1/f bnk - m ax + t resonance and primary side peak current will be modulated by voltage level of feedback. for the medium load condition (25%~50% of full load), the blanking time is modulated as a function of load current such that the upper limit of the blanking frequency varies fr om f bnk - max as load decreases where the blanking frequency reduction stop point is f bnk - min . for the light load condition (5%~25%) ), the blanking time for the valley detection is fixed such that the switching time is between f bnk - m in and f bnk - m in + t resonance and primary side peak current will be modulated by the function of v cs - imn modulation, as shown in figure 22 burst mode operation figure 21 shows when v fb drops below v fb - burst - l , the pwm output shuts off and the output voltage drops at a rate which is depended on the load current level. this causes the feedback voltage to rise. once v fb exceeds v fb - burst - h , fan60 4 resumes switching. w hen the fb voltage drops below the corresponding v cs - imi n - l , the peak currents in switching cycles are limited by v cs - imin - l regardless of fb voltage. thus, more power is delivered to the load than required and once fb voltage is pulled low below v fb - burst - l , switching stops again. in this manner, the burst mod e operation alternately enables and disables switching of the mosfet to reduce the switching losses. figure 21 burst - mode operation deep burst mode fan60 4 enters deep burst mode if fb voltage stays lower than v fb - burst - l for more than t deep - burst - entry (640 s). once FAN604 enters deep burst mode, the operating current is reduced to i dd - burst (300 a) to minimize power consumption. once feedback voltage is more than v fb - burst - h , power - on - reset occurs within a time period of t deep - burst - exit (25 s) and ic resumes switching with normal operating current, i dd - op . figure 22 frequency fold - back function parasitic trans mosfet oss eff c c c c ? ? ? ? - oss eff oss m resonance c l t ? ? ? ? 2 o u t p u t v o l t a g e v f b v f b - b u r s t - h v f b - b u r s t - l v c s - i m i n - l i p k v d s f b n k - m a x = 1 / t b n k - m i n t e x t t e x t t e x t f i x e d b l a n k i n g t i m e m o d u l a t e d b l a n k i n g t i m e t b n k t b n k t b n k f i x e d b l a n k i n g t i m e v f b f b n k - m i n = 1 / t b n k - m a x
FAN604 www. onsemi.com 12 valley detection there will be a logic propagation delay from vs zero - crossing detection (v s - zcd ) to ic gate turn on and a mosfet gate drives propagation delay from gate pin to mosfet turn on. we can assume the sum of these propagation delays to be t zcd - to - pwm ( 175ns ) , as shown in figure 23 . however, if 1/2 t f is l ong er than t zcd - to - pwm , the switching occurs away from the valley causing higher losses. the time period of resonant ringing is dependent on l m and c oss - eff. typically , the time period of resonance ringing is around 1~1.5 s depending on the system parameters. hence, the switching may occur at a point different from the valley depending on the system. when pcb layout is poor, it may cause noise on the vs pin. the vs pin needs to be in parallel with the capacitor (c vs ) less than 10 pf to filter the noise. inherent and forced frequency modulation typically, the bulk capacitor of flyback converter has a longer charging time in low line than in high li ne. thus, the voltage ripple (? v dc ) in low line is higher as shown in figure 24 . this large ripple results in 4~6% variation of the switching frequency in low line for a valley switched converter , the switching frequency could va ry accordingly . this frequency var iation s catters emi noise nearby frequency band, this is helpful to meet emi requirement easily. hence, the emi performance in low line is satisfied. however, in high line, the ripple is very small and consequent ly t he emi performance for high line may suffer. in order to maintain good emi performance for high line, forced frequency modulation is provided. FAN604 varies the valley switching point from 0 to t fm - range (265 ns) in every t fm - period (2.5 ms) as shown in figure 25 . since the drain voltage at which the switching occurs does not change much with this variation, there is minimum impact on the efficiency. figure 23 the valley detection circuit and behaior figure 24 inherent frequency modulation figure 25 forced frequency modulation r vs 1 r vs 2 v aux vs zero - crossing detection n a c vs vd c vs < 10 pf v a u x t o n t d t f / 2 0 v v s t z c d - t o - p w m g a t e v s z e r o - c r o s s i n g d e t e c t t f v d c v d c a c i n b r i d g e d i o d e l f c b l k 1 c b l k 2 v d s ? t r e s o n a n c e 2 6 5 n s v d c n v o i p k v d s
FAN604 www. onsemi.com 13 output voltage detection figure 26 shows the vs voltage is sampled (v s - sh ) after t vs - bnk of gate turn - off so that the ringing does not introduce any error in the sampling. FAN604 dynamically varies t vs - bnk with load. at heavy load, t vs - bnk =t vs - bnk1 (1.8 s) when v fb > v fb - bnk - h . at light - load, t vs - bnk =t vs - bnk2 (1. 0 s) when v fb < v fb - bnk - l . this dynamic variation ensures that vs sampling occurs after ringing due to leakage inductance has stopped and before secondary current goe s to zero. (eq. 3 ) figure 26 output voltage detection line voltage detection the FAN604 indirectly senses the line voltage through the vs pin while the mosfet is turned on , as illustrated in figure 27 mosfet turn - on period, the auxiliary winding voltage, v aux , is proportional to the input bulk capacitor voltage, v blk , due to the transformer coupling between the primary and auxiliary windings. during the mosfet conduction time, the line voltage detector clamps the vs pin voltage to v s - clamp (0 v), and then the current i vs flowing out of vs pin is expressed as: ( eq. 4 ) t he i vs current, reflecting the line voltage information, is used for brownout protect ion and cc control correction weighting. cv / cc pwm operation principle figure 27 shows a simplified cv / cc pwm control circuit of the FAN604 . the constant voltage (cv) regulation is implement ed in the same manner as the conventional isolated power supply, where the output voltage is sensed using a voltage divider and compared with the internal reference of the shunt regulator to generate a compensation signal. the compensation signal is transf erred to the primary side through an opto - coupler and scaled down by attenuator a v to generate a comv signal. this comv signal is applied to the pwm comparator to determine the duty cycle. the constant current (cc) regulation is implemented internally with primary - side control. the output current estimator calculates the output current using the transformer primary - side current and diode current discharge time. by comparing the estimated output current with internal reference signal, a comi signal is genera ted to determine the duty cycle. these two control signals, comv and comi, are compared with an internal sawtooth waveform (v saw ) by two pwm comparators to determine the duty cycle. figure 27 illustrates the outputs of two comparators, combined with an or gate, to determine the mosfet turn - off instant. either of comv or comi, the lower signal determines the duty cycle . d uring cv r egulation, comv determines the duty cycle while comi is saturated to high level. during cc regulation, comi determines the duty cycle while comv is saturated to high level. figure 27 simplified pwm control circuit and pwm operation for cv/cc regulation 2 1 2 sh - s vs vs vs s a o r r r n n v v ? ? g a t e v s t v s - b n k v s - s h p a vs blk vs n n r v i 1 ? c v c o m v c o m i v s a w g a t e c c f b z e r o c u r r e n t d e t e c t o r c s i o e s t i m a t o r p w m c o n t r o l l o g i c b l o c k a v v s v o v b l k 4 c o m v c o m i v s a w z c o m p g a t e z o f f t r i g o s c o n t r i g c c r 0 . 8 v v s l i n e v o l t a g e d e t e c t o r 5 v i v s l i n e s i g n a l n a r v s 1 r v s 2 0 v v a u x v a u x v s - c l a m p n p n s - v a u x = v b l k ( n a / n p )
FAN604 www. onsemi.com 14 primary - side constant current operation figure 28 shows the key waveforms of a flyback converter operation in dcm. the output current is estimated by calculating the averag e of output diode current in one switching cycle: (eq. 5 ) when the diode current reaches zero, the transformer winding voltage begins to drop sharply and vs pin voltage drops as well. when vs pin voltage drops below the v s - sh by more than 500 mv, zero current detection of diode current is obtained. the output current can be programmed by setting the resistor as of ccr : (eq. 6 ) when pcb layout is poor, it may cause noise on the ccr pin. the ccr pin needs to be in parallel with the capacitor (c ccr ) less than 4.7n f stabilizing the voltage against noise . line v oltage compensation the output current estimation is also affected by the turn - off delay of the mosfet as illustrated in figure 29 . the actual mosfets turn - off time is delayed due to the mosfet gate charge and gate drivers capability , resulting in peak current detection e rror as (eq. 7 ) where l m is the transformers primary side magnetizing inductance. since the output current error is proportional to the line voltage , the FAN604 incorporat es line voltage compensation to improve output current estimation accuracy . line information is obtained through the line voltage detector as shown in figure 27 . i comp is an internal current source, which is proportional to line voltage. the line compensation gain is programmed by using cs pin series resistor, r cs_comp , depending on the mosfet turn - o ff delay, t off.dly . i comp creates a voltage drop, v offset , across r cs_comp . this line compensation offset is proportional to the dc link capacitor voltage, v blk , and turn - off delay, t off.dly . figure 29 demonstrates the effect of the line compensation. figure 28 waveforms for estimate output current figure 29 effect of mosfet turn - off delay and line voltage compensation ff s p pk cc ref cs ff s p s dis pk cs cs o e n n a v r e n n t t v r i _ 1 2 1 1 2 1 ? ? ? ? ) 1 2 ( 1 _ _ offset cc ref ff p s pk cs o ccr ccr v e n n a r i i r ? ? ? ? ? ? ? dly off m blk pk ds t l v i . ? ? g a t e v s i o _ e s t m v c s - p k t o n t d i s t s t q r 1 . 8 s 5 0 0 m v v s - s h z e r o c u r r e n t d e t e c t 1 . 8 s 5 0 0 m v v s - s h i d i o d e v r e f _ c c i c c r v r e f _ c c z e r o c u r r e n t d e t e c t o r c s i o e s t i m a t o r p w m c o n t r o l l o g i c b l o c k v s v o v b l k 4 c o m i z c o m p g a t e z o f f t r i g o s c o n t r i g c c r n a r v s 1 r v s 2 v a u x n p n s s / h a p k v c s - p k c c c r r c c r t d i s v c c r a p k v c s - p k r c s r c s _ c o m p c c c r : 1 n f ~ 4 . 7 n f a c t u a l d i o d e c u r r e n t e s t i m a t e d d i o d e c u r r e n t g a t e c s c c s f r c s _ c o m p r c s i c o m p + - v o f f s e t i d s v o f f s e t - h v g s t o f f . d l y i d s r c s v c s v o f f s e t - l v g s t o f f . d l y i d s r c s v c s v g s v c s i d s r c s l o w l i n e h i g h l i n e t o f f . d l y i d s r c s i d s r c s i d s - s h r c s i d s p k r c s i d s p k n p / n s i d s - s h n p / n s v g s c c s f < 2 0 p f t d i s i d s r c s i d s r c s
FAN604 www. onsemi.com 15 ccm prevention t he constant current calculation logic is based on flyback converter operation in dcm. the output current is estimated by calculating the averag e of output diode current in one switching cycle . if flyback converter goes into ccm operation , the discharge time of magnetizing current will be fixed. once this discharge time is fixed, it will increase the average of output diode current . during the cc region, w hen output voltage becomes lower, the time that the magnetizing current decrease s down to zero is longer , as shown in figure 30 . FAN604 provides the lower operation frequency that can be down to 17 khz ( f osc - min ) to prevent the system goes into ccm operation . figure 30 the m inimum operation frequency hv startup and brown - in figure 31 shows the high - voltage (hv) startup circuit. an internal jfet provides a high voltage current source, whose characteristics are shown in figure 32 . to improve reliability and surge immunity, it is typical to use a r hv resistor between the hv pin and the bulk capacitor voltage. the actual current flowing into the hv pin at a given bulk capac itor voltage and startup resistor value is determined by the intersection point of characteristics i - v line and the load line as shown in figure 32 . during startup , the internal startup circuit is enabled and the bulk capacitor voltage supplies the current, i hv , to charge the hold - up capacitor, c vdd , through r hv . when the v dd voltage reaches v dd - on , the sampling circuit shown in figure 31 is turned on for t hv - det (100 s) to sample the bulk capacitor voltage. voltage across r ls is compared with reference which generates a signal to start switching. if brown - in condition is not detected within this time, switching does not start. equation 8 can be used to progra m the brown - in of the system. if line voltage is lower than the prog rammed brown - in voltage, FAN604 goes in auto - restart mode. (eq. 8 ) once switching starts, the internal hv startup circuit is disabled. during normal switching, the line voltage information is obtained from the i vs signal. once the hv startup circuit is disabled, the energy stored in c vdd supplies the ic operating current until the transformer auxiliary winding voltage reaches the nominal value. therefore, c vdd should be properly designed to prevent v dd from dropping below v dd - off threshold (typically 5.5 v) before the auxiliary winding bu ilds up enough voltage to supply v dd . during startup, the ic current is limited to i dd - st (300 a). figure 31 hv startup circuit figure 32 characteristics of hv pin v d s t o n t d f o s c - m i n i l m v i n n v o n v o n v o t d t d i o v o c v - c c c u r v e c c r e g i o n c v r e g i o n u v p ref ls hv jeft ls in v r r r r v ? ? ? ? ac l ine c dd hv vdd r hv + - v dd . on / v dd . off vdd good r ls = 1 . 2 k 8 5 c x 1 c x 2 s 1 s 2 brown in + - v ref = 0 . 845 v v dd = v dd - on ( 17 . 2 v ) r jfet = 6 . 4 k 5 0 0 v 1 0 0 v 2 0 0 v 3 0 0 v 4 0 0 v 1 0 m a i h v 1 . 2 m a 2 m a v h v blk hv v r blk v
FAN604 www. onsemi.com 16 protections the FAN604 protection functions include vdd over - voltage protection (vdd - ovp), brownout protection, vs over - voltage protection (vs - ovp), vs under - voltage protection (vs - uvp), and ic internal over - temperature protection (otp). the vdd - ovp, brownout protection , vs - ovp and otp are implemented with auto - restart mode. the vs - uvp is implemented with extend auto - restart mode. when the auto - restart mode protection is triggered, switching is terminated and the mosfet remains off, causing vdd to drop because of ic operating cu rrent i dd - op (2 ma). when vdd drops to the vdd turn - off voltage of v dd - off (5.5 v), operation current reduces to i dd - burst (300 a). when the vdd voltage drops further to v dd - hv - on , the protection is reset and the supply current drawn from hv pin begins to charg e the vdd hold - up capacitor. when vdd reaches the turn - on voltage of v dd - on (17.2 v), the FAN604 resumes normal operation. in this manner, the auto - restart mode alternately enables and disables the switching of the mosfet until the abnormal condition is eliminated as shown in figure 33 . when the extend auto - restart mode protection is triggered via vs under - voltage protection (vs - uvp), switching is terminated and the mosfet remains off, causing vdd to drop. while v dd drops t o v dd - hv - on for hv startup circuit enable, then ic enters extend auto - restart period with two cycles as sho wn figure 34 . during extend auto - restart period, vdd voltage swings between v dd - on and v dd - hvon without gate switching, and ic operation current is reduced to i dd - burst of 300 a for slowing down the vdd capacitor discharging slope. as extend auto - restart period ends, normal operation resumes. figure 33 auto - restart mode operation figure 34 extend auto - restart mode operation vdd over - voltage - protection (vdd - ovp) vdd over - voltage protection prevents ic damage from over - voltage stress. it is operated in auto - restart mode. when the vdd voltage exceeds v dd - ovp (29.0 v) for the de - bounce time, t d - vddovp (70 s), due to abnormal condition, the protection is tr iggered. this protection is typically caused by an open circuit of secondary side feedback network. brownout protection line voltage information is used for brownout protection. when the i vs current out of the vs pin during the mosfet conduction time is l ess than 450 a for longer than 16.5 ms, the brownout protection is triggered. the input bulk capacitor voltage to trigger brownout protection is given as (eq. 9 ) ic internal over - temperature - protection (otp) the internal temperature - sensing circuit disables the pwm output if the junction temperature exceeds 140c (t otp ) and the FAN604 enters auto - restart mode protection. v dd - off v dd - on v dd v ds power o n operating c urrent i dd - op v dd - o vp fault r emoved fault o ccurs v dd - hv - on i dd - brust v dd - off v dd - on v dd v ds power o n operating c urrent i dd - op vs uvp occurs v dd - hv - on i dd - brust extend auto - restart p a vs blk.bo n n r a v 1 450 2 . 1 ? ? ? ?
FAN604 www. onsemi.com 17 vs over - voltage - protection (vs - ovp) vs over - voltage protection prevents damage caused by output over - voltage condition. it is operated in auto - restart mode. figure 35 shows the internal circuit of vs - ovp protection. when abnormal system conditions occur, which cause vs sampling voltage to exceed v vs - ovp ( 2 . 3 v ) for more than 2 consecutive switching cycles (n vs - ovp ), pwm pulses are disabled and FAN604 enters auto - restart protection. vs over - voltage condition s are usually caused by open circuit of the secondary side feedback network or a fault condition in the vs pin voltage divider resistors. for vs pin voltage divider design, r vs1 is obtained from equation 9 , and r vs2 is determined by the desired vs - ovp protection function as (eq. 10 ) figure 35 vs - ovp protection circuit vs under - voltage - protection (vs - uvp) in the event of an output short, output voltage will drop and the primary peak current will increase. to prevent operation for a long time in this condition, FAN604 incorporates under - voltage protection through vs pin. figure 36 shows the internal circuit for vs - uvp. by sampling the auxiliary winding voltage on t he vs pin at the end of diode conduction time, the output voltage is indirectly sensed. when v s sampling voltage is less than v vs - uvp (0.65 v) and longer than de - bounce cycles n vs - uvp , vs - uvp is triggered and the FAN604 enters extend auto - restart mode. to avoid vs - uvp triggering during the startup sequence, a startup blanking time, t vs - uvp - blank (4 0 ms), is included for system power on. for vs pin voltage divider design, r vs1 is obtained from equation 9 and r vs2 is determined by equation 10 . v o - uvp can be determined by equation 11 . (eq. 11 ) figure 36 vs - uvp protection circuit externally triggered shutdown (sd) when v dd is v dd - on , shut - down comparing level is v sd - th - st (1.35v) , after the startup time t sd - st (1ms) , the comparing level is changed to v sd - th (1.0 v) . by pulling down sd pin voltage below the v sd - th (1.0 v) shutdown can be externally triggered and the FAN604 will enter auto - restart mode protection. it can be also used for external over - temperature - protection by connecting a ntc thermistor between the shutdown (sd) programming pin and ground. an i nternal constant current source i sd (103 a) creates a vol tage drop across the thermistor. the r esistance of the ntc thermistor becomes smaller as the ambient temperature increases, which reduces the voltage drop across the thermistor. sd pin voltage is sampled every gate cycle when v fb > v fb - burst - h and sampled continuously when v fb < v fb - burst - l . when the voltage at sd pin is sampled to be below the threshold voltage, v sd - th (1.0 v), for a de - bounce time of t d - sd (400 s), auto - restart protection is triggered. a capacitor may also be placed in parallel with the ntc thermistor to further improve the noise immunity. the capacitor should be designed such that sd pin voltage is more than v sd - th - st within the time of t sd - st . figure 37 external otp using sd pin 1 1 1 2 ? ? ? ? s a ovp vs ovp o vs vs n n v v r r s / h d q p w m c o u n t e r a u t o r e s t a r t v s v a u x n a r v s 1 r v s 2 2 . 3 v v s - o v p d e b o u n c e t i m e uvp vs vs vs a s uvp o v r r n n v ? ? ? ? ? ) 1 ( 2 1 s / h d q p w m c o u n t e r e x t e n d a u t o r e s t a r t v s n a r v s 1 r v s 2 0 . 6 5 v v s - u v p d e b o u n c e t i m e v a u x 1 0 3 a 5 v s d a u t o - r e s t a r t n t c t h e r m i s t o r d e b o u n c e c s d c s d : 1 n f ~ 2 0 n f v s b l a n k i n g v f b < v f b - b u r s t - l v d d t s d - s t v d d - o n v s d - t h - s t v s d - t h v s d
FAN604 www. onsemi.com 18 pulse - by - pulse current limit during startup or overload condition, the feedback loop is saturated to high and is unable to control the primary peak current. to limit the current during such conditions, FAN604 has pulse - b y - pulse current limit protection which forces the gate to turn off when the cs pin voltage reaches the current limit threshold, v cs - lim (0. 8 9 v). secondary - side diode shot protection when the secondary - side diode is damaged, the slope of the primary - side peak current will be sharp within leading - edge blanking time. to limit the current during such conditions, FAN604 has secondary - side diode short protection which forces the gate to turn off when the cs pin voltage reaches 1.6 v. after one switching cycle, it will operate in auto - restart mode as shown in fig ure 38 . current sense short protection current sense short protection prevents damage caused by cs pin open or short to ground. after two switching cycle, it will operate in auto - restart mode. fig ure 38 shows the internal circuit of current sense short protection. when abnormal system conditions occur, which cause cs pin voltage lower than 0.2 v after de - bounce time (t cs - short ) for more than 2 consecutive switching cycles, pwm pulses are disabled and FAN604 enters auto - restart protection. the i cs - short is an internal current source, which is proportional to line voltage. the de - bounce time (t cs - short ) is created by i cs - short , capacitor (2 pf) and threshold voltage ( 3.0 v). this de - bounce time (t cs - short ) is inversely proportional to the dc link capacitor voltage, v blk . fig ure 38 current sense protection circuit 2 p f 3 . 0 v i c s - s h o r t 0 . 2 v c c s f r c s _ c o m p r c s i d s g a t e c s d q p w m c o u n t e r a u t o r e s t a r t n p g a t e t c s - s h o r t v b l k 1 . 6 v 0 . 8 9 v d q c o u n t e r a u t o r e s t a r t p w m l e b p u l s e - b y - p u l s e
FAN604 www. onsemi.com 19 p cb layout guideline print circuit board (pcb) layout and design are very import for switching power supplies where the voltage and current change with high dv/dt and di/dt. good pcb layout minimizes excessive emi and prevent the power supply from being disrupted during surge/ esd tests. the following guidelines are recommended for layout designs. ? to improve emi performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitors c blk1 and c blk2 first, then to the transformer and mo sfet. ? t he primary - side high - voltage current loop is c blk2 - transformer - mosfet - r cs - c blk2 . the area enclosed by this current loop should be as small as possible . the trace for the control signal (fb, cs, vs and gate ) should not go across this primary high - voltage current loop to avoid interference. ? p lace r hv for protection against the inrush spike on the hv pin (150k is recommended). ? r cs should be connected to the ground of c blk2 directly. keep the trace short and wide (trace 4 to 1 ) and place it close to the cs pin to reduce switching noise. high - voltage traces related to the drain of mosfet and rcd snubber should be away from control circuits to prevent unnecessary interference. if a heat sink is used for the mosfet, connect this heat sink to gro und. ? a s indicated by 2 , the area enclosed by the transformer auxiliary winding, d aux and c vdd , should also be small. ? place c vdd , c vs , r vs2 , c fb , r ccr , c ccr , r cs_comp and c csf close to the controller for good decoupling and low switching noise. ? a s indicated by 3 , the ground of the control circuits should be connected as a single point first, then to other circuitry. ? connect ground by 3 to 2 to 4 to 1 sequence. this helps to avoid common impedance interference for the sense signal. ? regarding the es d discharge path, use the shortcut pad between ac line and dc output (most recommended). a nother method is to discharge the esd energy to the ac line through the primary - side main ground 1. b ecause esd energy is delivered from the secondary side to the primary side through the transformer stray capacitor or the y capacitor, the controller circuit should not be placed on the discharge path. 5 shows where the point - discharge route can be placed to effectively bypass the static electricity energy. ? for the surge path, select fusible resistor of wire wound type to reduce inrush current and surge energy and use input filter (two bulk capacitors and one inductance) to share the surge energy. figure 39 recommended layout for FAN604 v o d r c o c s n p n p d s n p r s n p c b l k 2 n s n a r v s 1 r v s 2 c v s l f c b l k 1 a c i n b r i d g e h v g a t e c s v d d v s g n d f b c s n p r s n s r f 1 r f 2 c v d d c c s f r c s _ c o m p r c s r g f r g r d g p h o t o c o u p l e r p h o t o c o u p l e r s h u n t r e g u l a t o r r b i a s 2 r b i a s 1 r c o m p c c o m p 1 c c o m p 2 r h v 1 c c r s d c f b t x c h o k e f u s e r c c r c c c r r h v 2 d a u x x c f a n 6 0 4 r s d n t c 1 2 3 4 c y 5 5
FAN604 www. onsemi.com 20 ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d device operating temperature range package shipping ? FAN604 mx - 4 0 ? c to + 12 5 ? c 10 - lead, small outline package (soic), jedec ms - 012, .150 - inch narrow body tape & reel

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