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approximate scale 1:1 package lp, 16 pin tssop with exposed thermal pad description designed for pwm (pulse width modulated) control of dc motors, the a3950 is capable of peak output currents to 2.8 a and operating voltages to 36 v. phase and enable input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied pwm control signals. internal synchronous rectification control circuitry is provided to lower power dissipation during pwm operation. internal circuit protection includes motor lead short-to- supply / short-to-ground, thermal shutdown with hysteresis, undervoltage monitoring of v bb and v cp , and crossover-current protection. the a3950 is supplied in a thin profile (<1.2 mm overall height) 16 pin tssop package (lp), and a very thin (0.75 mm nominal height) qfn package. both packages provide an exposed pad for enhanced thermal dissipation, and are lead (pb) free with 100% matte tin leadframe plating. a3950ds, rev. 7 features and benefits ? low r ds(on) outputs ? overcurrent protection ? motor lead short-to-supply protection ? short-to-ground protection ? sleep function ? synchronous rectification ? diagnostic output ? internal undervoltage lockout (uvlo) ? crossover-current protection dmos full-bridge motor driver packages: typical application diagrams a3950 package eu, 16 pin qfn with exposed thermal pad package lp package eu v bb 0.1 f 50 v 0.22 f 25 v 100 f 50 v 0.1 f 50 v 0.1 f 50 v a3950 eu package v dd 5 k? nc outa sense vbb mode nfault vreg vcp phase gnd sleep enable gnd cp2 cp1 outb v bb 0.1 f 50 v 0.22 f 25 v 0.1 f 50 v 0.1 f 50 v 100 f 50 v a3950 lp package v dd 5 k? sleep enable out a sense nf aul t mode phase gnd outb vbb vcp gnd cp2 cp1 vreg nc
2 selection guide part number packing package a3950slptr-t 13 in. reel, 4000 pieces / reel 16 pin tssop with exposed thermal pad a3950seutr-t 7 in. reel, 1500 pieces / reel 16 pin qfn with exposed thermal pad absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb 36 v output current i out 2.8 a transient output current i out t w < 500 ns 6 a sense voltage v sense 500 mv vbb to out x 36 v out x to sense 36 v logic input voltage v in C0.3 to 7 v operating ambient temperature t a range s C20 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg C40 to 125 oc dmos full-bridge motor driver a3950 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
3 uvlo stb stg tsd warning vbb outa outb sense low-side gate supply charge pump motor lead protection pad control logic bias supply gnd gnd sleep nfault phase enable v dd 5 k 5 k mode vreg 0.22 f 25 v 0.1 f 0.1 f 0.1 f 100 f outa vbb vcp load supply cp2 cp1 outb sense functional block diagram terminal list table name number description eu lp nfault 15 1 fault output, open drain mode 16 2 logic input phase 1 3 logic input for direction control gnd 2, 12 4,13 ground sleep 3 5 logic input enable 4 6 logic input outa 6 7 dmos full-bridge output a sense 7 8 power return vbb 8 9 load supply voltage outb 9 10 dmos full-bridge output b cp1 10 11 charge pump capacitor terminal cp2 11 12 charge pump capacitor terminal vcp 13 14 reservoir capacitor terminal vreg 14 15 regulator decoupling terminal nc 5 16 no connection pad C C exposed pad for thermal dissipation connect to gnd pins dmos full-bridge motor driver a3950 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
4 electrical characteristics at t j = 25c, v bb = 8 to 36 v, unless noted otherwise characteristics symbol test conditions min. typ. max. units motor supply current i bb f pwm < 50 khz C 6 8.5 ma charge pump on, outputs disabled C 3 4.5 ma sleep mode C C 10 a phase, enable, mode input voltage v ih 2.0 C C v v il C C 0.8 v sleep input voltage v ih 2.7 C C v v il C C 0.8 v phase, mode input current 1 i ih v in = 2.0 v C <1.0 20 a i il v in = 0.8 v C20 5 timing diagram: pwm control v bb v bb 1 2 3 4 6 7 8 9 a charge pump and vreg power-on delay ( 200 s) outb outa outa outb 5 a1 23 45 67 9 8 sleep enable phase mode v out a v bb 0 v bb 0 0 v outb i outx dmos full-bridge motor driver a3950 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
6 blank nf aul t motor lead short condition normal dc motor capacitance charge pump counter enable, source or sink high-z i outx i peak i ocp v out a v outb t blank t ocp timing diagram: overcurrent control dmos full-bridge motor driver a3950 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
7 device operation . the a3950 is designed to operate one dc motor. the output drivers are all low r ds(on) n-channel dmos drivers that feature internal synchronous rectification to reduce power dissipation. phase and enable inputs allow two-wire control with an additional mode pin for the brake function. a low current sleep mode is provided to minimize power consump - tion when the driver is disabled. in addition, the driver also has built-in protection from short-to-ground, short-to-battery, and shorted load events. logic inputs. if logic inputs are pulled up to v dd , it is good practice to use a high value pull-up resistor in order to limit cur - rent to the logic inputs should an overvoltage event occur. logic inputs include: sleep, mode, phase, and enable. the voltage on any logic input cannot exceed the specified maximum of 7 v. vreg . this supply voltage is used to run the sink-side dmos outputs. vreg is internally monitored and in the case of a fault condition, the outputs of the device are disabled. the vreg pin should be decoupled with a 0.22 f capacitor to ground. charge pump . the charge pump is used to generate a sup - ply above v bb to drive the source-side dmos gates. a 0.1 f ceramic monolithic capacitor should be connected between cp1 and cp2 for pumping purposes. a 0.1 f ceramic monolithic capacitor should be connected between vcp and vbb to act as a reservoir to run the high-side dmos devices. the vcp voltage level is internally monitored and, in the case of a fault condition, the outputs of the device are disabled. shutdown . in the event of a fault due to excessive junction temperature, or low voltage on vcp or vreg, the outputs of the device are disabled until the fault condition is removed. at power-on the uvlo circuit disables the drivers. sleep mode . control input sleep is used to minimize power consumption when the a3950 is not in use. this disables much of the internal circuitry, including the regulator and charge pump. a logic low setting puts the device into sleep mode, and a logic high setting allows normal operation. after coming out of sleep mode, provide a 1 ms interval before applying pwm signals, to allow the charge pump to stabilize. mode . control input mode is used to toggle between fast decay mode and slow decay mode. a logic high puts the device in slow decay mode. synchronous rectification is always enabled. braking . the braking function is implemented by driving the device in slow decay mode via the mode setting and applying an enable chop command. because it is possible to drive current in both directions through the dmos switches, this configuration effectively shorts out the motor generated bemf as long as the enable chop mode is asserted. the maximum current can be approximated by v bemf /r l . care should be taken to insure that the maximum ratings of the device are not exceeded in worse case braking situations: high speed and high-inertia loads. diagnostic output . the nfault pin signals a problem with the chip via an open drain output. a motor fault, undervoltage condition, or t j > 160c will drive the pin active low. this output is not valid when sleep puts the device into minimum power dissipation mode. tsd . two die temperature monitors are integrated on the chip. as die temperature increases towards the maximum, a thermal warning signal will be triggered at 160c. this fault drives the functional description control logic table 1 pin function phase enable mode sleep outa outb 1 1 x 1 h l forward 0 1 x 1 l h reverse x 0 1 1 l l brake (slow decay) 1 0 0 1 l h fast decay synchronous rectification 2 0 0 0 1 h l fast decay synchronous rectification 2 x x x 0 z z sleep mode 1 x indicates dont care, z indicates high impedance. 2 to prevent reversal of current during fast decay synchronous rectification, outputs go to the high impedance state as the current approaches 0 a. dmos full-bridge motor driver a3950 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
8 nfault low, but does not disable the operation of the chip. if the die temperature increases further, to approximately 175c, the full-bridge outputs will be disabled until the internal temperature falls below a hysteresis of 15c. overcurrent protection . referring to the figures below, the voltage on the output pins relative to supply are monitored to ensure that the motor lead is not shorted to supply or ground. if a short is detected, the full-bridge outputs are turned off, flag nfault is driven low, and a 1.2 ms fault timer is started. after this 1.2 ms period, t ocp , the device will then be allowed to follow the input commands and another turn-on is attempted. if there is still a fault condition, the cycle repeats. if, after t ocp expires, it is determined that the short condition is not present, the nfault pin is released and normal operation resumes. shorted load condition, output current waveform is shown along with the nfault output. shorted load condition illustrating repetitive cycles with a 1.2 ms delay. i short nfault 2 s / div. 2 a / div. fault asserted i short nfault 200 s / div. 2 a / div. t ocp = 1.2 ms fault asserted dmos full-bridge motor driver a3950 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
9 power dissipation . first order approximation of power dissipation in the a3950 can be calculated by first examining the power dissipation in the full-bridge during each of the operation modes. the a3950 features synchronous rectifica - tion, a feature that effectively shorts out the body diode by turning on the low r ds(on) dmos driver during the decay cycle. this significantly reduces power dissipation in the full-bridge. in order to prevent shoot-through, where both source and sink driver are on at the same time, the a3950 implements a 500 ns typical crossover delay time. for this period, the body diode in the decay current path conducts the current until the dmos driver turns on. this does affect power dissipation and should be considered in high current, high ambient temperature applications. in addition, motor parameters and switching losses can add power dissipation that could affect critical applications. drive current . this current path is through source dmos driver, motor winding, and sink dmos driver. power dissi - pation is i 2 r loses in one source and one sink dmos driver, as shown in the following equation: ) ( 2 d s(on)source d s(on)sink d r r i p + = (1) fast decay with synchronous rectification . this decay mode is equivalent to a phase change where the oppo - site drivers are switched on. when in fast decay, the motor current is not allowed to go negative (direction change). instead, as the current approaches zero, the drivers turn off. the power calculation is the same as the drive current calcu - lation, equation 1: slow decay sr (brake mode) . in this decay mode, both sink drivers turn on, allowing the current to circulate through the sink drivers and the load. power dissipation is i 2 r loses in the two sink dmos drivers: ) ( 2 d s(on)sink d r i p = 2 (2) applications information vbb drive current fast decay with synchronous rectification (reverse) slow decay with synchronous rectification (brake) 2 3 1 2 3 1 figure 1. current decay patterns dmos full-bridge motor driver a3950 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
10 sense pin. a low value resistor can be placed between the sense pin and ground for current sensing purposes. to mini - mize ground-trace ir drops in sensing the output current level, the current sensing resistor should have an independent ground return to the star ground point. this trace should be as short as possible. for low value sense resistors, the ir drops in the pcb can be significant, and should be taken into account. when selecting a value for the sense resistor be sure not to exceed the maximum voltage on the sense pin of 500 mv. ground . a star ground should be located as close to the a3950 as possible. the copper ground plane directly under the exposed thermal pad makes a good location for the star ground point. the exposed pad can be connected to ground for this purpose. layout. the printed circuit board should use a heavy ground - plane. for optimum electrical and thermal performance, the a3950 must be soldered directly onto the board. on the under - side of the a3950 package is an exposed pad, which provides a path for enhanced thermal dissipation. the thermal pad should be soldered directly to an exposed surface on the pcb. thermal vias are used to transfer heat to other layers of the pcb. the load supply pin, vbb, should be decoupled with an elec - trolytic capacitor (typically 100 f) in parallel with a ceramic capacitor placed as close as possible to the device. the ceramic capacitors between vcp and vbb, connected to vreg, and between cp1 and cp2, should be as close to the pins of the device as possible, in order to minimize lead inductance. u1 vbb outb gnd gnd cvbb1 cvbb2 c2 c3 c1 outa eu package shown v bb c1 c2 c3 cvbb2 pad cvbb1 a3950 eu package nc outa sense vbb mode nfault vreg vcp phase gnd sleep enable gnd cp2 cp1 outb dmos full-bridge motor driver a3950 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
11 eu package, 16 pin qfn with exposed thermal pad 1.15 c seating plane c 0.08 17x 16 16 2 1 1 2 16 2 1 a a terminal #1 mark area coplanarity includes exposed thermal pad and terminals b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only (reference jedec mo-220wggc) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c d d c reference land pattern layout (reference ipc7351 qfn65p400x400x80-17bm) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 3.80 0.35 0.65 3.80 0.65 0.75 0.05 2.15 2.15 0.30 0.05 0.40 0.10 4.00 0.15 4.00 0.15 2.15 2.15 b pcb layout reference view dmos full-bridge motor driver a3950 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
12 lp package, 16 pin tssop with exposed thermal pad c sea ting plane c 0.10 16x 6.10 0.65 0.45 1.70 3.00 5.00 0.10 3.00 3.00 3.00 1.20 max 0.15 max 0.65 0.25 (1.00) 4.40 0.10 6.40 0.20 0.60 0.15 4 4 0.25 +0.05 ?0.06 0.15 +0.05 ?0.06 2 1 16 gauge plane sea ting plane b a 16 2 1 a terminal #1 mark area b for reference only (reference jedec mo-153 abt) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown reference land pattern layout (reference ipc7351 sop65p640x110-17m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view exposed thermal pad (bottom surface) c c dmos full-bridge motor driver a3950 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
13 copyright ?2005-2014, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision 7 june 11, 2014 added transient output current to abs. max. ratings dmos full-bridge motor driver a3950 allegro microsystems, llc 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com

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