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fedl620 q504h - 01 issue date : aug . 31 , 2015 m l620 q503h / q504h ultra low power 16 - bit microcontroller 1 / 35 general description this lsi family is a high - performance 16 - bit cmos microcontroller into which rich peripheral circuits, such as synchronous serial port, uart, i 2 c bus interface (master), supply voltage level detect circuit, rc oscillation type a/d conve rter, and s uccessive approximation type a/d converter are incorporated around 16 - bit cpu nx - u16/100. the cpu nx - u16/100 is capable of efficient instruction execution in 1 - in s truction 1 - clock mode by 3 - stage pipe line architecture parallel proce s sing. the f lash rom that is installed as program memory achieves low - voltage low - power consumption operation (read operation) is most suitable for battery - driven applications. and, this lsi has a data flash - memory fill area by a software which can be written in. the on - chip debug function that is installed enables program debugging and programming. features ? cpu ? 16- bit risc cpu (cpu name: nx - u16/100) ? instruction system: 16- bit instructions ? instruction set: transfer, arithmetic operations, comparison, logic o perations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ? build - in on - chip debug function ? minimum instruction execution time 30.5 s (@32.768 khz s ystem clock) 62.5ns (@16 mhz system clock) ? built - in coprocessor for multiplication, division, and multiply - accumulate operations ? signed or unsigned operation setting ? multiplication: 16bit 16bit (operation time 4 cycles) ? division: 32bit / 16bit (operation time 8 cycles) ? division: 32bit / 32bit (operation time 16 cycles) ? multiply - accumulate (non - saturating): 16bit 16bit + 32bit (operation time 4 cycles) ? multiply - accumulate (saturating): 16bit 16bit + 32bit (operation time 4 cycles) ? internal memory ? supports isp function (re - writing the program memory area by software) ? number of segments product name flash memory sram program area * d ata area ml620 q503h 32k b ( 16k * : including 1kb of unusable test area ? interrupt controller (intc) ? 1 non - maskable interrupt sources (internal source: 1) ? 3 7 maskable interrupt sources (internal sources: 2 9 , external sources: 8) ? soft w are interrupt (swi): maximum 64 sources ? external interrupts and comparator allow edge selection and sampling selec tion ? priority level (4 - level) can be set for each interrupt ? time base counter (tbc) ? low - speed time base counter 1 channel
fed l620 q504h - 01 ml620 q503h / q504h 2 / 3 5 ? timer s (tmr) ? 8 bits 8 channels (timer0 - 7 : 16 - bit 4 configuration available by using timer0 - 1 or timer2 - 3, timer4 - 5 , timer6 - 7 ) ? selection of one shot timer mode is possible ? e xternal clock can be selected as timer clock . ? function timer s (ftm) ? 16- bit 4 channels ? equipped with the timer/capture/pwm functions using a 16 - bit counte r ? timer start/stop function b y software/event trriger(external pin or other timer) ? external pin can be selected as counter clock ? capture function (the measurement such as the pulse width is possible using external trigger input) ? two types of pwm with the same period and differen t duties and complementary pwm with the dead time set can be output . ? watchdog timer (wdt) ? non - maskable interrupt and reset ? free running ? overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s when lsclk = 32.768 khz) ? s ynchronous serial po rt (ssiof / ssio ) ? without fifos (ssio) : 1 channel ? with 4 - byte transmits and receives fifos (ssiof) : 1 channel ? master/slave are selectable ? lsb first/msb first are selectable ? 8 - bit length/16 - bit length are selectable ? phase/polarity of clock are selectable ? supports slave - select signal (only ssiof) ? uart ( uartf/uart ) ? without fifos ( uart ) : 1ch ? with 4 - byte transmits and receives fifos (uartf) : 1ch ? full duplex buffer system ? communication speed: settable within the range of 2400bps to 1 15200bps. ? programmable interface ( data length , parity , stop bits selectable ) ? i 2 c bus interface (i 2 c) ? master function 2 channel ? fast mode (400 kbps), standard mode (100 kbps) ? general - purpose ports (port) ? input port 2, input/output port 3 6 channels ? melody driver (melody) ? tempo: 15 types ? scale: 29 types (melody sound frequency: 508 hz to 10.922 khz) ? tone length: 63 types ? buzzer output mode ( 4 output modes , 8 buzzer frequencies, 7duty levels at 4.096khz /15 duty levels at other bu zzer frequencies) ? rc oscillation type a/d converter (rc - adc) ? time division 2 channels ? 24- bit counter
fed l620 q504h - 01 ml620 q503h / q504h 3 / 3 5 ? successive approximation type a/d converter (sa - adc) ? input 12 channels ? 12- bit a/d converter ? starting by trigger of timer/ftm function. ? capacitive touch sense function ? analog comparator (cmp) ? input 2ch ? common mode input voltage: 0.2v to v dd 0.2 v ? input offset voltage: 30mv(max) ? interrupt allow edge selection and sampling selection are selectable ? voltage level supervisor (v ls) ? threshold voltages: selectable from 13 levels ? interrupt or reset generate are s e lectable ? low level detector(lld) ? judgement voltage: 1.8v 0.2v ? usable as low level detection reset ? reset ? reset by the reset_n pin ? reset by power - on dete ction ? reset by overflow of watchdog timer (wdt) ? reset by voltage leve supervisor(vls) ? reset by low level detector(lld) ? clock ? low - speed clock: (this lsi can not guarantee the operation withou t low - speed clock) ? crystal oscillation ( 32.768 khz) ? external clock input (30khz to 36khz) ? built - in rc oscillation (32.768khz) ? high - speed clock: ? c rystal / c eramic oscillation (16 mhz) ? external clock input ( 300khz to 16 mhz) ? built - in rc oscillation (16mhz) ? power management ? halt mode: instructio n execution by cpu is suspended . all peripheral circuits can keep in operating states. ? halt - h mode: instruction execution by cpu is suspended . stop of high - speed oscillation automatically. all peripheral circuits can keep in operating states. ? deep - halt mode: instruction execution by cpu is suspended . some peripheral circuits (timer, ltb, etc. ) can keep in operating states. ? stop mode: stop of low - speed oscillation and high - speed oscillation (operations of cpu and peripheral circuits are stopped.) ? cloc k gear: the frequency of high - speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8 ,1/16,1/32 of the oscillation clock) ? block control function: power down (reset registers and stop clock supply) the circuits of unused peripherals.
fed l620 q504h - 01 ml620 q503h / q504h 4 / 3 5 ? shipme nt ? die * please contact our responsible sales person for the pad layout information. ? 48- pin plastic tqfp tray ml620 q503h - xxxtb waal ml620 q504h - xxxtb waal tape and reel ml620 q503h - xxxtb wabl ml620 q504h - xxxtb wabl ? guaranteed op erating range ? operating temperature (ambient) : ? 40 c to +85 c ? operating voltage: v dd = 1. 8 v to 5.5 v
fed l620 q504h - 01 ml620 q503h / q504h 5 / 3 5 block diagram block diagram of ml620 q503h / q504h figure 1 . block diagram of ml620 q503h / q504h program memory (flash) 32k/ 64k byte ssio x 1 ssio f x 1 sck0 sin0 sout0 uart x 1 uart f x 1 rxd0 txd0 i 2 c x 2 sda0 scl0 int 2 ram 2k/6 k byte interrupt controller cpu (nx - u16/100) timing controller sp on i i instructin ecer s ntrer instructin register t int int int int 1 wt int 8 t ier 8 int unctin tier pio p t t p t 1 p1 t p11 p t p int 8 p t p p t p ata us tmot t st rstn os t t1 os os1 s o ot s p er r s in rs rt rt rm s1 in1 rs1 rt1 rst tst psw1 ~ psw r1 ~ r sr1 ~ srsr p r ~ 1 ss int 1 nag aratr mpp mpm int s sin sot s1 s1 tmot s int 1 in t in11 mp1p mp1m r tst1n int 1 si p t p p t p tmi r t ss mo c rcessr ui int 1 in m int 1 ata as mer te
fed l620 q504h - 01 ml620 q503h / q504h 6 / 3 5 pin configuration pin layout of ml620 q503h / q504h t qfp package external intteruput inputpin(exi) can be assigned to p00 - p05, pxt0 - 1, p20- p57. *0 to *7 and *0$ to *7$ has following functions. but 0$ - 7$ ha s limit e d function. please refer to the pin list . *0 : sda0, sout0, rxd0 *4 : sda1, soutf0, rxdf0 *1 : scl0, sin0 , txd0 *5 : scl1, sinf0, txdf0 *2 : sck0, tmout ,tmcki *6 : lsclko,sckf0, tmout, tmcki *3 : md0, tmout , tmcki *7 : outclk,ssf0, tmout, tmcki *0$ : sout0, rxd0 *4$ : soutf0, rxdf0 *1$ : sin0 , txd0 *5$ : sin f0, txdf0 *2$ : sck0, tmout *6$ : sckf0, tmout *3$ : md0(p33 only), tmout *7$ : ssf0, tmout figure 2 . pin layout of ml62 0 q503h / q504h tqfp package 12 1 2 3 4 5 6 7 8 9 10 11 25 26 27 28 29 30 31 32 33 34 35 36 24 23 22 21 20 19 18 17 16 15 14 13 38 39 40 41 42 43 44 45 46 47 48 37 osc0 | p 1 0 clkin | osc1 | p 1 1 reset_n *0 | cmp0p | p3 0 *1 | cmp0m | p31 *2 $ | cmp1p | p32 *3 $ | cmp1 m | p33 *4 | ain0 | p34 *5 | ain1 | p35 *6 $ | ain2 | p36 *7 $ | ain3 | p37 v ref p05 | rcm p04 | rt0 p03 | ain11 | rs 0 | *3$ p02 | ain10 | rct 0 | *2$ p01 | ain9 | cs0 | *1$ p00 | ain8 | in0 | *0$ p23 | ain7 | rt1 | * 7 $ p22 | ain6 | rs1 | * 6 $ p21 | ain5 | cs1 | * 5 $ p20 | ain4 | in1 | * 4 $ v ss v dd p40 | led | *0 p41 | led | *1 p42 | *2 p43 | *3 p44 | *4 p45 | *5 p46 | *6 p47 | *7 p50 | *0 p51 | *1 p52 | led | *2 p53 | led | *3 *4 | p 54 *5 | p55 *6 | p56 *7 | p57 test0 test1_n v ddl v dd v ss v ddx lsclki | xt1 | pxt 1 xt0 | pxt 0
fed l620 q504h - 01 ml620 q503h / q504h 7 / 3 5 pin list pkg pin no . 1st function 2nd/3rd/4th function pin name i/o reset state function pin name i/o function pin name i/o function pin name i/o function 14, 45 v ss negative power supply pin 1 3, 44 v dd positive power supply pin 43 v ddl power supply pin for internal circuit (internally generated) 46 v ddx p ower supply pin for internal circuit (internally generated) 12 v ref i r eference voltage input pin of sa - adc 1 reset_n i p ull - up input reset input pin 42 test1_n i p ull - up input input pin for testing 41 test0 i/o pull - down input i nput/output pin for testing 48 pxt0/ exi i0 / xt0 i input disable input port/ external interrupt/ low - speed oscillation port 47 pxt1/ exi 1 / xt1 / lsclki i /o hi - z output input - output port/ external interrupt/ low - speed oscillation port l ow - speed external clock i nput 19 p00/ exi 00/ ain8 i/o hi - z output input - output port/ external interrupt/ sa- adc input in0 i rc- adc oscillation input sout0 o ssio data output rxd0 i uart data input 20 p01/ exi 01/ ain9 i/o hi - z output input - output port/ external interrupt/ sa- adc input cs0 o rc- adc reference capacitance connection pin sin0 i ssio data input txd0 o uart data output 21 p02/ exi 02/ ain10 i/o hi - z output input - output port/ external interrupt/ sa- adc input rct0 o rcadc resistor/capacitor sensor connec tion pin sck0 i/o ssio clock input/output tmout0 o ftm output 22 p03/ exi 03/ ain11 i/o hi - z output input - output port/ external interrupt/ sa- adc input rs0 o rc- adc reference resistor connection pin tmout1 o ftm output 23 p04/ exi 04 i/o hi - z output input - output port/ external interrupt rt0 o rc - adc measurement resistor sensor connection pin 24 p05/ exi 05 i/o hi - z output input - output port/ external interrupt rcm o rc- adc oscillation monitor 2 p10/ osc0 i/o hi - z output input - output port/ high - speed oscillation port 3 p11/ osc1 / clkin i/o hi - z output input - output port/ high - speed oscillation port high - speed external clock input 15 p20 / exi 20/ ain4 i/o hi - z output input - output port/ external interrupt/ sa- adc input in1 i rc- adc oscillation input soutf0 o ssiof data output rxdf0 i uartf data input 16 p21/ exi 21/ ain5 i/o hi - z output input - output port/ external interrupt/ sa- adc input cs 1 o rc- adc reference capacitance connection pin sinf0 i ssiof data input txdf0 o uartf data output 17 p22/ exi 22/ ain6 i/o hi - z output input - output port/ external interrupt/ sa- adc input rs1 o rc- adc reference resistor connection pin sckf0 i/o ssiof clock input/output tmout2 o ftm output
fed l620 q504h - 01 ml620 q503h / q504h 8 / 3 5 pkg pin no . 1st function 2nd/3rd/4th function pin name i/o reset state function pin name i/o function pin name i/o function pin name i/o function 18 p23/ exi 23/ ain7 i/o hi - z output input - output port/ external interrupt/ sa- adc input rt1 o rc - adc measurement resistor sensor connection pin ssf0 i/o ssiof select input/output tmout3 o ftm output 4 p30/ exi 30/ cmp0p i /o hi - z output input - output port/ external interrupt/ comparator plus input sda0 i/o i 2 c data input/output sout0 o ssio data output rxd0 i uart data input 5 p31/ exi 31/ cmp0m i/o hi - z output input - output port/ external interrupt/ comparator minus input sc l0 o i 2 c clock output sin0 i ssio data input txd0 o uart data output 6 p32/ exi 32/ cmp1p i/o hi - z output input - output port/ external interrupt/ comparator plus input sck0 i/o ssio clock input/output tmout4 o ftm output 7 p33/ exi 33/ cmp1m i/o hi - z output input - output port/ external interrupt/ comparator minus input md 0 o melody/buzzer output tmout5 o ftm output 8 p34/ exi 34/ ain0 i/o hi - z output input - output port/ external interrupt/ sa- adc input sda1 i/o i 2 c data input/output soutf0 o ssiof data output rxdf0 i uartf data input 9 p35/ exi 35/ ain1 i/o hi - z output input - output port/ external interrupt/ sa- adc input scl1 o i 2 c clock output sinf0 i ssiof data input txdf0 o uartf data output 10 p36/ exi 36/ ain2 i/o hi - z output input - output port/ external interrupt/ sa- adc input sckf0 i/o ssiof clock input/output tmout6 o ftm output 11 p37/ exi 37/ ain3 i/o hi - z output input - output port/ external interrupt/ sa- adc input ssf0 i/o ssiof select input/output tmout7 o ftm output 25 p40/ exi 40/ led i/o hi - z output input - out put port/ external interrupt/ led output sda0 i/o i 2 c data input/output sout0 o ssio data output rxd0 i uart data input 26 p41/ exi 41/ led i/o hi - z output input - output port/ external interrupt/ led output scl0 o i 2 c clock output sin0 i ssio data input txd 0 o uart data output 27 p42/ exi 42/ tmcki 0 i/o hi - z output input - output port/ external interrupt/ timer clock input sck0 i/o ssio clock input/output tmout8 o ftm output 28 p43/ exi 43/ tmcki 1 i/o hi - z output input - output port/ external interrupt/ timer clock input md 0 o melody/buzzer output tmout9 o ftm output 29 p44/ exi 44 i/o hi - z output input - output por t/ external interrupt sda1 i/o i 2 c data input/output soutf0 o ssiof data output rxdf0 i uartf data input 30 p45/ exi 45 i/o hi - z output input - output port/ external interrupt scl1 o i 2 c clock output sinf0 i ssiof data input txdf0 o uartf data output 31 p46 / exi 46/ tmcki 2 i/o hi - z output input - output port/ external interrupt/ timer clock input lsclko o low - speed clock output sckf0 i/o ssiof clock input/output tmouta o ftm output 32 p47/ exi 47/ tmcki 3 i/o hi - z output input - output port/ external interrupt/ ti mer clock input outclk o high - speed clock output ssf0 i/o ssiof select input/output tmoutb o ftm output 33 p50/ exi 50 i/o hi - z output input - output port/ external interrupt sda0 i/o i 2 c data input/output sout0 o ssio data output rxd0 i uart data input 34 p51/ exi 51 i/o hi - z output input - output port/ external interrupt scl0 o i 2 c clock output sin0 i ssio data input txd0 o uart data output 35 p52/ exi 52/ tmcki 4 / led i/o hi - z output input - output port/ external interrupt/ timer clock input/ led output sck0 i/o ssio clock input/output tmoutc o ftm output 36 p53/ exi 53/ tmcki 5 / led i/o hi - z output input - output port/ external interrupt/ timer clock input/ led output md 0 o melody/buzzer output tmoutd o ftm output
fed l620 q504h - 01 ml620 q503h / q504h 9 / 3 5 pkg pin no . 1st function 2nd/3rd/4th function pin name i/o reset state function pin name i/o function pin name i/o function pin name i/o function 37 p54/ exi 54 i/o hi - z output input - output port/ external interrupt sda1 i/o i 2 c data input/output soutf0 o ssiof data output rxdf0 i uartf data input 38 p55/ exi 55 i/o hi - z output input - output port/ external interrupt scl1 o i 2 c clock out put sinf0 i ssiof data input txdf0 o uartf dat a output 39 p56/ exi 56/ tmcki 6 i/o hi - z output input - output port/ external interrupt/ timer clock input lsclko o low - speed clock output sckf0 i/o ssiof clock input/output tmoute o ftm output 40 p57/ exi 57/ tmcki 7 i/o hi - z output input - output port/ extern al interrupt/ timer clock input outclk o high - speed clock output ssf0 i/o ssiof select input/output tmoutf o ftm output
fed l620 q504h - 01 ml620 q503h / q504h 10/ 3 5 pin description the pin name represents the function pin name of the primary function of each terminal, the pin mode represents the s et of mode register of port control. (1 st :primary function, 2 nd :secondary function, 3 rd : tertiary function, 4 th : quartic function) pin name i/o description lsi pin name pin mode logic system reset_n i reset input pin. when this pin is set to a ?l? level , system reset mode is set and the internal section is initialized. when this pin is set to a ?h? level subsequently, program execution starts. a pull - up resistor is internally connected. reset_n ? l xt0 i crystal connection pin for low - speed clock. capac itors c dl and c gl are connected across this pin and v ss as required. pxt0 1st ? xt1 o pxt1 1st ? lsclki i external clock input for low - speed clock. pxt 1 1st ? osc0 i crystal/ceramic connection pin for high - speed clock (16 mhz max.). capacitors c dh and c gh are connected across this pin and v ss . p10 1st ? osc1 o p11 1st ? clkin i external clock input for high - speed clock. p1 1 1st ? lsclk o o low - speed clock output pin. p46,p56 2nd ? outclk o high - speed clock output pin. p47,p57 2nd ? general - pur pose input/output port pxt 0 -p xt 1 i general - purpose input port (without pull - up/pull - down resister) . pxt 0 - p xt 1 1st ? p00 - p05 i/o general - purpose input/output port. p00 - p05 1st ? p10 - p11 i/o general - purpose input/output port. p10 - p11 1st ? p20 - p23 i/o ge neral - purpose input/output port. p20 - p23 1st ? p30 - p37 i/o general - purpose input/output port. p30 - p37 1st ? p40 - p47 i/o general - purpose input/output port. p40 - p47 1st ? p50 - p57 i/o general - purpose input/output port. p50 - p57 1st ? external interrupt ex ii0 - exii1 exi00 -05 exi20 -23 exi30 -37 exi40 -47 exi50 - 57 i external maskable interrupt input pins. it is possible, for each bit, to specify whether the interrupt is enabled and select the interrupt edge by software. pxt0 - pxt1 p00 - p05 p20 - p23 p30 - p37 p40 - p47 p50 - p57 1st h/l led led o n - channel open drain output pins to drive led. p40,p41,p52,p53 1st ? melody/buzzer md 0 ? melody/buzzer signal output pin. p33,p43,p53 2nd h uart txd0 o uart 0 data output pin. p01,p31,p41,p51 4th ? rxd0 i uart 0 data input pin. p00,p30,p40,p50 4th ? txd f0 o uart with fifo data output pin. p21,p35,p45,p55 4th ? rxd f0 i uart with fifo data input pin. p20,p34,p44,p54 4th ?
fed l620 q504h - 01 ml620 q503h / q504h 11/ 3 5 pin name i/o description lsi pin name pin mode logic i 2 c bus interface sda0 i/o i 2 c0 data input/out put pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull -up resistor. p30,p40,p50 2nd ? scl0 o i 2 c0 clock output pin. this pin has an nmos open drain output. when using this pin as a functio n of the i 2 c, externally connect a pull - up resistor. p31,p41,p51 2nd ? sda1 i/o i 2 c1 data input/output pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull -up resistor. p34,p44,p54 2nd ? scl 1 o i 2 c1 clock output pin. this pin has an nmos open drain output. when using this pin as a function of the i 2 c, externally connect a pull - up resistor. p35,p45,p55 2nd ? synchronous serial sck0 i/o synchronous serial (ssio) clock input/output pin. p02,p3 2,p42,p52 3rd ? sin0 i synchronous serial (ssio) data input pin. p01,p31,p41,p51 3rd ? sout0 o synchronous serial (ssio) data output pin. p00,p30,p40,p50 3rd ? sck f0 i/o synchronous serial with fifo(ssiof) clock input/output pin. p22,p36,p46,p56 3rd ? sin f0 i synchronous serial with fifo(ssiof) data input pin. p21,p35,p45,p55 3rd ? sout f0 o synchronous serial with fifo(ssiof) data output pin. p20,p34,p44,p54 3rd ? s sf0 i/o synchronous serial with fifo(ssiof) select input/ output pin. p23,p37,p47,p57 3rd l ftm tmout0 -9 tmouta -f o ftm output pin. p02,p03,p22,p23 p32,p33,p36,p37, p42,p4 3 ,p 46,p 4 7 p52,p53,p56,p57 4th ? tmcki 0 -7 i external clock input pin for ftm p42,p43,p46,p47, p52,p53,p56,p57 1st ? rc oscillation type a/d converter in0 i channel 0 oscillation input pin. p00 2nd ? cs0 o channel 0 reference capacitor connection pin. p01 2nd ? rs0 o r eference resistor connection pin of channel 0. p03 2nd ? rt0 o resistor sensor connection pin of channel 0 for measurement. p04 2nd ? rct0 o resi stor/capacitor sensor connection pin of channel 0 for measurement. p02 2nd ? rcm o rc oscillation monitor pin. p05 2nd ? in1 i oscillation input pin of channel 1. p20 2nd ? cs1 o reference capacitor connection pin of channel 1. p21 2nd ? rs1 o refe rence resistor connection pin of channel 1. p22 2nd ? rt1 o resistor sensor connection pin for measurement of channel 1. p23 2nd ?
fed l620 q504h - 01 ml620 q503h / q504h 12/ 3 5 pin name i/o description lsi pin name pin mode logic successive approximation type a/d converter v ref i reference volta ge input pin for successive approximation type a/d converter. v ref ? ? ain0 -11 i channel 0 analog input for successive approximation type a/d converter. p34 ,p35,p36,p37, p20,p21,p22,p23, p00,p01,p02,p03 1st ? analog comparator cmp0p i comparator0 non - i nverted input pin. p30 1st ? cmp0m i comparator0 inverted input pin. p31 1st ? cmp1p i comparator1 non - inverted input pin. p32 1st ? cmp1m i comparator1 inverted input pin. p33 1st ? for testing test 0 i/o input/output pin for testing. a pull - down re sistor is internally connected. test 0 ? ? test1_n i input pin for testing. a pull - up resistor is internally connected. test1_n ? ? power supply v ss ? negative power supply pin. v ss ? ? v dd ? positive power supply pin. v dd ? ? v ddl ? p ositive power sup ply pin (internally generated) for internal logic. capacitors c l0 and c l1 are connected between this pin and v ss . v ddl ? ? v ddx ? positive power supply pin (internally generated) for low - speed oscillation. capacitor c x1 is connected between this pin and v ss . v ddx ? ?
fed l620 q504h - 01 ml620 q503h / q504h 13/ 3 5 termination of unuse d pins table 1 shows methods of terminating the unused pins. table 1 termination of unused pins pin recommended pin termination reset_n open test0 open test1_n open v ref connect to v dd p0 0 to p05 open pxt0 to pxt1 open p10 to p11 open p20 to p23 open p30 to p37 open p40 to p47 open p50 to p57 open note: for unused input ports or unused input/output ports, if the corresponding pins are configured as high - impedance inputs and left open, the supply current may become excessively large. therefore, it is recommended to configure those pins as either inputs with a pull - down resistor/pull - up resistor or outputs.
fed l620 q504h - 01 ml620 q503h / q504h 14/ 3 5 electric characteris tics a bsolute m aximum r atings (v ss = 0v ) parameter s ymbol c o ndition rating unit power supply voltage 1 v dd ta = 25c - 0.3 to + 6 .0 v power supply voltage 2 v ddl ta = 25c - 0.3 to + 2.0 v power supply voltage 3 v ddx ta = 25c - 0.3 to + 2.0 v input voltage v in ta = 25c - 0.3 to v dd +0.3 v output voltage v out ta = 2 5 c - 0.3 to v dd +0.3 v output current 1 i out1 port 0 to 2 ta = 25c -12 to +11 ma output current 2 i out 2 port 3 to 5 ta = 25c -12 to + 20 ma power dissipation pd ta = 25c 0.9 w storage temperature t stg D -55 to +150 c
fed l620 q504h - 01 ml620 q503h / q504h 15/ 3 5 r ecommended o perating c onditions (v ss = 0v ) parameter symbol condition range unit operating temperature (ambience) t op D -40 to +85 c operating voltage v dd D 1. 8 to 5.5 v reference voltage v ref D 1.8 to v dd v operating frequency cpu >' f op D 30k to 16 .8 m hz low - speed e xternal clock input f ext l D 30k to 36k hz high - speed e xternal clock input f ext h D 2m to 16m hz low speed crystal oscillation frequency f xtl D 32.768k hz low speed crystal oscillation external capacitor 1 c dl using vt - 200- fl(from sii 6.8 to 12 pf c gl 6.8 to 12 low speed crystal oscillation external capacitor 2 c dl using dt - 26(from daishinku) 12 to 16 pf c gl 12 to 16 low speed crystal *1 oscillation external capacitor 3 c dl using vt - 200- f(from sii 1 2 to 22 pf c gl 12 to 22 high speed c rystal/ ceramic oscillation frequency f xth D 16m hz high speed crystal oscillation external capacitor c dh using nx8045gb (from nihon denpa kogyo ) 12 to 20 pf c gh 12 to 20 ceramic oscillation external capacito r c dh using fcstce16m 0 v53 (from murata manufacturing) build in cl type 0 to 5 pf c gh 0 to 5 v ddl external capacitor * 2 c l esr Q 500m 2.2 30% f v ddx external capacitor c x D f please use this crystal except deephalt mode because thi s lsi may not be functioning at deephalt mode with the crystal. p lease evaluate the matching when other crystal oscillator/ cera mic oscillator is used. *2 please evaluate on user ? s conditions, put on c l0 ( = 0.1uf) if necessary .
fed l620 q504h - 01 ml620 q503h / q504h 16/ 3 5 operating conditions of f lash memory ( v ss = 0v ) parameter symbol c o ndition range unit operating temperature (ambience) t op data area : write/erase -40 to + 85 c program area : write/erase 0 to + 40 c operating voltage write time v dd w rite/erase 1.8 to 5.5 v c epd d ata ar ea (1,024b x 2) 10,000 times c epp program area 100 times e rase unit D block erase p rogram area 8 kb data area 2 sector erase 1 kb erase time(maximum) D block erase/sector erase 100 ms write unit D D 1 word ( 2 byte) D
fed l620 q504h - 01 ml620 q503h / q504h 17/ 3 5 ac characteristics (oscillation, reset) *1 : mean value of 1024 cycle. *2 : guarantee value at the time of the shipment. ( v dd =1.8 to 5.5 v , v ss = 0v , ta = - 4 0 to + 85 c , unless otherwise specified ) parameter symbol condition rating unit m easuring circuit min. typ. max. low speed crystal oscillation start time t xt l D D D 2 s 1 high speed crystal oscillation start time t xt h D D D 2 0 ms low speed buil t - in rc oscillation f requency *1*2 f lcr ta=25 c typ -1 .5 % 32.768 typ +1 .5 % k hz ta= -40 ~ 85c typ -5 % 32.768 typ + 5 % h igh speed build - in rc oscillation frequency *1*2 f hcr ta=25 c typ -1% 16 typ +1% mhz ta= -40 to 85c typ -5% 16 typ +5% r eset pulse width p rst D 200 D D us reset noise elimination pulse width p nrst D D D 0. 3 us power - on reset activation power rise time t por ? ? ? 10 m s p rst rstn terna reset seuence 1 t por power on reset sequence p rst 0.3* v dd 0.3* v dd
fed l620 q504h - 01 ml620 q503h / q504h 18/ 3 5 d c charac teristics (idd) (v dd =1.8 to 5.5 v, v ss =0v, ta= - 40 to +85 c ? 0.25 0.8 1.3 a 1 ta= - 40 to 85 c ? ? 15 18 power consumption 2 idd2 deep - halt m ode * 2 * 4 (lbtc function) low - speed crystal oscillating (32.768khz) high - speed oscillation is stopped. ta=25 c ? 0.45 1.3 1.6 a ta= - 40 to 85 c ? ? 15 18 power consumption 3 idd3 halt mode * 2 * 4 (ltbc function) low - speed crystal oscillating (32.768kh z) high speed oscillation is stopped. ta=25 c ? 2 2.7 3.0 a ta= - 40 to 85 c ? ? 18 19 power consumption 4 idd4 cpu low - speed * 1 * 4 low - speed built - in cr oscillating high speed oscillation is stopped. ta=25 c ? 10 12 13 a ta= - 40 to 85 c ? ? 25 28 power consumption 5 idd5 cpu high - speed(16mhz) * 1 * 4 high - speed built - in cr oscillating ta=25 c ? 4 5.5 5.5 ma ta= - 40 to 85 c ? ? 6 6 power consumption 6 idd6 cpu high - speed(16mhz) * 1 * 3 * 4 high speed crystal oscillating (16mhz) ta=25 c ? 6 7.5 9.4 ma ta= - 40 to 85 c ? ? 8 9.9 * 1 at cpu activity rate =100% >& no halt state >' * 2 : using 32.768khz crystal oscillator vt -200- fl (from sii)(c gl /c dl 12pf) using 32.768khz crystal oscillator dt - 26(from daishinku)(c gl /c dl 12pf * 3 : using nx8045gb(from nihon denpa kogyo) (c gh /c dh 16pf) * 4 : blkcon0~blkcon5 valid bits are all ?1?.
fed l620 q504h - 01 ml620 q503h / q504h 19/ 3 5 d c characteristics (vls) (v dd =1.8 to 5.5 v, v ss =0v, ta= - 40 to +85 c , unless otherwise specified) parameter symbol condition rating *1 unit measuring circuit min. typ. max. vls judge voltage (v dd =fall) v vls vlscon = 3h 1.798 1.898 1.998 v 1 vlscon = 4h 1.900 2.000 2.100 vlscon = 5h 1.993 2.093 2.193 vlscon = 6h 2.096 2.196 2.296 vlscon = 7h 2.209 2.309 2.409 vls con = 8h 2.309 2.409 2.509 vlscon = 9h 2.505 2.605 2.705 vlscon = ah 2.700 2.800 2.900 vlscon = bh 2.968 3.068 3.168 vlscon = c h 3.294 3.394 3.494 vlscon = d h 3.697 3.797 3.897 vlscon = e h 4.126 4.226 4.326 vlscon = f h 4. 567 4.667 4.767 v vls hysteresis width (v dd =rise) h vls ? v vls x 1.8% v vls x 3.8% v vls x 6.3% v d c characteristics (lld) ( v dd =1.8 to 5.5 v , v ss = 0v , ta = - 4 0 to + 85 c , unless otherwise specified ) parameter symbol condition rating unit measuring circuit min. typ. max. lld judge voltage vllr D 1. 6 0 1. 8 0 2 . 0 0 v 1 d c characteristics (analog comp a rator) ( v dd =1.8 to 5.5 v , v ss = 0v , ta = - 4 0 to + 85 c , unless otherwise specified ) p arameter symbol c ondition r ating u nit measuring circuit min. typ. max. common input voltage range v cmpin D 0.2 D v dd - 0.2 v 1 i nput offset voltage v cmpof D -30 D 3 0 mv comparator judge time t cmp cmpp - cmp m =4 0mv D D 2 s
fed l620 q504h - 01 ml620 q503h / q504h 20/ 3 5 d c characteristics (vohl , iohl) (v dd =1.8 to 5.5 v, v ss =0v, ta= - 40 to +85 c , unless otherwise specified) parameter symbol co ndition rating unit measuring circuit min. typ. max. output voltage 1 ( p00 - p05, p10 - p11 p20 - p23, p30 - p37 p40 - p47, p50 - p57 ) voh1 3.6 v < ioh= - 2.5 ma v dd -0. 6 ? ? v 2 1.8v ioh= - 1.0ma v dd - 0.5 ? ? vol1 3.6 v < io l=+ 5.0 ma ? ? 0. 6 1.8v iol=+0.5ma ? ? 0.4 output voltage 2 ( p40,p41, p52, p53 ) (led mode is selected) vol2 3.6 v < 5.5 v iol=+5.0ma ? ? 0. 4 2.7v v dd 3.6v iol=+5.0ma ? ? 0.6 1.8v v dd < 2.7v iol=+2.0ma ? ? 0.4 outpu t voltage 3 ( p30,p31, p34, p35, p40, p41, p44, p45, p50, p51, p54, p55 ) (i 2 c mode is selected) vol3 iol3= +3ma (i 2 cspec) (v dd 2v) ? ? 0.4 output voltage 4 ( p30, p31, p34, p35, p40, p41, p44, p45, p50, p51, p54, p55 ) (i 2 c mode is selected) vol4 iol3= +2ma(i 2 cspec) (v dd < 2v) ? ? v dd 0.2 output leak 1 ( p00 - p05,p20 - p23, p30 - p37, p40 - p47, p50 - p57 ) iooh1 voh=v dd (at high impedance) ? ? +1 a 3 iool1 vol=v ss (at high impedance) -1 ? ? output leak 2 ( p10 - p11 ) iooh2 voh=v dd (at high impedance) ? ? + 2 iool2 vol=v ss (at high impedance) -2 ? ?
fed l620 q504h - 01 ml620 q503h / q504h 21/ 3 5 d c characteristics (iihl) ( v dd =1.8 to 5.5 v , v ss = 0v , ta = - 4 0 to + 85 c , unless otherwise specified ) parameter symbol condition rating *1 unit measuring circuit min. typ. max. input current 1 (reset _n , test1_n) iih1 vih1=v dd D D 1 a 4 iil1 vil1=v ss -900 -3 00 -20 input current 2 (test 0 ) iih 2 vih 2 =v dd 20 300 90 0 iil 2 vil 2 =v ss -1 D D input current 3 ( pxt0 - pxt1, p00 - p05 , p20 - p23 , p30 - p37 , p40 - p47 , p50 - p57 ) iih3 vih3=v dd (at pull down ) 1 15 200 iil3 vil3=v ss (at pu ll up) - 200 - 15 - 1 iih3z vih3=v dd (at high impedance) D D 1 iil3z vil3=v ss (at high impedance) -1 D D input current 4 ( p 10- p11 ) iih 4 vih 4 =v dd (at pull down ) 1 1 5 200 iil 4 vil 4 =v ss (at pull up) -200 -1 5 -1 iih 4 z vih 4 =v dd (at high imped ance) D D 2 iil 4 z vil 4 =v ss (at high impedance) -2 D D * 1 : typ.rating is ta=25 c , v dd =3.0v d c characteristics (vihl) ( v dd =1.8 to 5.5 v , v ss = 0v , ta = - 4 0 to + 85 D 0. 7 v dd D v dd v 5 vil 1 D 0 D 0. 3 v dd input terminal capacitance ( reset _n , test 0 , test 1_n , pxt0 - pxt1,, p00 - p05 , p 10- p11 , p20 - p23 , p30 - p37 , p40 - p47 , p50 - p57 ) cin f=10khz v rms = 50mv ta=25 c D D 10 pf D
fed l620 q504h - 01 ml620 q503h / q504h 22/ 3 5 m easuring circuit m easuring circuit 1 measuring circuit 2 input pins v vih vil output pins ( * 1 ) input logic circuit to determine the specified measuring conditions. ( * 2) measured at the specified output pins. ( * 2 ) ( * 1) v dd v ref v ddl v ss v ddx v dd v r ef v ddx c x c v 8 rsta osciatr t o s ss 1m rsta osciatr t1 o s1 8 crsta sciatr t r aisinu 1m crsta sciatr n8 r nin ena g 1 f c x : 0.33 f c gl : 12pf c dl : 12pf c gh : 1 6 pf c dh : 1 6 pf
fed l620 q504h - 01 ml620 q503h / q504h 2 3 / 3 5 measuring circuit 3 measuring circuit 4 input pins a output pins (*3) me asured at the specified output pins. ( * 3 ) v dd v ref v ddl v ss v ddx input pins a vih vil output pins ( * 1 ) input logic circuit to determine the specified measuring conditions. (*2) measured at the specified output pins. ( * 2 ) ( * 1) v dd v ref v ddl v ss v ddx
fed l620 q504h - 01 ml620 q503h / q504h 24/ 3 5 measuring circuit 5 input pins vih vil o utput pins ( * 1 ) input logic circuit to determine the specified measuring conditions. ( * 1) w aveform monitoring v dd v ref v ddl v ss v ddx
fed l620 q504h - 01 ml620 q503h / q504h 25/ 3 5 a c characteristics ( extern al interr u pt ) ( v dd =1. 8 to 5.5 v , v ss = 0v , ta = - 4 0 to + 85 D 3.5 x sysclk t nul exi0 - 7 ( ri sing - edge interrupt) exi0 - 7 ( falling - edge interrupt) exi0 - 7 (both - edge interrupt) t nul t nul
fed l620 q504h - 01 ml620 q503h / q504h 26/ 3 5 ac characteristics ( synchronous serial port) ( v dd =1. 8 to 5.5 v , v ss = 0v , t a = - 4 0 to + 85 c , unless otherwise specified ) p arameter s ymbol c ondit i on r ating unit min. typ. max. sck input cycle (slave mode) t scyc h igh - speed oscillation is not active 10 D D s h igh speed oscillation is active 500 D D n s sck output cycle (master mode) t scyc D D sck* 1 D s sck input pulse width (slave mode) t sw h igh - speed oscillation is not active 4 D D s h igh spe e d oscillation is active 200 D D ns sck output pulse width (master mode) t sw D t scyc 0.4 t scyc 0.5 t scyc 0.6 s sout output delay time (slave mode) t sd D D D 180 ns sout output delay time (master mode) t sd D D D 80 ns sin input s etup time (slave mode ) t ss D 50 D D ns sin input h o ld time t sh D 50 D D ns * 1 the clock period which is selected by the below registers(min:250ns@reguraly, min:500ns@p02, p22 is used) in case of ssio : s0ck2 - 0 of serial port 0 mode register(sio0mod). in case of ssiof : sf0b r9 - 0 of siof0 port register(sf0brr) t sd sck 0 sckf0 sin 0 sinf0 sout 0 soutf0 t sd t ss t sh t sw t s cyc t sw
fed l620 q504h - 01 ml620 q503h / q504h 27/ 3 5 ac characteristics ( v dd =1. 8 to 5.5 v , v ss = 0 v , ta = - 4 0 to + 85 c , unl ess otherwise specified ) p arameter s ymbol c ondition r ating unit min. typ. max. scl clock frequency f scl D 0 D 100 khz scl hold time (start / restart condition) t hd:sta D 4.0 D D s scl ?l ? level time t low D 4.7 D D s scl ?h ? level time t high D 4.0 D D s scl setup time (restart condition) t su:sta D 4.7 D D s sda hold time t hd:dat D 0 D 3.45 s sda setup time t su:dat D 0.25 D D s s cl setup time (stop condition) t su:sto D 4.0 D D s bus - free time t buf D 4.7 D D s ac characteristics ( v dd =1. 8 to 5.5 v , v ss = 0v , ta = - 4 0 to + 85 c , unless otherwise specified ) p arameter s ymbol c ondition r ateing unit min. typ. max. scl clock frequency f scl D 0 D 400 khz scl hold time (start/restart condition) t hd:sta D 0.6 D D s scl ?l ? level time t low D 1.3 D D s scl ?h ? level time t high D 0. 6 D D s scl setup time (restart condition) t su:sta D 0.6 D D s sda hold time t hd:dat D 0 D 0.9 s sda setup time t su:dat D 0.1 D D s s cl setup time (stop condition) t su:sto D 0.6 D D s bus - free time t buf D 1.3 D D s scl sda start condition restart condition s top condition t buf t hd :sta t low t high t su:sta t hd:sta t su:dat t hd:dat t su:sto
fed l620 q504h - 01 ml620 q503h / q504h 28/ 3 5 ac character istics ( v dd =1. 8 ~ 5.5 v, v ss = 0v , ta = - 40 ~ +85 oscillation frequency v dd = 3.0v cvr=820pf cs=560pf ramd0=0 f osc1_0 resister for oscillati on =1k ? 528 ? khz f osc2_0 resister for oscillation =10k ? 59 ? khz f osc3_0 resister for oscillation =100k ? 5.9 ? khz rs to rt oscillation frequency ratio * 1 v dd = 3.0v cvr=820pf cs=560pf ramd0=0 kf1_0 rt0, rt0 - 1, rt1=1k 8.225 8.94 9.655 ? kf2_ 0 rt0, rt0 - 1, rt1=10k 0.99 1 1.01 ? kf3_0 rt0, rt0 - 1, rt1=100k 0.093 0.101 0.109 ? oscillation frequency v dd = 5 .0v cvr=820pf cs=560pf ramd0=1 f osc1_0 resister for oscillation =1k ? 528 ? khz f osc2_0 resister for oscillation =10k ? 59 ? khz f osc 3_0 resister for oscillation =100k ? 5.9 ? khz rs to rt oscillation frequency ratio * 1 v dd = 5 .0v cvr=820pf cs=560pf ramd0=1 kf1_0 rt0, rt0 - 1, rt1=1k 8.225 8.94 9.655 ? kf2_0 rt0, rt0 - 1, rt1=10k 0.99 1 1.01 ? kf3_0 rt0, rt0 - 1, rt1=100k 0.093 0.101 0.109 ? * 1 kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor o n the same conditions. kfx = f oscx (rt0 - cs0 oscillation) f oscx (rt0 - 1 - cs0 oscillation) f oscx (rt1 - cs1 oscillation) f oscx (rs0 - cs0 oscillation) , f oscx (rs0 - cs0 oscillation) , f oscx (rs1 - cs1 oscillation) ( x = 1, 2, 3 )
fed l620 q504h - 01 ml620 q503h / q504h 29/ 3 5 measuring circuit note ? pl ease have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and in0/in1 pin), including cvr0/cvr1. especially, do not have long wire between in0/in1 and rs0/rs1. the coupling capacitance on t he wires may occur incorrect a/d conversion. also, please do not have signals which may be a source of noise around the node. ? when rt0/rt1 (thermistor and etc.) requires long wiring due to the restricted placement, please shield the signal by v ss (gnd) . ? please make wiring to components (capacitor, resist or and etc.) necess a ry for objective measurement. wiring to rese rved components may affect to the a/d conversion operation by noise the components itself may have . v dd v ref v ddl v ddx c l1 c l0 c x v ss c v rt0, rt0 - 1, rt1: 1k cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf rcm m easure frequency (f oscx ) input pins vih vil (*1) input logi c circuit to determine the specified measuring conditions. cs0 rt0 in1 cs1 rs1 rt1 cs0 rs0 rs0 r c t0 r t 0 - 1 ct0 rt0 cs1 rs1 rt1 in0 cvr0 cvr1 (*1)
fed l620 q504h - 01 ml620 q503h / q504h 30/ 3 5 electrical characteristics of successive approximation type a/d converter ( v dd = 1.8 to 5.5 v , v ss = 0v , ta = - 4 0 to + 85 c , unless otherwi se specified ) parame ter s ymbol c ondition r ating u nit min. typ. max. r esolution n D D D Q Q D Q < D Q < D + 10 differential non- linearity error dnl 2.7v Q Q D Q < D Q < D + 9 zero - scale error v off 2.2v Q Q D + 6 1.8v Q v ref < D + 10 full - scale error fse 2.2v Q v ref Q 5.5 v -6 D + 6 1.8v Q < D + 10 i nput impidance ri D D D 5 k reference voltage v ref D 1.8 D v dd v c onversion time t conv u sing high - speed clock (max. 4mhz) D 170 D c lk using low - speed clock D 16 D measuring circuit a v dd v ss - ri Q
fed l620 q504h - 01 ml620 q503h / q504h 31/ 3 5 power - on and shutdown procedures in case of power - on or shutdown of v dd , the procedures and constraint s are shown as following. v dd 30mv or less over 2sec 0.1 v dd 0.9 v dd 10ms or less ( v ss = 0)
fed l620 q504h - 01 ml620 q503h / q504h 32/ 3 5 application circuit example *: make a decision the parameters afte r evaluating on an user ? s con ditions when designing circuits for mass production. p50 /sda c d h p11/osc1 r d 16m hz xtal c v : 1uf * c l1 : 2.2uf c l0 : open* c x 1 : 0.33 uf c gl : 12~ 16pf * c dl : 12~ 16pf * c g h : 12~ 20pf * c d h : 12~ 20pf * r d : 0 ? * c av : 1uf * r s0, r s1 : 1 0 k ? cs0, cs1 : 560 pf cvr0, cvr1 : 820 pf rt0, rt1 : thermistor (103at/se mitec) x h : nx8045gb / 16.000mhz, nihon denpa kogyo x l : dt -26, daishinku x h x l 3.3v c v v dd reset_n reset_n test0 test1_n c x1 c l1 c l0 v ddx v ddl v ss c g h p10/osc0 c d l c g l p xt0 /xt0 pxt1/ xt1 32.768 k hz xtal p33 /md0 buzzer p40 /led p41 /led p32 (output) p51 /scl sda scl wp vcc a0 a1 a2 vss led i 2 c eeprom ml620 q503h / q504h p00/in0 p01/cs0 p03/rs0 p04/rt0 p02/rct0 p05/rcm p20/in1 p21/cs1 p22/rs1 p23/rt1 v ref cs0 cvr0 rs0 rt0 rs1 cs1 rt1 c av cvr1
fed l620 q504h - 01 ml620 q503h / q504h 33/ 3 5 package dimensions ml620 q503h / q504h package dimensions notes for mounting the surface mount type package the surface mount type packages are very suscepti ble to heat in reflow and humidity absorbed in storage. therefore, before you perform reflow mounting, contact a rohm sales office for the product name, package name, pin number, package code and desired mounting conditions(reflow method, temperature and t imes).
fed l620 q504h - 01 ml620 q503h / q504h 34/ 3 5 revision history document no. date page description previous edition current edition fedl620 q504h - 01 aug . 31 .201 5 ? ? fi nal e dition issued
fed l620 q504h - 01 ml620 q503h / q504h 35/ 3 5 notes 1) the information cont ained herein is subject to change without notice. 2) although lapis semiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. therefore, in order to prevent person al injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail - safe procedures. lapis semiconductor shall have no responsibility for any damages arising out of the use of our products beyond the rating specified by lapis semiconductor. 3) examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate the st andard usage and operations of the products.the peripheral conditions must be taken into account when designing circuits for mass production. 4) the technical information specified herein is intended only to show the typical functions of the products and exa mples of application circuits for the products. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of lapis semiconductor or any third party with respect to the information contained in this document ; therefore lapis semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) the products are intended for use in general electronic equipment (i.e. av/oa devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) the products specified in this document are not designed to be radiation tolerant. 7) for use of our products in applic ations requiring a high degree of reliability (as exemplified below), please contact and consult with a lapis semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime pre vention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) do not use our products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repea ters. 9) lapis semiconductor shall have no responsibility for any damages or injury arising from non - compliance with the recommended usage conditions and specifications contained herein. 10) lapis semiconductor has used reasonable care to ensure the accuracy of the information contained in this document. however, lapis semiconductor does not warrant that such information is error - free and lapis semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such informatio n. 11) please use the products in accordance with any applicable environmental laws and regulations, such as the rohs directive. for more details, including rohs compatibility, please contact a rohm sales office. lapis semiconductor shall have no responsibili ty for any damages or losses resulting non - compliance with any applicable laws or regulations. 12) when providing our products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all ap plicable export laws and regulations, including without limitation the us export administration regulations and the foreign exchange and foreign trade act. 13) this document, in part or in whole, may not be reprinted or reproduced without prior consent of lap is semiconductor. copyright 2015 lapis semiconductor co., ltd. 2 - 4 - 8 shinyokohama, kouhoku - ku, yokohama 222 - 8575, japan http://www.lapis - semi.com/en/

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