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rev. 1.0 7/15 copyright ? 2015 by silicon laboratories si5341/40 si5341/40 l ow -j itter , 10-o utput , a ny -f requency , a ny -o utput c lock g enerator features device sele ctor guide applications description ? generates up to 10 independent output clocks ? ultra-low jitter: <100 fs rms typical ? multisynth? technology enables any- frequency synthesis on any-output ? highly configurable outputs compatible with lvds, lvpecl, cml, lvcmos, hcsl, or programmable voltage ? input frequency range: ?? external crystal: 25, 48-54 mhz ?? differential clock: 10 to 750 mhz ?? lvcmos clock: 10 to 250 mhz ? output frequency range: ?? differential: 100 hz to 712.5 mhz ?? lvcmos: 100 hz to 250 mhz ? output-output skew: 20 ps typ ? adjustable output-output delay ? optional zero delay mode ? independent glitchless on-the-fly output frequency changes ? dco mode with frequency steps as low as 0.001 ppb ? independent output clock supply pins: 3.3 v, 2.5 v, or 1.8 v ? built-in power supply filtering and regulation ? status monitoring: los, lol ? serial interface: i 2 c or spi (3-wire or 4-wire) ? user programmable (2x) non-volatile otp memory ? clockbuilder tm pro software utility simplifies device configuration and assigns customer part numbers ? si5341 : 4 input, 10 output, compact 9x9 mm, 64 qfn ? SI5340 : 4 input, 4 output, compact 7x7 mm, 44 qfn ? temperature range: ?40 to +85 c ? pb-free, rohs -6 compliant grade max output frequency f requency synthesis mode si534xa 712.5 mhz integer + fractional si534xb 350 mhz si534xc 712.5 mhz integer only si534xd 350 mhz ? clock tree generation replacing xos, buffers, signal format translators ? any-frequency clock translation ? clocking for fpgas, processors, memory ? ethernet switches/routers ? otn framers/mappers/processors ? test equipment & instrumentation ? broadcast video functional block diagram ordering information see section 8. 9x9 mm 7x7 mm si5341/40 fb_in in0 in_sel[1:0] in1 in2 xb xa xtal int int int osc multi synth out0 int out1 int out2 int out3 int out4 int out5 int out6 int out7 int out8 int out9 int multi synth multi synth multi synth multi synth SI5340 si5341 pll int nvm i 2 c/spi control/ status
si5341/40 2 rev. 1.0
si5341/40 rev. 1.0 3 t able o f c ontents 1. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4. detailed block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 5. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 5.1. power-up and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2. frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3. inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.4. fault monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1 5.5. outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.6. power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.7. in-circuit programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.8. serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 5.9. custom factory preprogr ammed devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.10. enabling features and/or configuration settings not av ailable in clockbuilder pro for factory pre-programmed devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1. addressing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.2. high-level register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9. package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 9.1. si5341 9x9 mm 64-qfn package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 9.2. SI5340 7x7 mm 44-qfn package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10. pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 12. device errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
si5341/40 4 rev. 1.0 1. typical application schematic figure 1. using the si5341 to replace a traditional clock tree xa xb 25 mhz traditional disc rete clock tree level translator clock generator 161.1328125 mhz buffer 133.33 mhz buffer one si5341 replaces: 3x crystal oscillators (xo) 2x buffers 1x clock generator 2x level translators 1x delay line clock tree on-a-chip xa xb 25 mhz 200 mhz 2.5v lvcmos 2x 161.1328125 mhz lvds 2x 133.33 mhz 1.8v lvcmos buffer 125 mhz level translator buffer delay line 4x 125 mhz 3.3v lvcmos 3x 125 mhz lvpecl si5341 1x 161.1328125 mhz lvds 1x 161.1328125 mhz lvds 2x 133.33 mhz 1.8v lvcmos 2x 125 mhz 3.3v lvcmos 2x 125 mhz 3.3v lvcmos 2x 200 mhz 2.5v lvcmos 2x 200 mhz 2.5v lvcmos 1x 125 mhz lvpecl 1x 125 mhz lvpecl 1x 125 mhz lvpecl
si5341/40 rev. 1.0 5 2. electrical specifications table 1. recommended operating conditions (v dd =1.8v 5%, v dda =3.3v 5%,t a = ?40 to 85 c) parameter symbol min typ max units ambient temperature t a ? 4 02 58 5 c junction temperature tj max ??1 2 5 c core supply voltage v dd 1.71 1.80 1.89 v v dda 3.14 3.30 3.47 v output driver supply voltage v ddo 3.14 3.30 3.47 v 2.38 2.50 2.62 v 1.71 1.80 1.89 v *note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise noted.
si5341/40 6 rev. 1.0 table 2. dc characteristics (v dd =1.8v 5%, v dda =3.3v 5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max units core supply current i dd si5341 note 1 ? 100 150 ma SI5340 note 2 ?85130ma i dda si5341 note 1 ?115125ma SI5340 note 2 ?115125ma output buffer supply current i ddox lvpecl output 3 @ 156.25 mhz ?2125ma lvds output 3 @ 156.25 mhz ?1518ma 3.3 v lvcmos 4 output @ 156.25 mhz ?2125ma 2.5 v lvcmos 4 output @ 156.25 mhz ?1618ma 1.8 v lvcmos 4 output @ 156.25 mhz ?1213ma total power dissipation p d si5341 notes 1,5 ? 830 980 mw SI5340 notes 2,5 ? 685 815 mw notes: 1. si5341 test configuration: 7 x 2.5 v lvds outputs enab led @156.25 mhz. excludes power in termination resistors. 2. SI5340 test configuration: 4 x 2.5 v lvds outputs enabl ed @ 156.25 mhz. excludes power in termination resistors. 3. differential outputs terminated into an ac-coupled 100 ?? load. 4. lvcmos outputs measured into a 6-inch 50 ? pcb trace with 5 pf load. the lvcmos outputs were set to outx_cmos_drv=3, which is th e strongest driver setting. refer to the si 5341/40 family reference manual for more details on register settings. 5. detailed power consumption for any c onfiguration can be estimated using clockbuilderpro when an evaluation board (evb) is not available. all evbs support detaile d current measurements for any configuration. 50 50 100 out out i ddo differential output test configuration 0.1 uf 0.1 uf 50 outa i ddo 5 pf lvcmos output test configuration 6 inch outb
si5341/40 rev. 1.0 7 table 3. input specifications (v dd =1.8v 5%, v dda =3.3v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max units differential or single-ended/ lvcmos ac-coupled (in0/in0 , in1/in1 , in2/in2 , fb_in/fb_in ) input frequency range f in differential 10 ? 750 mhz single-ended/lvcmos 10 ? 250 input voltage swing 5 v in differential ac coupled fin < 250 mhz 100 ? 1800 mvpp_se differential ac coupled 250 mhz < fin < 750 mhz 225 ? 1800 mvpp_se single-ended ac coupled fin < 250 mhz 100 ? 3600 mvpp_se slew rate 1, 2 sr 400 ? ? v/s duty cycle dc 40 ? 60 % capacitance c in ?2 ? pf dc-coupled cmos input buffer (in0, in1, in2) 4 input frequency f in 10 ? 250 mhz input voltage v il ?0.2 ? 0.33 v v ih 0.49 ? ? v slew rate 1, 2 sr 400 ? ? v/s duty cycle dc clock input 40 ? 60 % minimum pulse width pw pulse input 1.6 ? ? ns input resistance r in ?8 ? k ? differential or single-ended/lvcmos clock at xa/xb input frequency range f in frequency range for best output jitter performance 48 ? 200 mhz 10 ? 200 mhz input single-ended voltage swing v in_se 365 ? 2000 mvpp_se notes: 1. imposed for jitter performance. 2. rise and fall times can be estimated usi ng the following simplified equation: tr/tf 80-20 = ((0.8 - 0.2) * v in_vpp_se ) / sr. 3. v ddio is determined by the io_vdd_sel bit. it is selectable as v dda or v dd . 4. dc-coupled cmos input buffer selection is not supported in clockbuilder pro for new designs. for single-ended lvcmos inputs to in0,1,2 it is required to ac-couple into the differential input buffer. 5. voltage swing is specified as single-ended mvpp. 6. contact silicon labs technical support for more details. ?
si5341/40 8 rev. 1.0 input differential voltage swing v in_diff 365 ? 2500 mvpp_diff slew rate 1, 2 sr imposed for best jitter per- formance 400 ? ? v/s input duty cycle dc 40 ? 60 % table 4. control input pin specifications (v dd =1.8v 5%, v dda =3.3v 5%, v dds = 3.3 v 5%, 1.8 v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max units si5341 control input pins (i2c_sel, in_sel[1:0], rst , oe , sync , a1, sclk, a0/cs , finc, fdec, sda/sdio) input voltage v il ? ? 0.3xv ddio *v v ih 0.7xv ddio *? ? v input capacitance c in ?2? pf input resistance r in ?20? k ? minimum pulse width t pw rst , sync , finc, and fdec 100 ? ? ns frequency update rate f ur finc and fdec ? ? 1 mhz SI5340 control input pins (i 2c_sel, in_sel[1:0], rst , oe , a1, sda, sdi, sclk, a0/cs , sda/sdio) input voltage v il ? ? 0.3xv ddio *v v ih 0.7xv ddio *? ? v input capacitance c in ?2? pf input resistance r in ?20? k ? minimum pulse width t pw rst only 100 ? ? ns *note: v ddio is determined by the io_vdd_se l bit. it is selectable as v dda or v dd . refer to the reference manual for more details on register settings. table 3. input specifications (v dd =1.8v 5%, v dda =3.3v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max units notes: 1. imposed for jitter performance. 2. rise and fall times can be estimated usi ng the following simplified equation: tr/tf 80-20 = ((0.8 - 0.2) * v in_vpp_se ) / sr. 3. v ddio is determined by the io_vdd_sel bit. it is selectable as v dda or v dd . 4. dc-coupled cmos input buffer selection is not supported in clockbuilder pro for new designs. for single-ended lvcmos inputs to in0,1,2 it is required to ac-couple into the differential input buffer. 5. voltage swing is specified as single-ended mvpp. 6. contact silicon labs technical support for more details. ?
si5341/40 rev. 1.0 9 table 5. differential clock output specifications (v dd = 1.8 v 5%, v dda =3.3v 5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = ?40 to 85 c) parameter symbol test co ndition min typ max units output frequency f out 0.0001 ? 712.5 mhz duty cycle dc f out < 400 mhz 48 ? 52 % 400 mhz < f out < 712.5 mhz 45 ? 55 % output-output skew t sk outputs on same multisynth, normal mode ?2050 ps outputs on same multisynth, pow power mode ?20100 ps out-out skew t sk_out measured from the positive to negative output pins ?0100 ps output amplitude 1, 5 normal mode v out v ddo =3.3v, 2.5 v, or 1.8 v lvds 350 470 550 mvpp_se v ddo =3.3v or 2.5 v lvpecl 660 810 1000 low power mode v out v ddo =3.3v, 2.5 v, or 1.8 v lvds 300 420 530 mvpp_se v ddo =3.3v or 2.5 v lvpecl 620 820 1060 notes: 1. the typical normal mode (or low power mode) lvds maxi mum is 100 mv (or 80 mv) higher than the tia/eia-644 maximum. for normal and low-power modes, the amplitudes are programmable through register settings and can be stored in nvm. each output driver can be programmed independently. see a ppendix a of the si5341/40 reference manual. 2. driver output impedance depends on se lected output mode (normal, low power). 3. measured for 156.25 mhz carrier frequency. sinewav e noise added to vddo (1.8 v = 50 mvpp, 2.5 v/ 3.3 v = 100 mvpp) and noise spur amplitude measured. 4. measured across two adjacent outputs, both in lvds mode , with the victim running at 155.52 mhz and the aggressor at 156.25 mhz. refer to application note, ?an862: optimizi ng si534x jitter performance in next generation internet infrastructure systems?, guidan ce on crosstalk minimization. 5. for other amplitudes see appendix a of the si5341/40 reference manual. 6. see note 4, but in this case the m easurement is across two output clocks that have a single clock between them. 7. same as note 4, but the SI5340 has less crosstalk due to the spacing of adjacent outputs. outx outx vpp_se vpp_se vpp_diff = 2*vpp_se vcm vcm
si5341/40 10 rev. 1.0 common mode voltage 1 normal mode or low power modes v cm v ddo = 3.3 v lvds 1.10 1.25 1.35 v lvpecl 1.90 2.05 2.15 v ddo = 2.5 v lvpecl lvds 1.15 1.25 1.35 v ddo = 1.8 v sub-lvds 0.87 0.93 1.0 rise and fall times (20% to 80%) t r /t f normal mode ? 170 240 ps low power mode ? 300 430 differential output impedance 2 z o normal mode ? 100 ? ? low power mode ? 650 ? ? power supply noise rejection 3 psrr normal mode 10 khz sinusoidal noise ? ?93 ? dbc 100 khz sinusoidal noise ? ?93 ? 500 khz sinusoidal noise ? ?84 ? 1 mhz sinusoidal noise ? ?79 ? low power mode 10 khz sinusoidal noise ? ?98 ? dbc 100 khz sinusoidal noise ? ?95 ? 500 khz sinusoidal noise ? ?84 ? 1 mhz sinusoidal noise ? ?76 ? table 5. differential clock output specifications (continued) (v dd = 1.8 v 5%, v dda =3.3v 5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = ?40 to 85 c) parameter symbol test co ndition min typ max units notes: 1. the typical normal mode (or low power mode) lvds maxi mum is 100 mv (or 80 mv) higher than the tia/eia-644 maximum. for normal and low-power modes, the amplitudes are programmable through register settings and can be stored in nvm. each output driver can be programmed independently. see a ppendix a of the si5341/40 reference manual. 2. driver output impedance depends on se lected output mode (normal, low power). 3. measured for 156.25 mhz carrier frequency. sinewav e noise added to vddo (1.8 v = 50 mvpp, 2.5 v/ 3.3 v = 100 mvpp) and noise spur amplitude measured. 4. measured across two adjacent outputs, both in lvds mode , with the victim running at 155.52 mhz and the aggressor at 156.25 mhz. refer to application note, ?an862: optimizi ng si534x jitter performance in next generation internet infrastructure systems?, guidan ce on crosstalk minimization. 5. for other amplitudes see appendix a of the si5341/40 reference manual. 6. see note 4, but in this case the m easurement is across two output clocks that have a single clock between them. 7. same as note 4, but the SI5340 has less crosstalk due to the spacing of adjacent outputs. outx outx vpp_se vpp_se vpp_diff = 2*vpp_se vcm vcm
si5341/40 rev. 1.0 11 output-output crosstalk xtalk si5341 note 4 ??75? dbc si5341 note 6 ??85? dbc SI5340 note 7 ??85? dbc table 6. output status pin specifications (v dd =1.8v 5%, v dda =3.3v 5%, v dds = 3.3 v 5%, 1.8 v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max units si5341 status output pins (lol , intr ), sda/sdio 2 , sdo output voltage v oh i oh = ?2 ma v ddio 1 x 0.75 ? ? v v ol i ol = 2 ma ? ? v ddio 1 x 0.15 v SI5340 status output pins (intr ), lol , los_xaxb , sda/sdio 2 , sdo output voltage v oh i oh = ?2 ma v ddio 1 x 0.75 ? ? v v ol i ol = 2 ma ? ? v ddio 1 x 0.15 v notes: 1. v ddio is determined by the io_vdd_sel bit. it is selectable as v dda or v dd . refer to the reference manual for more details on register settings. 2. the v oh specification does not apply to the open-drain sda/sdio ou tput when the serial interface is in i2c mode or is unused with i2c_sel pulled high. v ol remains valid in all cases. table 5. differential clock output specifications (continued) (v dd = 1.8 v 5%, v dda =3.3v 5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = ?40 to 85 c) parameter symbol test co ndition min typ max units notes: 1. the typical normal mode (or low power mode) lvds maxi mum is 100 mv (or 80 mv) higher than the tia/eia-644 maximum. for normal and low-power modes, the amplitudes are programmable through register settings and can be stored in nvm. each output driver can be programmed independently. see a ppendix a of the si5341/40 reference manual. 2. driver output impedance depends on se lected output mode (normal, low power). 3. measured for 156.25 mhz carrier frequency. sinewav e noise added to vddo (1.8 v = 50 mvpp, 2.5 v/ 3.3 v = 100 mvpp) and noise spur amplitude measured. 4. measured across two adjacent outputs, both in lvds mode , with the victim running at 155.52 mhz and the aggressor at 156.25 mhz. refer to application note, ?an862: optimizi ng si534x jitter performance in next generation internet infrastructure systems?, guidan ce on crosstalk minimization. 5. for other amplitudes see appendix a of the si5341/40 reference manual. 6. see note 4, but in this case the m easurement is across two output clocks that have a single clock between them. 7. same as note 4, but the SI5340 has less crosstalk due to the spacing of adjacent outputs. outx outx vpp_se vpp_se vpp_diff = 2*vpp_se vcm vcm
si5341/40 12 rev. 1.0 table 7. lvcmos clock output specifications (v dd = 1.8 v 5%, v dda =3.3v 5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max units output frequency 0.0001 ? 250 mhz duty cycle dc f out < 100 mhz 47 ? 53 % 100 mhz < f out < 250 mhz 44 ? 55 output-to-output skew t sk ??100ps output voltage high 1, 2, 3 v oh v ddo = 3.3 v outx_cmos_drv=1 i oh = ?10 ma v ddo x 0.75 ?? v outx_cmos_drv=2 i oh = ?12 ma ? ? outx_cmos_drv=3 i oh = ?17 ma ? ? v ddo = 2.5 v outx_cmos_drv=1 i oh = ?6 ma v ddo x 0.75 ?? v outx_cmos_drv=2 i oh = ?8 ma ? ? outx_cmos_drv=3 i oh = ?11 ma ? ? v ddo = 1.8 v outx_cmos_drv=2 i oh = ?4 ma v ddo x 0.75 ?? v outx_cmos_drv=3 i oh = ?5 ma ? ? notes: 1. driver strength is a register programma ble setting and stored in nvm. options are outx_cmos_drv = 1, 2, 3. refer to the reference manual for more details on register settings. 2. i ol /i oh is measured at v ol /v oh as shown in the dc test configuration. 3. a series termination resistor (r s) is recommended to help match the source impedance to a 50 ? pcb trace. a 5 pf capacitive load is assumed. the lvcmos outputs were set to outx_cmos_drv = 3. dc test configuration zs i ol /i oh v ol /v oh 50 ? out out i ddo trace length 5 inches 50 ? 4.7 pf 4.7 pf 56 ? 499 ? 499 ? 56 ? ac test configuration 50 ?? probe, scope 50 ?? probe, scope 0.1 uf 0.1 uf
si5341/40 rev. 1.0 13 output voltage low 1, 2, 3 v ol v ddo = 3.3 v outx_cmos_drv=1 i ol =10ma ? ? v ddo x 0.15 v outx_cmos_drv=2 i ol =12ma ? ? outx_cmos_drv=3 i ol =17ma ? ? v ddo =2.5v outx_cmos_drv=1 i ol =6ma ? ? v ddo x 0.15 v outx_cmos_drv=2 i ol =8ma ? ? outx_cmos_drv=3 i ol =11ma ? ? v ddo =1.8v outx_cmos_drv=2 i ol =4ma ? ? v ddo x 0.15 v outx_cmos_drv=3 i ol =5ma ? ? lvcmos rise and fall times 3 (20% to 80%) tr/tf vddo = 3.3v ? 420 550 ps vddo = 2.5 v ? 475 625 ps vddo = 1.8 v ? 525 705 ps table 7. lvcmos clock output specifications (continued) (v dd = 1.8 v 5%, v dda =3.3v 5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max units notes: 1. driver strength is a register programma ble setting and stored in nvm. options are outx_cmos_drv = 1, 2, 3. refer to the reference manual for more details on register settings. 2. i ol /i oh is measured at v ol /v oh as shown in the dc test configuration. 3. a series termination resistor (r s) is recommended to help match the source impedance to a 50 ? pcb trace. a 5 pf capacitive load is assumed. the lvcmos outputs were set to outx_cmos_drv = 3. dc test configuration zs i ol /i oh v ol /v oh 50 ? out out i ddo trace length 5 inches 50 ? 4.7 pf 4.7 pf 56 ? 499 ? 499 ? 56 ? ac test configuration 50 ?? probe, scope 50 ?? probe, scope 0.1 uf 0.1 uf
si5341/40 14 rev. 1.0 table 8. performance characteristics (v dd =1.8v 5%, v dda =3.3v 5%, t a =?40 to 85c) parameter symbol test condition min typ max units v co frequency range f vco 13.5 ? 14.256 ghz pll loop bandwidth f bw ?1.0? mhz initial start-up time t start time from power-up to when the device generates clocks (input frequency > 48 mhz) ?3045 ms por 1 to serial interface ready t rdy ??15 ms pll lock time 6 t acq f in = 19.44 mhz 22 ? 180 ms output delay adjustment t delay_- frac f vco =14ghz delay is controlled by the multi- synth ?0.28? ps t delay_int ?71.4? ps t range ? 9.14 ? ns jitter generation locked to external clock 2 j gen integer mode 3 12 khz to 20 mhz ? 0.135 0.175 ps rms fractional/dco mode 4 12 khz to 20 mhz ? 0.160 0.205 ps rms j per derived from integrated phase noise ? 0.140 ? ps pk-pk j cc ? 0.250 ? ps pk j per n = 10,000 cycles integer or fractional mode 3,4 . measured in the time domain. performance is limited by the noise floor of the equipment. ? 7.3 ? ps pk-pk j cc ?8.1? ps pk notes: 1. measured as time from valid v dd and v dd33 rails (90% of their value) to when the serial interface is ready to respond to commands. measured in spi 4-wire mode, with sclk @ 10 mhz. 2. jitter generation test conditions f in = 100 mhz, f out = 156.25 mhz lvpecl. 3. integer mode assumes that the ou tput dividers (nn/nd) are conf igured with an integer value. 4. fractional and dco modes assume that the output dividers (nn/nd) are configured with a fractional value and the feedback divider is integer. 5. initiate a soft reset command to align the outputs to within +/- 100 ps. 6. pll lock time is measured by first letting the pll lock, then tu rning off the input clock, and then turning on the input clock. the time from the first edge of the input clock being re-applied until lol de-asserts is the pll lock time.
si5341/40 rev. 1.0 15 jitter generation locked to external xtal xtal frequency = 48 mhz j gen integer mode 3 12 khz to 20 mhz ? 0.090 0.150 ps rms fractional/dco mode 4 12 khz to 20 mhz ? 0.120 0.165 ps rms j per derived from integrated phase noise ? 0.150 ? ps pk-pk j cc ? 0.270 ? ps pk j per n = 10, 000 cycles integer or fractional mode 3,4 . measured in the time domain. performance is limited by the noise floor of the equipment. ? 7.3 ? ps pk-pk j cc ?7.8? ps pk xtal frequency = 25 mhz j gen integer mode 12 khz to 20 mhz 0.125 0.330 ps rms fractional 12 khz to 20 mhz 0.170 0.360 ps rms table 8. performance characteristics (continued) (v dd =1.8v 5%, v dda =3.3v 5%, t a =?40 to 85c) parameter symbol test condition min typ max units notes: 1. measured as time from valid v dd and v dd33 rails (90% of their value) to when the serial interface is ready to respond to commands. measured in spi 4-wire mode, with sclk @ 10 mhz. 2. jitter generation test conditions f in = 100 mhz, f out = 156.25 mhz lvpecl. 3. integer mode assumes that the ou tput dividers (nn/nd) are conf igured with an integer value. 4. fractional and dco modes assume that the output dividers (nn/nd) are configured with a fractional value and the feedback divider is integer. 5. initiate a soft reset command to align the outputs to within +/- 100 ps. 6. pll lock time is measured by first letting the pll lock, then tu rning off the input clock, and then turning on the input clock. the time from the first edge of the input clock being re-applied until lol de-asserts is the pll lock time.
si5341/40 16 rev. 1.0 table 9. i 2 c timing specifications (scl,sda) parameter symbol test condition min max min max units standard mode 100 kbps fast mode 400 kbps scl clock frequency f scl ? 100 ? 400 khz hold time (repeated) start condition t hd:sta 4.0 ? 0.6 ? s low period of the scl clock t low 4.7 ? 1.3 ? s high period of the scl clock t high 4.0 ? 0.6 ? s set-up time for a repeated start condition t su:sta 4.7 ? 0.6 ? s data hold time t hd:dat 100 ? 100 ? ns data set-up time t su:dat 250 ? 100 ? ns rise time of both sda and scl signals t r ? 1000 20 300 ns fall time of both sda and scl signals t f ? 300 ? 300 ns set-up time for stop condition t su:sto 4.0 ? 0.6 ? s bus free time between a stop and start con- dition t buf 4.7 ? 1.3 ? s data valid time t vd:dat ?3.45 ? 0.9s data valid acknowledge time t vd:ack ?3.45 ? 0.9s
si5341/40 rev. 1.0 17 figure 2. i 2 c serial port timing standard and fast modes
si5341/40 18 rev. 1.0 figure 3. 4-wire spi serial interface timing table 10. spi timing specifications (4-wire) (v dd = 1.8 v 5%, v dda = 3.3v 5%, t a =?40 to 85c) parameter symbol min typ max units sclk frequency f spi ??20mhz sclk duty cycle t dc 40 ? 60 % sclk period t c 50 ? ? ns delay time, sclk fall to sdo active t d1 ?12.518 ns delay time, sclk fall to sdo t d2 ?1015ns delay time, cs rise to sdo tri-state t d3 ?1015ns setup time, cs to sclk t su1 5??ns hold time, cs to sclk rise t h1 5??ns setup time, sdi to sclk rise t su2 5??ns hold time, sdi to sclk rise t h2 5??ns delay time between chip selects (cs )t cs 2??t c sclk cs sdi sdo t su1 t d1 t su2 t d2 t c t cs t d3 t h2 t h1
si5341/40 rev. 1.0 19 figure 4. 3-wire spi serial interface timing table 11. spi timing specifications (3-wire) (v dd = 1.8 v 5%, v dda =3.3v 5%, t a = ?40 to 85 c) parameter symbol min typ max units sclk frequency f spi ??20mhz sclk duty cycle t dc 40 ? 60 % sclk period t c 50 ? ? ns delay time, sclk fall to sdio turn-on t d1 ?12.520 ns delay time, sclk fall to sdio next-bit t d2 ?1015ns delay time, cs rise to sdio tri-state t d3 ?1015ns setup time, cs to sclk t su1 5??ns hold time, cs to sclk rise t h1 5??ns setup time, sdi to sclk rise t su2 5??ns hold time, sdi to sclk rise t h2 5??ns delay time between chip selects (cs )t cs 2??t c sclk cs sdio t su1 t d1 t su2 t d2 t c t cs t d3 t h2 t h1
si5341/40 20 rev. 1.0 table 12. crystal specifications parameter symbol test condition min typ max units crystal frequency range f xtal_48-54 frequency range for best jitter performance 48 ? 54 mhz load capacitance c l_48-54 ?8?pf shunt capacitance c o_48-54 ?? 2 pf crystal drive level d l_48-54 ??200w equivalent series resistance r esr_48-54 refer to the si5341/40 family reference manual to determine esr. crystal frequency range f xtal_25 ?25?mhz load capacitance c l_25 ?8?pf shunt capacitance c o_25 ?? 3 pf crystal drive level d l_25 ??200w equivalent series resistance r esr_25 refer to the si5341/40 family reference manual to determine esr notes: 1. the si5341/40 is designed to work with crystals that meet the specifications in table 12. 2. refer to the si5341/40 family reference manual for recommended 48 to 54 mhz crystals.
si5341/40 rev. 1.0 21 table 13. thermal characteristics parameter symbol test condition * value units si5341 64qfn thermal resistance junction to ambient ? ja still air 22 c/w air flow 1 m/s 19.4 air flow 2 m/s 18.3 thermal resistance junction to case ? jc 9.5 thermal resistance junction to board ? jb 9.4 ? jb 9.3 thermal resistance junction to top center ? jt 0.2 SI5340C44qfn thermal resistance junction to ambient ? ja still air 22.3 c/w air flow 1 m/s 19.4 air flow 2 m/s 18.4 thermal resistance junction to case ? jc 10.9 thermal resistance junction to board ? jb 9.3 ? jb 9.2 thermal resistance junction to top center ? jt 0.23 *note: based on pcb dimension: 3? x 4.5?, pc b thickness: 1.6 mm, pcb land/via und er gnd pad: 36, number of cu layers: 4
si5341/40 22 rev. 1.0 table 14. absolute maximum ratings 1,2,3,4 parameter symbol test condition value units storage temperature range t stg ?55 to +150 c dc supply voltage v dd ?0.5 to 3.8 v v dda ?0.5 to 3.8 v v ddo ?0.5 to 3.8 v input voltage range v i1 in0-in2, fb_in ?0.85 to 3.8 v v i2 in_sel[1:0], rst , oe , sync , i2c_sel, sdi, sclk, a0/cs a1, sda/sdio finc/fdec ?0.5 to 3.8 v v i3 xa/xb ?0.5 to 2.7 v latch-up tolerance lu jesd78 compliant esd tolerance hbm 100 pf, 1.5 k ? 2.0 kv junction temperature t jct ?55 to 150 c soldering temperature (pb-free profile) 4 t peak 260 c soldering temperature time at t peak (pb-free profile) 4 t p 20-40 sec notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. 64-qfn and 44-qfn packages are rohs-6 compliant. 3. for msl and more packaging information, go to www.silabs.com/support/qualit y/pages/rohsinformation.aspx . 4. the device is compliant with jedec j-std-020.
si5341/40 rev. 1.0 23 3. typical operat ing characteristics figure 5. integer mode48 mhz crystal, 625 mhz output (2.5 v lvds) r?x r?x rex r?x rx rx r?x r?x rx rx r?x r?x rex r?x rx rx r?x d l l l d
si5341/40 24 rev. 1.0 figure 6. integer mode48 mhz crystal, 156.25 mhz output (2.5 v lvds) r?x r?x rex r?x rx rx r?x r?x rx rx r?x r?x rex r?x rx rx r?x d l l l d
si5341/40 rev. 1.0 25 figure 7. fractional mode48 mhz crystal, 155.52 mhz output (2.5 v lvds) r?x r?x rex r?x rx rx r?x r?x rx rx r?x r?x rex r?x rx rx r?x l l l d d
si5341/40 26 rev. 1.0 4. detailed block diagrams figure 8. si5341 block diagram vdd vdda 3 sda/sdio a1/sdo sclk a0/cs i2c_sel spi/ i 2 c nvm rst zero delay mode fb_in fb_in oe si5341 generator clock r 0 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 1 out0 vddo0 out0 out2 vddo2 out2 out3 vddo3 out3 out4 vddo4 out4 out5 vddo5 out5 out6 vddo6 out6 out7 vddo7 out7 out8 vddo8 out8 out9 vddo9 out9 out1 vddo1 out1 p fb lpf pd m n m d pll in_sel[1:0] xa xb 25mhz, 48-54mhz xtal p 2 p 1 p 0 in0 in0 in1 in1 in2 in2 fdec finc frequency control n 0n n 0d t 0 n 2n n 2d n 3n n 3d n 4n n 4d t 2 t 3 t 4 n 1n n 1d t 1 multisynth sync dividers/ drivers status monitors lol intr osc p xaxb
si5341/40 rev. 1.0 27 figure 9. SI5340 detailed block diagram rst oe n n0 n d0 t 0 n 2n n 2d n 3n n 3d t 2 t 3 n n1 n d1 t 1 lpf pd pll m n m d lol intr losxab sda/sdio a1/sdo sclk a0/cs i2c_sel spi/ i 2 c nvm status monitors multisynth r 0 r 2 r 3 r 1 out0 vddo0 out0 out2 vddo2 out2 out3 vddo3 out3 out1 vddo1 out1 dividers/ drivers zero delay mode fb_in fb_in p fb in_sel[1:0] p 2 p 1 p 0 in0 in0 in1 in1 in2 in2 xa xb 25mhz, 48-54mhz xtal osc p xaxb SI5340 generator clock vdd vdda 4 2
si5341/40 28 rev. 1.0 5. functional description the si5341/40 combines a wide band pll with next generation multisynth technology to offer the industry?s most versatile and high performanc e clock generator. the pll lo cks to either an external crystal between xa/xb or to an external clock connected to xa/xb or in0,1,2. a fractional or integer multiplier takes the selected input clock or crystal frequency up to a very high frequency that is then divided by the multisynth out put stage to any frequency in the range of 100 hz to 712.5 mhz on each output. the mu ltisynth stage can divide by both integer and fractional values.the high-resolution fractional mult isynth dividers enables true any-frequency input to any-frequency on any of the outputs. the output drivers offer flexible output formats which are independently configurable on each of the outputs. this clock generator is fully configurable via its serial interface (i 2 c/spi) and includes in-circuit programmable non-volatile memory. 5.1. power-up and initialization once power is applied, the device begins an initialization period where it do wnloads default register values and configuration data from nvm and performs other initia lization tasks. communicating with the device through the serial interface is possible once th is initialization period is complete . no clocks will be generated until the initialization is done. there are two types of resets availabl e. a hard reset is functionally similar to a device power- up. all registers will be restored to the values stored in nvm, and all circuits will be restored to their initial state including the serial interface. a hard reset is initiated using the rst pin or by asserting the hard reset bit. a soft reset bypasses the nvm download. it is simply us ed to initiate register configuration changes. figure 10. si5341 power-up and initialization power-up serial interface ready rst pin asserted hard reset bit asserted initialization nvm download soft reset bit asserted
si5341/40 rev. 1.0 29 5.2. frequency configuration the phase-locked loop is fully contained and does not requ ire external loop filter components to operate. its function is to phase lock to the selected input and prov ide a common reference to the multisynth high-performance fractional dividers. a crosspoint mux connects any of the multisynth divide d frequencies to any of the outputs drivers. additional output integer dividers prov ide further frequency division by an even integer from 2 to (2^25)-2. the frequency configuration of the device is programmed by setting the input dividers (p), the pll feedback fractional divider (mn/ md), the multisynth frac tional dividers (nn/nd), and th e output integer dividers (r). silicon labs? clockbuilder pro configuration utility de termines the optimum divider values for any desired i nput and output frequency plan. 5.3. inputs the si5341/40 requires either an external crystal at it s xa/xb pins or an external clock at xa/xb or in0,1,2. 5.3.1. xa/xb clock and crystal input an internal crystal oscillator exists between pin xa and xb. when this oscillator is enabled, an external crystal connected across these pins will oscillate and provide a clock inpu t to the pll. a crystal frequency of 25 mhz can be used although crystals in the frequency range of 48 mhz to 54 mhz are recommended for best jitter performance. frequency offsets due to c l mismatch can be adjusted using the frequency adjustment feature which allows frequency adjustments of 1000 ppm. the si 5341/40 family reference manual provides additional information on pcb layout recommendations for the cr ystal to ensure optimum jitter performance. refer to table 12 for crystal specifications. the si5341/40 can also accommodate an external input clock instead of a crystal. this allows the use of crystal oscillator (xo) instead of a xtal. sele ction between the external xtal or input clock is controlled by register configuration. the internal crystal load capacitors (c l ) are disabled in the input clock mode. refer to table 3 for the input clock requirements at xaxb. both a single-ended or a differ ential input clock can be connected to the xa/xb pins as shown in figure 11. a p xaxb divider is available to accommodate external clock frequencies higher than 54 mhz.
si5341/40 30 rev. 1.0 figure 11. xaxb external crystal and clock connections 5.3.2. input clocks (in0, in1, in2) a differential or single-ended clock can be applied at in2, in1, or in0. the recommended input termination schemes are shown in figure 12. figure 12. termination of differential and lvcmos input signals 100 differentialconnection 2xc l 2xc l xb xa 2xc l 2xc l xb xa single \ ended ? xo ? connection crystal ?? connection osc xb xa xtal 2xc l 2xcl si5341/40 si5341/40 si5341/40 note: ? 2.0 ? vpp_se ? max xo ? with ? clipped ? sine ? wave ? output 2xc l 2xc l xb xa osc si5341/40 note: ? 2.0 ? vpp_se ? max ? cmos ? output r2 r1 xo ? vdd r1 r2 3.3 ? v 523 ? 442 ? 2.5 ? v 475 ? 649 ? 1.8 ? v 158 ? 866 ? 100 0.1 ? uf 0.1 ? uf 0.1 ? uf 0.1 ? uf 0.1 ? uf 0.1 ? uf 0.1 ? uf single \ ended ? connection note: ? 2.5 ? vpp? diff ? max x1 x2 nc nc x1 x2 nc nc x1 x2 nc nc x2 x1 osc osc ac coupled lvcmos or single ended 50 3.3v, 2.5v, 1.8v lvcmos or single ended signal inx inx ac coupled differential inx inx 50 50 50 differential driver lvds, lvpecl, cml 50 si5341/40 si5341/40 0.1 uf 0.1 uf 0.1 uf 0.1 uf 0.1 uf
si5341/40 rev. 1.0 31 5.3.3. input selection (in0, in1, in2, xa/xb) the active clock input is selected using the in_sel[1:0] pins or by register control. a register bit determines input selection as pin or register selectable. there are internal pull ups on the in_sel pins. 5.4. fault monitoring the si5341/40 provides fault indicators which monitor lo ss of signal (los) of the inputs (in0, in1, in2, xa/xb, fb_in) and loss of lock (lol) for the pll. this is shown in figure 13. figure 13. los and lol fault monitors 5.4.1. status indicators the state of the status monitors are accessible by readin g registers through the serial interface or with dedicated pin (lol ). each of the status indicator register bits has a co rresponding sticky bit in a separate register location. once a status bit is asserted its corr esponding sticky bit (_flg) will remain asserted until cleared. writing a logic zero to a sticky register bit clears its state. 5.4.2. interrupt pin (intr) an interrupt pin (intr ) indicates a change in state with any of the stat us registers. all status registers are maskable to prevent assertion of the interrupt pin. the state of the intr pin is reset by clearing the status registers. table 15. manual input selection using in_sel[1:0] pins in_sel[1:0] selected input 00 in0 01 in1 10 in2 1 1 xa/xb pll lpf pd mn in0 in0 los0 p 0 in1 in1 p 1 fb_in fb_in in2 in2 p 2 lol si5341/40 xb xa osc p fb md losxab los1 los2 losfb lol los0 los1 los2 losxab intr
si5341/40 32 rev. 1.0 5.5. outputs the si5341 supports 10 differential output drivers wh ich can be independently configured as differential or lvcmos. the SI5340 supports 4 output drivers indep endently configurable as differential or lvcmos. 5.5.1. output signal format the differential output amplitude and common mode voltag e are both fully programmable and compatible with a wide variety of signal formats including lvds and lvpecl. in addition to supporting differential signals, any of the outputs can be configured as lvcmos (3.3 v, 2.5 v, or 1. 8 v) drivers providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs. 5.5.2. differential output terminations the differential output drivers support both ac-couple d and dc-coupled terminations as shown in figure 14. figure 14. supported differential output terminations 100 50 50 internally self-biased ac coupled lvds/lvpecl 50 50 ac coupled lvpecl/cml vdd ? 1.3v 50 50 50 50 100 dc coupled lvds outx outx outx outx outx outx v ddo = 3.3v, 2.5v, 1.8v v ddo = 3.3v, 2.5v v ddo = 3.3v, 2.5v, 1.8v si5341/40 si5341/40 si5341/40 3.3v, 2.5v, 1.8v lvcmos v ddo = 3.3v, 2.5v, 1.8v 50 rs 50 rs dc coupled lvcmos outx outx si5341/40 ac coupled hcsl r1 outx outx v ddo = 3.3v, 2.5v, 1.8v si5341/40 50 50 r1 r2 r2 vdd rx standard hcsl receiver vdd rx option 1 for v cm = 0.37 v 3.3 v 2.5 v 1.8 v 442 ohms 332 ohms 243 ohms 56.2 ohms 59 ohms 63.4 ohms r1 r2
si5341/40 rev. 1.0 33 5.5.3. differential output modes there are two selectable* differential output modes: no rmal and low power. each output can support a unique mode. in this document, the terms, lvds and lvpecl, refer to driver formats that are compatible with these signaling standards. ? differential normal mode: when an output driver is configured in normal mode, its output amplitude is selectable as one of 7 settings ranging from ~130 mvpp_se to ~920 mvpp_se in increments of ~100 mv. see appendix a for additional information. the output impedance in the normal mode is 100 ?? differential ?? any of the terminations shown in figure 14 are supported in this mode. ? differential low power mode: when an output driver is configured in low power mode, its output amplitude is configurable as one of 7 settings ranging from ~ 200 mvpp_se to ~1600 mvpp_se in increments of ~200 mv. when in differential low power mode, the output im pedance of the driver is much greater than 100 ??? however the signal integrity will still be optimum as long as the differential clock trac es are properly terminated in their characteristic impedance. any of the termination s shown in figure 14 are supported in this mode. *note: not all amplitude levels are available for selection in the cbpro device configuration wizard. refer to sections 5.9 and 5.10 for more information. see also appe ndix a of the si5341/40 reference manual. 5.5.4. programmable common mode voltage for differential outputs the common mode voltage (v cm ) for the differential normal and low power modes are programmable so that lvds specifications can be met and for the best signal integrity with different supply voltages. when dc coupling the output driver it is essential that the receiver should have a relatively high common mode impedance so that the common mode current from the output driver is very small. 5.5.5. lvcmos output terminations lvcmos outputs are typically dc-coupled as shown in figure 15. figure 15. lvcmos output terminations 3.3v, 2.5v, 1.8v lvcmos v ddo = 3.3v, 2.5v, 1.8v 50 rs 50 rs dc coupled lvcmos outx outx
si5341/40 34 rev. 1.0 5.5.6. lvcmos output impedance and drive strength selection each lvcmos driver has a configurable output impedan ce. it is highly recommended that the minimum output impedance (strongest drive setting) is selected and a suit able series resistor (rs) is chosen to match the trace impedance. 5.5.7. lvcmos output signal swing the signal swing (v ol /v oh ) of the lvcmos output drivers is set by the voltage on the vddo pins. each output driver has its own vddo pin allowing a unique outp ut voltage swing for each of the lvcmos drivers. 5.5.8. lvcmos output polarity when a driver is configured as an lvcmos output it generates a clock signal on both pins (outx and outx ). by default the clock on the outx pin is generated with complementary pola rity with the clock on the outx pin. the lvcmos outx and outx outputs can also be generated in phase. 5.5.9. output enable/disable the oe pin provides a convenient method of disab ling or enabling the output drivers. when the oe pin is held high all outputs will be disabled. when held low, the outputs will be enabled. outputs in the enabled state can be individually disabled th rough register control. 5.5.10. output driver state when disabled the disabled state of an output driver is configurable as: disable low or disable high. 5.5.11. synchronous/asynchronous output disable feature outputs can be configured to disable synchronously or asynchronously. the default state is synchronous output disable. in synchronous disable mode th e output will wait until a clock period has completed before the driver is disabled. this prevents unwanted runt pulses from occurring when disabling an output. in asynchronous disable mode the output clock will disable immediately without waiting for th e period to complete . table 16. nominal output impedance vs outx_cmos_drv (register) cmos_drive_selection vddo outx_cmos_drv=1 outx_cm os_drv=2 outx_cmos_drv=3 3.3 v 38 ? 30 ? 22 ? 2.5 v 43 ? 35 ? 24 ? 1.8 v ? 46 ? 31 ? *note: refer to the si5341/40 family reference manual for more information on register settings.
si5341/40 rev. 1.0 35 5.5.12. output delay control ( ? t 0 C ? t 4 ) the si5341/40 uses independe nt multisynth dividers (n 0 - n 4 ) to generate up to 5 unique frequencies to its 10 outputs through a crosspoint switch. by default all clocks are phase aligned. a delay path ( ? t 0 - ? t 4 ) associated with each of these dividers is available for applications that nee d a specific output skew co nfiguration. each delay path is controlled by a register parameter call nx_delay with a resolution of ~0.28 ps over a range of ~9.14 ns. this is useful for pcb trace length mismatch compensation. after the delay controls are configured, the soft reset bit soft_rst must be set high so that the output del ay takes effect and the outputs are re-aligned. figure 16. example of independently configurable path delays all delay values are restored to their nvm programmed values after power-up or after a hard reset. delay default values can be written to the nvm allo wing a custom delay offset configuration at power-up or after a hardware reset. n 0 t 0 n 1 t 1 n 2 t 2 n 3 t 3 n 4 t 4 out2 vddo2 out2 vddo3 r 2 out3 out3 r 3 out1 vddo1 out1 r 1 out5 vddo5 out5 vddo6 r 5 out6 out6 r 6 out4 vddo4 out4 r 4 out7 vddo7 out7 vddo8 r 7 out8 out8 r 8 out0 vddo0 out0 r 0 vddo9 out9 out9 r 9
si5341/40 36 rev. 1.0 5.5.13. zero delay mode a zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs. the zero delay mode is c onfigured by opening the internal feedback loop through software configuration and closing the loop externally as shown in figure 17. this helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. any one of the outputs can be fed back to the fb_in pins, although us ing the output driver th at achieves the shortest trace length will help to minimize the input-to-output delay. it is recommended to connect out9 (si5341) or out3 (SI5340) to fb_in for external feedback. the fb_in input pins must be term inated and ac-coupled when zero delay mode is used. a differential external feedback path connection is necessary for best performance. figure 17. si5341 zero delay mode setup 5.5.14. sync pin (synchronizing r dividers) all the output r dividers are reset to the default nvm regi ster state after a power-up or a hard reset. this ensures consistent and repeatable phase alignment across all output drivers to within 100 ps of the expected value from the nvm download. resetting the device using the rst pin or asserting the hard reset bit will have the same result. the sync pin provides another method of re-aligning the r dividers without resetting the device, however, the outputs will only align to wi thin 50 ns when using the sync pin. this pin is positive edge triggered. asserting the sync register bit provides the same function as the sync pin. a soft reset will align the outputs to within 100 ps of the expected value based upon the nx_delay parameter. 5.5.15. output crosspoint the output crosspoint allows any of the n dividers to connect to any of the clock outputs. zero delay mode si5341 in_sel[1:0] in0 in0 in1 in1 in2 in2 p 0 p 1 p 2 out0 vddo0 out0 out2 vddo2 out2 out3 vddo3 out3 out7 vddo7 out7 out8 vddo8 out8 out9 vddo9 out9 out1 vddo1 out1 multisynth & dividers fb_in fb_in 100 external feedback path pd lpf m n m d n 9n n 9d r 9 f fb = f in f in p fb pll
si5341/40 rev. 1.0 37 5.5.16. digitally controll ed oscillator (dco) modes each multisynth can be digitally controlled to so that all outputs connected to the multisynth change frequency in real time without any transition glitches. there are two ways to control the multisynth to accomplish this task: ?? use the frequency increment/decre ment pins or register bits ?? write directly to the numerator of the multisynth divider. an output that is controlled as a dco is useful for simple tasks such as frequency margining or cpu speed control. the output can also be used for more sophisticated tasks such as fifo management by adjusting the frequency of the read or write clock to the fifo or using the output as a variable local osc illator in a radio application. 5.5.16.1. dco with frequency increment/decrement pins/bits each of the multisynth fractional dividers can be indepen dently stepped up or down in predefined steps with a resolution as low as 0.001 ppb. setting of the step size and control of the frequency increment or decrement is accomplished by setting the step size with the 44 bit fr equency step word (fstepw). when the finc or fdec pin or register bit is assert ed the output frequency will increment or decrement respectivley by the amount specified in the fstepw. 5.5.16.2. dco with direct register writes when a multisynth numerator and its corresponding update bit is written, the new numerator value will take effect and the output frequency will change wit hout any glitches. the multisynth numerator and denominator terms can be left and right shifted so that the least significant bi t of the numerator word represents the exact step resolution that is needed for your application. 5.6. power management several unused functions can be powered down to minimize power consumption. consult the si5341/40 family reference manual and clockbuilder pro configuration utility for details. 5.7. in-circuit programming the si5341/40 is fully configurable using the serial interface (i 2 c or spi). at power-up the device downloads its default register values from internal non-volatile memory (nvm). application specific default configurations can be written into nvm allowing the device to generate spec ific clock frequencies at power-up. writing default values to nvm is in-circuit programmable with normal operating power supply voltages applied to its v dd and v dda pins. the nvm is two time writable. once a new configuration has been written to nvm, the old configuration is no longer accessible. refer to the si5341/40 family reference manual for a detailed procedure for writing registers to nvm. 5.8. serial interface configuration and operation of the si5341/40 is cont rolled by reading and writing registers using the i 2 c or spi interface. the i2c_sel pin selects i 2 c or spi operation. communication with both 3.3v and 1.8v host is supported. the spi mode operates in either 4-wire or 3-wire. see the si5341/40 family reference manual for details. 5.9. custom factory preprogrammed devices for applications where a serial interface is not ava ilable for programming the device, custom pre-programmed parts can be ordered with a specific configuration written into nvm. a fa ctory pre-programmed device will generate clocks at power-up. custom, factory-preprogrammed devices are available. use the clockbuilder pro custom part number wizard ( www.silabs.com/clockbuilderpro ) to quickly and easily request and generate a custom part number for your configuration. in less than th ree minutes, you will be able to generate a custom pa rt number with a detailed data sheet addendum matching your design?s configuration. once you receive the confirmation email with the data sheet addendum, simply place an order with your local silicon labs sales re presentative. samp les of your pre- programmed device will ship to yo u typically within two weeks.
si5341/40 38 rev. 1.0 5.10. enabling features and/or configuration settings not a vailable in cloc kbuilder pro for factory pre-programmed devices as with essentially all software utilit ies, clockbuilder pro is continuously updated and enhanced. by registering at www.silabs.com and opting in for updates to software, you will be notified when ever changes ar e made and what the impact of those changes are. this update process will ultimately ena ble clockbuilder pro users to access all features and register setting values documented in this data sheet and the si5341/40 family reference manual. however, if you must enable or access a feature or regist er setting value so that the device starts up with this feature or a register setting, but the feature or register setting is not yet available in cbpro, you must contact a silicon labs applic ations engineer for assistance. an example of this ty pe of feature or custom setting is the customizable amplitudes for the clock ou tputs. after careful review of your project file and custom requirements, a silicon labs applicati ons engineer will email back your cbpro project file with your sp ecific features and register settings enabled, using what is referred to as the manual "settings override" feature of cbpro. "override" settings to match your request(s) will be listed in your design re port file. examples of setting "overrides" in a cbpro design report are shown below: once you receive the updated design file, simply open it in cbpro. after you create a custom opn, the device will begin operation after startup with the values in the nvm file, including the silicon labs -supplied overri de settings. figure 18. flowchart to order custom parts with features not available in cbpro setting overrides location customer name engineering name type target dec value hex value 0x0435[0] force_hold_plla ola_ho_force no nvm n/a 1 0x1 0x0b48[0:4] oof_div_clk_dis oof_div_clk_dis user opn & evb 0 0x00 no yes contact ? silicon ? labs ? technical ? support to ? submit ? & ? review ? your ? non \ standard ? configuration ? request ? & ? cbpro ? project ? file configure ? device ? using ? cbpro load ? project ? file into ? cbpro ? and ? test receive ? updated ? cbpro ? project ? file? from silicon ? labs ? with ? ?settings ? override? generate ? custom ? opn ? in ? cbpro does ? the ? updated ? cbpro ? project ? file? match ? your requirements? yes place ? sample ? order start do ? i ? need ? a ? pre \ programmed ? device ? with ? a ? feature ? or ? setting ? which ? is ? unavailable ? in ? clockbuilder ? pro?
si5341/40 rev. 1.0 39 6. register map the register map is divided into multiple pages where ea ch page has 256 addressable registers. page 0 contains frequently accessible registers such as alarm status, resets, device identification, etc. other pages contain registers that need less frequent access such as frequen cy configuration, and general device settings. a high level map of the registers is shown in section ?6.2. high-level register map? . refer to the si5341/40 family reference manual for a complete list of regi sters descriptions and settings. 6.1. addressing scheme the device registers are accessible using a 16-bit address which consists of an 8-bit pa ge address + 8-bit register address. by default the page address is set to 0x00. cha nging to another page is accomplished by writing to the ?set page address? byte located at address 0x01 of each page. 6.2. high-level register map table 17. high-level register map 16-bit address content 8-bit page address 8-bit register address range 00 00 revision ids 01 set page address 02?0a device ids 0b?15 alarm status 17?1b intr masks 1c reset controls 2c?e1 alarm configuration e2?e4 nvm controls fe device ready status 01 01 set page address 08?3a output driver controls 41?42 output driver disable masks fe device ready status
si5341/40 40 rev. 1.0 02 01 set page address 02?05 xtal frequency adjust 08?2f input divider (p) settings 30 input divider (p) update bits 35?3d pll feedback divider (m) settings 3e pll feedback divider (m) update bit 47?6a output divider (r) settings 6b?72 user scratch pad memory fe device ready status 03 01 set page address 02?37 multisynth divider (n0?n4) settings 0c multisynth divider (n0) update bit 17 multisynth divider (n1) update bit 22 multisynth divider (n2) update bit 2d multisynth divider (n3) update bit 38 multisynth divider (n4) update bit 39?58 finc/fdec settings n0?n4 59?62 output delay ( ? t) settings 63?94 frequency readback n0?n4 fe device ready status 04?08 00?ff reserved 09 01 set page address 49 input settings 1c zero delay mode settings a0?ff 00?ff reserved table 17. high-level register map (continued) 16-bit address content 8-bit page address 8-bit register address range
si5341/40 rev. 1.0 41 7. pin descriptions gnd pad in1 in1 in_sel0 in_sel1 sync rst x1 xa xb x2 oe intr vdda in2 in2 sclk a0/cs sda/sdio a1/sdo vdd rsvd rsvd vddo0 out0 out0 fdec out1 out1 vddo2 out2 out2 finc lol vdd out6 out6 vddo6 out5 out5 vddo5 i2c_sel out4 out4 vddo4 out3 out3 vddo3 vddo7 out7 out7 vddo8 out8 out8 out9 out9 vddo9 vdd fb_in fb_in in0 in0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vddo1 si5341 64qfn top view rsvd rsvd *1' 3dg in1 in1 in_sel0 intr x1 xa xb x2 oe rst vdda vdda in2 a0/cs sda/sdio a1/sdo out0 out0 vddo0 sclk i2c_sel out1 out1 vddo1 vddo3 out3 out3 fb_in fb_in in0 in0 SI5340 44qfn top view 1 2 3 4 5 6 7 8 9 10 33 32 31 30 29 28 27 26 25 24 12 13 14 15 16 17 18 19 20 21 44 43 42 41 40 39 38 37 36 35 vdd out2 out2 vddo2 vdds lol los_xaxb vdd in_sel1 in2 11 23 nc 22 vdd vdd 34
si5341/40 42 rev. 1.0 table 18. pin descriptions pin name pin number pin type 1 function si5341 SI5340 inputs xa 8 5 i crystal and external clock input these pins are used to connect an external crystal or an external clock. see section ?5.3.1. xa/xb clock and crystal input? and ?figure 11. xaxb external crystal and clock connections? for connection information. if in_sel[1:0] = 11b, then the xaxb input is selected. if the xaxb input is not used and powered down, then both inputs can be left uncon nected. clockbuild er pro will power down an input that is set as "unused". xb 9 6 i x1 7 4 i xtal shield connect these pins directly to the xtal ground pins. x1, x2, and the xtal ground pins must not be connected to the pcb ground plane. do not ground the crystal ground pins. refer to the si5341/40 family referenc e manual for layout guidelines. these pins should be left disconnected when connecting xa/xb pins to an external reference clock. x2 10 7 i in0 63 43 i clock inputs these pins accept both differential and single-ended clock sig- nals. refer to "5.3.2. input clock s (in0, in1, in2)" on page 30 for input termination options. these pins are high-impedance and must be terminated externally. if both the inx and inx (with over- strike) inputs are un-used and powered down, then both inputs can be left floating. clockbuilder pro will power down an input that is set as "unused". in0 64 44 i in1 1 1 i in1 22 i in2 14 10 i in2 15 11 i fb_in 61 41 i external feedback input these pins are used as the external feedback input (fb_in/ fb_in ) for the optional zero delay mode. see "5.5.13. zero delay mode" on page 36 for details on the optional zero delay mode. if fb_in and fb_in (with overstrike) are un-used and powered down, then both inputs can be le ft floating. clockbuilder pro will power down an input that is set as "unused". fb_in 62 42 i notes: 1. i = input, o = output, p = power. 2. the io_vdd_sel control bit (0x0943 bit 0) selects 3.3 v or 1. 8 v operation for the serial interface pins, control input pins, and status output pins. refer to the si5341/40 family reference manual for more information on register settings. 3. if neither serial interface is used, leave pins i2c_sel, a1/sdo, and a0/cs disconnected and tie sda/sdio and sclk low.
si5341/40 rev. 1.0 43 outputs out0 24 20 o output clocks these output clocks support a programmable signal amplitude when configured as a differential output. desired output signal for- mat is configurable using regist er control. termination recommen- dations are provided in "5.5.2. differential output terminations" on page 32 and "5.5.5. lvcmos output terminations" on page 33. unused outputs should be left unconnected. out0 23 19 o out1 28 25 o out1 27 24 o out2 31 31 o out2 30 30 o out3 35 36 o out3 34 35 o out4 38 ? o out4 37 ? o out5 42 ? o out5 41 ? o out6 45 ? o out6 44 ? o out7 51 ? o out7 50 ? o out8 54 ? o out8 53 ? o out9 59 ? o out9 58 ? o table 18. pin descriptions (continued) pin name pin number pin type 1 function si5341 SI5340 notes: 1. i = input, o = output, p = power. 2. the io_vdd_sel control bit (0x0943 bit 0) selects 3.3 v or 1. 8 v operation for the serial interface pins, control input pins, and status output pins. refer to the si5341/40 family reference manual for more information on register settings. 3. if neither serial interface is used, leave pins i2c_sel, a1/sdo, and a0/cs disconnected and tie sda/sdio and sclk low.
si5341/40 44 rev. 1.0 serial interface i2c_sel 39 38 i i2c select 2 this pin selects the serial interface mode as i 2 c (i2c_sel = 1) or spi (i2c_sel = 0). this pin is internally pulled up by a ~ 20 k ? resistor to the voltage selected by the io_vdd_sel register bit. sda/sdio 18 13 i/o serial data interface 2 this is the bidirectional data pin (sda) for the i 2 c mode, or the bidirectional data pin (sdio) in the 3-wire spi mode, or the input data pin (sdi) in 4-wire spi mode. when in i 2 c mode, this pin must be pulled-up using an external resistor of at least 1 k ? . no pull-up resistor is needed when in spi mode. a1/sdo 17 15 i/o address select 1/serial data output 2 in i 2 c mode, this pin functions as the a1 address input pin and does not have an internal pull up or pull down resistor. in 4-wire spi mode this is the serial data output (sdo) pin (sdo) pin and drives high to the voltage selected by the io_vdd_sel pin. sclk 16 14 i serial clock input 2 this pin functions as the se rial clock input for both i 2 c and spi modes.this pin is internally pulled up by a ~20 k ? resistor to the voltage selected by the io_vdd_sel register bit. in i 2 c mode this pin should have an external pull up of at least 1 k ? . no pull-up resistor is needed when in spi mode. a0/cs 19 16 i address select 0/chip select 2 this pin functions as the hardware controlled address a0 in i 2 c mode. in spi mode, this pin func tions as the chip select input (active low). this pin is in ternally pulled up by a ~20 k ? resistor to the voltage selected by the io_vdd_sel register bit. table 18. pin descriptions (continued) pin name pin number pin type 1 function si5341 SI5340 notes: 1. i = input, o = output, p = power. 2. the io_vdd_sel control bit (0x0943 bit 0) selects 3.3 v or 1. 8 v operation for the serial interface pins, control input pins, and status output pins. refer to the si5341/40 family reference manual for more information on register settings. 3. if neither serial interface is used, leave pins i2c_sel, a1/sdo, and a0/cs disconnected and tie sda/sdio and sclk low.
si5341/40 rev. 1.0 45 control/status intr 12 33 o interrupt 2 this pin is asserted low when a change in device status has occurred. this interrupt has a push pull output and should be left unconnected when not in use. rst 617 i device reset 2 active low input that performs power-on reset (por) of the device. resets all internal logic to a known state and forces the device registers to their default values. clock outputs are disabled during reset. this pin is internally pulled up with a ~20 k ? resistor to the voltage selected by the io_vdd_sel bit. oe 11 12 i output enable 2 this pin disables all outputs when held high. this pin is internally pulled low and can be left unconnected when not in use. lol 47 ? o loss of lock 2 this output pin indicates when the dspll is locked (high) or out- of-lock (low). an external pu ll up or pull down is not needed. ?27 o loss of lock this output pin indicates when the dspll is locked (high) or out- of-lock (low). an external pull up or pull down is not needed. the voltage on the vdds pin sets the voh/vol for this pin. see table 6. los_xaxb ?28 o loss of signal this output pin indicates a loss of signal at the xa/xb pins. sync 5? i output clock synchronization 2 an active low signal on this pin resets the output dividers for the purpose of re-aligning the output clocks. for a tighter alignment of the clocks, a soft reset should be applied. this pin is internally pulled up with a ~20 k ? resistor to the voltage selected by the io_vdd_sel bitand can be left unconnected when not in use. fdec 25 ? i frequency decrement pin 2 this pin is used to step-down the output frequency of a selected output. the affected output driver and its frequency change step size is register configurable. this pin is internally pulled low with a ~20 k ? resistor and can be left unconnected when not in use. table 18. pin descriptions (continued) pin name pin number pin type 1 function si5341 SI5340 notes: 1. i = input, o = output, p = power. 2. the io_vdd_sel control bit (0x0943 bit 0) selects 3.3 v or 1. 8 v operation for the serial interface pins, control input pins, and status output pins. refer to the si5341/40 family reference manual for more information on register settings. 3. if neither serial interface is used, leave pins i2c_sel, a1/sdo, and a0/cs disconnected and tie sda/sdio and sclk low.
si5341/40 46 rev. 1.0 finc 48 ? i frequency increment pin 2 this pin is used to step-up the output frequency of a selected out- put. the affected output and its frequency change step size is reg- ister configurable. this pin is internally pulled low with a ~20 k ? resistor and can be left unconnected when not in use. in_sel0 3 3 i input reference select 2 the in_sel[1:0] pins are used in the manual pin controlled mode to select the active clock input as shown in table 15. these pins are internally pulled up with a ~20 k ? resistor to the voltage selected by the io_vdd_sel bit and can be left unconnected when not in use. in_sel1 4 37 i rsvd 20 ? ? reserved these pins are connected to the die. leave disconnected. 21 ? ? 55 ? ? 56 ? ? nc ? 22 ? no connect these pins are not connected to the die. leave disconnected. power vdd 32 21 p core supply voltage the device core operates from a 1.8 v supply. a 1.0 f bypass capacitor is recommended 46 32 60 39 ?40 vdda 13 8 p core supply voltage 3.3 v this core supply pin requires a 3.3 v power source. a 1.0 f bypass capacitor is recommended. ?9 p vdds ? 26 p status output voltage the voltage on this pin determines the v ol /v oh on lol and los_xaxb status output pins. a 0.1 f to 1.0 f bypass capacitor is recommended. table 18. pin descriptions (continued) pin name pin number pin type 1 function si5341 SI5340 notes: 1. i = input, o = output, p = power. 2. the io_vdd_sel control bit (0x0943 bit 0) selects 3.3 v or 1. 8 v operation for the serial interface pins, control input pins, and status output pins. refer to the si5341/40 family reference manual for more information on register settings. 3. if neither serial interface is used, leave pins i2c_sel, a1/sdo, and a0/cs disconnected and tie sda/sdio and sclk low.
si5341/40 rev. 1.0 47 vddo0 22 18 p output clock supply voltage 0C9 supply voltage (3.3 v, 2.5 v, 1.8 v) for outx, outx outputs. see the si5341/40 family reference manual for power supply fil- tering recommendations. leave vddo pins of unused ou tput drivers unconnected. an alternate option is to connect the vddo pin to a power supply and disable the output driver to minimize current consumption. vddo1 26 23 p vddo2 29 29 p vddo3 33 34 p vddo4 36 ? p vddo5 40 ? p vddo6 43 ? p vddo7 49 ? p vddo8 52 ? p vddo9 57 ? p gnd pad p ground pad this pad provides electrical and thermal connection to ground and must be connected for proper ope ration. use as many vias as practical and keep the via length to an internal ground plan as short as possible. table 18. pin descriptions (continued) pin name pin number pin type 1 function si5341 SI5340 notes: 1. i = input, o = output, p = power. 2. the io_vdd_sel control bit (0x0943 bit 0) selects 3.3 v or 1. 8 v operation for the serial interface pins, control input pins, and status output pins. refer to the si5341/40 family reference manual for more information on register settings. 3. if neither serial interface is used, leave pins i2c_sel, a1/sdo, and a0/cs disconnected and tie sda/sdio and sclk low.
si5341/40 48 rev. 1.0 8. ordering guide ordering part number (opn) number of input/output clocks output clock frequency range (mhz) frequency synthesis mode package temperature range si5341 si5341a-b-gm 1,2 4/10 0.0001 to 712.5 mhz integer and fractional mode 64-lead 9x9 qfn ?40 to 85 c si5341b-b-gm 1,2 0.0001 to 350 mhz si5341c-b-gm 1,2 0.0001 to 712.5 mhz integer mode only si5341d-b-gm 1,2 0.0001 to 350 mhz SI5340 SI5340a-b-gm 1,2 4/4 0.0001 to 712.5 mhz integer and fractional mode 44-lead 7x7 qfn ?40 to 85 c SI5340b-b-gm 1,2 0.0001 to 350 mhz SI5340c-b-gm 1,2 0.0001 to 712.5 mhz integer only SI5340d-b-gm 1,2 0.0001 to 350 mhz si5341/40-evb si5341-evb ?? ? evaluation board ? SI5340-evb notes: 1. add an r at the end of the opn to denote tape and reel ordering options. 2. custom, factory pre-programmed devices are available. ordering part numbers are assigned by silicon labs and the clockbuilder pro software utility. 3. custom part number format is: e.g., si5341a-bxxxxx-gm, w here ?xxxxx? is a unique numerical sequence representing the preprogrammed configuration. 4. see sections 5.9 and 5.10 for importan t notes about specifying a preprogrammed device to use features or device register settings not yet available in cbpro. si534fg-rxxxxx-gm timing product family f = clock generator f amily member (1, 0) g = device g rade (a, b) product r evision* custom ordering part number (opn) sequence id** package, ambient temperature range (qfn, -40c to +85c) *see ordering guide table for current product revision ** 5 digits; assigned by clockbuilder pro
si5341/40 rev. 1.0 49 9. package outlines 9.1. si5341 9x9 mm 64 -qfn package diagram figure 19 illustrates the package details for the si5341. table 19 lists the valu es for the dimensions shown in the illustration. figure 19. 64-pin quad flat no-lead (qfn) table 19. package dimensions dimension min nom max a0 . 8 00 . 8 50 . 9 0 a1 0.00 0.02 0.05 b0 . 1 80 . 2 50 . 3 0 d 9.00 bsc d2 5.10 5.20 5.30 e 0.50 bsc e 9.00 bsc e2 5.10 5.20 5.30 l0 . 3 00 . 4 00 . 5 0 aaa ? ? 0.15 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.10 eee ? ? 0.05 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the je dec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si5341/40 50 rev. 1.0 9.2. SI5340 7x7 mm 44 -qfn package diagram figure 20 illustrates the package details for the SI5340. table 20 lists the valu es for the dimensions shown in the illustration. figure 20. 44-pin quad flat no-lead (qfn) table 20. package dimensions dimension min nom max a0 . 8 00 . 8 50 . 9 0 a1 0.00 0.02 0.05 b0 . 1 80 . 2 50 . 3 0 d 7.00 bsc d2 5.10 5.20 5.30 e 0.50 bsc e 7.00 bsc e2 5.10 5.20 5.30 l0 . 3 00 . 4 00 . 5 0 aaa ? ? 0.15 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.10 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the je dec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. ?
si5341/40 rev. 1.0 51 10. pcb land pattern figure 21 illustrates the pcb land patt ern details for the devices. table 21 lists the values for the dimensions shown in the illustration. figure 21. pcb land pattern ? ?
si5341/40 52 rev. 1.0 table 21. pcb land pattern dimensions dimension si5341 (max) SI5340 (max) c1 8.90 6.90 c2 8.90 6.90 e 0.50 0.50 x1 0.30 0.30 y1 0.85 0.85 x2 5.30 5.30 y2 5.30 5.30 notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximu m material condition (mmc). least material condition is calculated based on a fabrication allowance of 0.05 mm. solder mask design 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 5. a stainless steel, laser-cut and electro- polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness shou ld be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land p ad size should be 1:1 for all perimeter pads. 8. a 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si5341/40 rev. 1.0 53 11. top marking figure 22. si5341-40 top markings table 22. si5341-40 top marking explanation line characters description 1 si5341g- SI5340g- base part number and device grade for low jitter, any-frequency, 10- output clock generator. si5341: 10-output, 64-qfn SI5340: 4-output, 44-qfn g = device grade (a, b, c, d). see "8. ordering guide" on page 48 for more information. ? = dash character. 2 rxxxxx-gm r = product revision. (see or dering guide for current revision). xxxxx = customer specific nvm sequ ence number. optional nvm code assigned for custom, factory pre-programmed devices. characters are not included for st andard, factory default configured devices. see ordering guide for more information. ?gm = package (qfn) and temperature range (?40 to +85 c) 3 yywwtttttt yyww = characters correspond to the year (yy) and work week (ww) of package assembly. tttttt = manufacturing trace code. 4 circle w/ 1.6 mm (64-qfn) or 1.4 mm (44-qfn) diameter pin 1 indicator; left-justified e4 tw pb-free symbol; center-justified tw = taiwan; country of origin (iso abbreviation) tw yywwtttttt rxxxxx-gm si5341g- e4 tw yywwtttttt rxxxxx-gm SI5340g- e4 64-qfn 44-qfn
si5341/40 54 rev. 1.0 12. device errata please log in or register at www.silabs.com to access the device errata document.
si5341/40 rev. 1.0 55 d ocument c hange l ist revision 0.9 to revision 0.95 ?? removed advanced product information revision history. ?? updated ordering guide and changed references to revision b ?? updated parametric tables 2,3,5,6,7,8 to reflect production characterization ?? updated terminology to align with clockbuilder pro software ?? ta b l e 9 : i 2 c data hold time specification corrected to 100 ns from 5 s revision 0.95 to revision 1.0 ?? general updates to typos in tables 2,3,4,5,8,11, and 12. ?? changed vin_diff minimum value in table 3 to be the same as vin_se. ?? added crosstalk spec for SI5340 to table 5. ?? changed the schematic for ac test configuration in table 7. ?? changed the pll lock time in table 8. ?? added a spec to table 8 for the vco frequency range. ?? changed the "delay time between chip selects" to be 2.0 clock periods. ?? changed note 2 in table 12 as only 25 and 48? 54 mhz crystals are supported. ?? changed the timing specs for i 2 c and spi. ?? added a 1.0 f bypass capacitor recommendation to be consistent with the reference manual. ?? updated output-to-output skew spec.
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