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summary t c901 04 a f g page 1 rev.1.0 0 20 15/10 / 16 tc90104 a fg multi system video decoder th e tc90104 a fg is a single chip ic that converts analog video signals to digi tal video signals ( itu - r b t. 601 / itu - r b t. 656 ycbcr 16, 8bit digital signal). additionally , the tc90104 a fg has a 3 - channel a/d converter as an analog input interface , and has 3 - line y/c separation and multi - system color decoder functionality. 1. features ? input : cvb s, y/c (s - video), y/cb/cr (d1, d2) ? multi - color decoder ? synchronous playback/ standard identification ? y/c separation : 3 - line ycs (ntsc/pal) bpf processing . (secam) ? picture process y : v - enhance, lt i, sharpness, noise cancel, contrast, brightness c : tof , acc , color gain, cti, noise cancel ? output : itu - r bt. 601 (d1) / itu - r bt. 656 (d1) / 16bit(d2) / 8bit serial(d2) . ? i 2 c - bus control ? p ackage : lqfp 64 p in ( 0.50 mm pitch ) ? power supply : 3.3 v , 2.5 v , 1. 5 v lqfp64 -p- 1010- 0.50e weight : 0.4 g ( typ. ) ? 201 5 toshiba corporation
summary t c901 04 a f g page 2 rev.1.0 0 20 15/10 / 16 2. block diagram to explain the function, there are omitted part for function block and application circuit. 3. pin layout 42m cb reference x?tal 656/601 hd s w c/cr scl sda vd clk ycbcr(d1/d2) cvbs/s 10bit adc s w hpll reference clock 2dycs c.dec cvbs1 cvbs2/y iic - bus process picture process format convert 8bit adc 8bit adc sync
summary t c901 04 a f g page 3 rev.1.0 0 20 15/10 / 16 4. pin descriptions pin no. pin n ame pin function pin type standard w ithstand v oltage [v] processing at unused time 1 vddda 2.5 v power supply for dac vdd 2.5 - 2 pllin input of pll circuit for clock in 2.5 - 3 vddpll 2.5 v power supply for pll circuit vdd 2.5 - 4 vcofil vco control b ias for pll circuit b ia s 2.5 - 5 vsspll gnd for pll circuit vss 0 - 6 vddxo 2.5v power supply for x?tal circuit vdd 2.5 - 7 xoin input for x?tal circuit in 2.5 - 8 xoout output for x?tal circuit out 2.5 - 9 vssxo gnd for x?tal ci rcuit gnd 0 - 10 vdd - d 3 1.5 v power supply for logic circuit vdd 1.5 - 11 sda serial data input/output i / o 5 - 12 scl serial clock input in 5 - 13 reset system reset in 3.3 - 14 vss digital gnd gnd 0 - 15 testout1 test output terminal 1 out 3.3 open 16 vd vd output out 3.3 open 17 hd hd output out 3.3 open 18 clk clock signal output out 3.3 - 19 vdd - io 3 3.3 v power supply for i/o circuit vdd 3.3 - 20 y7 y7 signal output (msb) * 1 out 3.3 - 21 y6 y6 signal output * 1 out 3.3 - 22 vss digital gnd gnd 0 - 23 vdd - d2 1.5v power supply for logic circuit vdd 1.5 - 24 y5 y5 signal output * 1 out 3.3 - 25 y4 y4 signal output * 1 out 3.3 - 26 vdd - io2 3.3v power supply for i/o circuit vdd 3.3 - 27 y3 y3 signal output * 1 out 3.3 - 28 y2 y2 signal output * 1 out 3.3 - 29 vss digital gnd gnd 0 - 30 y1 y1 signal output out 3.3 - 31 y0 y0 signal output out 3.3 - 32 testout2 test output terminal 2 out 3.3 open * 1 : it is available for sav/eav implantation when input signal is cvbs or ycbcr(d1) and output is itu - r b t. 656 format. it needs to use hd/vd output mode because it is not available for sav/eav implantation when output is d2 signal (54mhz 8bit).
summary t c901 04 a f g page 4 rev.1.0 0 20 15/10 / 16 pin no. pin name pin function pin type standard w ithstand v oltage [v] processing at unused time 33 nc non - connection out 3.3 - 34 vss digital gnd gnd 0 - 35 c0 c0 signal output (lsb) * 2 out 3.3 - 36 c1 c1 signal output * 2 out 3.3 - 37 vdd - d 1 1.5 v power supply for logic circuit vdd 1.5 - 38 c2 c2 signal output * 2 out 3.3 - 39 c3 c3 signal output * 2 out 3.3 - 40 vss digital gnd gnd 0 - 41 c4 c4 signal output * 2 out 3.3 - 42 c5 c5 signal output * 2 out 3.3 - 43 vdd - io 1 3.3 v power supply for i/o circuit vdd 3.3 - 44 c6 c6 signal output * 2 out 3.3 - 45 c7 c7 signal output * 2 out 3.3 - 46 slave sel i 2 c - bus slave - address selector in 3.3 - 47 vss digital gnd gnd 0 - 48 vss digital gnd gnd 0 - 49 v ddad1 2.5 v power supply for adc circuit vdd 2.5 - 50 cvbs1 in composite video signal input in 2.5 gnd via 0.1 f 51 vssad1 gnd for adc circuit gnd 0 - 52 cvbs2/ y in composite video / y signal input in 2.5 gnd via 0.1 f 53 vrt reference top voltage for adc b ias 2.5 - 54 c/cr in c / cr video signal input in 2.5 gnd via 0.1 f 55 vrm reference middle voltage for adc b ias 2.5 - 56 cb in cb video signal input in 2.5 gnd via 0.1 f 57 vrb reference bottom voltage for adc b ias 2.5 - 58 vddad2 2.5 v power supply for adc circuit vdd 2.5 - 59 ad _ bias reference voltage for adc b ias 2.5 - 60 vssad 2 gnd for adc circuit gnd 0 - 61 notusein1 to gnd via 10k resistor in 3.3 gnd via 10k resistor 62 notusein2 to gnd via 10k resistor in 3.3 gnd via 10k resistor 63 vssda gnd for dac circuit for clock gnd 0 - 64 daout output of dac circuit for clock out 2.5 - * 2 when 8bit output mode, output of c7 to c0 terminal are fixed to low. therefore these must be open.
summary t c901 04 a f g page 5 rev.1.0 0 20 15/10 / 16 5. function 5.1 overview ? a nalog in put interface for composite video signal , y/c signal (s signal ) , component signal (d1/d2) ? multi system 3 line comb filter (2d ycs) ? multi system color decoder and sync generation processing ? c olor system detection (selectable auto detection or manual setting) ? picture quality processing function ? digital output inte rface for itu - r b t. 601/656 5.2 input signal 5.2.1 input signal list input signal format frequency effective pixels total pixels fh [khz] fv [hz] fs [mhz] horizontal vertical horizontal vertical cvbs ntsc 15.75/15.734 60/59.94 27 720 240 858 262.5 pal /se cam 15.625 50 27 720 288 864 312.5 y/c ntsc 15.75/15.734 60/59.94 27 720 240 858 262.5 pal 15.625 50 27 720 288 864 312.5 ycbcr d1 480i 15.75/ 15.734 60 27 720 240 858 262.5 576i 15.625 50 27 720 288 864 312.5 d2 480p 31.5 /31.469 60 27 720 480 858 525 576p 31.25 50 27 720 576 864 625
summary t c901 04 a f g page 6 rev.1.0 0 20 15/10 / 16 5.2.2 input signal the tc90104 a fg is equipped with 3 -ch adc for composite video signal , y/ c signal and y cbcr signal input. the input - dynamic - range for adc is designed in avdd x 0.4 [v] with the normal input dynamic rang e being 1 vp - p (avdd = 2.5 v). be sure to use 0.7 vp - p (1 vp - p x 0.7) with 140ire input when using ntsc as the recommended reference input amplitude. 5.2.3 table of input ? output signal input signal processing output signal input format f h [ k hz] sampling c lock [mhz] internal format output clock [mhz] rgb 601 656 hd vd enb cvbs ntsc 15.75/15.734 27 4 : 2 : 2 13.5 / 27 - : 2 : 2 13.5 / 27 - : 2 : 2 13.5 / 27 - : 2 : 2 13.5 / 27 - : 2 : 2 13.5 / 27 - : 2 : 2 13.5 / 27 - : 2 : 2 27 - : 2 : 2 27 -
summary t c901 04 a f g page 7 rev.1.0 0 20 15/10 / 16 5.2.4 typical input level of analog input signal fig.1 reference input level to cvbs1(composite video) and cvbs2/y/g(s - video y, componet y) when 100% white (i.e., c omposite video input) cvbs , y, component - y signal need to input 0.7 vpp when 140ire, and also c signal (s - signal) need to input 0.2 vpp when 40ire. (vdd = 2.5 v , 140ire = 0.7 vpp at ntsc ) when use component - cbcr , cbcr - level is 0.7 vpp for 100%. an above waveform is color bar signal of 75% i nput terminal i nput level = vp - p *1 o utput : lsb *2 notes cvbs 0.7 vp - p (500 mvp - p ) 16 - 235 (for 8bit) output at 656/601 format y 0.7 vp - p (500 mvp - p ) 16 - 235 (for 8bit) output at 656/601 format c 0.2 vp - p (b urst signal) 31 - 225 (for 8bit) output at 656/601 format cb 0.7 vp - p 31 - 225 (for 8bit) output at 656/601 format cr 0.7 vp - p 31 - 225 (for 8bit) output at 656/601 format *1 about input level, it has indicate the case of ntsc. cvbs and y input level will be 140ire at the white of 100%. please adjust to 0.7 v this 100%. values in the ( ) is the level of from the pedestal to white 100 %. input level of c(= chroma signal) has indicate the burst level at the time of ntsc. input level of cbcr has indicate th e level of color - 100% at the time of ntsc. *2 about output level, it has indicate the case of ntsc. cvbs and y output level is white100% output level at the time of ntsc. values in the ( ) is the output level of from the pedestal to white 100 %. ou t put level of c( chroma signal) indicate the cbcr level at the time of color - 100%. output level of cbcr indicate the level of color - 100% at the time of ntsc. notes : th e above output level is influenc ed by the picture quality adjustment of contrast, gain, acc and others . i t does not indicate the maximum level. 100 -40 0 20 40 60 80 -20 256 51 767 0 1023 avdd0.4v 0.7vp-p < lsb >
summary t c901 04 a f g page 8 rev.1.0 0 20 15/10 / 16 // // / 39 0 255 128 217 0.7vp-p 103 0 255 153 128 0 20 -20 ire 0.2vp-p < lsb > < lsb >
summary t c901 04 a f g page 9 rev.1.0 0 20 15/10 / 16 5.2.5 output format the output format ( itu -r bt.656/601) is below. output signal bit data rate description y [0 - 7] 8 13.5 mhz/27 mhz ( itu - r bt. 601/656) y / ycbcr ( itu - r bt.601/656) c [0 - 7] 8 6.75 mhz cb / cr (clk : 13.5 mhz) clk 1 13.5 mhz/27 mhz 864fh/1728fh : 625 line system 858fh/1716fh : 525 line system polarity : negative (initial setting) hd 1 f h recovered horizontal sync signal vd 1 f v recovered vertical sync signal hd / vd pulse width in ?sync - through? mode 525i system 625i system hd pulse width 4.74 s ( 128 cycle @ 27 mhz clock ) vd pulse width 3 .0 h 2.5 h or 3.0 h *notes the hd pulse width used in itu - r b t. 656- compliant mode is the same as the zone defined from eav to sav. if a non - standard signal is input during itu - r b t. 656- compliant mode, then t he values may not necessarily be the values shown in the above chart. the vd pulse is synchronized using the hd standard. as a result, if the h cycle jitters, then the vd width will also jitter. also, in through mode, the phase with the hd will be off 0.5 h in odd/even.
summary t c901 04 a f g page 10 rev.1.0 0 20 15/10 / 16 5.2.5.1. 525i / 60hz input mode (1st field : odd) (2nd field :even) change of t hrough mode and itu - r b t. 656 mode itu - r b t. 656: field 1 ; line 4 eav field blanking ; start line 1 eav , finish line 10 eav change of t hrough mode and itu - r b t. 656 mode itu - r b t. 656: field 2 ; line 266 eav field blanking ; start line 264 eav , finish line 273 eav 525 1 2 3 4 5 6 7 8 9 10 19 20 hdout vdout o dd / even vdout field 1 through mode field 1 itu -r b t. 656 mode o dd / odd even / hdout vdout / odd even
summary t c901 04 a f g page 11 rev.1.0 0 20 15/10 / 16 5.2.5.2. hd and vd timing when 480p/60hz input 525p/59.94(fh = 31.469 khz)@54 mhz_8bit output h out (h: 31.469 khz = 1716ck_ effective horizontal period:26.630 s = 1438ck)
summary t c901 04 a f g page 12 rev.1.0 0 20 15/10 / 16 6. absolute maximum rating the maximum ratings are rated values which must not be exceeded during operation, even for an instant. exceeding the maximum rating may result in destruction, degradation or other damag e to the ic and other components. when designing applications for this ic, be sure that none of the maximum rating values will ever be exceeded. characteristics symbol rating unit power voltage1 (1.5 v system) vdd1 - 0.3 to vss + 2.0 v power voltage2 ( 2.5 v system) vdd2 - 0.3 to vss + 3.5 v power voltage3 ( 3.3 v system) vdd3 - 0.3 to vss + 3.9 v input voltage ( 1.5 v system) vin1 - 0.3 to vdd 1 + 0.3 v input voltage ( 2.5 v system) vin2 - 0.3 to vdd 2 + 0.3 v input voltage ( 3.3 v system) vin3 - 0.3 to vd d 3 + 0.3 v input voltage ( 3.3 v system, 5 v withstand voltage) vin4 (note s 1) - 0.3 to vss + 5.5 v potential difference between power pins (between 1.5 v system power pins) vdg1 (note s 2) 0.3 v potential difference between power pins (between 2.5 v system power pins) vdg2 (note s 2 ) 0.3 v potential difference between power pins (between 3.3 v system power pins) vdg3 (note s 2 ) 0.3 v power dissipation pd (note s 3 ) 2190 mw s torage temperature tstg - 40 to 125 c note1 : the withstand voltage for pins (sda, scl) is 5 v. note2 : for each of 1. 5 v and 2.5 v and 3.3 v, system power supply terminal is made into the same voltage . the maximum potential difference should not excee d rating for all power supply terminals then. in addition, potential difference between all v ss terminal must be under 0.01 v in this status. note 3 : if you intended to use a temperature higher than ta = 25c, reduce by 21.9 mw per one degree (c) increa se. 7. operating ranges the tc90104 a fg is not guaranteed to function correctly if it is used outside its specified power voltage rage (1.5 v system power : 1.40 v to 1.60 v, 2.5 v system power : 2.3 v to 2.7 v, 3.3 v system power : 3.0 v to 3.6v). please us e within the specified operating conditions. if you temporarily leave and then return to the specified operating conditions, this ic?s conditions will change, and so it is necessary to reset the ic?s power to continue using it correctly within the specifie d operating conditions. characteristics corresponding terminal symbol min typ. max unit power voltage of digital block 10, 23, 37 vdd -d 1.4 1.5 1.6 v power voltage of i/o block 19, 26, 43 vdd -io 3.0 3.3 3.6 v power voltage of xo block 6 vddxo 2.3 2.5 2 .7 v power voltage of pll block 3 vddpll 2.3 2.5 2.7 v power voltage of analog block 1, 49, 58 vddda, vddad 2.3 2.5 2.7 v operating templature topr -40 85 c
summary t c901 04 a f g page 13 rev.1.0 0 20 15/10 / 16 8. electrical ch a racteristic 8.1 dc characteristic ( ta = 25c , 1.5 v system = 1.50 0.1 v, 2.5 v system = 2.50 0.2 v, 3.3 v system = 3.30 0.3 v) characterist i c terminal no. symbol min typ. max unit note power supply current 10, 23, 37 idd1 (1.5 v system ) 46 70 ma d epend on load at 3.3 v system. 1, 3, 6, 49, 58 idd2 (2.5 v system ) 82 125 ma 19, 26, 43 idd3 (3.3 v system ) 10 ma input voltage 13, 46, 47, 48, 61, 62 vih vdd3x0.8 vdd 3 v i/o input terminal of 3.3 v system 11, 12 i/o input terminal of 5.0 v tlerant system 13, 46, 47, 48, 61, 62 vil vss vdd3x0.2 v i/o input terminal of 3.3 v system 11,12 i/o input terminal of 5.0 v tlerant system input current 13, 46, 47, 48, 61, 62 iih - 10 10 a i/o input terminal of 3.3 v system 11, 12 i/o input terminal of 5.0 v tlerant system 13, 46, 47, 48, 61, 62 iil - 10 10 a i/o input terminal of 3.3 v system 11, 12 i/o input terminal of 5.0 v tlerant system output voltage 15, 16, 17, 18, 20, 21, 24, 25, 2 7, 28, 30, 31, 32, 33, 35, 36, 38, 39, 41, 42, 44, 45 v oh vdd3 - 0.6 vdd3 v i/o out put terminal of 3.3 v system when l oad current : - 4 ma v ol vss 0.4 v i/o out put terminal of 3.3 v system when l oad current : + 4 ma
summary t c901 04 a f g page 14 rev.1.0 0 20 15/10 / 16 9. package lqfp64 - p - 1010 - 0.5 0 e unit : mm weight : 0.4 g ( typ. )
summary t c901 04 a f g page 15 rev.1.0 0 20 15/10 / 16 10. revision history date revisi on contents 2015 / 1 0 / 16 1.0 0 first edition
summary t c901 04 a f g page 16 rev.1.0 0 20 15/10 / 16 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collectively "toshiba"), reserve the right to make changes to the i nformation in this document, and related hardware, software and systems (collectively "p roduct") without notice. ? this document and any information herein may not be reproduced without prior written permission from toshiba. even with toshi ba's written permission, reproduction is permissible only if reproduction is without alteration/omission . ? though toshiba works continually to improve product's quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, softwar e and systems which minimize risk and avoid situations in which a malfunction or failure of product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. before customers use the product, create designs incl uding the product, or incorporate the product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data s heets and application notes for product and the precautions and conditions set forth in the "toshiba semiconductor reliability handbook" and (b) the instructions for the application with which the product will be used with or for. customers are solely resp onsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this product in such design or a pplications; (b) evaluating and determining the applicability of any informa tion contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. toshiba assumes no liability for c ustomers' product design or applications. ? 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