supertex inc. hv9110 supertex inc. www.supertex.com doc.# dsfp-hv9110 a031214 features ? 10 to 120v input voltage range ? current-mode control ? high eficiency ? up to 1.0mhz internal oscillator ? internal start-up circuit ? low internal noise ? 50% maximum duty cycle applications ? dc/dc converters ? distributed power systems ? isdn equipment ? pbx systems ? modems general description the supertex hv9110 is a bicmos/dmos single-output, pulse width modulator ic intended for use in high-speed, high-eficiency switch mode power supplies. it provides all the functions necessary to implement a single-switch current mode pwm, in any topology, with a minimum of external parts. because the hv9110 utilizes supertexs proprietary bicmos/dmos technology, it requires less than one tenth of the operating power of conventional bipolar pwm ics, and can operate at more than twice their switching frequency. the dynamic range for regulation is also increased, to approximately 8 times that of similar bipolar parts. it starts directly from any dc input voltage between 10 and 120vdc, requiring no external power resistor. the output stage is push-pull cmos and thus requires no clamping diodes for protection, even when signiicant lead length exists between the output and the external mosfet. the clock frequency is set with a single external resistor. accessory functions are included to permit fast remote shutdown (latching or nonlatching) and under voltage shutdown. for similar ics intended to operate directly from up to 450vdc input, please consult the data sheets for the hv9120 and hv9123. for detailed circuit and application information, please refer to application notes an-h13 and an-h21 to an-h24. high-voltage, current-mode pwm controller functional block diagram + ? + ? + ? ref gen + ? + ? modulator comparator osc r s q current limit comparator comp osc in osc out fb vref bias vdd +vin pre-regulator/startup 8.6v 8.1v undervoltage comparator s r q vdd shutdownreset -vin sense output error amplifier 4v to internal circuits 1.2v current sources to v dd 2v 4 5 3 11 12 2 6 1 10 14 13 8 7 t q downloaded from: http:///
2 supertex inc. www.supertex.com hv9110 doc.# dsfp-hv9110 a031214 bias output +vin sense -vin fb vdd osc out shutdown osc in vref nc reset comp bia s ou tp u t +vin s en s e -vin f b vdd o s s h u td o wn osc in v ref n c r e s et c o mp absolute maximum ratings parameter value input voltage, v in 120v logic voltage, v dd 15.5v logic linear input, fb and sense input voltage -0.3v to v dd +0.3v operating temperature range -55c to +125c storage temperature range -65c to +150c power dissipation 750mw stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the speciications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin conigurationproduct marking y = last digit of year sealedww = week sealed l = lot number c = country of origin* a = assembler id* = ?green? packaging *may be part of top marking top marking bottom marking hv9110ng yww llllllll ccccccccc aaa 14-lead soic (narrow body) 14-lead soic (narrow body) electrical characteristics (unless otherwise speciied, v dd = 10v, +v in = 48v, -v in = 0v, r bias = 390k?, r osc = 330k?, t a = 25c.) sym parameter # min typ max units conditions reference v ref output voltage - 3.92 4.00 4.08 v r l = 10m? - 3.82 4.00 4.16 r l = 10m?, t a = -55c to 125c z out output impedance # 15 30 45 k --- i short short circuit current - - 125 250 a v ref = -v in v ref change in v ref with temperature # - 0.25 - mv/c t a = -55c to 125c oscillator f max oscillator frequency - 1.0 3.0 - mhz r osc = 0m f osc initial accuracy 1 - 80 100 120 khz r osc = 330k - 160 200 240 r osc = 150k - voltage stability - - - 15 % 9.5v< v dd <13.5v - temperature coeficient # - 170 - ppm/c t a = -55c to 125c notes: # guaranteed by design. 1. stray capacitance on osc in pin must be 5.0pf. package may or may not include the following marks: si or part number package options packing HV9110NG-G 14-lead soic (narrow body) 53/tube HV9110NG-G m905 14-lead soic (narrow body) 2500/reel ordering information typical thermal resistance package ja 14-lead soic (narrow body) 75c/w -g denotes a lead (pb)-free / rohs compliant package downloaded from: http:///
3 supertex inc. www.supertex.com hv9110 doc.# dsfp-hv9110 a031214 electrical characteristics (cont.) (unless otherwise speciied, v dd = 10v, +v in = 48v, -v in = 0v, r bias = 390k?, r osc = 330k?, t a = 25c.) sym parameter # min typ max units conditions pwm d max maximum duty cycle # 49.0 49.4 49.6 % --- d min minimum duty cycle - - - 0 % --- maximum pulse width before pulse drops out # - 80 125 ns --- current limit maximum input signal - 1.0 1.2 1.4 v v fb = 0v t d delay to output # - 80 120 ns v sense = 1.5v, v comp 2.0v error ampliier v fb feedback voltage - 3.96 4.00 4.04 v v fb shorted to comp i in input bias current - - 25 500 na v fb = 4.0v v os input offset voltage - nulled during trim - --- a vol open loop voltage gain # 60 80 - db --- gb unity gain bandwidth # 1.0 1.3 - mhz --- z out out impedance # see fig. 1 --- i source output source current - -1.4 -2.0 - ma v fb = 3.4v i sink output sink current - 0.12 0.15 - ma v fb = 4.5v psrr power supply rejection # see fig. 2 db --- pre-regulator/startup +v in input voltage - 10 - 120 v i in < 10a; v cc > 9.4v +i in input leakage current - - - 10 a v dd > 9.4v v th v dd pre-regulator turn-off threshold voltage - 8.0 8.7 9.4 v i prereg = 10a v lock undervoltage lockout - 7.0 8.1 8.9 v --- supply i dd supply current - - 0.75 1.0 ma c l < 75pf i q quiescent supply current - - 0.55 - ma shutdown = -v in i bias nominal bias current - - 20 - a --- v dd operating range - 9.0 - 13.5 v --- note: # guaranteed by design. downloaded from: http:///
4 supertex inc. www.supertex.com hv9110 doc.# dsfp-hv9110 a031214 electrical characteristics (cont.) (unless otherwise speciied, v dd = 10v, +v in = 48v, -v in = 0v, r bias = 390k?, r osc = 330k?, t a = 25c.) shutdown logic t sd shutdown delay # - 50 100 ns c l = 500pf, v sense = -v in t sw shutdown pulse width # 50 - - ns t rw reset pulse width # 50 - - ns --- t lw latching pulse width # 25 - - ns shutdown and reset low v il input low voltage - - - 2.0 v --- v ih input high voltage - 7.0 - - v --- i ih input current, input high voltage - - 1.0 5.0 a v in = v dd i il input current, input low voltage - - -25 -35 a v in = 0v output v oh output high voltage - v dd -0.25 - - v i out = 10ma - v dd -0.3 - - i out = 10ma, t a = -55c to 125c v ol output low voltage - - - 0.2 v i out = -10ma - - - 0.3 i out = -10ma, t a = -55c to 125c r out output resistance pull up - - 15 25 i out = 10ma pull down - - 8.0 20 pull up - - 20 30 i out = 10ma, t a = -55c to 125c pull down - - 10 30 t r rise time # - 30 75 ns c l = 500pf t f fall time # - 20 75 ns c l = 500pf note: # guaranteed by design. sym parameter # min typ max units conditions shutdown reset output h h normal operation h h l normal operation, no change l h off, not latched l l off, latched l h l off, latched, no change truth table downloaded from: http:///
5 supertex inc. www.supertex.com hv9110 doc.# dsfp-hv9110 a031214 test circuits detailed description preregulator the preregulator/startup circuit for the hv9110 consists of a high-voltage, n-channel, depletion-mode, dmos transistor driven by an error ampliier to form a variable current path between the vin terminal and the vdd terminal. the maxi - mum current (about 20ma) occurs when v dd = 0, with current reducing as v dd rises. this path shuts off altogether when v dd rises to somewhere between 7.8 and 9.4v, so that if v dd is held at 10 or 12v by an external source (generally the supply the chip is controlling), no current other than leakage is drawn through the high voltage transistor. this minimizes dissipation. an external capacitor between vdd and vss is generally required to store energy used by the chip in the time be - tween shutoff of the high voltage path and the vdd supplys output rising enough to take over powering the chip. this capacitor should have a value of 100x or more the effective gate capacitance of the mosfet being driven, i.e., c storage 100 x (gate charge of fet at 10v) as well as very good high frequency characteristics. stacked polyester or ceramic caps work well. electrolytic capacitors are generally not suitable. a common resistor divider string is used to monitor v dd for both the under voltage lockout circuit and the shutoff circuit of the high voltage fet. setting the under voltage sense point about 0.6v lower on the string than the fet shutoff point guarantees that the under voltage lockout always re - leases before the fet shuts off. bias circuit an external bias resistor, connected between the bias pin and vss is required by the hv9110 to set currents in a se - ries of current mirrors used by the analog sections of the chip. the nominal external bias current requirement is 15 to 20a, which can be set by a 390k? to 510k? resistor if a 10v v dd is used, or a 510k? to 680k? resistor if v dd will be 12v. a precision resistor is not required; 5% is ine. clock oscillator the clock oscillator of the hv9110 consists of a ring of cmos inverters, timing capacitors, and a frequency dividing lip-lop. a single external resistor between the osc in and osc out is required to set the oscillator frequency (see graph). one major difference exists between the supertex hv9110 and competitive 9110s. on the supertex part, the oscillator is shut off when a shutoff command is received. this saves about 150a of quiescent current, which aids in the construction of power supplies that meet ccitt specii - cation i-430, and in other situations where an absolute mini - mum of quiescent power dissipation is required. + ? reference 0.1v swept 10hz - 1.0mhz 0.1f 10.0v 4.0v 100k 1% 100k1% psrr + ? reference 60.4k 40.2k 1.0v swept 100hz - 2.2mhz te ktronix p6021 (1 turn secondary) +10v(v dd ) gnd(-v in ) (fb) note: set feedback voltage so that v comp = v divide 1.0mv before connecting transformer error amp z out 0.1f v 1 v 2 v 2 v 1 downloaded from: http:///
6 supertex inc. www.supertex.com hv9110 doc.# dsfp-hv9110 a031214 reference the reference of the hv9110 consists of a stable bandgap reference followed by a buffer ampliier which scales the voltage up to approximately 4.0v. the scaling resistors of the reference buffer ampliier are trimmed during manufac - ture so that the output of the error ampliier, when connected in a gain of C1 coniguration, is as close to 4.0v as possible. this nulls out any input offset of the error ampliier. as a con - sequence, even though the observed reference voltage of a speciic part may not be exactly 4.0v, the feedback voltage required for proper regulation will be. a 50k? resistor is placed internally between the output of the reference buffer ampliier and the circuitry it feeds (refer - ence output pin and non-inverting input to the error ampli - ier). this allows overriding the internal reference with a low impedance voltage source 6.0v. using an external refer - ence reinstates the input offset voltage of the error ampliier, and its effect of the exact value of feedback voltage required. because the reference of the hv9110 is a high impedance node, and usually there will be signiicant electrical noise near it, a bypass capacitor between the reference pin and vss is strongly recommended. the reference buffer ampli - ier is intentionally compensated to be stable with a capaci - tive load of 0.01 to 0.1f. error ampliier the error ampliier in the hv9110 is a true low-power dif - ferential input operational ampliier intended for around the ampliier compensation. it is of mixed cmos-bipolar con - struction: a pmos input stage is used so the common mode range includes ground and the input impedance is very high. this is followed by bipolar gain stages which provide high gain without the electrical noise of all-mos ampliiers. the ampliier is unity gain stable. current sense comparators the hv9110 uses a true dual comparator system with in - dependent comparators for modulation and current limiting. this allows the designer greater latitude in compensation design, as there are no clamps (except esd protection) on the compensation pin. like the error ampliier, the compara - tors are of low-noise bicmos construction. remote shutdown the shutdown and reset pins of the 9110 can be used to perform either latching or non-latching shutdown of a con - verter as required. these pins have internal current source pull-ups so they can be driven from open drain logic. when not used they should be left open, or connected to vdd. output buffer the output buffer of the hv9110 is of standard cmos con - struction (p-channel pull-up, n-channel pull-down). thus the body-drain diodes of the output stage can be used for spike clipping if necessary, and external schottky diode clamping of the output is not required. shutdown timing waveforms v dd 50% 0 t d output sense 1.5v 0 t sd 50% 90% 90% v dd output 0 shutdown v dd 0 t lw 50% 50% t sw 50% 50% t rw reset 0 v dd shutdown 0 v dd 50% t f 10ns t r , t f 10ns t r 10ns downloaded from: http:///
7 supertex inc. www.supertex.com hv9110 doc.# dsfp-hv9110 a031214 typical performance curves psrr - error amplifier and reference output switching frequency vs. oscillator resistance 10k 100k 1m r os ? f o 80 70 60 50 40 30 20 10 0 -10 error amplifier open oop ainphase ain d phase o 180 120 60 0 -60 -120 -180 frequency 10 6 10 5 10 4 10 3 10 2 10 1.0 0.1 100 1k 10k 100k 1m 10m error amplifier output mpedance 0 -10 -20 -30 -40 -50 -60 -70 -80 1m 100k 10k hv9113 hv9110, 9111, 9112 ias resistance ? 10 5 10 6 10 7 ias urrent a 100 10 0 v dd = 12v pssr d frequency ? frequency fig. fig. fig. fig. fig. v dd = 10v 10 100 1k 10k 100k 1m 100 1k 10k 100k 1m downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc . does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2014 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 8 hv9110 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv9110 a031214 14-lead soic (narrow body) package outline (ng) 8.65x3.90mm body, 1.75mm height (max), 1.27mm pitch symbol a a1 a2 b d e e1 e h l l1 l2 1 dimension (mm) min 1.35* 0.10 1.25 0.31 8.55* 5.80* 3.80* 1.27 bsc 0.25 0.40 1.04 ref 0.25 bsc 0 o 5 o nom - - - - 8.65 6.00 3.90 - - - - max 1.75 0.25 1.65* 0.51 8.75* 6.20* 4.00* 0.50 1.27 8 o 15 o jedec registration ms-012, variation ab, issue e, sept. 2005. * this dimension is not speciied in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-14soicng, version f041309. top vi ew side vi ew vi ew a-a vi ew b a a seating plane 14 1 seating plane gauge plane l l1 l2 1 view b h h b a a2 a1 e e e1 d note 1 (index area d/2 x e1/2) note: 1. this chamfer feature is optional. if it is not present, then a pin 1 identiier must be located in th e index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. downloaded from: http:///
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