_____________________________________________________________________________________________________________________________ _________________ DSC2011 page 1 mk - q - b - p - d - 120426 02 - 2 low - jitter configurable dual cmos oscillator dsc 2011 general description the dsc 201 1 series of high performance dual output cmos oscillators utilize a proven silicon mems technology to provide excellent jitter and stability while incorporating additional device functionality . the two cmos outputs are controlled by separate supply voltages to allow for independent voltage level control. the frequencies of the outputs can be identical or independently derived from a common pll frequency source. the DSC2011 has provision for up to eight u ser - defined pre - programmed, pin - selectable output freq uency combinations. the DSC2011 is also equipped with indep endent pin - selectable output drive strengths for each output to reduce emi and noise. DSC2011 is packaged in a 14 - pin 3.2x2.5 mm qfn package and available in temperature grades from ext. commercial to automotive. block diagram features ? low rms phase jitter: <1 ps (typ) ? high stability: 1 0 , 25, 50 ppm ? wide temp erature range o automotive : - 55 to 125 c o ext. industrial: - 40 to 10 5 c o industrial: - 40 to 85 c o ext. commercial: - 20 to 70 c ? high supply noise rejection: - 50 dbc ? two independent cmos outputs ? pin - selectable configurations o 2 - bit output drive strength o 3 - bit output frequency combinations ? short lead times: 2 weeks ? wide freq. range: o cmos output: 2.3 to 170 mhz ? miniature footprint of 3.2x2.5mm ? excellent shock & vibration immunity o qualified to mil - std - 883 ? high reliability o 20x better mtf than quartz oscillators ? supply range of 2.25 to 3.6 v ? lead free & rohs compliant applications ? consumer electronics ? storage area networks o sata, sas , fibre channel ? passive optical networks o epon, 10g - epon, gpon, 10g - pon ? ethernet o 1g, 10gbase - t/kr/lr/sr, and fcoe ? hd/sd/sdi video & surveillance ? pci express
_____________________________________________________________________________________________________________________________ _________________ DSC2011 page 2 mk - q - b - p - d - 120426 02 - 2 DSC2011 low - jitter configurable dual cmos oscillator pin description pin no. pin name pin type description 1 enable i enables outputs when high and disables when low 2 nc na leave unconnected or grounded 3 o2s0 i least significant bit for drive strength selection for output 2 4 gnd power ground 5 fs0 i least significant bit for frequency selection 6 fs1 i middle bit for frequency selection 7 fs2 i most significant bit for frequency selection 8 output1 o cmos output 1 9 o1s0 i least significant bit for drive strength selection for output 1 10 o1s1 i most significant bit for drive strength selection for output 1 11 output2 o cmos output 2 12 vdd 2 power power supply for output 2 13 vdd power power supply 14 o2s1 i most significant bit for drive strength selection for output 2 operational description the DSC2011 is a dual output cmos oscillator consisting of a mems resonator and a support pll ic . the two cmos outputs are generated through independent 8 - bit programmable dividers from the output of the internal pll . for temp ranges up to industrial, two constraints are imposed on the output frequencies: 1) f 2 =m x f 1 /n , where m and n are even intege rs between 4 and 254 , 2) 1.2ghz < n x f 2 < 1.7ghz . p lease consult factory for acceptable frequency combinations for other temp ranges . the actual frequencies output by the DSC2011 are controlled by an internal pre - programmed memory (otp). this memory sto res all coefficients required by the pll for up to eight different frequency combinations. three contr ol pins (fs0 C fs2) select the output frequency combination. discera supports customer defined versions of the DSC2011. standard frequency options are described in in the following section s . the DSC2011 has independent control of the output voltage levels of the two outputs. the high voltage level of output 1 is equal to the main supply voltage, vdd (pin 1 3 ). vdd 2 (pin 1 2 ) sets the high voltage level of output 2. vdd2 must be equal to or less than vdd at all times to insure proper operation. vdd2 can be as low as 1.65v. when enable (pin 1) is floated or connected to v dd , the DSC2011 is in operational mode. driving enabl e to ground will tri - state both output drivers (hi - impedance mode). the DSC2011 has programmable output drive strength for each output. using two control pins (oxs0 - oxs 1 ) for each output, the drive strength can be independently adjusted to match circuit b oard impedances to reduce power supply noise, overshoot/undershoot and emi. table 1 displays typical rise / fall times for the output with a 15pf load capacitance as a function of these control pins at v dd =3.3v and room temperature. table 1. rise/fall ti mes for drive strengths output drive strength bits [o x s 1 , o x s 0 ] - default [11] 00 01 10 11 t r (ns) 1.6 1.4 1.2 1. 1 t f (ns) 2.4 2 .2 1. 5 1. 4
_____________________________________________________________________________________________________________________________ _________________ DSC2011 page 3 mk - q - b - p - d - 120426 02 - 2 DSC2011 low - jitter configurable dual cmos oscillator output clock frequencies table 2 lists the standard frequency configurations and the associated ordering information to be used in conjunction with the ordering code above. customer defined combinations are available. table 2. pre - programmed pin - selectable output frequency c ombinations ordering info freq (mhz) freq select bits [fs2, fs1, fs0] C d efault is [ 111 ] 000 001 010 011 100 101 110 111 e 000 1 f out1 27 25 50 54 48 24 24 24 f out2 24 125 125 2 7 24 50 54 27 e 000 2 f out1 106.25 100 125 100 156.25 156.25 125 156.25 f out2 2 5 100 50 50 25 125 25 156.25 e0004 f o ut1 24 75 125 48 74.25 148.5 50 25 f out2 24 75 125 48 74.25 148.5 50 25 e0005 f out1 25 0* 0* 0* 0* 0* 0* 25 f out2 25 0* 0* 0* 0* 0* 0* 25 e000 6 f out1 27 74.175 74.25 148.35 148.5 0* 0* 0* f out2 1 3.5 37.0875 37.125 74.175 74.25 0* 0* 0* e000 7 f out1 24 0* 0* 0* 0* 0* 0* 0* f out2 4 0 0* 0* 0* 0* 0* 0* 0* e000 8 f out1 40 40 40 20 40 20 40 20 f out 2 200 128 120 120 100 100 80 80 exxxx f out1 contact factory for additional configurations. f out2 frequency select bit are weakly tied high so if left unconnected the default setting will be [111] and the device will output the associated frequency highlighted in bold . 0* C denotes invalid selection, output frequency is not specified.
_____________________________________________________________________________________________________________________________ _________________ DSC2011 page 4 mk - q - b - p - d - 120426 02 - 2 DSC2011 low - jitter configurable dual cmos oscillator absolute maximum ratings item min max unit condition supply voltage - 0.3 +4.0 v input voltage - 0.3 v dd +0.3 v junction temp - +150 c storage temp - 55 +150 c soldering temp - +260 c 40 sec max. esd hbm mm cdm - 4000 400 1500 v note: 1000+ years of data retention on internal memory ordering code specifications (unless specified otherwise: t= 25 c , max cmos drive s trength ) notes: 1. pin 4 v dd should be filtered with 0.01uf capacitor. 2. output is enabled if enable pad is floated or not connected. 3. t su is time to 100ppm stable output frequency after v dd is applied and outputs are enabled. 4. output waveform and test circuit figures below define the parameters. 5. period jitter includes crosstalk from adjacent output. parameter condition min. typ. max. unit supply voltage 1 v dd 2.25 3.6 v supply current i dd en pin low C output s are d isabled 2 1 2 3 ma supply current 2 i dd en pin high C outputs are enabled c l = 15 pf, f o1 = f o 2 = 1 25 mhz 32 ma frequency stability f includes frequency variations due to initial tolerance, temp. and power supply voltage 10 2 5 50 ppm aging f 1 year @ 25c 5 ppm startup time 3 t su t= 25c 5 ms input logic levels input logic hig h input logic low v ih v il 0.75 x v d d - - 0.25 x v dd v output disable time 4 t da 5 ns output enable time t en 20 n s pull - up resistor 2 pull - up exist s on all digital io 40 k cmos output s output logic levels output logic high output logic low v oh v ol i= 6ma 0.9xv dd - - 0.1xv dd v output transition time 4 rise time fall time t r t f 20% to 80% c l =15pf 1.1 1. 4 2 2 n s frequency f 0 commercial/ i ndustrial temp range auto motive temp range 2.3 170 100 mhz output duty cycle sym 4 5 5 5 % period jitter 5 j per f o 1 = f o 2 = 125 mhz 3 ps rms integrated phase noise j cc 200khz to 20mhz @ 125mhz 100khz to 20mhz @ 125mhz 12khz to 20mhz @ 125mhz 0.3 0.38 1. 7 2 ps rms DSC2011 xxxxx freq (mhz) see freq. table - packing t: tape & reel : tube f i 2 package f : 3.2x2.5mm temp range e: - 20 to 70 i: - 40 to 85 l: - 40 to 105 m: - 55 to 125 stability 1: 50ppm 2: 25ppm 5: 10 ppm t
_____________________________________________________________________________________________________________________________ _________________ DSC2011 page 5 mk - q - b - p - d - 120426 02 - 2 DSC2011 low - jitter configurable dual cmos oscillator nominal performance parameters (unless specified otherwise: t=25 c, v dd =3.3 v) cmos phase jitter (integrated phase noise) output waveform: cmos v oh v ol v il 1/f o output enable t da t en t f t r v ih 0.0 0.5 1.0 1.5 2.0 2.5 0 200 400 600 800 1000 phase jitter (ps rms) low - end of integration bw: x khz to 20 mhz 25mhz - cmos 50mhz - cmos 106mhz - cmos 125mhz - cmos
_____________________________________________________________________________________________________________________________ _________________ DSC2011 page 6 mk - q - b - p - d - 120426 02 - 2 DSC2011 low - jitter configurable dual cmos oscillator solder reflow profile package dimensions 3.2 x 2.5 mm 14 lead plastic package disclaimer: micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in th is data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrels terms and conditions of sale for such products, micrel assumes no liability whatsoever, and mi crel disclaims any express or implied warranty relating to the sale and/or use of micrel products includ ing liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right . micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are inte nded for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchasers us e or sale of micrel products for use in life support appliances, devices or systems is a purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. micrel , inc. 2180 fortune drive , san jose, california 95131 usa phone: +1 (408) 944 - 0800 fax: +1 (408) 474 - 1000 email: hbwhelp @ micrel .com www.micrel.com msl 1 @ 260 c refer to jstd - 020c ramp - up rate (200 c to peak temp) 3 c/sec max. preheat time 150 c to 200 c 60 - 180 sec time maintained above 217 c 60 - 150 sec peak temperature 255 - 260 c time within 5 c of actual peak 20 - 40 sec ramp - down rate 6 c/sec max. time 25 c to peak temperature 8 min max. 60 - 150 sec 20 - 40 sec 60 - 180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 3c/sec max. 60 - 150 sec 20 - 40 sec 60 - 180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 60 - 150 sec 20 - 40 sec 60 - 180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 3c/sec max.
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