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1. general description the uhf epcglobal generation 2 standard a llows the commercialized provision of mass adoption of uhf rfid technology for passive smart tags and labels. main fields of applications are supply chain management and logistics for worldwide use with special consideration of european, us and chinese frequencies to ensure that operating distances of several me ters can be realized. the nxp semiconductors ucode product family is compliant to this epc gen2 standard offering anti-collision and co llision arbitration functionality. this allows a reader to simultaneously operate multiple labels/tags within its antenna field. the ucode based label/ tag requires no extern al power supply for contactless operation. its contactless interface generates the power supply via the antenna circuit by propagative energy transmission from the interrogator (r eader), while the system clock is generated by an on-chip oscillator. data transmitted from the interr ogator to the label/tag is demodulated by the interface, and it also modulates the interrogator's electromagnetic field for data transmission from the label/tag to the interrogator. a label/tag can be then operated without the need for line of sight or battery, as long as it is connected to a dedicated antenna for the targeted frequency range. when the label/tag is within the interrogator's operating range, the high-speed wireless interface allows data transmission in both directions. with the ucode i 2 c product, nxp semiconductors in troduces now the possibility to combine 2 independent uhf interfaces (following epc gen 2 standard) with an i 2 c interface. its large memory can be then read or write via both interfaces. this i 2 c functionality enables the standard epc gen 2 functionalities to be linked to an electronic device microprocessor. by linking the rich functionalities of the epc gen 2 standards to the electronics world, the ucode i 2 c product opens a whole new range of application. the i 2 c interface needs to be supplied externally and supports standard and fast i 2 c modes. its large memory is based on a field proven non-volatile memory technology commonly used in high quality automotive applications sl3s4011_4021 ucode i2c rev. 3.1 ? 3 july 2013 204931 product data sheet company public
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 2 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 2. features and benefits 2.1 uhf interface ? dual uhf antenna port ? ? 18 dbm read sensitivity ? ? 11 dbm write sensitivity ? ? 23 dbm read & write sensitivity with the chip powered ? compliant to epcglobal radio-frequency id entity protocols class-1 generation-2 uhf rfid protocol for communications at 860 mhz to 960 mhz version 1.2.0 ? wide rf interface temperature range: ? 40 c up to +85 c ? memory read protection ? interrupt output ? rf - i 2 c bridge function based on sram memory 2.2 i 2 c interface ? supports standard (100 khz) and fast (400 khz) mode (see ref. 1 ) ? ucode i 2 c can be used as standard i 2 c eeproms 2.3 command set ? all mandatory epc gen2 v1.2.0 commands ? optional commands: access, block write (32 bit) ? custom command: changeconfig 2.4 memory ? 3328-bit user memory ? 160-bit epc memory ? 96-bit tag identifier (tid) including 48-bit unique serial number ? 32-bit kill password to permanently disable the tag ? 32-bit access password to allow a transi tion into the secured transmission state ? data retention: 20 years at 55 c ? write endurance: 50 kcycles at 85 c 2.5 package ? sot-902-3; mo-255b footprint ? outline 1.6 1.6 mm ? thickness ? 0.5 mm
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 3 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 3. applications ? firmware downloads ? return management ? counterfeit protection and authentication ? production information ? theft protection and deterrence ? production automation ? device customization/product configuration ? offline diagnostics 4. ordering information [1] rfp1, rfn1 table 1. ordering information type number package name description version SL3S4011FHK xqfn8 single differential rf front end [1] - plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 1.6 0.5 mm sot902-3 sl3s4021fhk xqfn8 dual differential rf front end - plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 1.6 0.5 mm sot902-3
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 4 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 5. block diagram fig 1. block diagram rfp1 differential uhf frontend 1 rfn1 rfn2 differential uhf frontend 2 non volatile memory i 2 c interface iso18000-6 digital interface analog uhf antenna 2 uhf antenna 1 i 2 c driver/scl int signalling driver 50 ns spike input filter rfp2 scl sda i 2 c driver/sda ce ouput driver 50 ns spike input filter vddb vddb power management/ gnd 001aao224
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 5 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 6. pinning information 6.1 pinning 6.2 pin description (1) dimension a: 1.6 mm (2) dimension b: 0.5 mm fig 2. pin configuration 001aao225 vdd transparent top view side view 4 8 6 5 7 3 1 2rf1n rf1p scl a b gnd a rf2n sda rf2p table 2. pin description pin symbol description 1 rf1p active antenna 1 connector 2 rf1n antenna 1 3scl i 2 c clock / _int 4 vdd supply 5sda i 2 c data 6 rf2n antenna 2 7 rf2p active antenna 2 connector 8 gnd ground
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 6 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 7. mechanical specification 7.1 sot902 specification 8. functional description 8.1 air interface standards the ucode i 2 c fully supports all mandatory parts of the "specification for rfid air interface epcglobal, epc radio-frequency identity protocols, class-1 generation-2 uhf rfid, protocol for communications at 860 mhz to 960 mhz, version 1.2.0". 8.2 power transfer the interrogator provides an rf field that powers the tag, equipped with a ucode i 2 c. the antenna transforms the impedance of free space to the chip input impedance in order to get the maximum possible power for the ucode i 2 c on the tag. the rf field, which is oscillating on the opera ting frequency provided by the interrogator, is rectified to provide a smoo thed dc voltage to the analog and digital modules of the ic. for i 2 c operation the ucode i 2 c has to be supplied externally via the vdd pin. 8.3 data transfer air interface 8.3.1 interrogator to tag link an interrogator transmits in formation to the ucode i 2 c by modulating a uhf rf signal. the ucode i 2 c receives both information and operating energy from this rf signal. tags are passive, meaning that they receive all of their operating energy from the interrogator's rf waveform. an interrogator is using a fixed modulation and data rate for the duration of at least one inventory round. the interrogator communicates to the ucode i 2 c by modulating an rf carrier using dsb-ask with pie encoding. 8.3.2 tag to reader link an interrogator receives information from a ucode i 2 c by transmitting an unmodulated rf carrier and listening for a backscattered reply. the ucode i 2 c backscatters by switching the reflection coefficient of its antenna between two states in accordance with the data being sent. table 3. mechanical properties xqfn8 package name outline code package size reel format sot902 sot902-3 size:1.6 mm 1.6 mm 4000 pcs thickness: 0.5 mm 7? diameter carrier tape width 8 mm carrier pocket pitch 4 mm
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 7 of 31 nxp semiconductors sl3s4011_4021 ucode i2c the ucode i 2 c communicates information by backscatter-modulating the amplitude and/or phase of the rf carrier. interrogator s shall be capable of demodulating either demodulation type. the encoding format, selected in response to interrogator commands, is either fm0 baseband or miller-m odulated subaltern. 8.4 data transfer to i 2 c interface the ucode i 2 c memory can be read/written similar to a standard i 2 c serial eeprom device. the address space is arranged in a linear manner. when performing a sequential read the address pointer is increased linearly from start of the epc memory to the end of the user memory. at the end address of each bank the address pointer jumps automatically to the first address in the subsequent bank. in i 2 c write modes only even address values are accepted, due to the word wise organization of the eeprom. regarding arbitration between rf and i 2 c, see section 11 ? rf interface/i 2 c interface arbitration ? ). write operation : ? write word ? write block (2 words) read operation: ? current address read ? random address read ? sequential current read ? random sequential read 8.5 supported commands the ucode i 2 c supports all mandatory epcglobal v1.2.0 commands. in addition the ucode i 2 c supports the following optional commands. ? access ? blockwrite (32 bit) the ucode i 2 c features the following custom commands described in more detail later: ? changeconfig 8.6 ucode i 2 c memory the ucode i 2 c memory is implemented according to epcglobal gen2 and organized in four sections all access ible via both rf and i 2 c operation except the reserved memory section which only accessible via rf:
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 8 of 31 nxp semiconductors sl3s4011_4021 ucode i2c the logical addresses of all memory banks begin at zero (00h). in addition to the 4 memory banks one configuration word to handle the ucode i 2 c specific features is available at epc bank 01b address 200h. the configuration word is described in detail in section ?ucode i 2 c special features?. table 4. ucode i 2 c memory sections name size bank reserved memory (32-bit access and 32-bit kill password) 64 bit 00b epc (excluding 16 bit crc-16 and 16-bit pc) 160 bit 01b download register 16 bit 01b ucode i 2 c configuration word 16 bit 01b tid (including unique 48 bit serial number) 96 bit 10b user memory 3328 bit 11b
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 9 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 8.6.1 ucode i 2 c overall memory map [1] sl3s4011 epc: e200 680d 0000 0000 0000 0000 0000 0000 0000 0000 sl3s4021 epc: e200 688d 0000 0000 0000 0000 0000 0000 0000 0000 [2] see tid paragraph table 5. memory map bank address memory address type content initial value remark rf i 2 c bank 00 00h to 1fh not accessible via i 2 c reserved kill password all 00h unlocked memory 20h to 3fh not accessible via i 2 c reserved access password all 00h unlocked memory bank 01 epc 00h to 0fh 2000h epc crc-16: refer to ref. 5 memory mapped calculated crc 10h to 1fh 2002h epc pc 3000h unlocked memory 20h to 2fh 2004h epc epc bit [0 to 15] [1] unlocked memory ... epc ... unlocked memory 20h to bfh 2016h epc epc bit [144 to 159] unlocked memory 1f0h to 1ffh 203eh epc download register for the bridge function 200h to 20fh 2040h epc configuration word, see section 9.2 bank 10 tid 00h to 0fh 4000h tid tid header n.a. locked memory 10h to 1fh 4002h tid tid header n.a. locked memory 20h to 2fh 4004h tid xtid_header 0000h locked memory 30h to 3fh 4006h tid tid serial number [2] locked memory 40h to 4fh 4008h tid tid serial number n.a. locked memory 50h to 5fh 400ah tid tid serial number n.a. locked memory bank 11 user memory 000h to 00fh 6000h um user memory bit [0 to 15] all 00h unlocked memory 010h to 01fh 6002h um user memory bit [16 to 31] all 00h unlocked memory ... um all 00h unlocked memory cf0h to cffh 619eh um user memory bit [3311 to 3327] all 00h unlocked memory
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 10 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 8.6.2 ucode i 2 c tid memory details table 6. ucode i 2 c tid description model number type first 32 bit of tid memory class id mask designer id config word indicator sub version number version (silicon) number ucode sl3s4011 e200680d e2h 006h 1 0000b 0001101 ucode sl3s4021 e200688d e2h 006h 1 0001b 0001101 fig 3. ucode i 2 c tid memory structure aaa-006851 class identifier ms byte ms bit ls bit tid mask-designer identifier model number xtid header serial number 000 7bits 11 11 15 0 0 47 07h 13h 1fh 5fh 00h addresses cfh 00h addresses 08h 14h 20h 2fh 30h e2h (ean.ucc) tid example (ucode i 2 c) 006h (nxp) 0000h sub version number version number 000b or 001b 0001101b (ucode i 2 c) 60 03 bits 0 1fh 14h 18h addresses 19h 80dh or 88dh (ucode i 2 c) ls byte
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 11 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 9. supported features the ucode i 2 c is equipped with a number of additional features and a custom command. nevertheless, the chip is designed in a way that standard epcglobal read / write / access commands can be used to operat e the features. the memory map in the previous section describes the configuration word used to control the additional features located af ter address 200h of the epc memory, hence ucode i 2 c features are controlled by bits locate d in the epc number space. for this reason the standard read / write comma nds of a uhf epcglobal compliant reader can be used to select the flags or activate/deactivate features if the memory bank is not locked. in case of locked memory banks the changeconfig custom command has to be used. the bits (flags) of the configurationword ar e selectable using the standard epc select command. 9.1 ucode i 2 c special feature ? externally supplied flag the flag will indicate the availabi lity of an external supply. ? rf active flag the flag will indicate on which rf port powe r is available and signal transmission ongoing. ? rf interface on/off switching for privacy reasons the two rf ports as well as the i 2 c interface can be switched on/off by toggling the related bits of the configurationword. the configurationword is accessible via rf and i 2 c interface. alth ough it is possible to k ill the rf interface via the kill feature of epc gen2, a minimum of one port shall be active at all times. in the case of the dual port version, either one or both rf can be active. in the case of the single front end version, the rf port can not be deactivated. ? i 2 c interface on/off switching for privacy reasons the i 2 c port can be disabled by toggling the related bit of the config-word but only via rf. ? rf - i 2 c bridge feature the ucode i 2 c can be used as an rf- i 2 c bridge to directly forward data from the rf interface to the i 2 c interface and vice versa. the ucode i 2 c is equipped with a download/upload register of 16-bit data buffer located in the epc bank. the data received via rf can be read via i 2 c like regular memory content. in case the buffer is empty reading the register returns nak. this feature can be combined with the download indicator. ? upload indicator flag (i 2 c to uhf) - address 203h in the configuration word the flag will indicate if data in the download/upload register is available. will be automatically cleared when the download/upload register is read out via uhf. ? download indicator flag (uhf to i 2 c) - address 200h in the configuration word the flag will indicate if data in the download/upload register is available. will be automatically cleared when the download/upload register is read out via i 2 c.
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 12 of 31 nxp semiconductors sl3s4011_4021 ucode i2c ? interrupt signaling/download indicator the ucode i 2 c features two methods of signaling: 1. signaling via configword "download/upload indicator" (200h or 203h): ? the download/upload in dicator will go high as soon new data from the rf reader or from the i 2 c interface is written to the buffer re gister. this flag can be polled via i 2 c read or using the select command. re ading an empty bu ffer register will return nak. ? the download/upload indicator will automatically retu rn to low as soon as the data is read. 2. interrupt signaling via the i 2 c-scl line: ? if the scl int enabler of the configword is set (20bh) the scl line will be pulled low for at least 210 ? s in case new data was written by the reader or at least 85 ? s in case new data has been read by the reader (see figure 4 ? scl interrupt signalling ? and table 7 ? interrupt signaling via the i2c-scl line timing ? ). [1] this timing parameter is dependent on the chosen return link frequency. [2] at 640 khz return link frequency. remark: the features can even be operated (enabled/disabled) with '0' as access password. it is recommended to set an access password to avoid unauthorized manipulation of the features via the rf interface. 9.2 ucode i 2 c special features control mechanism special features of the ucode i 2 c are managed using a configuration word (configword) located at the end of the epc memory bank (address 200h via rf or 2040h via i 2 c) - see ta b l e 8 and table 9 . fig 4. scl interrupt signalling table 7. interrupt signaling via the i2c-scl line timing symbol min typ max unit t scl low_write 210 266 320 ? s t scl low_read [1] 85 102 [2] 7800 ? s aaa-005682 uhf write dl reg command scl uhf scl read dl reg command read dl reg response write dl reg response t scl low_read t scl low_write
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 13 of 31 nxp semiconductors sl3s4011_4021 ucode i2c the bits of the configword are selectable (using the standard epc select command) and can be read, via rf, using standard epc read command and via i 2 c. they can be modified using the changeconfig cust om command or standard read/write commands or via the i 2 c interface (if allowed). [1] indicator bits are reset at power-up but cannot be changed by command [2] permanent bits are permanently stored bits in the memory [3] defaults values for bit3/bit2/bit1 are 0/0/1 (see ta b l e 1 4 ) table 8. configuration word accessible located at address 200h via uhf of the epc bank and i 2 c address 2040h (1 rf front end version sl3s4011) feature bit type via rf via i 2 c address access address access download indicator indicator [1] 200h read 2040h read externally supplied flag indicator 201h read read rf active flag indicator 202h read read upload indicator indicator 203h read read i 2 c address bit 3 [3] permanent [2] 204h r/w read only i 2 c address bit 2 [3] permanent 205h r/w read only i 2 c address bit 1 [3] permanent 206h r/w read only i 2 c port on/off permanent 207h r/w read only uhf antenna port1 on locked 208h read only read only rfu 209h rfu 20ah scl int enable permanent 20bh r/w read only bit for read protect user memory permanent 20ch r/w r/w bit for read protect epc permanent 20dh r/w r/w bit for read protect tid snr (48 bits) permanent 20eh r/w r/w psf alarm flag permanent 20fh r/w read only table 9. configuration word accessible located at address 200h via uhf of the epc bank and i 2 c address 2040h (2 rf front end version sl3s4021) feature bit type via rf via i 2 c address access address access download indicator indicator [1] 200h read 2040h read externally supplied flag indicator 201h read read rf active flag indicator 202h read read upload indicator indicator 203h read read i 2 c address bit 3 [3] permanent [2] 204h r/w read only i 2 c address bit 2 [3] permanent 205h r/w read only i 2 c address bit 1 [3] permanent 206h r/w read only i 2 c port on/off permanent 207h r/w read only uhf antenna port1 on/off permanent 208h r/w r/w uhf antenna port2 on/off permanent 209h r/w r/w rfu 20ah
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 14 of 31 nxp semiconductors sl3s4011_4021 ucode i2c [1] indicator bits are reset at power-up but cannot be changed by command [2] permanent bits are permanently stored bits in the memory [3] defaults values for bit3/bit2/bit1 are 0/0/1 (see ta b l e 1 4 ) scl int enable permanent 20bh r/w read only bit for read protect user memory permanent 20ch r/w r/w bit for read protect epc permanent 20dh r/w r/w bit for read protect tid snr (48 bits) permanent 20eh r/w r/w psf alarm flag permanent 20fh r/w read only table 9. configuration word accessible located at address 200h via uhf of the epc bank and i 2 c address 2040h (2 rf front end version sl3s4021) feature bit type via rf via i 2 c address access address access
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 15 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 9.3 change config command the ucode i 2 c changeconfig custom command allows handling the special features described in the previous paragraph. as long the epc bank is not write locked standard epc read/write commands can be used to modify the flags. the bits to be toggled in the configur ation register need to be set to '1'. e.g. sending 0000 0000 0000 0000 1001 xor rn16 will ac tivate the epc read protect and psf bit. sending the very same comman d a second time will di sable the features. the reply of the changec onfig will return the cu rrent register setting. the features can only be activated/deactivated in the open or secured state and with a non-zero access password. if the epc memo ry bank is locked for writing, the changeconfig command is needed to modify the configurationword. table 10. changeconfig custom command command rfu data rn crc-16 no. of bits 16 8 16 16 16 description 11100000 00000111 00000000 toggle bits xor rn16 handle - table 11. changeconfig custom response table starting state condition response next state ready all - ready arbitrate, reply, acknowledged all - arbitrate open valid handle, status word needs to change backscatter unchanged statusword immediately open valid handle, status word does not need to change backscatter statusword immediately open secured valid handle, status word needs to change backscatter modified statusword, when done secured valid handle, status word does not need to change backscatter statusword immediately secured invalid handle - secured killed all - killed
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 16 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 9.4 ucode i 2 c memory bank locking mechanism 9.4.1 possibilities 9.4.2 via rf the ucode i 2 c memory banks can be locked following epc gen2 mandatory command via rf (see table ta b l e 1 3 ). table 12. memory banks locking possibilities for ucode i 2 c via rf and i 2 c i 2 c interface rf interface memory bank lock (entire bank) permalock (entire bank) lock (entire bank) via access password permalock (entire bank) via access password 01 epc yes yes yes yes 11 user memory yes yes yes yes table 13. lock payload and usage kill pwd access pwd epc memory tid memory user memory 19 18 17 16 15 14 13 12 11 10 mask skip/write skip/write skip/write skip/write skip/writ e skip/write skip/write skip/write skip/write skip/write 98 76 54 32 10 action pwd read/write permalock pwd read /write permalock pwd write permalock pwd write permalock pwd write permalock
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 17 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 9.4.3 via i2c the epc gen2 locking bits for the memory banks are also accessible via the i 2 c interface for read and write operation and are located at the i 2 c address 803ch. but it is not possible to read and write the access and kill password. fig 5. i 2 c memory bank lock write and read access data byte 1 mask field action field kill pwd skip/ write skip/ write skip/ write skip/ write skip/ write skip/ write skip/ write skip/ write skip/ write skip/ write xxxxxx xxxxxx access pwd user memory rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu epc memory tid memory kill pwd n/a n/a permalock permalock permalock n/a n/a pwd write pwd write pwd write access pwd user memory epc memory tid memory data byte 2 lsb msb data byte 3 data byte 4 lsb msb aaa-003734
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 18 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 10. i 2 c commands 10.1 ucode i 2 c operation for details on i 2 c interface refer to ref. 1 . the ucode i 2 c supports the i 2 c protocol. this is summarized in figure 7 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. the device is always a slave in all communications. 10.2 start condition start is identified by a falling edge of serial data (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer command. the ucode i 2 c continuously monitors (except during a wr ite cycle) serial data (sda) and serial clock (scl) for a start condition, an d will not respond unless one is given. fig 6. i 2 c bus protocol scl sda scl 123 78 9 123 789 ack msb ack msb start condition sda input sda change stop condition stop condition start condition sda scl sda 001aao231
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 19 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 10.3 stop condition stop is identified by a rising edge of serial data (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the ucode i 2 c and the bus master. a read command that is followed by noack can be followed by a stop condition to force the ucode i 2 c into the standby mode. a stop condition at the end of a write command triggers the internal write cycle. 10.4 acknowledge bit (ack) the acknowledge bit is used to indicate a succ essful byte transfer. the bus transmitter, whether it be bus master or slave device, releases serial data (sda) after sending eight bits of data. during the 9th clock pulse period , the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. 10.5 data input during data input, the ucode i 2 c samples serial data (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low. 10.6 addressing to start communication between a bus master and the ucode i 2 c slave device, the bus master must initiate a start condition. following this, the bus master sends the device select code. the 7-bit device select code co nsists of a 4-bit device identifier (value ah) which is initialized in wafer test and cannot be changed in the user mode. three additional bits in the configuration word are reserved to alter the device address via rf interface after initialization. this a llows up to eight ucode i 2 c devices to be connected to a bus master at the same time. the 8th bit is the read/write bit (rw). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the ucode i 2 c gives an acknowledgment on serial data (sda) during the 9th bit time. if the ucode i 2 c does not match the device select code, it deselects itself from the bus. [1] initial values - can be changed - see also table 8 and table 9 . table 14. device select code device type identifier device address in configuration word 204h to 206h r/w device select code b7 b6 b5 b4 b3 b2 b1 b0 value 1 0 1 0 0 [1] 0 [1] 1 [1] 1/0
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 20 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 10.7 write operation the byte address must be an even value due to the word wise organization of the eeprom. following a start condition the bus master send s a device select code with the read/write bit (rw) reset to 0. the ucode i 2 c acknowledges this, as shown in figure 7 and waits for two address bytes. the ucode i 2 c responds to each address byte with an acknowledge bit, and then waits for the data byte. each data byte in the memory has a 16-bit (t wo byte wide) address. the most significant byte ( ta b l e 1 5 ) is sent first, followed by the least significant byte ( table 15 ). bits b15 to b0 form the address of the byte in memory. when the bus master generates a stop condi tion immediately after the ack bit (in the "10th bit" time slot), either at the end of a word write or a page write, the internal write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. during the internal write cycle, serial data (sda) is disabled internally, and the ucode i 2 c does not respond to any requests. table 15. i 2 c addressing most significant byte b15 b14 b13 b12 b11 b10 b9 b8 epc address epc/lock epc memory bank epc memory word address least significant byte b7 b6 b5 b4 b3 b2 b1 b0 epc address epc memory word address msb/ lsb fig 7. i 2 c write operation ack word write page write page write (cont?d) ack ack ack ack stop start r/w dev select data in 1 byte address data in 2 byte address ack stop 001aao230 ack ack ack ack start r/w dev select data in 1 byte address data in 2 byte address ack data in n
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 21 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 10.7.1 word write after the device select code and the address word, the bus master sends one word data. if the addressed location is write-protected, the ucode i 2 c replies with nack, and the location is not modified. if, instead, the addressed location is not write-protected, the ucode i 2 c replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 7 . 10.7.2 page write the page write mode allows 2 words to be wr itten in a single write cycle, provided that they are all located in the same 'row' in the memory: that is, the most significant memory address bits (b12-b2) are the same and b1= 0 and b0 = 0. if more than two words are sent than each additional byte will cause a nack on sda. the bus master sends from 1 to 2 words of da ta, each of which is acknowledged by the ucode i 2 c. the transfer is terminated by the bu s master generating a stop condition. 10.8 read operation after the successful completion of a read operation, the ucode i 2 c's internal address counter is incremented by one, to point to the next byte address. fig 8. i 2 c read operation ack ack no ack current address read random address read sequential current read sequential random read ack ack ack no ack stop start start start stop r/w r/w r/w r/w dev select * dev select * byte address data out dev select data out byte address ack ack ack no ack no ack stop stop start dev select data out 1 data out n 001aao229 ack ack ack ack ack start start r/w r/w dev select * dev select * byte address data out 1 byte address ack data out n
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 22 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 10.8.1 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 8 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the read/write bit (rw) set to 1. the ucode i 2 c acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 10.8.2 current address read for the current address read operation, following a start condition, the bus master only sends a ucode i 2 c select code with the read/write bit (rw) set to 1. the ucode i 2 c acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 8 , without acknowledging the byte. 10.8.3 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the ucode i 2 c continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 8 . the output data comes from consecutive ad dresses, with the internal address counter automatically incremented after each byte output. 10.8.4 acknowledge in read mode for all read commands, the ucode i 2 c waits, after each byte read, for an acknowledgment during the 9th bit time. if the bus master does not drive serial data (sda) low during this time, the ucode i 2 c terminates the data transfer and switches to its standby mode. 10.8.5 epc memory bank handling after the last memory address within one epc memory bank, the address counter 'rolls-over' to the next epc memory bank, and the ucode i 2 c continues to output data from memory address 00h in the successive epc memory bank. example: epc bank 01 ? epc bank 10 ? epc bank 11 ? epc bank 01
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 23 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 11. rf interface/i 2 c interface arbitration the ucode i 2 c needs to arbitrate the eeprom access betw een the rf and the i 2 c interface. the arbitration is implemented as following: ? first come, first serve strategy - the interf ace which provides data by having a first valid preamble on rf envelope (begin of a command) or a start condition and a valid i 2 c device address on the i 2 c interface will be favored. ? i 2 c access to the chip memory is possible re gardless if it is in the epc gen2 secured state or not ? during an i 2 c command, starting with an i 2 c start followed by valid i 2 c device address and ending with an i 2 c stop condition, any rf command is ignored. ? during any epc gen2 command any i 2 c command is ignored 12. limiting values [1] stresses above those listed under absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the operating conditions and electrical characterist ics section of this specification is not implied. [2] this product includes circuitry spec ifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggest ed that conventional precautions be taken to avoid applying greater than the rated maxima. [3] for esd measurement, the die chip has been mounted into a cdip8 package. [4] for esd measurement, the die chip has been mounted into a cdip8 package. table 16. limiting values [1] [2] [3] [4] in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd. symbol parameter conditions min max unit die v max maximum voltage on pin vdd, sda, scl, gnd ? 0.3 3.6 v t stg storage temperature ? 55 +125 ?c t amb ambient temperature ? 40 +85 ?c v esd electrostatic discharge voltage human body model; snw-fq-302a - ? 2kv charged device model - ? 500 v
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 24 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 13. characteristics [1] some legacy standard-mode devices had fixed input levels of v il = 1.5 v and v ih = 3.0 v. refer to component data sheets. [2] maximum vih = vdd(max) + 0.5 v or 5.5 v, which ever is lower. see component data sheets. [3] the same resistor value to drive 3 ma at 3.0 v vdd provides t he same rc time constant when using <2 v vdd with a smaller cur rent draw. [4] only applies to fast mode and fast mode plus. table 17. characteristics symbol parameter conditions min typ max unit eeprom characteristics t ret retention time t amb ? 55 ?c2 0--y e a r n endu(w) write endurance t amb ? 85 ?c 50000 - - cycle interface characteristics p tot total power dissipation - - 30 mw f oper operating frequency 840 - 960 mhz p min minimum operating power supply read mode - ? 18 - dbm write mode - ? 11 - dbm read and write mode with v dd input - ? 23 - dbm v dd supply voltage i 2 c, on v dd input 1.8 - 3.6 v v dd supply voltage rise time requirements 100 - - ? s i dd supply current from vdd in i 2 c read mode -10- ? a from vdd in i 2 c write mode -40- ? a z impedance (package) 915 mhz - 12,7-j 199 - ? - modulated jammer suppression ? 1.0 mhz - ? 4-db - unmodulated jammer suppression ? 1.0 mhz - ? 4-db v il low-level input voltage [1] -0.5 - 0.3 v dd v v ih high-level input voltage [1] 0.7 v dd -- [2] v v hys hysteresis of schmitt trigger inputs [4] 0.05 v dd --v v ol1 low-level output voltage 1 (open-drain or open-collector) at 3 ma sink current [3] ; v dd > 2 v 0- 0.4v v ol2 low-level output voltage 2 [4] (open-drain or open-collector) at 2 ma sink current[3]; v dd ? 2 v 0 - 0.2v dd v
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 25 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 14. package outline fig 9. package outline sot902-3 references outline version european projection issue date iec jedec jeita sot902-3 - - - mo-255 - - - sot902-3_po 11-08-16 11-08-18 unit mm max nom min 0.5 0.05 0.00 1.65 1.60 1.55 1.65 1.60 1.55 0.6 0.5 0.1 0.05 a dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. xqfn8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm sot902-3 a 1 b 0.25 0.20 0.15 deee 1 l 0.45 0.40 0.35 vw 0.05 yy 1 0.05 0 1 2 mm scale terminal 1 index area b a d e x c y c y 1 terminal 1 index area 3 l e 1 e ac b v c w 2 1 5 6 7 metal area not for soldering 8 4 e 1 e b a 1 a detail x
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 26 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 15. abbreviations 16. references [1] i 2 c-bus specification and user manual (nxp standard um10204.pdf / rev. 03 - 19 june 2007) [2] epc radio-frequency identi ty protocols class-1 generation-2 uhf rfid protocol for communications at 860 mh z - 960 mhz version 1.2.0 [3] epc conformance standard version 1.0.5 [4] esd method snw -fq-302a [5] iso/iec 18000-1: information technology - radio frequency identification for item management - part 1: reference architecture and definition of parameters to be standardized table 18. abbreviations acronym description crc cyclic redundancy check cw continuous wave eeprom electrically erasable pr ogrammable re ad only memory epc electronic product code (containing header, domain manager, object class and serial number) fm0 bhi phase space modulation hbm human body model ic integrated circuit lsb least significant byte/bit msb most significant byte/bit nrz non-return to zero coding rf radio frequency rtf reader talks first tari type a reference interval (iso 18000-6) uhf ultra high frequency x xb value in binary notation xx hex value in hexadecimal notation
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 27 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 17. revision history table 19. revision history document id release date data sheet status change notice supersedes sl3s4011_4021 v. 3.1 20130703 product data sheet - sl3s4011_4021 v. 3.0 modifications: ? general update sl3s4011_4021 v. 3.0 20130416 product data sheet - sl3s4011_4021 v. 2.3 modifications: ? data sheet status changed to product data sheet sl3s4011_4021 v. 2.3 20130305 preliminary data sheet - sl3s4011_4021 v. 2.2 modifications: ? general update ? security status changed into company public sl3s4011_4021 v. 2.2 20121127 preliminary data sheet sl3s4011_4021 v. 2.1 modifications: ? general update sl3s4011_4021 v. 2.1 20120726 preliminary data sheet - sl3s4001fhk v. 2.0 modifications: ? general update sl3s4011_4021 v. 2.0 20120627 preliminary data sheet - sl3s4001fhk v. 1.2 modifications: ? general update sl3s4001fhk v. 1.2 20111004 objective data sheet - sl3s4001fhk v. 1.1 modifications: ? table 1 ?ordering information?: updated ? figure 3 ?ucode i2c wafer layout?: values updated sl3s4001fhk v. 1.1 20110707 objective data sheet - sl3s4001fhk v. 1.0 modifications: ? table 3 ?mechanical properties xqfn8?: updated ? section 10.6 ?addressing?: updated sl3s4001fhk v. 1.0 20110609 objective data sheet - -
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 28 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 29 of 31 nxp semiconductors sl3s4011_4021 ucode i2c export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 18.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. ucode ? is a trademark of nxp b.v. i 2 c-bus ? logo is a trademark of nxp b.v. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
sl3s4011_4021 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet company public rev. 3.1 ? 3 july 2013 204931 30 of 31 nxp semiconductors sl3s4011_4021 ucode i2c 20. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .3 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 3. mechanical properties xqfn8 . . . . . . . . . . . . . .6 table 4. ucode i 2 c memory sections . . . . . . . . . . . . . .8 table 5. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 6. ucode i 2 c tid description . . . . . . . . . . . . . . .10 table 7. interrupt signaling via the i2c-scl line timing .12 table 8. configuration word accessible located at address 200h via uhf of the epc bank and i 2 c address 2040h (1 rf front end version sl3s4011) . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 9. configuration word accessible located at address 200h via uhf of the epc bank and i 2 c address 2040h (2 rf front end version sl3s4021) . . . . . . . . . . . . . . . . . . . . . 13 table 10. changeconfig custom command. . . . . . . . . . . 15 table 11. changeconfig custom response table . . . . . . . 15 table 12. memory banks locking possibilities for ucode i 2 c via rf and i 2 c . . . . . . . . . . . . . . . 16 table 13. lock payload and usage . . . . . . . . . . . . . . . . . 16 table 14. device select code. . . . . . . . . . . . . . . . . . . . . . 19 table 15. i 2 c addressing . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 16. limiting values [1][2] [3][4] . . . . . . . . . . . . . . . . . . 23 table 17. characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24 table 18. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 19. revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 21. figures fig 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 fig 2. pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .5 fig 3. ucode i 2 c tid memory structure . . . . . . . . . . .10 fig 4. scl interrupt signalling . . . . . . . . . . . . . . . . . . . .12 fig 5. i 2 c memory bank lock write and read access . . .17 fig 6. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .18 fig 7. i 2 c write operation . . . . . . . . . . . . . . . . . . . . . . . .20 fig 8. i 2 c read operation . . . . . . . . . . . . . . . . . . . . . . . .21 fig 9. package outline sot902-3 . . . . . . . . . . . . . . . . .25
nxp semiconductors sl3s4011_4021 ucode i2c ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 3 july 2013 204931 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 uhf interface . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 command set . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.4 memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.5 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 mechanical specification . . . . . . . . . . . . . . . . . 6 7.1 sot902 specification . . . . . . . . . . . . . . . . . . . . 6 8 functional description . . . . . . . . . . . . . . . . . . . 6 8.1 air interface standards . . . . . . . . . . . . . . . . . . . 6 8.2 power transfer . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.3 data transfer air interface . . . . . . . . . . . . . . . . . 6 8.3.1 interrogator to tag link . . . . . . . . . . . . . . . . . . . 6 8.3.2 tag to reader link . . . . . . . . . . . . . . . . . . . . . . . 6 8.4 data transfer to i 2 c interface . . . . . . . . . . . . . . 7 8.5 supported commands . . . . . . . . . . . . . . . . . . . 7 8.6 ucode i 2 c memory. . . . . . . . . . . . . . . . . . . . . 7 8.6.1 ucode i 2 c overall memory map . . . . . . . . . . . 9 8.6.2 ucode i 2 c tid memory details . . . . . . . . . . 10 9 supported features . . . . . . . . . . . . . . . . . . . . . 11 9.1 ucode i 2 c special feature . . . . . . . . . . . . . . 11 9.2 ucode i 2 c special features control mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9.3 change config command . . . . . . . . . . . . . . . 15 9.4 ucode i 2 c memory bank locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.4.1 possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.4.2 via rf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.4.3 via i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 i 2 c commands . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.1 ucode i 2 c operation. . . . . . . . . . . . . . . . . . . 18 10.2 start condition . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.3 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.4 acknowledge bit (ack). . . . . . . . . . . . . . . . . . 19 10.5 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.6 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.7 write operation. . . . . . . . . . . . . . . . . . . . . . . . 20 10.7.1 word write . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.7.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.8 read operation . . . . . . . . . . . . . . . . . . . . . . . 21 10.8.1 random address read . . . . . . . . . . . . . . . . . 22 10.8.2 current address read . . . . . . . . . . . . . . . . . . 22 10.8.3 sequential read . . . . . . . . . . . . . . . . . . . . . . 22 10.8.4 acknowledge in read mode . . . . . . . . . . . . . 22 10.8.5 epc memory bank handling . . . . . . . . . . . . . 22 11 rf interface/i 2 c interface arbitration. . . . . . . 23 12 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 23 13 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24 14 package outline. . . . . . . . . . . . . . . . . . . . . . . . 25 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 26 16 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 17 revision history . . . . . . . . . . . . . . . . . . . . . . . 27 18 legal information . . . . . . . . . . . . . . . . . . . . . . 28 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 28 18.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 29 19 contact information . . . . . . . . . . . . . . . . . . . . 29 20 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 21 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 22 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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