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low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer 83940D datasheet 83940D revision b 3/25/15 1 ?2015 integrated device technology, inc. g eneral d escription the 83940D is a low skew, 1-to-18 lvpecl-to-lvc- mos/lvttl fanout buffer. the 83940D has two select- able clock inputs. the pclk, npclk pair can accept lvpecl, cml, or sstl input levels. the lvcmos_ clk can accept lvcmos or lvttl input levels. the low impedance lvcmos/lvttl outputs are designed to drive 50 series or parallel terminated transmission lines. the 83940D is characterized at full 3.3v and 2.5v or mixed3.3v core, 2.5v output operating supply modes. guaranteed output and part-to-part skew characteristics make the 83940D ideal for those clock distribution applications demanding well de ned performance and repeatability. b lock d iagram p in a ssignment f eatures ? 18 lvcmos/lvttl outputs ? selectable lvcmos_clk or lvpecl clock inputs ? pclk, npclk supports the following input types: lvpecl, cml, sstl ? lvcmos_clk accepts the following input levels: lvcmos or lvttl ? maximum output frequency: 250mhz ? output skew: 150ps (maximum) ? part to part skew: 750ps (maximum) ? additive phase jitter, rms: < 0.03ps (typical) ? full 3.3v and 2.5v or mixed 3.3v core, 2.5v output supply modes ? 0? to 70? ambient operating temperature ? lead-free package available 32-lead lqfp 7mm x 7mm x 1.4mm package body y pacakge top view 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 q6 q7 q8 v dd q9 q10 q11 gnd gnd gnd lvcmos_clk clk_sel pclk npclk v dd v ddo v ddo q12 q13 q14 gnd q15 q16 q17 gnd q5 q4 q3 v ddo q2 q1 q0 ics83940D
low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer 83940D data sheet 2 revision b 3/25/15 t able 1. p in d escriptions number name type description 1, 2, 12, 17, 25 gnd power power supply ground. 3 lvcmos_clk input pulldown clock input. lvcmos / lvttl interface levels. 4 clk_sel input pulldown clock select input. selects lvcmos / lvttl clock input when high. selects pclk, npclk inputs when low. lvcmos / lvttl interface levels. 5 pclk input pulldown non-inverting differential lvpecl clock input. 6 npclk input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left oating. 7, 21 v dd power core supply pins. 8, 16, 29 v ddo power output supply pins. 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 q17, q16, q15, q14, q13, q12, q11, q10, q9, q8, q7, q6, q5, q4, q3, q2, q1, q0 output clock outputs. lvcmos / lvttl interface levels. note: pullup and pulldown refers to internal input resistors. see table 2, pin characteristics, for typical values. t able 2. p in c haracteristics symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf c pd power dissipation capacitance (per output) 6pf r pullup input pullup resistor 51 k r pulldown input pulldown resistor 51 k r out output impedance 18 28 t able 3a. c lock s elect f unction t able t able 3b. c lock i nput f unction t able control input clock clk_sel pclk, npclk lvcmos_clk 0 selected de-selected 1 de-selected selected inputs outputs input to output mode polarity clk_sel lvcmos_clk pclk npclk q0:q17 0 0 1 low differential to single ended non inverting 0 1 0 high differential to single ended non inverting 0 0 biased; note 1 low single ended to single ended non inverting 0 1 biased; note 1 high single ended to single ended non inverting 0 biased; note 1 0 high single ended to single ended inverting 0 biased; note 1 1 low single ended to single ended inverting 1 0 low single ended to single ended non inverting 1 1 high single ended to single ended non inverting note 1: please refer to the application information section, ?iring the differential input to accept single ended levels?
revision b 3/25/15 83940D data sheet 3 low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer a bsolute m aximum r atings supply voltage, v dd 3.6v inputs, v i -0.3v to v dd + 0.3v outputs, v o -0.3v to v ddo + 0.3v input current, i in ?0ma storage temperature, t stg -40? to 125? note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress speci cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac charac- teristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer 83940D data sheet 4 revision b 3/25/15 t able 4a. dc c haracteristics , v dd = v ddo = 3.3v ?5%, t a = 0? to 70 symbol parameter test conditions minimum typical maximum units v ih input high voltage lvcmos_clk 2.4 v dd v v il input low voltage lvcmos_clk 0.8 v v pp peak-to-peak input voltage pclk, npclk 500 1000 mv v cmr input common mode voltage; note 1, 2 pclk, npclk v dd - 1.4 v dd - 0.6 v i in input current ?00 ? v oh output high voltage i oh = -20ma 2.4 v v ol output low voltage i ol = 20ma 0.5 v i dd core supply current 25 ma note 1: for single ended applications, the maximum input voltage for pclk, npclk is v dd + 0.3v. note 2: common mode voltage is de ned as v ih . t able 5a. ac c haracteristics , v dd = v ddo = 3.3v ?5%, t a = 0? to 70 symbol parameter test conditions minimum typical maximum units f max output frequency 250 mhz t plh propagation delay pclk, npclk; note 1, 5 f 150mhz 1.6 3.0 ns lvcmos_clk; note 2, 5 f 150mhz 1.8 3.0 ns t plh propagation delay pclk, npclk; note 1, 5 f > 150mhz 1.6 3.3 ns lvcmos_clk; note 2, 5 f > 150mhz 1.8 3.2 ns tsk(o) output skew; note 3, 5 pclk, npclk measured on rising edge @v ddo /2 150 ps lvcmos_clk 150 ps tsk(pp) part-to-part skew; note 6 pclk, npclk f 150mhz 1.4 ns lvcmos_clk f 150mhz 1.2 ns tsk(pp) part-to-part skew; note 6 pclk, npclk f > 150mhz 1.7 ns lvcmos_clk f > 150mhz 1.4 ns tsk(pp) part-to-part skew; note 4, 5 pclk, npclk measured on rising edge @v ddo /2 850 ps lvcmos_clk 750 ps tjit buffer additive phase jitter, rms; refer to additive phase jitter section, note 7 0.03 ps t r / t f output rise/fall time 0.5 to 2.4v 0.3 1.1 ns odc output duty cycle f < 134mhz 45 50 55 % 134mhz f 250mhz 40 50 60 % all parameters measured at 200mhz unless noted otherwise. note 1: measured from the differential input crossing point to the output v ddo /2. note 2: measured from v dd /2 to v ddo /2. note 3: de ned as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddo /2. note 4: de ned as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. using the same type of inputs on each device, the outputs are measured at v ddo /2. note 5: this parameter is de ned in accordance with jedec standard 65. note 6: de ned as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. using the same type of inputs on each device, the outputs are measured at v ddo /2. note 7: driving only one input clock.
revision b 3/25/15 83940D data sheet 5 low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer t able 4b. dc c haracteristics , v dd = 3.3v ?5%, v ddo = 2.5v ?5%, t a = 0? to 70 t able 5b. ac c haracteristics , v dd = 3.3v ?5%, v ddo = 2.5v ?5%, t a = 0? to 70 symbol parameter test conditions minimum typical maximum units v ih input high voltage lvcmos_clk 2.4 v dd v v il input low voltage lvcmos_clk 0.8 v v pp peak-to-peak input voltage pclk, npclk 300 1000 mv v cmr input common mode voltage; note 1, 2 pclk, npclk v dd - 1.4 v dd - 0.6 v i in input current ?00 ? v oh output high voltage i oh = -20ma 1.8 v v ol output low voltage i ol = 20ma 0.5 v i dd core supply current 25 ma note 1: for single ended applications, the maximum input voltage for pclk, npclk is v dd + 0.3v. note 2: common mode voltage is de ned as v ih . symbol parameter test conditions minimum typical maximum units f max output frequency 250 mhz t plh propagation delay pclk, npclk; note 1, 5 f 150mhz 1.7 3.2 ns lvcmos_clk; note 2, 5 f 150mhz 1.7 3.0 ns t plh propagation delay pclk, npclk; note 1, 5 f > 150mhz 1.6 3.4 ns lvcmos_clk; note 2, 5 f > 150mhz 1.8 3.3 ns tsk(o) output skew; note 3, 5 pclk, npclk measured on rising edge @v ddo /2 150 ps lvcmos_clk 150 ps tsk(pp) part-to-part skew; note 6 pclk, npclk f 150mhz 1.5 ns lvcmos_clk f 150mhz 1.3 ns tsk(pp) part-to-part skew; note 6 pclk, npclk f > 150mhz 1.8 ns lvcmos_clk f > 150mhz 1.5 ns tsk(pp) part-to-part skew; note 4, 5 pclk, npclk measured on rising edge @v ddo /2 850 ps lvcmos_clk 750 ps tjit buffer additive phase jitter, rms; refer to additive phase jitter section, note 7 0.03 ps t r / t f output rise/fall time 0.5 to 1.8v 0.3 1.2 ns odc output duty cycle f < 134mhz 45 50 55 % all parameters measured at 200mhz unless noted otherwise. note 1: measured from the differential input crossing point to the output v ddo /2. note 2: measured from v dd /2 to v ddo /2. note 3: de ned as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddo /2. note 4: de ned as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. using the same type of inputs on each device, the outputs are measured at v ddo /2. note 5: this parameter is de ned in accordance with jedec standard 65. note 6: de ned as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. using the same type of inputs on each device, the outputs are measured at v ddo /2. note 7: driving only one input clock.
low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer 83940D data sheet 6 revision b 3/25/15 t able 4c. dc c haracteristics , v dd = v ddo = 2.5v?%, t a = 0? to 70 symbol parameter test conditions minimum typical maximum units v ih input high voltage lvcmos_clk 2 v dd v v il input low voltage lvcmos_clk 0.8 v v pp peak-to-peak input voltage pclk, npclk 300 1000 mv v cmr input common mode voltage; note 1, 2 pclk, npclk v dd - 1.4 v dd - 0.6 v i in input current ?00 ? v oh output high voltage i oh = -12ma 1.8 v v ol output low voltage i ol = 12ma 0.5 v i dd core supply current 25 ma note 1: for single ended applications, the maximum input voltage for pclk, npclk is v dd + 0.3v. note 2: common mode voltage is de ned as v ih . t able 5c. ac c haracteristics , v dd = v ddo = 2.5v?%, t a = 0? to 70 symbol parameter test conditions minimum typical maximum units f max output frequency 200 mhz t plh propagation delay; pclk, npclk; note 1, 5 f 150mhz 1.2 3.8 ns lvcmos_clk; note 2, 5 f 150mhz 1.5 3.2 ns t plh propagation delay; pclk, npclk; note 1, 5 f > 150mhz 1.5 3.7 ns lvcmos_clk; note 2, 5 f > 150mhz 2 3.6 ns tsk(o) output skew; note 3, 5 pclk, npclk measured on rising edge @v ddo /2 200 ps lvcmos_clk 200 ps tsk(pp) part-to-part skew; note 6 pclk, npclk f 150mhz 2.6 ns lvcmos_clk f 150mhz 1.7 ns tsk(pp) part-to-part skew; note 6 pclk, npclk f > 150mhz 2.2 ns lvcmos_clk f > 150mhz 1.7 ns tsk(pp) part-to-part skew; note 4, 5 pclk, npclk measured on rising edge @v ddo /2 1.2 ns lvcmos_clk 1.0 ns tjit buffer additive phase jitter, rms; refer to additive phase jitter section, note 7 0.03 ps t r / t f output rise/fall time 0.5 to 1.8v 0.3 1.2 ns odc output duty cycle f < 134mhz 45 55 % all parameters measured at 200mhz unless noted otherwise. note 1: measured from the differential input crossing point to the output v ddo /2. note 2: measured from v dd /2 to v ddo /2. note 3: de ned as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddo /2. note 4: de ned as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. using the same type of inputs on each device, the outputs are measured at v ddo /2. note 5: this parameter is de ned in accordance with jedec standard 65. note 6: de ned as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. using the same type of inputs on each device, the outputs are measured at v ddo /2. note 7 driving only one input clock.
revision b 3/25/15 83940D data sheet 7 low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer a dditive p hase j itter input/output additive phase jitter at 155.52mhz = 0.03ps (typical) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1m 10m 100m the spectral purity in a band at a speci c offset from the fun- damental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the speci ed plot in many applications. phase noise is de ned as the ratio of the noise power present in a 1hz band at a speci ed offset from the fun- damental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the as with most timing speci cations, phase noise measurements have issues. the primary issue relates to the limitations of the equipment. often the noise oor of the equipment is higher than the noise oor of the device. this is illustrated above. the 1hz band to the power in the fundamental. when the required offset is speci ed, the phase noise is called a dbc value, which simply means dbm at a speci ed offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. device meets the noise oor of what is shown, but can actually be lower. the phase noise is dependant on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z
low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer 83940D data sheet 8 revision b 3/25/15 p arameter m easurement i nformation 2.5v o utput l oad ac t est c ircuit 3.3v c ore /2.5v o utput l oad ac t est c ircuit 3.3v c ore /3.3v o utput l oad ac t est c ircuit d ifferential i nput l evel p art - to -p art s kew o utput s kew
revision b 3/25/15 83940D data sheet 9 low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer p ropagation d elay 3.3v o utput r ise /f all t ime 2.5v o utput r ise /f all t ime
low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer 83940D data sheet 10 revision b 3/25/15 a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609.
revision b 3/25/15 83940D data sheet 11 low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer lvpecl c lock i nput i nterface the pclk /npclk accepts lvpecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2f show interface ex- amples for the pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to con rm the driver termination requirements. f igure 2a. pclk/npclk i nput d riven by an o pen c ollector cml d river f igure 2b. pclk/npclk i nput d riven by a b uilt -i n p ullup cml d river f igure 2c. pclk/npclk i nput d riven by a 3.3v lvpecl d river f igure 2f. pclk/npclk i nput d riven by a 3.3v lvds d river pclk/npclk 2.5v zo = 60 ohm sstl hiperclocks pclk npclk r2 120 3.3v r3 120 zo = 60 ohm r1 120 r4 120 2.5v f igure 2e. pclk/npclk i nput d riven by an sstl d river hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm 3.3v hiperclocks pclk npclk r2 84 r3 125 input zo = 50 ohm r4 125 r1 84 lvpecl 3.3v 3.3v zo = 50 ohm c2 r2 1k r5 100 zo = 50 ohm 3.3v 3.3v c1 r3 1k lvds r4 1k hiperclocks pclk npclk r1 1k zo = 50 ohm 3.3v pclk/npclk 3.3v r5 100 - 200 3.3v 3.3v hiperclocks pclk npclk r1 125 pclk/npclk r2 125 r3 84 c1 c2 zo = 50 ohm r4 84 zo = 50 ohm r6 100 - 200 3.3v lvpecl f igure 2d. pclk/npclk i nput d riven by a 3.3v lvpecl d river with ac c ouple
low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer 83940D data sheet 12 revision b 3/25/15 r eliability i nformation t ransistor c ount the transistor count for 83940D is: 820 t able 6. ja vs . a ir f low t able for 32 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8?/w 55.9?/w 50.1?/w multi-layer pcb, jedec standard test boards 47.9?/w 42.1?/w 39.4?/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
revision b 3/25/15 83940D data sheet 13 low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer p ackage o utline - y s uffix for 32 l ead lqfp t able 7. p ackage d imensions jedec variation all dimensions in millimeters symbol bba minimum nominal maximum n 32 a -- -- 1.60 a1 0.05 -- 0.15 a2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 d 9.00 basic d1 7.00 basic d2 5.60 ref. e 9.00 basic e1 7.00 basic e2 5.60 ref. e 0.80 basic l 0.45 0.60 0.75 0 -- 7 ccc -- -- 0.10 reference document: jedec publication 95, ms-026
low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer 83940D data sheet 14 revision b 3/25/15 t able 8. o rdering i nformation part/order number marking package shipping pack- aging temperature 83940Dylf ics83940Dylf 32 lead ?ead free lqfp tray 0? to 70? 83940Dylft ics83940Dylf 32 lead ?ead free lqfp tape and reel 0? to 70?
revision b 3/25/15 83940D data sheet 15 low skew, 1-to-18 lvpecl-to-lvcmos / lvttl fanout buffer revision history sheet rev table page description of change date a t5a t5b t5c 4 5 6 3.3v ac characteristics table - ? tsk(pp) test conditions, replaced ? with ? ? corrected units to ?s from ?s? ? odc - corrected test conditions to read ?34mhz f 250mhz? from ? 250mhz? 3.3v/2.5v ac characteristics table - tsk(pp) test conditions, replaced ? with ? ? corrected units to read ?s from ?s? 2.5v ac characteristics table - tsk(pp) test conditions, replaced ? with ? ? corrected units to ?s?from ?s? 10/11/02 at2 2 7 pin characteristics table - changed r out 25 maximum to 28 maximum. delete r pullup row. 3.3v output load ac test circuit diagram - corrected gnd equation to read -1.65v... from -1.165v... added lvttl to title. updated format. 12/12/02 b t1 t2 t5a t5b t5c 2 2 4 5 6 7 10 11 pin description table - added pullup and pulldown to pin 6, npclk. pin characteristics table - added r pullup row. added tjit row. added tjit row. added tjit row. added additive phase jitter section. updated single ended signal driving differential input diagram. added lvpecl clock interface section. 10/9/03 b t5a - t5c 1 4 - 6 11 14 added ?ead-free?bullet to features section. added note 7. updated lvpecl clock input interface section. ordering information table - added ?ead-free?part number. 6/15/04 b t8 14 16 updated datasheet? header/footer with idt from ics. removed ics pre x from part/order number column. added contact page. 8/9/10 b t8 14 ordering information - removed leaded devices. updated data sheet format. 3/25/15
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