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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, pl ease contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maxim-ic.com. dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 19-5122; rev 2; 11/10 ordering information functional diagram general description the max5392 dual, 256-tap, volatile, low-voltage, lin- ear taper digital potentiometer offers three end-to-end resistance values of 10k i , 50k i , and 100k i . operating from a single +1.7v to +5.5v power supply, the device provides a low 35ppm/ n c end-to-end temperature coef- ficient. the device features an i 2 c interface. the small package size, low supply operating voltage, low supply current, and automotive temperature range of the max5392 makes the device uniquely suited for the portable consumer market, battery-backup industrial applications, and the automotive market. the max5392 is specified over the automotive -40 n c to +125 n c temperature range and is available in a 16-pin tssop package. applications low-voltage battery applications portable electronics mechanical potentiometer replacement offset and gain control adjustable voltage references/linear regulators automotive electronics features s dual, 256-tap linear taper positions s single +1.7v to +5.5v supply operation s low 12 a quiescent supply current s 10k i , 50k i , 100k i end-to-end resistance values s i 2 c-compatible interface s wiper set to midscale on power-up s -40 n c to +125 n c operating temperature range note: all devices are specified over the -40 c to +125 n c oper- ating temperature range. + denotes a lead(pb)-free/rohs-compliant package. evaluation kit available part pin-package end-to-end resistance (k i ) max5392laue+ 16 tssop 10 max5392maue+ 16 tssop 50 MAX5392NAUE+ 16 tssop 100 latch i 2 c charge pump byp gnd v dd 256 decoder 256 decoder wa ha la hbwb lb latch por scl sda a0 a1 a2 max5392 downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 2 ______________________________________________________________________________________ stresses beyond those listed under ?absolute maximu m ratings? may cause permanent damage to the device . these are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of the specifications is not implied. exposur e to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ...........................................................-0.3v to +6v h_, w_, l_ to gnd ......................................-0.3v to the lower of (v dd + 0.3v) and +6v all other pins to gnd .............................................-0.3v to +6v continuous current in to h_, w_, and l_ max5392l ..................................................................... q 5ma max5392m .................................................................... q 2ma max5392n ..................................................................... q 1ma continuous power dissipation (t a = +70 n c) 16-pin tssop (derate 11.1mw/ n c above +70 n c) ...888.9mw operating temperature range ....................... -40 n c to +125 n c junction temperature ....................................................+150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................+300 n c soldering temperature (reflow) ......................................+260 n c electrical characteristics (v dd = +1.7v to +5.5v, v h_ = v dd , v l_ = 0, t a = t min to t max , unless otherwise noted. typical values are at v dd = +1.8v, t a = +25 n c.) (note 1) absolute maximum ratings parameter symbol conditions min typ max units resolution n 256 tap dc performance (voltage divider mode) integral nonlinearity inl (note 2) -0.5 +0.5 lsb differential nonlinearity dnl (note 2) -0.5 +0.5 lsb dual code matching register a = register b -0.5 +0.5 lsb ratiometric resistor tempco ( d v w /v w )/ d t, no load 5 ppm/ n c full-scale error code = ffh max5392l -3 -2.2 lsb max5392m -1 -0.6 max5392n -0.5 -0.3 zero-scale error code = 00h max5392l 2.2 3 lsb max5392m 0.6 1.0 max5392n 0.3 0.5 dc performance (variable resistor mode) integral nonlinearity r-inl max5392l (note 3) -1.5 +1.5 lsb max5392m (note 3) -0.75 +0.75 max5392n (note 3) -0.5 +0.5 differential nonlinearity r-dnl (note 3) -0.5 +0.5 lsb dc performance (resistor characteristics) wiper resistance r wl (note 4) 200 i terminal capacitance c h _, c l_ measured to gnd 10 pf wiper capacitance c w _ measured to gnd 50 pf end-to-end resistor tempco tc r no load 35 ppm/ n c end-to-end resistor tolerance d r hl wiper not connected -25 +25 % downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +1.7v to +5.5v, v h_ = v dd , v l_ = 0, t a = t min to t max , unless otherwise noted. typical values are at v dd = +1.8v, t a = +25 n c.) (note 1) parameter symbol conditions min typ max units ac performance crosstalk (note 5) -90 db -3db bandwidth bw code = 80h, 10pf load, v dd = 1.8v max5392l 600 khz max5392m 100 max5392n 50 total harmonic distortion plus noise thd+n measured at w, v h_ = 1v rms at 1khz 0.02 % wiper settling time t s (note 6) max5392l 400 ns max5392m 1200 max5392n 2200 charge-pump feedthrough at w_ v rw f clk = 600khz, c byp = 0nf 600 nv p-p power supplies supply voltage range v dd 1.7 5.5 v standby current v dd = 5.5v 27 f a v dd = 1.7v 12 digital inputs minimum input high voltage v ih v dd = 2.6v to 5.5v 70 % x v dd v dd = 1.7v to 2.6v 75 maximum input low voltage v il v dd = 2.6v to 5.5v 30 % x v dd v dd = 1.7v to 2.6v 25 input leakage current -1 +1 f a input capacitance 5 pf timing characteristics?i 2 c (notes 7 and 8) maximum scl frequency f scl 400 khz setup time for start condition t su:sta 0.6 f s hold time for start condition t hd:sta 0.6 f s scl high time t high 0.6 f s scl low time t low 1.3 f s downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 4 ______________________________________________________________________________________ figure 1. voltage-divider and variable resistor configurations electrical characteristics (continued) (v dd = +1.7v to +5.5v, v h_ = v dd , v l_ = 0, t a = t min to t max , unless otherwise noted. typical values are at v dd = +1.8v, t a = +25 n c.) (note 1) note 1: all devices are 100% production tested at t a = +25 n c. specifications over temperature limits are guaranteed by design and characterization. note 2: dnl and inl are measured with the potentiometer configured as a voltage-divider (figure 1) with h_ = v dd and l_ = gnd. the wiper terminal is unloaded and measured with a high-input-impedance voltmeter. note 3: r-dnl and r-inl are measured with the potentiometer configured as a variable resistor (figure 1). dnl and inl are mea- sured with the potentiometer configured as a variable resistor. h_ is unconnected and l_ = gnd. for v dd = +5v, the wiper terminal is driven with a source current of 400 f a for the 10k i configuration, 80 f a for the 50k i configuration, and 40 f a for the 100k i configuration. for v dd = +1.7v, the wiper terminal is driven with a source current of 150 f a for the 10k i configu- ration, 30 f a for the 50k i configuration, and 15 f a for the 100k i configuration. note 4: the wiper resistance is the worst value measured by injecting the currents given in note 3 to w_ with l_ = gnd. r w_ = (v w_ - v h_ )/i w_ . note 5: drive ha with a 1khz gnd to v dd amplitude tone. la = lb = gnd. no load. wb is at midscale with a 10pf load. measure wb. note 6: the wiper-settling time is the worst-case 0 to 50% rise time, measured between tap 0 and tap 127. h_ = v dd , l_ = gnd, and the wiper terminal is loaded with 10pf capacitance to ground. note 7: digital timing is guaranteed by design and characterization, not production tested. note 8: the scl clock period includes rise and fall times (t r = t f ). all digital input signals are specified with t r = t f = 2ns and timed from a voltage level of (v il + v ih )/2. note 9: an appropriate bus pullup resistance must be selected depending on board capacitance. for i 2 c-bus specification infor- mation from nxp semiconductor (formerly philips semiconductor), refer to the um10204: i 2 c-bus specification and user manual. h l w w n.c. l parameter symbol conditions min typ max units data setup time t su:dat 100 ns data hold time t hd:dat 0 f s sda, scl rise time t r 0.3 f s sda, scl fall t f 0.3 f s setup time for stop condition t su:sto 0.6 f s bus free time between stop and start condition t buf minimum power-up rate = 0.2v/ f s 1.3 f s pulse suppressed spike width t sp 50 ns capacitive load for each bus c b (note 9) 400 pf downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 _______________________________________________________________________________________ 5 typical operating characteristics (v dd = 1.8v, t a = +25c, unless otherwise noted.) supply current vs. temperature max5392 toc01 temperature (c) supply current (a) 110 95 80 65 50 35 20 5 -10 -20 5 10 15 20 25 30 0 -40 125 v dd = 5v v dd = 1.8v v dd = 2.6v supply current vs. digital input voltage max5392 toc02 digital input voltage (v) supply current (a) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 10 100 1000 10,000 1 0 5.0 v dd = 5v v dd = 2.6v v dd = 1.8v supply current vs. supply voltage max5392 toc03 v dd (v) i dd (a) 5.2 4.7 4.2 3.7 3.2 2.7 2.2 15 20 25 30 10 1.7 resistance (w_-to-l_) vs. tap position (10k i ) max5392 toc04 tap position w_-to-l_ resistance (k i ) 1 2 3 4 5 6 7 8 9 10 0 204 153 102 51 0 255 resistance (w_-to-l_) vs. tap position (50k i ) max5392 toc05 tap position w_-to-l_ resistance (k i ) 5 10 15 20 25 30 35 40 45 50 0 204 153 102 51 0 255 resistance (w_-to-l_) vs. tap position (100k i ) max5392 toc06 tap position w_-to-l_ resistance (k i ) 10 20 30 40 50 60 70 80 90 100 0 204 153 102 51 0 255 wiper resistance vs. wiper voltage (10k i ) wiper voltage (v) wiper resistance ( i ) 0.5 80 100 120 140 60 0 1.0 max5392 toc07 v dd = 5v v dd = 2.6v v dd = 1.8v 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 end-to-end resistance percentage change vs. temperature max5392 toc08 temperature (c) end-to-end resistance % change 110 95 -25 -10 5 35 50 65 20 80 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 100k i 10k i 50k i -0.03 -40 125 variable resistor dnl vs. tap position (10k i ) max5392 toc09 tap position dnl (lsb) 204 153 102 51 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 -0.10 0 255 i wiper = 150a downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 6 ______________________________________________________________________________________ typical operating characteristics (continued) (v dd = 1.8v, t a = +25c, unless otherwise noted.) variable resistor dnl vs. tap position (50k i ) max5392 toc10 tap position dnl (lsb) 204 153 102 51 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 -0.10 0 255 i wiper = 30a variable resistor dnl vs. tap position (100k i ) max5392 toc11 tap position dnl (lsb) 204 153 102 51 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 -0.10 0 255 i wiper = 15a variable resistor inl vs. tap position (10k i ) max5392 toc12 tap position inl (lsb) 204 153 102 51 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 255 i wiper = 150a variable resistor inl vs. tap position (50k i ) max5392 toc13 tap position inl (lsb) 204 153 102 51 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 255 i wiper = 30a variable resistor inl vs. tap position (100k i ) max5392 toc14 tap position inl (lsb) 204 153 102 51 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 255 i wiper = 15a voltage-divider dnl vs. tap position (10k i ) max5392 toc15 tap position dnl (lsb) 204 153 102 51 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 -0.10 0 255 voltage-divider dnl vs. tap position (50k i ) max5392 toc16 tap position dnl (lsb) 204 153 102 51 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 -0.10 0 255 voltage-divider dnl vs. tap position (100k i ) max5392 toc17 tap position dnl (lsb) 204 153 102 51 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 -0.10 0 255 voltage-divider inl vs. tap position (10k i ) max5392 toc18 tap position inl (lsb) 204 153 102 51 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 255 downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v dd = 1.8v, t a = +25c, unless otherwise noted.) voltage-divider inl vs. tap position (100k i ) max5392 toc20 tap position inl (lsb) 204 153 102 51 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 255 voltage-divider inl vs. tap position (50k i ) max5392 toc19 tap position inl (lsb) 204 153 102 51 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 255 tap-to-tap switching transient (code 127 to 128) 10k i max5392 toc21 v w_-l_ 20mv/divscl 5v/div 400ns/div v dd = 5v tap-to-tap switching transient (code 127 to 128) 100k i max5392 toc23 v w_-l_ 20mv/divscl 5v/div 1 s/div v dd = 5v tap-to-tap switching transient (code 127 to 128) 50k i max5392 toc22 v w_-l_ 20mv/divscl 5v/div 1s/div v dd = 5v p0wer-on transient (50k i ) max5392 toc24 v w_-l_ 1v/divv cc 5v/div 2 s/div downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 8 ______________________________________________________________________________________ typical operating characteristics (continued) (v dd = 1.8v, t a = +25c, unless otherwise noted.) crosstalk vs. frequency max5392 toc28 frequency (khz) crosstalk (db) 100 10 1 0.1 -120 -100 -80 -60 -40 -20 0 -140 0.01 1000 100k i 50k i 10k i charge-pump feedthrough at w_ vs. c byp max5392 toc31 capacitance (pf) voltage (nv rms ) 600 400 200 100 200 300 400 500 600 700 0 0 800 byp ramp time vs. c byp max5392 toc30 byp capacitance (f) ramp time (ms) 0.08 0.05 0.04 0.02 20 40 60 80 100 120 0 0 0.10 total harmonic distortion plus noise vs. frequency max5392 toc29 frequency (khz) thd+n (%) 10 1 0.1 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0 0.01 100 10k i 50k i 100k i charge-pump feedthrough at w_ vs. frequency max5392 toc32 frequency (khz) amplitude (v rms ) 800 700 600 500 400 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 300 900 midscale frequency response (10k i ) frequency (khz) gain (db) 1000 100 10 1 0.1 -20 -10 0 10 -30 0.01 10,000 max5392 toc25 v dd = 1.8v v dd = 5v v in = 1v p-p c w = 10pf midscale frequency response (50k i ) frequency (khz) gain (db) 1000 100 10 1 0.1 -20 -10 0 10 -30 0.01 10,000 max5392 toc26 v dd = 1.8v v dd = 5v v in = 1v p-p c w = 10pf midscale frequency response (100k i ) frequency (khz) gain (db) 1000 100 10 1 0.1 -20 -10 0 10 -30 0.01 10,000 max5392 toc27 v dd = 1.8v v dd = 5v v in = 1v p-p c w = 10pf downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 _______________________________________________________________________________________ 9 pin description pin configuration 1615 14 13 12 11 10 1 23 45 6 7 v dd n.c.scl sda hb la wa ha top view max5392 a0 a1 a2 byp lb 9 8 gnd i.c. wb + tssop pin name function 1 ha resistor a high terminal. the voltage at ha can be higher or lower than the voltage at la. current can flow into or out of ha. 2 wa resistor a wiper terminal 3 la resistor a low terminal. the voltage at la can be higher or lower than the voltage at ha. current can flow into or out of la. 4 hb resistor b high terminal. the voltage at hb can be higher or lower than the voltage at lb. current can flow into or out of hb. 5 wb resistor b wiper terminal 6 lb resistor b low terminal. the voltage at lb can be higher or lower than the voltage at hb. current can flow into or out of lb. 7 byp internal power-supply bypass. for additional charge-pump filtering, bypass to gnd with a capaci- tor close to the device. 8 i.c. internally connected. connect to gnd. 9 gnd ground 10 a2 address input 2. connect to v dd or gnd. 11 a1 address input 1. connect to v dd or gnd. 12 a0 address input 0. connect to v dd or gnd. 13 sda i 2 c-compatible serial-data input/output. a pullup resistor is required. 14 scl i 2 c-compatible serial-clock input. a pullup resistor is required. 15 n.c. no connection. not internally connected. 16 v dd power-supply input. bypass v dd to gnd with a 0.1 f f capacitor close to the device. downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 10 _____________________________________________________________________________________ detailed description the max5392 dual, 256-tap, volatile, low-voltage linear taper digital potentiometer offers three end-to-end resis- tance values of 10k i , 50k i , and 100k i . the potenti- ometer consists of 255 fixed resistors in series between terminals h_ and l_. the potentiometer wiper, w_, is programmable to access any one of the 256 tap points on the resistor string. the potentiometers are programmable independently of each other. the max5392 features an i 2 c interface. charge pump tthe max5392 contains an internal charge pump that guarantees the maximum wiper resistance, r wl , to be less than 200 for supply voltages down to 1.7v. pins h_, w_, and l_ are still required to be less than v dd + 0.3v. a bypass input, byp, is provided to allow addi- tional filtering of the charge-pump output, further reduc- ing clock feedthrough that can occur on h_, w_, or l_. the nominal clock rate of the charge pump is 600khz. byp should remain resistively unloaded as any addi- tional load would increase clock feedthrough. see the charge-pump feedthrough at w_ vs. c byp graph in the typical operating characteristics for c byp sizing guide- lines with respect to clock feedthrough to the wiper. the value of c byp does affect the startup time of the charge pump; however, c byp does not impact the ability to communicate with the device, nor is there a minimum c byp requirement. the maximum wiper impedance specification is not guaranteed until the charge pump is fully settled. see the byp ramp time vs. c byp graph in the typical operating characteristics for c byp impact on charge-pump settling time. i 2 c digital interface the i 2 c interface contains a shift register that decodes the command and address bytes, routing the data to the appropriate control registers. data written to a control register immediately updates the wiper position. the wipers a and b power up in midposition, d[7:0] = 80h. serial addressing the max5392 operates as a slave device that receives data through an i 2 c/smbus k -compatible 2-wire serial interface. the interface uses a serial-data access line (sda) and a serial-clock line (scl) to achieve bidirec- tional communication between master(s) and slave(s). a master, typically a microcontroller, initiates all data transfers to the port and generates the scl clock that synchronizes the data transfer. see figure 2. connect a pullup resistor, typically 4.7k i , between each of the sda and scl lines to a voltage between v dd and 5.5v. smbus is a trademark of intel corp. figure 2. i 2 c serial-interface timing diagram sdascl start condition (s) t low t buf t high t hd:sta t hd:sta t su:dat t r t f t su:std repeatd start condition (sr) acknowledge (a) stop condition (p) start condition (s) t hd:dat t su:dta downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 ______________________________________________________________________________________ 11 figure 3. start and stop conditions figure 4. slave address figure 5. bit transfer each transmission consists of a start (s) condition sent by a master, followed by a 7-bit slave address plus a nop/ w bit. see figures 3, 4, and 7. start and stop conditions scl and sda remain high when the interface is inactive. a master controller signals the beginning of a transmis- sion with a start condition by transitioning sda from high to low while scl is high. the master controller issues a stop condition by transitioning the sda from low to high while scl is high, after finishing communi- cating with the slave. the bus is then free for another transmission. see figure 2. bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable while scl is high. see figure 5. acknowledge the acknowledge bit is a clocked 9th bit that the recipi- ent uses to handshake receipt of each byte of data. see figure 6. each byte transferred requires a total of 9 bits. the master controller generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse, so the sda line remains stable low during the high period of the clock pulse. p stop condition s start condition sda scl lsb msb start sdascl 0 1 0 1 a2 a1 a0 ack nop/w sdascl data stable, data valid change of data allowed downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 12 _____________________________________________________________________________________ slave address the max5392 includes a 7-bit slave address (figure 4). the 8th bit following the 7th bit of the slave address is the nop/ w bit. set the nop/ w bit low for a write command and high for a no-operation command. the device does not support readback. the device provides three address inputs (a0, a1, and a2), allowing up to eight devices to share a common bus (table 1). the first 4 bits (msbs) of the factory-set slave addresses are always 0101. a2, a1, and a0 set the next 3 bits of the slave address. connect each address input to v dd or gnd. each device must have a unique address to share a common bus. message format for writing write to the devices by transmitting the device?s slave address with nop/ w (8th bit) set to zero, followed by at least 2 bytes of information. the first byte of informa- tion is the command byte. the second byte is the data byte. the data byte goes into the internal register of the device as selected by the command byte (figure 7 and table 2). table 1. slave addresses figure 6. acknowledge figure 7. command and single data byte received 9 8 2 1 start condition sclsda clock pulse for acknowledgment not acknowledge acknowledge address inputs slave address a2 a1 a0 gnd gnd gnd 0101000 gnd gnd v dd 0101001 gnd v dd gnd 0101010 gnd v dd v dd 0101011 v dd gnd gnd 0101100 v dd gnd v dd 0101101 v dd v dd gnd 0101110 v dd v dd v dd 0101111 s 0 a a a p acknowledge nop/w how control byte and data byte map into device registers acknowledge d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 slave address command byte 1 data byte downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 ______________________________________________________________________________________ 13 command byte use the command byte to select the destination of the wiper data. see table 2. command descriptions reg a: the data byte writes to register a and the wiper of potentiometer a moves to the appropriate position. d[7:0] indicates the position of the wiper. d[7:0] = 00h moves the wiper to the position closest to la. d[7: 0] = ffh moves the wiper closest to ha. d[7:0] is 80h following power-on. reg b: the data byte writes to register b and the wiper of potentiometer b moves to the appropriate position. d[7:0] indicates the position of the wiper. d[7:0] = 00h moves the wiper to the position closest to lb. d[7: 0] = ffh moves the wiper to the position closest to hb. d[7:0] is 80h following power-on. reg a and b: the data byte writes to registers a and b and the wipers of potentiometers a and b move to the appropriate position. d[7:0] indicates the position of the wiper. d[7:0] = 00h moves the wipers to the posi- tion closest to l_. d[7:0] = ffh moves the wipers to the position closest to h_. d[7:0] is 80h following power-on. applications information variable gain amplifier figure 8 shows a potentiometer adjusting the gain of a noninverting amplifier. figure 9 shows a potentiometer adjusting the gain of an inverting amplifier. adjustable dual regulator figure 10 shows an adjustable dual linear regulator using a dual potentiometer as two variable resistors. table 2. i 2 c command byte summary figure 8. variable gain noninverting amplifier figure 9. variable gain inverting amplifier figure 10. adjustable dual linear regulator address byte command byte data byte scl cycle number start (s) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 stop (p) a6 a5 a4 a3 a2 a1 a0 w ack (a) r7 r6 r5 r4 r3 r2 r1 r0 ack (a) d7 d6 d5 d4 d3 d2 d1 d0 ack (a) reg a 0 1 0 1 a2 a1 a0 0 0 0 0 1 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 reg b 0 1 0 1 a2 a1 a0 0 0 0 0 1 0 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 reg a and b 0 1 0 1 a2 a1 a0 0 0 0 0 1 0 0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 v in v out h l w v in v out h l w v out1 v out2 out1out2 set1set2 in v+ l l h h w w max8866 downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 14 _____________________________________________________________________________________ adjustable voltage reference figure 11 shows an adjustable voltage reference circuit using a potentiometer as a voltage-divider. variable gain current to voltage converter figure 12 shows a variable gain current to voltage con- verter using a potentiometer as a variable resistor. lcd bias control figure 13 shows a positive lcd bias control circuit using a potentiometer as a voltage-divider. figure 14 shows a positive lcd bias control circuit using a potentiometer as a variable resistor. programmable filter figure 15 shows a programmable filter using a dual potentiometer. offset voltage adjustment circuit figure 16 shows an offset voltage adjustment circuit using a dual potentiometer. figure 11. adjustable voltage reference figure 12. variable gain i-to-v converter figure 13. positive lcd bias control using a voltage divider figure 14. positive lcd bias control using a variable resistor chip information process: bicmos out in +2.5v v ref gnd l h w max6037 l r1 r2 r3 v out i s h w v out = -i s x ((r3 x (1 + r2/r1)) + r2) l v out h w 1.8v l v out h w 1.8v downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 ______________________________________________________________________________________ 15 figure 15. programmable filter figure 16. offset voltage adjustment circuit package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 tssop u16+2 21-0066 90-0117 v out v in la ha wb lb hb r2 r1 r3 wa v out lb hb wb wa la ha 1.8v downloaded from: http:///
dual, 256-tap, volatile, low-voltage, linear taper digital potentiometer max5392 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 1/10 initial release ? 1 4/10 added soldering temperature in absolute maximum ratings ; corrected code in conditions of -3db bandwidth specification in electrical characteristics 2, 3 2 11/10 changed electrical characteristics heading and corrected figures 9, 12, 14, 15, 16 2, 3, 4, 13, 14, 15 downloaded from: http:///

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