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this is information on a product in full production. november 2014 docid025108 rev 5 1/43 bluenrg bluetooth ? low energy wireless network processor datasheet - production data features ? bluetooth specification v4.0 compliant master and slave single-mode bluetooth low energy network processor ? embedded bluetooth low energy protocol stack: gap, gatt, sm, l2cap, ll, rf-phy ? bluetooth low energy profiles provided separately ? operating supply voltage: from 2.0 to 3.6 v ? 8.2 ma maximum tx current (@0 dbm, 3.0 v) ? down to 1.7 a current consumption with active ble stack ? integrated linear regulator and dc-dc step- down converter ? up to +8 dbm available output power (at antenna connector) ? excellent rf link budget (up to 96 db) ? accurate rssi to allow power control ? proprietary application controller interface (aci), spi based, allows interfacing with an external host application microcontroller ? full link controller and host security ? high performance, ultra-low power cortex-m0 32-bit based architecture core ? on-chip non-volatile flash memory ? aes security co-processor ? low power modes ? 16 or 32 mhz crystal oscillator ? 12 mhz ring oscillator ? 32 khz crystal oscillator ? 32 khz ring oscillator ? battery voltage monitor and temperature sensor ? compliant with the following radio frequency regulations: etsi en 300 328, en 300 440, fcc cfr47 part 15, arib std-t66 ? available in qfn32 (5 x 5 mm) and wlcsp34 (2.66 x 2.56 mm) packages ? operating temperature range: -40 c to 85 c applications ? watches ? fitness, wellness and sports ? consumer medical ? security/proximity ? remote control ? home and industrial automation ? assisted living ? mobile phone peripherals ? pc peripherals qfn32 wlcsp34 table 1. device summary order code package packing bluenrgqtr qfn32 (5 x 5 mm) tape and reel BLUENRGCSP wlcsp34 (2.66 x 2.56 mm) tape and reel www.st.com
contents bluenrg 2/43 docid025108 rev 5 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 absolute maximum ratings and thermal data . . . . . . . . . . . . . . . . . . . . 16 6 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 rf general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.3 rf transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.4 rf receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.5 high speed crystal oscillator (hsxosc) characteristics . . . . . . . . . . . . . 23 7.5.1 high speed crystal oscillator (hsxosc) . . . . . . . . . . . . . . . . . . . . . . . . 23 7.6 low speed crystal oscillator (lsxosc) characteristics . . . . . . . . . . . . . . 25 7.7 high speed ring oscillator (hsrosc) characteristics . . . . . . . . . . . . . . . 25 7.8 low speed ring oscillator (lsrosc) characteristics . . . . . . . . . . . . . . . . 25 7.9 n-fractional frequency synthesizer characteristics . . . . . . . . . . . . . . . . . . 25 7.10 auxiliary blocks characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 block diagram and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1 core, memory and peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.2 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.4 bluetooth low energy radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 application controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
docid025108 rev 5 3/43 bluenrg contents 43 11 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12 pcb assembly guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
list of tables bluenrg 4/43 docid025108 rev 5 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. external component list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. rf general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. rf transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. rf receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. high speed crystal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. low speed crystal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. high speed ring oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. low speed ring oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 table 15. n-fractional frequency synthesizer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 16. auxiliary blocks characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 17. spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 18. bluenrg operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 19. bluenrg transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 20. qfn32 (5 x 5 x 1 pitch 0.5 mm) mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 21. wlcsp34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . 39 table 22. flip chip csp (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile recommendation . 40 table 23. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
docid025108 rev 5 5/43 bluenrg list of figures 43 list of figures figure 1. bluenrg application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. bluenrg pinout top view (qfn32). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. bluenrg pinout top view (wlcsp34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. bluenrg pinout bottom view (wlcsp34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. bluenrg application circuit: active dc-dc converter qfn32 package . . . . . . . . . . . . . . . 12 figure 6. bluenrg application circuit: non active dc-dc converter qfn32 package . . . . . . . . . . . 13 figure 7. bluenrg application circuit: active dc-dc converter wlcsp package . . . . . . . . . . . . . . 13 figure 8. bluenrg application circuit: non active dc-dc converter wlcsp package. . . . . . . . . . . 14 figure 9. simplified block diagram of the amplitude regulated oscillator . . . . . . . . . . . . . . . . . . . . . . 24 figure 10. bluenrg block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11. power management strategy using ldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 12. power management strategy using step-down dc-dc converter . . . . . . . . . . . . . . . . . . . 29 figure 13. simplified state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 14. qfn32 (5 x 5 x 1 pitch 0.5 mm) drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 15. wlcsp34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 16. flip chip csp (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile recommendation . 40
description bluenrg 6/43 docid025108 rev 5 1 description the bluenrg is a very low power bluetooth low energy (ble) single-mode network processor, compliant with bluetooth specification v4.0. the bluenrg can act as master or slave. the entire bluetooth low energy stack runs on the embedded cortex m0 core. the non-volatile flash memory allows on-field stack upgrading. the bluenrg allows applications to meet of the tight advisable peak current requirements imposed with the use of standard coin cell batteries. the maximum peak current is only 10 ma at 1 dbm of output power. ultra low-power sleep modes and very short transition times between operating modes allow very low average current consumption, resulting in longer battery life. the bluenrg offers the option of interfacing with external microcontrollers using spi transport layer.
docid025108 rev 5 7/43 bluenrg general description 43 2 general description the bluenrg is a single-mode bluetooth low energy master/slave network processor, compliant with the bluetooth specification v4.0. it integrates a 2.4 ghz rf transceiver and a powerful cortex-m0 microcontroller, on which a complete power-optimized stack for bluetooth single mode protocol runs, providing: ? full master and slave role support ? gap: central, peripheral, observer or broadcaster roles ? att/gatt: client and server ? sm: privacy, authentication and authorization ? l2cap ? link layer: aes-128 encryption and decryption an on-chip non-volatile flash memory allows on-field bluetooth low energy stack upgrade. the bluenrg is equipped with bluetooth low energy profiles in c source code. the device allows applications to meet of the tight advisable peak current requirements imposed with the use of standard coin cell batteries. if the high efficiency embedded dc-dc step-down converter is used, the maximum input current is only 15 ma at the highest output power (+8 dbm). even if the dc-dc converter is not used, the maximum input current is only 29 ma at the highest output power, still preserving battery life. ultra low-power sleep modes and very short transition time between operating modes result in very low average current consumption during real operating conditions, providing very long battery life. two different external matching networks are suggested: standard mode (tx output power up to +5 dbm) and high power mode (tx output power up to +8 dbm). the external host application processor, where the application resides, is interfaced with the bluenrg through an application controller interface protocol which is based on a standard spi interface.
general description bluenrg 8/43 docid025108 rev 5 figure 1. bluenrg application block diagram application controller interface bluetooth low energy stack 2.4ghz radio bluenrg-n application bluetooth low energy profiles application controller interface application processor spi am17561v1
docid025108 rev 5 9/43 bluenrg pin description 43 3 pin description the bluenrg pinout is shown in figure 2 , figure 3 and figure 4 . in table 2 a short description of the pins is provided. figure 2. bluenrg pinout top view (qfn32) figure 3. bluenrg pinout top view (wlcsp34) note: top view (balls are underneath). spi_mosi spi_clk test1 vbat3 test2 test3 spi_irq test4 fxtal1 fxtal0 test6 test7 vdd1v8 test5 test9 test11 test12 test8 rf0 sxtal1 spi_miso sxtal0 vbat1 resetn smpsfilt1 smpsfilt2 test10 spi_cs vdd1v2 no_smps rf1 vbat2 gnd pad am17562v2 a b c d e f 123456 gams1803141400sg
pin description bluenrg 10/43 docid025108 rev 5 figure 4. bluenrg pinout bottom view (wlcsp34) f e d c b a 123456 gams0203141520sg table 2. pinout description pins name i/o description qfn32 wlcsp 1 e2 spi_mosi i spi_mosi 2 e1 spi_clk i spi_clk 3 d2 spi_irq o spi_irq 4 d1 test1 i/o test pin 5 c1 vbat3 vdd 2.0-3.6 battery voltage input 6 c2 test2 i/o test pin connected to gnd 7 b1 test3 i/o test pin connected to gnd 8 b2 test4 i/o test pin connected to gnd 9 a1 test5 i/o test pin connected to gnd 10 b3 test6 i/o test pin connected to gnd 11 a2 test7 i/o test pin connected to gnd 12 a3 vdd1v8 o 1.8 v digital core 13 a4 test8 i/o test pin not connected 14 a5 test9 i/o test pin not connected 15 b4 test11 i/o test pin not connected (qfn32) test pin connected to gnd (wlcsp) 16 b5 test12 i/o test pin not connected (qfn32) test pin connected to gnd (wlcsp) 17 a6 fxtal1 i 16/32 mhz crystal 18 b6 fxtal0 i 16/32 mhz crystal 19 - vbat2 vdd 2.0-3.6 battery voltage input 20 c6 rf1 i/o antenna + matching circuit 21 d6 rf0 i/o antenna + matching circuit 22 e6 sxtal1 i 32 khz crystal
docid025108 rev 5 11/43 bluenrg pin description 43 23 e5 sxtal0 i 32 khz crystal 24 d5 vbat1 vdd 2.0-3.6 battery voltage input 25 e4 resetn i reset and deep sleep control 26 f6 smpsfilt1 o smps output 27 - no_smps i power management strategy selection 28 f5 smpsfilt2 i/o smps input/output 29 f3 vdd1v2 o 1.2 v digital core 30 e3 test10 i/o test pin connected to gnd 31 f2 spi_cs i spi_cs 32 f1 spi_miso o spi_miso - c3 gnd gnd ground - d3 gnd gnd ground - d4 gnd gnd ground - f4 smps-gnd gnd smps ground table 2. pinout description (continued) pins name i/o description qfn32 wlcsp
application circuits bluenrg 12/43 docid025108 rev 5 4 application circuits the schematics below are purely indicative. for more detailed schematics, please refer to the "reference design" and "layout guidelines" which are provided as separate documents. figure 5. bluenrg application circuit: active dc-dc converter qfn32 package resetn r1 c17 2.0 v to 3.6 v power supply c20 xtal1 c9 c21 c7 c10 c18 c13 c6 c14 c8 c3 c12 c2 u1 gnd pad bluenrg 1 spi_mosi 2 spi_clk 3 spi_irq 4 test1 5 vbat3 6 test2 7 test3 8 test4 9 test5 test6 10 test7 11 12 vdd1v8 test8 13 test9 14 15 test11 16 test12 24 vbat1 23 sxtal0 22 sxtal1 rf0 21 rf1 20 vbat2 19 18 fxtal0 17 fxtal1 32 spi_miso 31 spi_cs 30 test10 29 vdd1v2 28 smpsfilt2 27 no_smps 26 smpsfilt1 25 resetn l2 c11 l1 c15 c5 u2 application mcu spi_mosi spi_clk spi_irq spi_cs spi_miso l3 c19 c1 xtal2 c4 c16 l4
docid025108 rev 5 13/43 bluenrg application circuits 43 figure 6. bluenrg application circuit: non active dc-dc converter qfn32 package figure 7. bluenrg application circuit: active dc-dc converter wlcsp package resetn c11 2.0 v to 3.6 v power supply c17 u2 application mcu spi_mosi spi_clk spi_irq spi_cs spi_miso c18 l2 c21 c19 c15 l3 u1 gnd pad bluenrg 1 spi_mosi 2 spi_clk 3 spi_irq 4 test1 5 vbat3 6 test2 7 test3 8 test4 9 test5 test6 10 test7 11 12 vdd1v8 test8 13 test9 14 15 test11 16 test12 vbat1 24 23 sxtal0 22 sxtal1 rf0 21 rf1 20 vbat2 19 18 fxtal0 17 fxtal1 32 spi_miso 31 spi_cs 30 test10 29 vdd1v2 28 smpsfilt2 27 no_smps 26 smpsfilt1 25 resetn c3 c20 c16 l4 r1 c6 c10 c5 c7 xtal2 c1 c12 c9 c4 xtal1 c13 c14 c8 resetn u2 2.0 v to 3.6 v power supply application mcu spi_mosi spi_clk spi_irq spi_cs spi_miso c18 l1 c21 c19 l2 c15 c3 c20 l3 r1 c2 c6 c16 l4 c5 c7 c10 xtal2 c1 c12 c4 xtal1 c9 c8 c14 c17 u1 bluenrg_wlcsp e2 spi_mosi e1 spi_clk d2 spi_irq test1 d1 vbat3 c1 test2 c2 b1 test3 b2 test4 test5 a1 b3 test6 test7 a2 a3 vdd1v8 test8 a4 a5 test9 b4 test11 b5 test12 vbat1 d5 e5 sxtal0 e6 sxtal1 rf0 d6 rf1 c6 gnd c3 b6 fxtal0 a6 fxtal1 f1 spi_miso f2 spi_cs e3 test10 f3 vdd1v2 f5 smpsfilt2 f4 smps_gnd f6 smpsfilt1 e4 resetn gnd d3 gnd d4 c11
application circuits bluenrg 14/43 docid025108 rev 5 figure 8. bluenrg application circuit: non active dc-dc converter wlcsp package resetn l2 r1 2.0 v to 3.6 v power supply c15 c19 xtal2 c8 c5 l3 c12 c16 c17 l4 c4 c20 c6 c10 c21 c18 u1 bluenrg_wlcsp e2 spi_mosi e1 spi_clk d2 spi_irq d1 test1 c1 vbat3 c2 test2 b1 test3 b2 test4 test5 a1 test6 b3 test7 a2 a3 vdd1v8 a4 test8 test9 a5 b4 test11 b5 test12 d5 vbat1 e5 sxtal0 e6 sxtal1 rf0 d6 rf1 c6 gnd c3 b6 fxtal0 a6 fxtal1 f1 spi_miso f2 spi_cs e3 test10 f3 vdd1v2 f5 smpsfilt2 f4 smps_gnd f6 smpsfilt1 e4 resetn gnd d3 gnd d4 c9 u2 application mcu spi_mosi spi_clk spi_irq spi_cs spi_miso c14 c1 c7 c11 c3 xtal1 table 3. external component list component description c1 decoupling capacitor c2 dc-dc converter output capacitor c3 dc-dc converter output capacitor c4 decoupling capacitor for 1.2 v digital regulator c5 decoupling capacitor for 1.2 v digital regulator c6 decoupling capacitor c7 32 khz crystal loading capacitor (1) c8 32 khz crystal loading capacitor (1) c9 rf balun/matching network capacitor high performance rf balun/matching network capacitor standard mode c10 rf balun/matching network capacitor high performance rf balun/matching network capacitor standard mode c11 rf balun/matching network capacitor high performance rf balun/matching network capacitor standard mode c12 decoupling capacitor c13 decoupling capacitor
docid025108 rev 5 15/43 bluenrg application circuits 43 c14 rf balun/matching network capacitor high performance rf balun/matching network capacitor standard mode c15 rf balun/matching network capacitor high performance rf balun/matching network capacitor standard mode c16 rf balun/matching network capacitor high performance rf balun/matching network capacitor standard mode c17 16/32 mhz crystal loading capacitor c18 16/32 mhz crystal loading capacitor c19 decoupling capacitor for 1.8 v digital regulator c20 decoupling capacitor for 1.8 v digital regulator c21 rf balun/matching network capacitor high performance, rf balun/matching network capacitor standard mode l1 dc-dc converter input inductor, isat > 100 ma, q > 25 l2 rf balun/matching network inductor high performance rf balun/matching network inductor standard mode l3 rf balun/matching network inductor high performance rf balun/matching network inductor standard mode l4 rf balun/matching network inductor high performance rf balun/matching network inductor standard mode r1 pull-down resistor on the spi_irq line (can be replaced by the internal pull-down of the application mcu) xtal1 32 khz crystal (optional) xtal2 16/32 mhz crystal 1. values valid only for the crystal ndk nx3215sa-32.768 khz-exs00a-mu00003. for other crystals refer to what specified in their datasheet. table 3. external component list (continued) component description
absolute maximum ratings and thermal data bluenrg 16/43 docid025108 rev 5 5 absolute maximum ratings and thermal data note: absolute maximum ratings are those values above which damage to the device may occur. functional operation under these conditions is not implied. all voltages are referred to gnd. table 4. absolute maximum ratings pin parameter value unit 5, 19, 24, 26, 28 dc-dc converter supply voltage input and output -0.3 to +3.9 v 12, 29 dc voltage on linear voltage regulator -0.3 to +3.9 v 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 25, 27, 30, 31, 32 dc voltage on digital input/output pins -0.3 to +3.9 v 13, 14, 15,16 dc voltage on analog pins -0.3 to +3.9 v 17, 18, 22, 23 dc voltage on xtal pins -0.3 to +1.4 v 20, 21 (1) dc voltage on rf pins -0.3 to +1.4 v t stg storage temperature range -40 to +125 c v esd - hbm electrostatic discharge voltage 2.0 kv 1. +8 dbm input power at antenna connector in standard mode, +11 dbm in high power mode, with given reference design. table 5. thermal data symbol parameter value unit r thj-amb thermal resistance junction-ambient 34 (qfn32) 50 (wlcsp36) c/w r thj-c thermal resistance junction-case 2.5 (qfn32) 25 (wlcsp36) c/w
docid025108 rev 5 17/43 bluenrg general characteristics 43 6 general characteristics table 6. recommended operating conditions symbol parameter min. typ. max. unit v bat operating battery supply voltage 2.0 3.6 v t a operating ambient temperature range -40 +85 c
electrical specification bluenrg 18/43 docid025108 rev 5 7 electrical specification 7.1 electrical characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat = 3.0 v. all performance data are referred to a 50 ?? antenna connector, via reference design, qfn32 package version. table 7. electrical characteristics symbol parameter test conditions min. typ. max. unit power consumption when dc-dc converter active i bat supply current reset 5 na standby (ram2 off) standby (ram2 on) 1.3 2 a sleep 32khz xo on (ram2 off) 32khz xo on (ram2 on) 32khz ro on (ram2 off) 32khz ro on (ram2 on) 1.7 2.4 2.8 3.5 a active cpu, flash and ram off cpu, flash and ram on 2 3.3 ma rx high power mode rx standard mode 7.7 7.3 ma tx standard mode +5dbm 0dbm -2dbm -6dbm -9dbm -12dbm -15dbm -18dbm tx high power mode +8dbm +4dbm +2dbm -2dbm -5dbm -8dbm -11dbm -14dbm 11 8.2 7.2 6.7 6.3 6.1 5.9 5.8 15.1 10.9 9 8.3 7.7 7.1 6.8 6.6 ma power consumption when dc-dc converter not active
docid025108 rev 5 19/43 bluenrg electrical specification 43 i bat supply current reset 5 na standby (ram2 off) standby (ram2 on) 1.4 2 a sleep 32khz xo on (ram2 off) 32khz xo on (ram2 on) 32khz ro on (ram2 off) 32khz ro on (ram2 on) 1.7 2.4 2.8 3.5 a active cpu, flash and ram off 2.3 ma rx high power mode rx standard mode 14.5 14.3 ma tx standard mode +5dbm 0dbm -2dbm -6dbm -9dbm -12dbm -15dbm -18dbm tx high power mode +8dbm +4dbm +2dbm -2dbm -5dbm -8dbm -11dbm -14dbm 21 15.4 13.3 12.2 11.5 11 10.6 10.4 28.8 20.5 17.2 15.3 14 13 12.3 12 ma digital spi input and output (spi_miso, spi_mosi, spi_clk, spi_irq and reset) c in port i/o capacitance 1.29 1.38 1.67 pf t rise rise time 0.1*vdd to 0.9*vdd, cl=50pf 5 19 ns t fall fall time 0.9*vdd to 0.1*vdd, cl=50pf 6 22 ns v ih logic high level input voltage 0.65 vdd v il logic low level input voltage 0.35 vdd v oh high level output voltage (ulpi port) vdd = 3.3 v 2.4 v v ol low level output voltage (ulpi port) vdd = 3.3 v 0.4 v digital spi input spi_cs table 7. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
electrical specification bluenrg 20/43 docid025108 rev 5 7.2 rf general characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v. all performance data are referred to a 50 ?? antenna connector, via reference design, qfn32 package version. c in port i/o capacitance 1.29 1.38 1.67 pf c in port i/o capacitance 1.29 1.38 1.67 pf t rise rise time 0.1*vdd to 0.9*vdd, cl=50pf 5.05 18.5 ns t fall fall time 0.9*vdd to 0.1*vdd, cl=50pf 5.647 21.93 ns v ih logic high level input voltage 0.65 vdd v il logic low level input voltage 0.35 vdd table 7. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit table 8. rf general characteristics symbol parameter test conditions min. typ. max. unit freq frequency range 2400 2483.5 mhz f ch channel spacing 2 mhz rf ch rf channel center frequency 2402 2480 mhz
docid025108 rev 5 21/43 bluenrg electrical specification 43 7.3 rf transmitter characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat = 3.0 v. all performance data are referred to a 50 ?? antenna connector, via reference design, qfn32 package version. table 9. rf transmitter characteristics symbol parameter test conditions min. typ. max. unit mod modulation scheme gfsk bt bandwidth-bit period product 0.5 m index modulation index 0.45 0.5 0.55 dr air data rate 1 mbps st acc symbol time accuracy 50 ppm p max maximum output power high power standard mode at antenna connector +8 +5 +10 +7 dbm p rfc minimum output power high power standard mode -15 -18 db p rfc rf power accuracy 2 db p bw1m 6 db bandwidth for modulated carrier (1 mbps) using resolution bandwidth of 100khz 500 khz p rf1 1 st adjacent channel transmit power 2 mhz using resolution bandwidth of 100 khz and average detector -20 dbm p rf2 2 nd adjacent channel transmit power >3mhz using resolution bandwidth of 100 khz and average detector -30 dbm p spur spurious emission harmonics included. using resolution bandwidth of 1 mhz and average detector -41 dbm cf dev center frequency deviation during the packet and including both initial frequency offset and drift 150 khz freq drift frequency drift during the packet 50 khz ifreq drift initial carrier frequency drift 20 khz driftrate max maximum drift rate 400 hz/ s z load optimum differential load standard mode @ 2440 mhz high power mode @ 2440 mhz 25.9 + j44.4 25.4 + j20.8
electrical specification bluenrg 22/43 docid025108 rev 5 7.4 rf receiver characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v. all performance data are referred to a 50 ?? antenna connector, via reference design, qfn32 package version. table 10. rf receiver characteristics symbol parameter test conditions min. typ. max. unit rx sens sensitivity ber <0.1% - -88 dbm p sat saturation standard mode high power mode ber <0.1% 8 11 dbm z in input differential impedance standard mode @ 2440 mhz high power mode @ 2440 mhz 31.4 - j26.6 28.8 - j18.5 ? rf selectivity with ble equal modulation on interfering signal c/i co- channel co-channel interference wanted signal=-67dbm, ber 0.1% - 9 dbc c/i 1 mhz adjacent (+1 mhz) interference wanted signal=-67dbm, ber 0.1% 2 dbc c/i 2 mhz adjacent (+2 mhz) interference wanted signal=-67dbm, ber 0.1% -34 dbc c/i 3 mhz adjacent (+3 mhz) interference wanted signal=-67dbm, ber 0.1% -40 dbc c/i 4 mhz adjacent ( 4 mhz) interference wanted signal=-67dbm, ber 0.1% -34 dbc c/i 6 mhz adjacent ( 6 mhz interference wanted signal=-67dbm ber 0.1% -45 dbc c/i 25 mhz adjacent ( 25 mhz) interference wanted signal=-67dbm, ber 0.1% -64 dbc c/i image image frequency interference -2mhz wanted signal=-67dbm, ber 0.1% -20 dbc c/i image1 mhz adjacent (1 mhz) interference to in-band image frequency -1mhz -3mhz wanted signal=-67dbm, ber 0.1% 5 -25 dbc out of band blocking (interfering signal cw) c/i block interfering signal frequency 30 mhz ? 2000 mhz wanted signal=-67dbm, ber 0.1%, measurement resolution 10 mhz - -30 dbm c/i block interfering signal frequency 2003 mhz ? 2399 mhz wanted signal=-67dbm, ber 0.1%, measurement resolution 3 mhz -35 dbm
docid025108 rev 5 23/43 bluenrg electrical specification 43 7.5 high speed crystal oscillator (hsxosc) characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat = 3.0 v. 7.5.1 high speed crystal oscillator (hsxosc) the bluenrg includes a fully integrated, low power 16/32 mhz xtal oscillator with an embedded amplitude regulation loop. in order to achieve low power operation and good frequency stability of the xtal oscillator, certain considerations with respect to the quartz load capacitance c0 need to be taken into account. figure 9 shows a simplified block diagram of the amplitude regulated oscillator used on the bluenrg. c/i block interfering signal frequency 2484 mhz ? 2997 mhz wanted signal=-67 dbm, ber 0.1%, measurement resolution 3 mhz - -35 dbm c/i block interfering signal frequency 3000 mhz ? 12.75 ghz wanted signal=-67dbm, ber 0.1%, measurement resolution 25 mhz -30 dbm intermodulation characteristics (cw signal at f 1 , ble interfering signal at f 2 ) p_im(3) input power of im interferes at 3 and 6 mhz distance from wanted signal wanted signal=-64dbm, ber 0.1% - -33 dbm p_im(-3) input power of im interferes at -3 and -6 mhz distance from wanted signal wanted signal=-64dbm, ber 0.1% -43 dbm p_im(4) input power of im interferes at 4 and 8 mhz distance from wanted signal wanted signal=-64dbm, ber 0.1% -33 dbm p_im(5) input power of im interferes at 5 and 10 mhz distance from wanted signal wanted signal=-64dbm, ber 0.1% -33 dbm table 10. rf receiver characteristics (continued) symbol parameter test conditions min. typ. max. unit table 11. high speed crystal oscillator characteristics symbol parameter test conditions min. typ. max. unit f nom nominal frequency 16/32 mhz f tol frequency tolerance includes initial accuracy, stability over temperature, aging and frequency pulling due to incorrect load capacitance. 50 ppm esr equivalent series resistance 100 p d drive level 100 w
electrical specification bluenrg 24/43 docid025108 rev 5 figure 9. simplified block diagram of the amplitude regulated oscillator low power consumption and fast startup time is achieved by choosing a quartz crystal with a low load capacitance c0. a reasonable choice for capacitor c0 is 12 pf. to achieve good frequency stability, the following equation needs to be satisfied: equation 1 where c1?=c1+cpcb1+cpad, c2?= c2+cpcb2+cpad, where c1 and c2 are external (smd) components, cpcb1 and cpcb2 are pcb routing parasites and cpad is the equivalent small-signal pad-capacitance. the value of cpad is around 0.5 pf for each pad. the routing parasites should be minimized by placing quartz and c1/c2 capacitors close to the chip, not only for an easier matching of the load capacitance c0, but also to ensure robustness against noise injection. connect each capacitor of the xtal oscillator to ground by a separate via.
docid025108 rev 5 25/43 bluenrg electrical specification 43 7.6 low speed crystal oscillator (lsxosc) characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v. note: this values are the correct ones for nx3215sa-32.768 khz-exs00a-mu00003. 7.7 high speed ring oscillator (hsrosc) characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v, qfn32 package version. 7.8 low speed ring oscillator (lsrosc) characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v, qfn32 package version. 7.9 n-fractional frequency synthesizer characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v, f c = 2440 mhz. table 12. low speed crystal oscillator characteristics symbol parameter test conditions min. typ. max. unit f nom nominal frequency 32.768 khz f tol frequency tolerance includes initial accuracy, stability over temperature, aging and frequency pulling due to incorrect load capacitance. 50 ppm esr equivalent series resistance 90 k p d drive level 0.1 w table 13. high speed ring oscillator characteristics symbol parameter test conditions min. typ. max. unit f nom nominal frequency 12 16 mhz table 14. low speed ring oscillator characteristics symbol parameter test conditions min. typ. max. unit 32 khz ring oscillator (lsrosc) f nom nominal frequency 37.4 khz f tol frequency tolerance 500 ppm
electrical specification bluenrg 26/43 docid025108 rev 5 7.10 auxiliary blocks characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v, f c = 2440 mhz. qfn32 package version. table 15. n-fractional frequency synthesizer characteristics symbol parameter test conditions min. typ. max. unit pn synth rf carrier phase noise at 1mhz offset from carrier -113 dbc/hz at 3mhz offset from carrier -119 dbc/hz at 6mhz offset from carrier tbd dbc/hz at 25mhz offset from carrier tbd dbc/hz lock time pll lock time 40 s to time pll turn on / hop time including calibration 150 s table 16. auxiliary blocks characteristics symbol parameter test conditions min. typ. max. unit analog temperature sensor t rerr error in temperature (after calibration) -4 0 +4 c t slope temperature coefficient 3.1 mv/c t icc current consumption 10 a t ts-out output voltage level 1 v battery indicator and brown-out reset (bor) v blt1 battery level thresholds 1 2.7 v v blt2 battery level thresholds 2 2.5 v v blt3 battery level thresholds 3 2.3 v v blt4 battery level thresholds 4 2.1 v a blt battery level thresholds accuracy 5% v abor ascending brown-out threshold 1.79 v v dbor descending brown-out threshold 1.73 v
docid025108 rev 5 27/43 bluenrg block diagram and descriptions 43 8 block diagram and descriptions a block diagram of the bluenrg is shown in figure 10 . in the following subsections a short description of each module is given. figure 10. bluenrg block diagram 8.1 core, memory and peripherals the bluenrg contains an arm cortex-m0 microcontroller core that supports ultra-low leakage state retention mode and almost instantaneously returning to fully active mode on critical events. the memory subsystem consists of 64 kb flash, and 12 kb ram. flash is used for the m0 program. no ram or flash resources are available to the external microcontroller driving the bluenrg. the application controller interface (aci) uses a standard spi slave interface as transport layer, basing in five physical wires: ? 2 control wires (clock and slave select) ? 2 data wires with serial shift-out (mosi and miso) in full duplex ? 1 wire to indicate data availability from the slave
block diagram and descriptions bluenrg 28/43 docid025108 rev 5 all the spi pins have an internal pull-down except for the csn that has a pull-up. all the spi pins, except the csn, are in high impedance state during the low-power states. the irq pin needs a pull-down external resistor. the bluenrg integrates a temperature sensor to report the silicon temperature. the characteristics of the temperature sensor are defined in table 16 . the device embeds a battery level detector to monitor the supply voltage. the characteristics of the battery level detector are defined in table 16 . 8.2 power management the bluenrg integrates both a low dropout voltage regulator (ldo) and a step-down dc- dc converter, and one of them can be used to power the internal bluenrg circuitry. however even when the ldo is used, the stringent maximum current requirements, which are advisable when coin cell batteries are used, can be met and further improvements can be obtained with the dc-dc converter at the sole additional cost of an inductor and a capacitor. the internal ldos supplying both the 1.8 v digital blocks and 1.2 v digital blocks require decoupling capacitors for stable operation. figure 11 and figure 12 , show the simplified power management schemes using ldo and dc-dc converter. table 17. spi interface name direction width description spi_cs in 1 spi slave select = spi enable. spi_clk in 1 spi clock (max 8 mhz). spi_mosi in 1 master output, slave input. spi_miso out 1 master input, slave output. spi_irq out 1 slave has data for master.
docid025108 rev 5 29/43 bluenrg block diagram and descriptions 43 figure 11. power management strategy using ldo figure 12. power management strategy using step-down dc-dc converter vbatt 2v - 3.6v external decoupling capacitor smps off external decoupling capacitor ldos 1.2v ldo digital logic 1.2v ldos 1.2v ldo digital logic 1.8v vbatt 2v - 3.6v not connected am17566 1 vbatt 2v - 3.6v vout_smps external decoupling capacitor external decoupling capacitor external inductor smps external decoupling capacitor ldos 1.2v ldo digital logic 1.2v ldos 1.2v ldo digital logic 1.8v am17667v1
block diagram and descriptions bluenrg 30/43 docid025108 rev 5 8.3 clock management the bluenrg integrates two low-speed frequency oscillators (lsosc) and two high speed (16 mhz or 32 mhz) frequency oscillators (hsosc). the low frequency clock is used in low power mode and can be supplied either by a 32.7 khz oscillator that uses an external crystal and guarantee up to 50 ppm frequency tolerance, or by a ring oscillator with maximum 500 ppm frequency tolerance, which does not require any external components. the primary high frequency clock is a 16 mhz or 32 mhz crystal oscillator. there is also a fast-starting 12 mhz ring oscillator that provides the clock while the crystal oscillator is starting up. frequency tolerance of high speed crystal oscillator is 50 ppm. the usage of the 16 mhz (or 32 mhz) crystal is strictly necessary. 8.4 bluetooth low energy radio the bluenrg integrates a rf transceiver compliant to the bluetooth specification and to the standard national regulations in the unlicensed 2.4 ghz ism band. the rf transceiver requires very few external discrete components. it provides 96 db link budgets with excellent link reliability, keeping the maximum peak current below 15 ma. in transmit mode, the power amplifier (pa) drives the signal generated by the frequency synthesizer out to the antenna terminal through a very simple external network. the power delivered as well as the harmonic content depends on the external impedance seen by the pa. the output power is programmable from -18 dbm to +8 dbm, to allow a user-defined power control system and to guarantee optimum power consumption for each scenario.
docid025108 rev 5 31/43 bluenrg operating modes 43 9 operating modes several operating modes are defined for the bluenrg: ? reset mode ? sleep mode ? standby mode ? active mode ? radio mode ? receive radio mode ? transmit radio mode in reset mode, the bluenrg is in ultra-low power consumption: all voltage regulators, clocks and the rf interface are not powered. the bluenrg enters reset mode by asserting the external reset signal. as soon as it is de-asserted, the device follows the normal activation sequence to transit to active mode. in sleep mode either the low speed crystal oscillator or the low speed ring oscillator are running, whereas the high speed oscillators are powered down as well as the rf interface. the state of the bluenrg is retained and the content of the ram is preserved. while in sleep mode, the bluenrg waits until an internal timer expires and then it goes into active mode. the transition from sleep mode to active mode can also be activated through the spi interface. standby mode and sleep mode are equivalent but the low speed frequency oscillators are powered down. in standby mode the bluenrg can be activated through the spi interface. in active mode the bluenrg is fully operational: all interfaces, including spi and rf, are active as well as all internal power supplies together with the high speed frequency oscillator. the mcu core is also running. radio mode differs from active mode as also the rf transceiver is active and it is capable of either transmitting or receiving. figure 13 reports the simplified state machine:
operating modes bluenrg 32/43 docid025108 rev 5 figure 13. simplified state machine active rx tx sleep reset t reset -active t sleep -active t active -sleep t t tx-active rx-active t active -rx t active -tx standby t standby -active t active -stabndby table 18. bluenrg operating modes state digital ldo spi lsosc hsosc core rf synt. rx chain tx chain reset off register contents lost off off off off off off off standby on register contents retained on off off off off off off sleep on register contents retained on on off off off off off active on register contents retained on - on on off off off rx on register contents retained on - on on on on off tx on register contents retained on - on on on off on
docid025108 rev 5 33/43 bluenrg operating modes 43 table 19. bluenrg transition times transition maximum time condition reset-active (1) 1. these measurements are taken using nx3225sa-16.000 mhz-exs00a-cs05997. 1.5 ms 32 khz not available 7 ms 32 khz ro 94 ms 32 khz xo standby-active (1) 0.42 ms 32 khz not available 6.2 ms 32 khz ro 93 ms 32 khz xo sleep-active (1) 0.42 ms active-rx 125 s channel change 61 s no channel change active-tx 131 s channel change 67 s no channel change rx-tx or tx-rx 150 s
application controller interface bluenrg 34/43 docid025108 rev 5 10 application controller interface the application controller interface is based on a standard spi module with speeds up to 8 mhz. the application controller interface defines a software protocol providing functions to access all the services offered by the layers of the embedded bluetooth stack. the aci commands are described in the bluenrg aci command interface document.
docid025108 rev 5 35/43 bluenrg package mechanical data 43 11 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package mechanical data bluenrg 36/43 docid025108 rev 5 figure 14. qfn32 (5 x 5 x 1 pitch 0.5 mm) drawing
docid025108 rev 5 37/43 bluenrg package mechanical data 43 table 20. qfn32 (5 x 5 x 1 pitch 0.5 mm) mechanical data dim. mm min. typ. max. a 0.80 0.85 1.00 a1 0 0.02 0.05 a3 0.20 ref b 0.25 0.25 0.30 d 5.00 bsc e 5.00 bsc d2 3.2 3.70 e2 3.2 3.70 e 0.5 bsc l 0.30 0.40 0.50 0 14 k 0.20
package mechanical data bluenrg 38/43 docid025108 rev 5 figure 15. wlcsp34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) drawing 1. the corner of terminal a1 must be identified on the top surface by using a laser marking dot see figure 3 . adc8471362_c1 see note 1
docid025108 rev 5 39/43 bluenrg package mechanical data 43 table 21. wlcsp34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) mechanical data (1) 1. wlcsp stands for wafer level chip scale package. dim. mm. notes min. typ. max. a 0.50 a1 0.20 b 0.27 (2) 2. the typical ball diameter before mounting is 0.25 mm. d 2.50 2.56 2.58 (3) 3. d = f + d1 + f. d1 2.00 e 2.60 2.66 2.68 (4) 4. e = g + e1 + g. e1 2.00 e 0.40 f 0.28 g 0.33 ccc 0.05
pcb assembly guidelines bluenrg 40/43 docid025108 rev 5 12 pcb assembly guidelines for flip chip mounting on the pcb, stmicroelectronics recommends the use of a solder stencil aperture of 330 x 330 m maximum and a typical stencil thickness of 125 m. flip chips are fully compatible with the use of near eutectic 95.8% sn, 3.5% ag, 0.7% cu solder paste with no-clean flux. st's recommendations for flip chip board mounting are illustrated on the soldering reflow profile shown in figure 16. figure 16. flip chip csp (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile recommendation dwell time in the soldering zone (with temperature higher than 220 c) has to be kept as short as possible to prevent component and substrate damage. peak temperature must not exceed 260 c. controlled atmosphere (n 2 or n 2 h 2 ) is recommended during the whole reflow, especially above 150 c. flip chips are able to withstand three times the previous recommended reflow profile to be compatible with a double reflow when smds are mounted on both sides of the pcb plus one additional repair. a maximum of three soldering reflows are allowed for these lead-free packages (with repair step included). table 22. flip chip csp (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile recommendation profile value typ. max. temp. gradient in preheat (t = 70 ? 180 c) 0.9 c/s 3 c/s temp. gradient (t = 200 ? 225 c) 2 c/s 3 c/s peak temp. in reflow 240 - 245 c 260 c time above 220 c 60 s 90 s temp. gradient in cooling -2 to - 3 c/s -6 c/s time from 50 to 220 c 160 to 220 s 250 0 50 100 150 200 240 210 180 150 120 90 60 30 300 270 - 6c/s 240-245 c 2 - 3 c/s temperature (c) -2 c/s -3 c/s time (s) 0.9 c/ s 60 sec (90 max)
docid025108 rev 5 41/43 bluenrg pcb assembly guidelines 43 the use of a no-clean paste is highly recommended to avoid any cleaning operation. to prevent any bump cracks, ultrasonic cleaning methods are not recommended.
revision history bluenrg 42/43 docid025108 rev 5 13 revision history table 23. document revision history date revision changes 09-aug-2013 1 initial release. 07-feb-2014 2 ? datasheet promoted from preliminary data to production data ? added wlcsp34 package to table 1: device summary ? deleted references to ?low power adc? throughout the document. ? added pin information for the wlcsp package to figure 3 on page 9 , table 2: pinout description ? updated figure 5 and figure 6 on page 13 ? added figure 7: bluenrg application circuit: active dc-dc converter wlcsp package and figure 8: bluenrg application circuit: non active dc-dc converter wlcsp package ? modified high performance and standard mode values in figure 3: external component list ? changed all references the term ?slave? to ?ram2 off?, and ?master? to ?ram2 on? in figure 7: electrical characteristics ? modified title of table 16 ? modified figure 10.: bluenrg block diagram ? corrected error in typical bsc value for reference ?e? in table 20 . ? added wlcsp package drawing and dimensions data ( figure 15 and table 21 ) ? minor text corrections throughout the document. 19-mar-2014 3 added: ? figure 3 on page 9 . updated: ? figure 5 and figure 6 on page 13 , figure 7 and figure 8 on page 14 . 21-mar-2014 4 added: ? section 12: pcb assembly guidelines on page 40 . 17-nov-2014 5 updated: table 2 , table 3 , table 5 , table 11 , table 12 , table 15 , section 7.7 and section 8 , added: section 7.5.1
docid025108 rev 5 43/43 bluenrg 43 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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