rev. 2.4 - 5/27/98 1 1 2 3 4 5 6 7 8 9 10 11 12 preliminary 4 megabit 3.3v static ram 512k x 8-bit features n high-speed access times com?: 8, 10, 12, 15, and 20 ns ind?.: 12, 15 and 20 ns n low power operation - pdm31096sa active: 300 ma (max) standby: 25mw n single +3.3v ( 0.3v) power supply n ttl-compatible inputs and outputs n packages plastic soj (400 mil) - so plastic tsop (ii) - t description the pdm31096 is a high-performance cmos static ram organized as 524,288 x 8 bits. writing is accomplished when the write enable (we ) and chip enable ce inputs are both low. reading is accomplished when we remains high and ce and oe are both low. the pdm31096 operates from a single +3.3v power supply and all the inputs and outputs are fully ttl- compatible. the pdm31096 is available in a 36-pin 400-mil plas- tic soj package and a 44-pin plastic tsop (ii) package. pdm31096 a
? ? ? ? ? a
0
18 i/o
? ? i/o 0
7 ? ? ? ? ? ?
addresses decoder memory matrix input
data
control column i/o ? ? ce we oe functional block diagram
pdm31096 2 rev. 2.4 - 5/27/98 preliminary truth table (1) note: 1. h = v ih , l = v il , x = don? care oe we ce i/o mode x x h hi-z standby x x x hi-z standby lhld out read xlld in write h h l hi-z output disable pin description name description a18-a0 address inputs i/o7-i/o0 data inputs/outputs oe output enable input we write enable input ce chip enable inputs nc no connect v cc power (+3.3v) v ss ground 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 23 24 25 26 27 28 a4 a3 a2 a1 a0 ce i/o0 i/o1 vcc vss i/o2 i/o3 we a18 a17 a16 a15 a14 nc a5 a6 a7 a8 oe i/o7 i/o6 vss vcc i/o5 i/o4 a9 a10 a11 a12 a13 nc 13 14 29 30 31 36 32 33 34 35 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 12 15 16 29 30 31 32 nc nc a4 a3 a2 a1 a0 ce i/oo i/o1 vcc vss i/o2 i/o3 we a18 a17 a16 a15 a14 nc nc nc nc nc a5 a6 a7 a8 oe i/o7 i/o6 vss vcc i/o5 i/o4 a9 a10 a11 a12 a13 nc nc nc 13 14 33 34 35 36 37 38 39 40 41 42 43 44 19 20 21 22 17 18 23 24 25 26 27 28 soj tsop (ii) absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. appropriate thermal calculations should be performed in all cases and speci?ally for those where the chosen package has a large thermal resistance (e.g., tsop). the cal- culation should be of the form : t j = t a + p * q ja where t a is the ambient temperature, p is average operating power and q ja the thermal resistance of the package. for this product, use the following q ja value: soj: 59 o c/w tsop : tbd symbol rating com l. ind. unit v term terminal voltage with respect to v ss ?.5 to +4.6 ?.5 to +4.6 v t bias temperature under bias ?5 to +125 ?5 to +135 c t stg storage temperature ?5 to +125 ?5 to +150 c p t power dissipation 1.0 1.0 w i out dc output current 50 50 ma t j maximum junction temperature (2) 125 145 c pin con?uration
pdm31096 rev. 2.4 - 5/27/98 3 1 2 3 4 5 6 7 8 9 10 11 12 preliminary dc electrical characteristics (v cc = 3.3v 0.3v) note:1.v il (min) = ?.0v for pulse width less than 20 ns power supply characteristics notes: all values are maximum guaranteed values. capacitance (1) (t a = +25 c, f = 1.0 mhz) note: 1. this parameter is determined by device characterization but is not production tested. symbol parameter test conditions min. max. unit i li input leakage current v cc = max., v in = v ss to v cc ? 5 m a i lo output leakage current v cc = max., ce = v ih v out = v ss to v cc ? 5 m a v il input low voltage ?.3 (1) 0.8 v v ih input high voltage 2.2 vcc+0.3 v v ol output low voltage i ol = 8 ma, v cc = min. 0.4 v v oh output high voltage i oh = ? ma, v cc = min. 2.4 v -8 -10 -12 -15 -20 symbol parameter com l. com l. com l ind. com l ind. com l ind. unit i cc operating current ce = v il 230 215 200 220 160 200 120 160 ma f = f max = 1/t rc v cc = max. i out = 0 ma i sb standby current ce = v ih 50 45 40 45 35 40 30 35 ma f = f max = 1/t rc v cc = max. i sb1 full standby current ce 3 v cc ?0.2v 10 10 10 15 10 15 10 15 ma f = 0 v cc = max., v in 3 v cc ?0.2v or 0.2v symbol parameter max. unit c in input capacitance 8 pf c out output capacitance 8 pf
pdm31096 4 rev. 2.4 - 5/27/98 preliminary recommended dc operating conditions ac test conditions symbol parameter min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v v ss supply voltage 0 0 0 v industrial ambient temperature ?0 25 85 c commercial ambient temperature ? 25 70 c input pulse levels v ss to 3.0v input rise and fall times 2.5 ns input timing reference levels 1.5v output reference levels 1.5v output load see figures 1 and 2 figure 1. output load equivalent figure 2. output load equivalent (for t lzce , t hzce , t lzwe , t hzwe , t lzoe , t hzoe ) +3.3v +3.3v 317 w 317 w 351 w 351 w d out d out 30 pf 5 pf
pdm31096 rev. 2.4 - 5/27/98 5 1 2 3 4 5 6 7 8 9 10 11 12 preliminary read cycle no. 1 (4, 5) read cycle no. 2 (2, 4, 6) ac electrical characteristics * v cc = 3.3v + 5% description -8* -10* ?2 ?5 ?0 read cycle sym min max min max min max min max min max units read cycle time t rc 8 10?2?5?0 ns address access time t aa 8 10?2?5?0 ns chip enable access time t ace 8 10?2?5?0 ns output hold from address change t oh 3???? ns chip enable to output in low z (1,3) t lzce 3???? ns chip disable to output in high z (1,2,3) t hzce ????? ns output enable access time t aoe ????? ns output enable to output in low z (1,3) t lzoe 0???? ns output disable to output in high z (1,3) t hzoe ????? ns t rc
t aa
t oh
previous data valid d out addr
data valid t rc
t ace
t aa
t lzce
t hzce
t lzoe
t hzoe
t aoe
addr
ce
oe
d out data valid
pdm31096 6 rev. 2.4 - 5/27/98 preliminary write cycle no. 1 (write enable controlled) write cycle no. 2 (write enable controlled) t wc
t aw
t wp
t cw
t ah
t as
t dh
t ds
t lzwe
t hzwe
addr
ce
we
d out high-z d in data valid note: output enable (oe ) is inactive (high) t wc
t aw
t wp
t cw
t ah
t as
t dh
t ds
addr
ce
we
d out high-z d in data valid
pdm31096 rev. 2.4 - 5/27/98 7 1 2 3 4 5 6 7 8 9 10 11 12 preliminary write cycle no. 3 (chip enable controlled) ac electrical characteristics * v cc = 3.3v + 5% notes: (for two previous electrical characteristics tables) 1. the parameter is tested with cl = 5 pf as shown in figure 2. transition is measured 200 mv from steady state voltage. 2. at any given temperature and voltage condition, t hzce is less than t lzce . 3. this parameter is sampled. 4. we is high for a read cycle. 5. the device is continuously selected. all the chip enables are held in their active state. 6. the address is valid prior to or coincident with the latest occuring chip enable. description -8* -10* -12 -15 -20 write cycle sym min. max. min. max. min. max. min. max. min. max. units write cycle time t wc 8 10?2?5?0 ns chip enable to end of write t cw 8 10?0?1?3 ns address valid to end of write t aw 8 10?0?1?3 ns address setup time t as 0???? ns address hold from end of write t ah 0???? ns write pulse width t wp 7??? 10 ns data setup time t ds 5???? ns data hold time t dh 0???? ns write disable to output in low z (1,3) t lzwe 0???? ns write enable to output in high z (1,3) t hzwe ? 5??? ns note: output enable (oe ) is inactive (high) t wc
t aw
t wp
t cw
t ah
t as
t dh
t ds
addr
ce
we
d out high-z d in data valid
pdm31096 8 rev. 2.4 - 5/27/98 preliminary device type power speed package type process temp. range preferred shipping container commercial (0 to +70 c) industrial (?0 c to +85 c) 8/10 commercial only 12 15 20 sa standard power blank i a automotive ( ?0 c to +105 c) blank tubes tr tape & reel ty tray pdm31096 - (512kx8) static ram xxxxx x xx x x x so 36-pin 400-mil plastic soj t 44-pin 400-mil plastic tsop (ii) ordering information faster memories for a faster world
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