1. general description the 74ahc573-q100; 74ahct573-q100 is a high-speed si-gate cmos device and is pin compatible with low-power schottky ttl (l sttl). it is specified in compliance with jedec standard no. 7a. the 74ahc573-q100; 74ahct573-q100 consists of eight d-type transparent latches featuring separate d-type inputs for each latch and 3-state true outputs for bus oriented applications. a latch enable input (le) and an output enable input (oe ) are common to all latches. when pin le is high, data at the dn inputs enters the latches. in this condition the latches are transparent, i.e. a latch output will change state ea ch time its corresponding dn input changes. when pin le is low, the la tches store the information that is present at the dn inputs, after a set-up time pr eceding the high-to-low transition of le. when pin oe is low, the contents of the 8 latches are available at the outputs. when pin oe is high, the outputs go to the high-impedance off-state. operation of the oe input does not affect the state of the latches. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? balanced propagation delays ? all inputs have a schmitt trigger action ? common 3-state output enable input ? inputs accept voltages higher than v cc ? input levels: ? for 74ahc573-q100: cmos input level ? for 74ahct573-q100: ttl input level ? esd protection: ? mil-std-883, method 3015 exceeds 2000v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 74ahc573-q100; 74ahct573-q100 octal d-type transparant latch; 3-state rev. 1 ? 10 june 2013 product data sheet
74ahc_ahct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 10 june 2013 2 of 19 nxp semiconductors 74ahc573-q100; 74ahct573-q100 octal d-type transparant latch; 3-state 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74ahc573d-q100 ? 40 ? cto+125? c so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 74ahct573d-q100 74ahc573pw-q100 ? 40 ? cto+125? c tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 74ahct573pw-q100 74AHC573BQ-Q100 ? 40 ? cto+125? c dhvqfn20 plastic dual in-line compatible thermal enhanced very thin quad flat package no leads; 20 terminals; body 2.5 ? 4.5 ? 0.85 mm sot764-1 74ahct573bq-q100 fig 1. functional diagram mna809 3-state outputs latch 1 to 8 q0 q1 q2 q3 q4 q5 q6 q7 12 13 14 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 le oe 9 11 1 8 7 6 5 4 3 2
74ahc_ahct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 10 june 2013 3 of 19 nxp semiconductors 74ahc573-q100; 74ahct573-q100 octal d-type transparant latch; 3-state fig 2. logic symbol fig 3. iec logic symbol mna807 d0 d1 d2 d3 d4 d5 d6 d7 le oe q0 q1 q2 q3 q4 q5 q6 q7 1 11 12 13 14 15 16 17 18 19 9 8 7 6 5 4 3 2 mna808 12 13 14 15 16 17 18 11 c1 1 en1 1d 19 9 8 7 6 5 4 3 2 fig 4. logic diagram mna810 q4 d4 d le q q3 d3 d le q q2 d2 d le q q1 d1 d le lele q q0 d0 d latch 1 latch 2 latch 3 latch 4 latch 5 q le oe le le le le q5 d5 d le q latch 6 le q6 d6 d le q latch 7 le q7 d7 d le q latch 8 le
74ahc_ahct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 10 june 2013 4 of 19 nxp semiconductors 74ahc573-q100; 74ahct573-q100 octal d-type transparant latch; 3-state 5. pinning information 5.1 pinning 5.2 pin description (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 5. pin configuration so20 and tssop20 fig 6. pin configuration dhvqfn20 $ + & |