t ransient voltage suppressors for esd protection revision december 18, 2013 1 / 7 @ un semiconductor co., ltd. 2013 specifications are subject to change without notice. please refer to www.unsemi.com.tw for current information. u lc0544p10 u n semiconductor co., ltd. www.unsemi.com.tw s ymbol p arameter v alue u nits pp p p eak pulse power (tp=8/20s waveform) 5 0 w atts t j operating junction temperature range -55 to +150 oc t s tg s torage temperature range - 55 to +150 oc t l s oldering temperature, t max = 10s 260 oc de scription f eature f unctional diagram a pplications m echanical data m echanical characteristics ? 5 0 watts peak pulse power per line (tp=8/20s) ? p rotects four high speed lines ? l ow clamping voltage ? r ohs compliant ? i ec61000-4-2(esd): 15kv (air discharge) 1 0kv (contact discharge); ? i ec61000-4-4 (eft) 40a (5/50 s) ? i ec61000-4-5 (lighting) 2a (8/20 s) ? u sb 3.0 / usb 3.1 interfaces ? h dmi 1.4 / hdmi 2.0 interfaces ? v ideo graphics cards ? n otebooks, desktops, and servers ? p ortable instrumentation ? i ndustrial controls ? p eripherals ? d fn2510p10 (2.5x1.0mm) package ? m olding compound flammability rating : ul 94v-o ? w eight 5.0 millgrams (approximate) ? q uantity per reel : 3,000pcs ? r eel size : 7 inch ? l ead finish : lead free ? de vice marking: ul4l t he ULC0544P10 is ultra low capacitance tvs arrays designed to protect high speed data interfaces. this series has been specifically designed to protect sensitive components which are connected to high-speed data and transmission lines from over-voltage caused by esd (electrostatic discharge), cde (cable discharge events), and eft (electrical fast transients).
tr ansient voltage suppressors for esd protection revision december 18, 2013 2 / 7 @ un semiconductor co., ltd. 2013 specifications are subject to change without notice. please refer to www.unsemi.com.tw for current information. ulc 0544p10 un semiconductor co., ltd. www.unsemi.com.tw ch aracteristics sy mbol te st conditions mi n. ty p. ma x. un it re verse working voltage v rw m -- -- -- 5 v re verse breakdown voltage v br i t =1ma 6 -- -- v re verse leakage current i r v rw m =5v t=25 c -- -- 1 a ju nction capacitance c j i/o to gnd;v r =0v f=1mhz -- 0.35 -- pf po sitive clamping voltage v c i pp = 1a t p =8/20 s -- -- 14 v i pp = 2a t p =8/20 s -- -- 25 ele ctrical characteristics (@ 25 unless otherwise specified ) 60 n s 10 % pe rcent of peak pulse cu rrent % 30 n s tr = 0. 7~1ns ti me (n s) 90 % 10 0 % characteristic curves fig2. esd pulse waveform (according to iec 61000-4-2) fig3. esd clamping volatge & peak pulse curerent fi g4. pulse waveform fig 1. insertion loss
revision december 18, 2013 3 / 7 @ un semiconductor co., ltd. 2013 specifications are subject to change without notice. please refer to www.unsemi.com.tw for current information. transient voltage suppressors for esd protection ULC0544P10 un semiconductor co., ltd. www.unsemi.com.tw transmission line pulse (tlp) transmission line pulse (tlp) is a measurement technique used in the electrostatic discharge (esd) arena to characterize performance attributes of devices under esd stresses. tlp is able to obtain current versus voltage (i ? v) curves in which each data point is obtained with a 100 ns l ong pulse, with currents up to 40 a. tlp was first used in the esd field to study human body model (hbm) in integrated circuits, but it is an equally valid tool in the field of system level esd. the applicability of tlp to system level esd is illustrated in figure 1, which compares an 8 kv iec 61000 ?4 ? 2 current waveform with tlp current pulses of 8 and 16 a. the current levels and time duration for the pulses are similar and the initial rise time for the tlp pulse is comparable to the rise time of the iec 61000 ?4 ? 2?s initial current spike. this application note will give a basic introduction to tlp measurements and explain the datasheet parameters extracted from tlp for yeashin technology?s protection products. comparison of a current waveform of iec 61000 ?4 ?2 with tlp pulses at 8 and 16 a. the iec 61000 ?4 ? 2 esd waveforms is true to the standard and is shown here as captured on an oscilloscope. the points a, b, and c show the points on the waveforms specified in iec 61000 ?4 ?2. tlp characteristic
t ransient voltage suppressors for esd protection revision december 18, 2013 4 / 7 @ un semiconductor co., ltd. 2013 specifications are subject to change without notice. please refer to www.unsemi.com.tw for current information. u lc0544p10 u n semiconductor co., ltd. www.unsemi.com.tw e ye diagram d ata from the 90% level to the 10% level on the downward slope. 6 eye width : measure of the horizontal opening. to other transitions. 8 eye amplitude : difference between the logic 0 level and the logic 1 level histogram mean value. determine influence of j itter on the eye opening. 7 deterministic jitter : deviation of a transition 1 zero level : measure of the mean value of the logical 0. 2 one level : measure of the mean value of the logical 1. 3 rise time : measure of the transition time of the data from the 10% level to the 90% level on the upward slope. 4 fall time : measure of the transition time of the 5 9 bit rate : inverse of the bit period. eye height : measure of the vertical opening. determine eye closure due to noise. from its ideal time caused by reflections relative
t ransient voltage suppressors for esd protection revision december 18, 2013 5 / 7 @ un semiconductor co., ltd. 2013 specifications are subject to change without notice. please refer to www.unsemi.com.tw for current information. u lc0544p10 u n semiconductor co., ltd. www.unsemi.com.tw e ye diagram at 5gbps and 10gbps eye diagr am -- usb 3.1 mask at 10.0gbps. with component high speed test : 5gbps high speed test : 10gbps eye diagr am -- usb 3.1 mask at 10.0gbps. without component eye diagram -- usb 3.0 mask at 5.0gbps. without component eye diagram -- usb 3.0 mask at 5.0gbps. with component
t ransient voltage suppressors for esd protection revision december 18, 2013 6 / 7 @ un semiconductor co., ltd. 2013 specifications are subject to change without notice. please refer to www.unsemi.com.tw for current information. u lc0544p10 u n semiconductor co., ltd. www.unsemi.com.tw d fn2510p10 package outline & dimensions
t ransient voltage suppressors for esd protection revision december 18, 2013 7 / 7 @ un semiconductor co., ltd. 2013 specifications are subject to change without notice. please refer to www.unsemi.com.tw for current information. u lc0544p10 u n semiconductor co., ltd. www.unsemi.com.tw l ayout diagram information fi gure 1. usb 3.1 layout diagram figure 2. hdmi 2.0 layout diagram
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