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product preview DS21Q55 note : this product preview contains preliminary information and is subject to change without notice. some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, visit: http://dbserv.maxim - ic.com/errata.cfm . please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information. x features: complete t1 (ds1)/isdn ? pri/j1 transceiver functionality complete e1 (cept) pcm - 30/isdn - pri transceiver functionality short - and long - haul line interface for clock/data recovery and wave shaping cmi coder/decoder crystal - less jitter att enuator dual hdlc controllers on - chip programmable bert generator and detector internal software - selectable receive and transmit side termination resistors dual two - frame elastic - store slip buffers to interface backplanes up to 16.384mhz 16.384mhz, 8.192mh z, 4.096mhz, or 2.048mhz clock output synthesized to recovered network clock programmable output clocks for fractional t1, e1, h0, and h12 applications interleaving pcm bus operation 8 - bit parallel control port, multiplexed or nonmultiplexed, intel or moto rola ieee 1149.1 jtag - boundary scan 3.3v supply with 5v tolerant i/o signaling system 7 (ss7) support applications: routers channel service units (csus) data service units (dsus) muxes switches channel banks t1/e1 test equipment dsl add/drop multiplexers ordering information DS21Q55 27mm bga (0 c to +70 c) DS21Q55n 27mm bga ( - 40 c to +85 c) 1. description the DS21Q55 is a quad mcm device featuring independent transceivers that can be software configured for t1, e1, or j1 operation. e ach is composed of a line interface unit (liu), framer, hdlc controllers, and a tdm backplane interface, and is controlled via an 8 - bit parallel port configured for intel or motorola bus operations. the DS21Q55 is software compatible with the ds2155 single transceiver. it is pin compatible with the ds21qx5y family of products. product preview ds21 q55 quad t1/e1/j1 transceiver www.maxim - ic.com
product preview DS21Q55 2 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 1. description the DS21Q55 is a quad mcm devices featuring independent transceivers that can be software configured for t1, e1, or j1 operation. each is composed of a line inter face unit (liu), framer, hdlc controllers, and a tdm backplane interface, and is controlled via an 8 - bit parallel port configured for intel or motorola bus operations. the DS21Q55 is software compatible with the ds2155 single transceiver. it is pin compat ible with the ds21qx5y family of products. the liu is composed of a transmit interface, receive interface, and a jitter attenuator. the transmit interface is responsible for generating the necessary wave shapes for driving the network and providing the co rrect source impedance depending on the type of media used. t1 waveform generation includes dsx ? 1 line build - outs as well as csu line build - outs of - 7.5db, - 15db, and - 22.5db. e1 waveform generation i ncludes g.703 wave shapes for both 75o coax and 120o twisted cables. the receive interface provides network termination and recovers clock and data from the network. the receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0db to 43db or 0db to 12db for e1 applications and 0db to 30db or 0db to 36db for t1 applications. the jitter attenuator removes phase jitter from the transmitted or received signal. the crystal - less jitter attenuator requires only a 2.048mhz mclk for both e1 and t1 applications (with the option of using a 1.544mhz mclk in t1 applications) and can be placed in either transmit or receive data paths. an additional feature of the liu is a cmi coder/decoder for interfacing to optical networks. on the tran smit side, clock data and frame - sync signals are provided to the framer by the backplane interface section. the framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the crc codes, and provides the b8zs/ hdb3 (zero code suppression) and ami line coding. the receive - side framer decodes ami, b8zs, and hdb3 line coding, synchronizes to the data stream, reports alarm information, counts framing/coding/crc errors, and provides clock/data and frame - sync signals to the backplane interface section. each transceiver has two hdlc controllers. the hdlc controllers transmit and receive data via the framer block. the hdlc controllers can be assigned to any time slot, group of time slots, portion of a time slot or to fd l (t1) or sa bits (e1). each controller has a 128 - byte transmit fifo and a 128 - byte receive fifo, thus reducing the amount of processor overhead required to manage the flow of data. in addition, there is built - in support for reducing the processor time req uired to handle ss7 applications. the backplane interface provides a versatile method of sending and receiving data from the host system. elastic stores provide a method for interfacing to asynchronous systems, converting from a t1/e1 network to a 2.048mh z, 4.096mhz, 8.192mhz or n x 64khz system backplane. the elastic stores also manage slip conditions (asynchronous interface). an interleave bus option (ibo) is provided to allow up to eight transceivers (two DS21Q55s) to share a high - speed backplane. the parallel port provides access for control and configuration of all the DS21Q55?s features. the extended system information bus (esib) function allows up to eight transceivers, 2 DS21Q55s, to be accessed via a single read for interrupt status or other user selectable alarm status information. diagnostic capabilities include loopbacks, prbs pattern generation/detection, and 16 - bit loop - up and loop - down code generation and detection.
product preview DS21Q55 3 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . the device fully meets all of the latest e1 and t1 specifications, inclu ding the following: ansi: t1.403 - 1995, t1.231 - 1993, t1.408 at&t: tr54016, tr62411 itu: g.703, g.704, g.706, g.736, g.775, g.823, g.932, i.431, o.151, o.161 etsi: ets 300 011, ets 300 166, ets 300 233, ctr4, ctr12 japanese: jtg.703, jti.431, jj - 20.11 (cmi coding only)
product preview DS21Q55 4 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 1.1 feature highlights the DS21Q55 contains all of the features of the previous generation of dallas semiconductor?s t1 and e1 transceivers plus many new features. 1.1.1 general 27mm, 1.27 pitch bga 3.3v supply with 5v tolerant inputs and output s pin compatible with ds21x5y family software compatible with the ds2155 evaluation kits ieee 1149.1 jtag - boundary scan driver source code available from the factory 1.1.2 line interface requires a single master clock (mclk) for both e1 and t1 operation. master clock can be 2.048mhz, 4.096mhz, 8.192mhz, or 16.384mhz. option to use 1.544mhz, 3.088mhz, 6.276mhz, or 12.552mhz for t1 - only operation fully software configurable short - and long - haul applications automatic receive sensitivity adjustments ranges include 0 db to - 43db or 0db to - 15db for e1 applications; 0db to - 36db or 0db to - 15db for t1 applications receive level indication in 2.5db steps from - 42.5db to - 2.5db internal receive termination option for 75 o , 100 o , and 120 o lines monitor application gain sett ings of 20db, 26db, and 32db g.703 receive - synchronization signal - mode flexible transmit - waveform generation t1 dsx - 1 line build - outs t1 csu line build - outs of - 7.5db, - 15db, and - 22.5db e1 waveforms include g.703 waveshapes for both 75o coax and 120 o twis ted cables ais generation independent of loopbacks alternating ones and zeros generation square - wave output open - drain output option nrz format option transmitter power - down transmitter 50ma short - circuit limiter with exceeded indication of current limit transmit open - circuit - detected indication line interface function can be completely decoupled from the framer/formatter 1.1.3 clock synthesizer output frequencies include 2.048mhz, 4.096mhz, 8.192mhz, and 16.384mhz derived from recovered receive clock 1.1.4 jitter at tenuator 32 - bit or 128 - bit crystal - less jitter attenuator
product preview DS21Q55 5 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . requires only a 2.048mhz master clock for both e1 and t1 operation with the option to use 1.544mhz for t1 operation can be placed in either the receive or transmit path or disabled limit trip indica tion 1.1.5 framer/formatter fully independent transmit and receive functionality full receive - and transmit - path transparency t1 framing formats include d4 (slc - 96) and esf detailed alarm - and status - reporting with optional interrupt support large path - and lin e - error counters for: - t1 ? bpv, cv, crc6, and framing bit errors - e1 ? bpv, cv, crc4, e - bit, and frame alignment errors - timed or manual update modes ds1 idle code generation on a per - channel basis in both transmit and receive paths - user - defined - digital mill iwatt ansi t1.403 - 1998 support e1ets 300 011 rai generation g.965 v5.2 link detect ability to monitor one ds0 channel in both the transmit and receive paths in - band repeating - pattern generators and detectors - three independent generators and detectors - pa tterns from 1 bit to 8 bits or 16 bits in length rcl, rlos, rra , and rais alarms now interrupt on change of state flexible signaling support - software - or hardware - based - interrupt generated on change of signaling data - receive - signaling freeze o n loss of sync, carrier loss, or frame slip addition of hardware pins to indicate carrier loss and signaling freeze automatic rai generation to ets 300 011 specifications expanded access to sa and si bits option to extend carrier - loss criteria to a 1ms per iod as per ets 300 233 japanese j1 support - ability to calculate and check crc6 according to the japanese standard - ability to generate yellow alarm according to the japanese standard 1.1.6 system interface dual two - frame, independent receive and transmit elastic stores - independent control and clocking - controlled - slip capability with status - minimum - delay mode supported maximum 16.384mhz backplane burst rate supports t1 to cept (e1) conversion programmable output clocks for fractional t1, e1, h0, and h12 applicatio ns interleaving pcm bus operation
product preview DS21Q55 6 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . hardware - signaling capability - receive - signaling reinsertion to a backplane, multiframe sync - availability of signaling in a separate pcm data stream - signaling freezing ability to pass the t1 f - bit position through the elas tic stores in the 2.048mhz backplane mode access to the data streams in between the framer/formatter and the elastic stores user - selectable synthesized clock output 1.1.7 hdlc controllers two independent hdlc controllers fast load and unload features for fifos s s7 support for fisu transmit and receive independent 128 - byte rx and tx buffers with interrupt support access fdl, sa, or single/multiple ds0 channels ds0 access includes nx64 or nx56 compatible with polled or interrupt - driven environments bit oriented cod e (boc) support 1.1.8 test and diagnostics programmable on - chip bit error rate testing (bert) pseudorandom patterns including qr ss user - defined repetitive patterns daly pattern error insertion single and continuous total - bit and errored - bit counts payload error insertion error insertion in the payload portion of the t1 frame in the transmit path errors can be inserted over the entire frame or selected channels insertion options include continuous and absolute number with selectable insertion rates f - bit corrupti on for line testing loopbacks (remote, local, analog, and per - channel loopback) 1.1.9 extended system information bus host can read interrupt and alarm status on up to eight ports with a single - bus read 1.1.10 control port 8 - bit parallel control port multiplexed or no nmultiplexed buses intel or motorola formats supports polled or interrupt - driven environments software access to device id and silicon revision software - reset supported automatic clear on power - up flexible register - space resets hardware reset pin
product preview DS21Q55 7 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . note: this data sheet assumes a particular nomenclature of the t1 and e1 operating environment. in each 125 m s t1 frame, there are 24 8 - bit channels plus a framing bit. it is assumed that the framing bit is sent first followed by channel 1. each channel is made u p of 8 bits, which are numbered 1 to 8. bit 1, the msb, is transmitted first. bit 8, the lsb, is transmitted last. the term ?locked? is used to refer to two clock signals that are phase - or frequency - locked or derived from a common clock (i.e., a 1.544mhz clock can be locked to a 2.048mhz clock if they share the same 8khz component).
product preview DS21Q55 8 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . table of contents 1.1 feature highlights ................................ ................................ ................................ ............................ 4 1.1.1 general ................................ ................................ ................................ ................................ .................. 4 1.1.2 line interface ................................ ................................ ................................ ................................ ....... 4 1.1.3 clock synthesizer ................................ ................................ ................................ .............................. 4 1.1.4 jitter attenuator ................................ ................................ ................................ ................................ ... 4 1.1.5 framer/formatter ................................ ................................ ................................ ............................... 5 1.1.6 system interface ................................ ................................ ................................ ................................ . 5 1.1.7 hdlc controllers ................................ ................................ ................................ ............................... 6 1.1.8 test and diagnostics ................................ ................................ ................................ ........................ 6 1.1.9 extended system information bus ................................ ................................ ............................... 6 1.1.10 control port ................................ ................................ ................................ ................................ .......... 6 1.2 document revision history ................................ ................................ ................................ ....... 12 2. block diagram ................................ ................................ ................................ ................................ ........... 13 3. pin function descrip tion ................................ ................................ ................................ .................. 14 3.1 t ransmit s ide p ins ................................ ................................ ................................ ................................ ..... 14 3.2 r eceive s ide p ins ................................ ................................ ................................ ................................ ........ 16 3.3 p arallel c ontrol p ort p ins ................................ ................................ ................................ ................. 18 3.4 e xtended s ystem i nformation b us ................................ ................................ ................................ ..... 20 3.5 jtag t est a ccess p ort p ins ................................ ................................ ................................ ................... 20 3.6 l ine i nterface p ins ................................ ................................ ................................ ................................ .... 21 3.7 s upply p ins ................................ ................................ ................................ ................................ ................... 22 3.8 p inout ................................ ................................ ................................ ................................ ............................ 23 3.9 p ackage ................................ ................................ ................................ ................................ ......................... 29 4. parallel port ................................ ................................ ................................ ................................ ............ 30 4.1 r egister m ap ................................ ................................ ................................ ................................ ............... 30 5. special per - channel register ope ration ................................ ................................ ......... 36 6. programming model ................................ ................................ ................................ .............................. 38 6.1 p ower - u p s equence ................................ ................................ ................................ ................................ .. 39 6.1.1 master mode register ................................ ................................ ................................ .................... 39 6.2 i nterrupt h andling ................................ ................................ ................................ ................................ .. 40 6.3 s tatus r egist ers ................................ ................................ ................................ ................................ ........ 40 6.4 i nformation r egisters ................................ ................................ ................................ ............................ 41 6.5 i nterrupt i nformation r egisters ................................ ................................ ................................ ........ 41 7. clock map ................................ ................................ ................................ ................................ ....................... 42 8. t1 framer/formatter control registers ................................ ................................ ......... 43 8.1 t1 c ontrol r egisters ................................ ................................ ................................ .............................. 43 8.2 t1 t ransmit t ransparency ................................ ................................ ................................ .................... 48 8.3 t1 r eceive - s ide d igital - m illiwatt c ode g eneration ................................ ................................ . 48 8.4 t1 i nformation r egister ................................ ................................ ................................ ........................ 50 9. e1 framer/formatter control registers ................................ ................................ ......... 52 9.1 e1 c ontrol r egisters ................................ ................................ ................................ .............................. 52 9.2 a utomatic a larm g eneration ................................ ................................ ................................ ............. 56 9.3 e1 i nformation r egisters ................................ ................................ ................................ ....................... 57 10. common control and s tatus registers ................................ ................................ ......... 59 11. i/o pin configuratio n options ................................ ................................ ................................ ... 66
product preview DS21Q55 9 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 12. loopback configurati on ................................ ................................ ................................ ............. 68 12.1 p er - c hannel l oopback ................................ ................................ ................................ ........................... 70 13. error count register s ................................ ................................ ................................ ................. 72 13.1 l ine c ode v iolation c ount r egister (lcvcr) ................................ ................................ .............. 73 13.2 p ath c ode v iolation c ount r egister (pcvcr) ................................ ................................ ............. 75 13.3 f ram es o ut o f s ync c ount r egister (foscr) ................................ ................................ ............... 76 13.4 e - b it c ounter r egister (ebcr) ................................ ................................ ................................ ........... 78 14. ds0 monitoring funct ion ................................ ................................ ................................ .............. 79 14.1 t ransmit ds0 m onitor r egisters ................................ ................................ ................................ ........ 79 14.2 r eceive ds0 m onitor r egisters ................................ ................................ ................................ ........... 80 15. signaling operation ................................ ................................ ................................ ......................... 81 15.1 r eceive s ignaling ................................ ................................ ................................ ................................ ...... 81 15.1.1 processor - based receive signaling ................................ ................................ ......................... 82 15.1.2 hardware - based receive signaling ................................ ................................ .......................... 82 15.2 t ransmit s ignaling ................................ ................................ ................................ ................................ ... 87 15.2.1 processor - based transmit signaling ................................ ................................ ........................ 87 15.2.2 software signaling insertion enable registe rs, e1 cas mode ................................ ....... 93 15.2.3 software signaling insertion enable registers, t1 mode ................................ .................. 95 16. per - channel idle code ge neration ................................ ................................ ..................... 97 16.1 i dle c ode p rogramming e xamples ................................ ................................ ................................ ...... 98 17. channel blocking reg isters ................................ ................................ ................................ .. 103 18. elastic stores opera tion ................................ ................................ ................................ ......... 106 18.1 r eceive s ide ................................ ................................ ................................ ................................ .............. 110 18.1.1 t1 mode ................................ ................................ ................................ ................................ ............ 110 18.1.2 e1 mo de ................................ ................................ ................................ ................................ ............ 110 18.2 t ransmit s ide ................................ ................................ ................................ ................................ ........... 111 18.2.1 t1 mode ................................ ................................ ................................ ................................ ............ 111 18.2.2 e1 mode ................................ ................................ ................................ ................................ ............ 111 18.3 e lastic s tores i nitialization ................................ ................................ ................................ ............. 111 18.4 m ini mum - d elay m ode ................................ ................................ ................................ ........................... 111 19. g.706 intermediate c rc - 4 updating (e1 mode only) ................................ ................ 113 20. t1 bit oriented code (boc) controller ................................ ................................ ......... 114 20.1 t ransmit boc ................................ ................................ ................................ ................................ .......... 114 20.2 r eceive boc ................................ ................................ ................................ ................................ ............. 114 21. additional (sa) and international (si) b it operation (e1 onl y) ................. 118 21.1 h ardware s cheme (m ethod 1) ................................ ................................ ................................ ........... 118 21.2 i nternal r egister s cheme b ased o n d oubl e - f rame (m ethod 2) ................................ .......... 118 21.3 i nternal r egister s cheme b ased o n crc4 m ultiframe (m ethod 3) ................................ ... 121 22. hdlc controllers ................................ ................................ ................................ ............................ 132 22.1 b asic o peration d etails ................................ ................................ ................................ ...................... 132 22.2 hdlc c onfiguration ................................ ................................ ................................ ............................ 134 22.2.1 fifo control ................................ ................................ ................................ ................................ .... 136 22.3 hdlc m apping ................................ ................................ ................................ ................................ ......... 137 22.3.1 receive ................................ ................................ ................................ ................................ .............. 137 22.3.2 transmit ................................ ................................ ................................ ................................ ............. 139 22.3.3 fifo information ................................ ................................ ................................ ............................ 144
product preview DS21Q55 10 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.3.4 receive packet bytes available ................................ ................................ ............................... 144 22.3.5 hdlc fifos ................................ ................................ ................................ ................................ .... 145 22.4 r eceive hdlc c ode e xample ................................ ................................ ................................ ............. 146 22.5 l egacy f dl s upport (t1 m ode ) ................................ ................................ ................................ ......... 146 22.5.1 receive section ................................ ................................ ................................ .............................. 146 22.5.2 transmit section ................................ ................................ ................................ ............................. 148 22.6 d4/slc ? 96 o peration ................................ ................................ ................................ ............................ 148 23. line interface unit (liu) ................................ ................................ ................................ ................ 149 23.1 liu o peration ................................ ................................ ................................ ................................ .......... 150 23.2 liu r eceiver ................................ ................................ ................................ ................................ ............. 150 23.2.1 receive level indicator ................................ ............................... error! bookmark not defined. 23.2.2 receive g.703 synchronization sig nal (e1 mode) ................................ ............................ 151 23.2.3 monitor mode ................................ ................................ ................................ ................................ ... 151 23.3 liu t ransmitter ................................ ................................ ................................ ................................ ..... 152 23.3.1 transmit short - circuit detector/limiter ................................ ................................ .................. 152 23.3.2 transmit open - circu it detector ................................ ................................ ................................ 152 23.3.3 transmit bpv error insertion ................................ ................................ ................................ ..... 152 23.3.4 transmit g.703 synchronization signal (e1 mode) ................................ ........................... 152 23.4 mclk p rescaler ................................ ................................ ................................ ................................ ..... 153 23.5 j itter a ttenuator ................................ ................................ ................................ ................................ .. 153 23.6 cmi (c ode m ark i nversion ) o ption ................................ ................................ ................................ . 153 23.7 liu c ontrol r egisters ................................ ................................ ................................ ......................... 154 23.8 r ecommended c ircuits ................................ ................................ ................................ ......................... 164 23.9 c omponent s pec ifications ................................ ................................ ................................ ................... 166 24. programmable in - band loop code gener ation and detection ................ 170 25. bert function ................................ ................................ ................................ ................................ ....... 177 25.1 bert r egister d escription ................................ ................................ ................................ ................. 178 25.2 ber t r epetitive p attern s et ................................ ................................ ................................ ............. 183 25.3 bert b it c ounter ................................ ................................ ................................ ................................ .. 184 25.4 bert e rror c ounter ................................ ................................ ................................ ............................ 185 26. payload error insert ion function ................................ ................................ ................... 186 26.1 n umber o f e rror r egisters ................................ ................................ ................................ ............... 188 26.1.1 number of errors left register ................................ ................................ ................................ 189 27. interleaved pcm bus operation ................................ ................................ ........................... 190 27.1 c hannel i nterleave m ode ................................ ................................ ................................ .................. 190 27.2 f rame i nter leave m ode ................................ ................................ ................................ ....................... 190 28. extended system info rmation bus (esib) ................................ ................................ ...... 193 29. programmable backpla ne clock synthesizer ................................ ...................... 197 30. fractional t1/e1 sup port ................................ ................................ ................................ ........... 198 31. jtag - boundary - scan architecture an d test - access port ......................... 199 31.1 i nstruction r egister ................................ ................................ ................................ ............................. 203 31.2 t est r egisters ................................ ................................ ................................ ................................ .......... 205 31.3 b oundary s can r egister ................................ ................................ ................................ ..................... 205 31.4 b ypass r egister ................................ ................................ ................................ ................................ ...... 205 31.5 i dentification r egister ................................ ................................ ................................ ........................ 205 32. functional timing di agrams ................................ ................................ ................................ .... 208 32.1 t1 m ode ................................ ................................ ................................ ................................ ...................... 208
product preview DS21Q55 11 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 32.2 e1 m ode ................................ ................................ ................................ ................................ ...................... 218 33. operating parameters ................................ ................................ ................................ ................. 231 34. ac timing parameters and diagrams ................................ ................................ ............... 233 34.1 m ultipexed b us ac c haracteristics ................................ ................................ .............................. 233 34.2 n onmultiplexed b us ac c haracteristics ................................ ................................ .................... 236 34.3 r eceive s ide ac c haracteristics ................................ ................................ ................................ ..... 239 34.4 t ransmit ac c haracteristics ................................ ................................ ................................ ........... 243 35. mechanical descripti ons ................................ ................................ ................................ ........... 247
product preview DS21Q55 12 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 1.2 document revision history 1) initial preliminary release
product preview DS21Q55 13 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 2. block diagram a simplified block diagram showing the major components of the DS21Q55 is shown in figure 4 - 1. details are shown in subsequent figures. the block diagram is then divided into three functional blocks: liu, framer, and backplane interface. block diagram figure 4 - 1 receive side framer transmit side formatter elastic store tsync tclk tchclk tser tchblk rchclk rchblk rmsync tssync tsysclk rser rsysclk rsync rfsync tlink tlclk timing control elastic store sync control timing control rlos/lotc local loopback tring ttip jitter attenuator either transmit or receive path receive line i/f clock / data recovery rring rtip remote loopback vco / pll bpclk 8.192mhz clock synthesizer rclk parallel control port (routed to all blocks) d0/ad0 bts int* wr*(r/w*) rd*(ds*) cs1* tstrst a0 mux transmit line i/f data clock sync framer loopback hdlc/boc controller lotc mux hdlc/boc controller sync clock data rlink rlclk transceiver #2 transceiver #3 transceiver #4 d1/ad1 d2/ad2 d3/ad3 d4/ad4 d5/ad5 d6/ad6 d7/ad7 a1 a2 a3 a4 a5 a6 a7/ale(as) mclk1 common mclk cs2* cs3* cs4* tposo tnego tclko tposi tnegi tclki mux mux rposo rnego rclko rposi rnegi rclki liuci esib esibrd esibs0 esibs1 signaling buffer tsig rsigf rsig signaling buffer jtag port jtclk jttst jtms jtdi jtdo mclk2
product preview DS21Q55 14 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 3. pin function description 3.1 transmit side pins signal name: tclk x signal description: transmit clock signal type: input a 1.544 mhz or a 2.048mhz primary clock. used to clock data throu gh the transmit - side formatter. signal name: tser x signal description: transmit serial data signal type: input transmit nrz serial data. sampled on the falling edge of tclk when the transmit - side elastic store is disabled. sampled on the f alling edge of tsysclk when the transmit - side elastic store is enabled. signal name: tchclk x signal description: transmit channel clock signal type: output a 192khz (t1) or 256khz (e1) clock that pulses high during the lsb of each channe l. can also be programmed to output a gated transmit - bit clock for fractional t1/e1 applications. synchronous with tclk when the transmit - side elastic store is disabled. synchronous with tsysclk when the transmit - side elastic store is enabled. useful for p arallel - to - serial conversion of channel data. signal name: tchblk x signal description: transmit channel block signal type: output a user - programmable output that can be forced high or low during any of the channels. synchronous with tcl k when the transmit - side elastic store is disabled. synchronous with tsysclk when the transmit - side elastic store is enabled. useful for locating individual channels in drop - and - insert applications, for external per - channel loopback, and for per - channel co nditioning. signal name: tsysclk x signal description: transmit system clock signal type: input 1.544mhz, 2.048mhz, 4.096mhz, 8.192mhz, or 16.384mhz clock. only used when the transmit - side elastic - store function is enabled. should be ti ed low in applications that do not use the transmit - side elastic store. see interleaved pcm bus operation for details on 4.096mhz, 8.192mhz, and 16.384mhz operation using the ibo. signal name: tlclk x signal description: transmit link clock signal type: output demand clock for the transmit link data [tlink] input. t1 mode: a 4khz or 2khz (zbtsi) clock. e1 mode: a 4khz to 20khz clock. signal name: tlink x signal description: transmit link data signal type: input if enable d, this pin will be sampled on the falling edge of tclk for data insertion into either the fdl stream (esf) or the fs - bit position (d4) or the z ? bit position (zbtsi) or any combination of the sa bit positions (e1).
product preview DS21Q55 15 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . signal name: tsync x sign al description: transmit sync signal type: input/output a pulse at this pin will establish either frame or multiframe boundaries for the transmit side. can be programmed to output either a frame or multiframe pulse. if this pin is set to output pulses at frame boundaries, it can also be set via iocr1 .3 to output double - wide pulses at signaling frames in t1 mode. signal name: tssync x signal description: transmit system sync signal type: input only used when the transmit - si de elastic store is enabled. a pulse at this pin will establish either frame or multiframe boundaries for the transmit side. should be tied low in applications that do not use the transmit - side elastic store. signal name: tsig x signal descri ption: transmit signaling input signal type: input when enabled, this input will sample signaling bits for insertion into outgoing pcm data stream. sampled on the falling edge of tclk when the transmit - side elastic store is disabled. sampled on the falli ng edge of tsysclk when the transmit - side elastic store is enabled. signal name: tposo x signal description: transmit positive data output signal type: output updated on the rising edge of tclko with the bipolar data out of the transmit - s ide formatter. can be programmed to source nrz data via the output - data format (iocr1 .0) - control bit. this pin is normally tied to tposi. signal name: tnego x signal description: transmit negative data output signal type: outp ut updated on the rising edge of tclko with the bipolar data out of the transmit - side formatter. this pin is normally tied to tnegi. signal name: tclko x signal description: transmit clock output signal type: output buffered clock that is used to clock data through the transmit - side formatter (either tclk or rclki). this pin is normally tied to tclki. signal name: tposi x signal description: transmit positive data input signal type: input sampled on the falling edge of tcl ki for data to be transmitted out onto the t1 line. can be internally connected to tposo by tying the liuc pin high. tposi and tnegi can be tied together in nrz applications.
product preview DS21Q55 16 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . signal name: tnegi x signal description: transmit negative data i nput signal type: input sampled on the falling edge of tclki for data to be transmitted out onto the t1 line. can be internally connected to tnego by tying the liuc pin high. tposi and tnegi can be tied together in nrz applications. signal name: tclki x signal description: transmit clock input signal type: input line interface transmit clock. can be internally connected to tclko by tying the liuc pin high. 3.2 receive side pins signal name: rlink x signal description: receive link data signal type: output t1 mode: updated with either fdl data (esf) or fs bits (d4) or z bits (zbtsi) one rclk before the start of a frame. e1 mode: updated with the full e1 data stream on the rising edge of rclk. signal name: rlclk x signal description: receive link clock signal type: output t1 mode: a 4khz or 2khz (zbtsi) clock for the rlink output. e1 mode: a 4khz to 20khz clock. signal name: rclk x signal description: receive clock signal type: output 1.544mhz ( t1) or 2.048mhz (e1) clock that is used to clock data through the receive - side framer. signal name: rchclk x signal description: receive channel clock signal type: output a 192khz (t1) or 256khz (e1) clock that pulses high during the lsb of each channel can also be programmed to output a gated receive - bit clock for fractional t1/e1 applications. synchronous with rclk when the receive - side elastic store is disabled. synchronous with rsysclk when the receive - side elastic store is enabled. us eful for parallel - to - serial conversion of channel data. signal name: rchblk x signal description: receive channel block signal type: output a user - programmable output that can be forced high or low during any of the 24 t1 or 32 e1 channe ls. synchronous with rclk when the receive - side elastic store is disabled. synchronous with rsysclk when the receive - side elastic store is enabled. also useful for locating individual channels in drop - and - insert applications, for external per - channel loopb ack, and for per - channel conditioning. see channel blocking registers . signal name: rser x signal description: receive serial data signal type: output received nrz serial data. updated on rising edges of rclk when the receive - side elastic s tore is disabled. updated on the rising edges of rsysclk when the receive - side elastic store is enabled.
product preview DS21Q55 17 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . signal name: rsync x signal description: receive sync signal type: input/output an extracted pulse, one rclk wide, is output at this pin which identifies either frame (iocr1 .5 = 0) or multiframe (iocr1.5 = 1) boundaries. if set to output - frame boundaries then via iocr1.6, rsync can also be set to output double - wide pulses on signaling frames in t1 mode. if the receive - sid e elastic store is enabled, then this pin can be enabled to be an input via iocr1.4 at which a frame or multiframe boundary pulse is applied. signal name: rfsync x signal description: receive frame sync signal type: output an extracted 8k hz pulse, one rclk wide, is output at this pin, which identifies frame boundaries. signal name: rmsync x signal description: receive multiframe sync signal type: output an extracted pulse, one rclk wide (elastic store disabled) or one rsy sclk wide (elastic store enabled), is output at this pin, which identifies multiframe boundaries. signal name: rsysclk x signal description: receive system clock signal type: input 1.544mhz, 2.048mhz, 4.096mhz, or 8.192mhz clock. only us ed when the receive - side elastic - store function is enabled. should be tied low in applications that do not use the receive - side elastic store. see interleaved pcm bus operation for details on 4.096mhz and 8.192mhz operation using the ibo. signal name: rsi g x signal description: receive signaling output signal type: output outputs signaling bits in a pcm format. updated on rising edges of rclk when the receive - side elastic store is disabled. updated on the rising edges of rsysclk when the rec eive - side elastic store is enabled. signal name: rlos/lotc x signal description: receive loss of sync/loss of transmit clock signal type: output a dual - function output that is controlled by the ccr1 .0 control bit. this pi n can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the tclk pin has not been toggled for 5 m sec. signal name: rsigf x signal description: receive signaling freeze s ignal type: output set high when the signaling data is frozen via either automatic or manual intervention. used to alert downstream equipment of the condition.
product preview DS21Q55 18 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . signal name: bpclk x signal description: back plane clock signal type: outpu t a user - selectable synthesized clock output that is referenced to the clock that is output at the rclk pin. signal name: rposo x signal description: receive positive data output signal type: output updated on the rising edge of rclko wi th bipolar data out of the line interface. this pin is normally tied to rposi. signal name: rnego x signal description: receive negative data output signal type: output updated on the rising edge of rclko with the bipolar data out of the line interface. this pin is normally tied to rnegi. signal name: rclko x signal description: receive clock output signal type: output buffered recovered clock from the network. this pin is normally tied to rclki. signal name: rposi x signal description: receive positive data input signal type: input sampled on the falling edge of rclki for data to be clocked through the receive - side framer. rposi and rnegi can be tied together for a nrz interface. can be internally connect ed to rposo by tying the liuc pin high. signal name: rnegi x signal description: receive negative data input signal type: input sampled on the falling edge of rclki for data to be clocked through the receive - side framer. rposi and rnegi ca n be tied together for a nrz interface. can be internally connected to rnego by tying the liuc pin high. signal name: rclki x signal description: receive clock input signal type: input clock used to clock data through the receive - side fram er. this pin is normally tied to rclko. can be internally connected to rclko by tying the liuc pin high. 3.3 parallel control port pins signal name: int * signal description: interrupt signal type: output flags host controller during events, a larms, and conditions defined in the status registers. active - low open - drain output. signal name: tstrst signal description: 3 - state control and device reset signal type: input a dual - function pin. a zero - to - one transition issues a hardw are reset to the DS21Q55 register set. a reset clears all configuration registers. configuration register contents are set to zero. leaving tstrst high will 3 - state all output and i/o pins (including the parallel control port). set low for normal operation . useful in - board level testing.
product preview DS21Q55 19 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . signal name: mux signal description: bus operation signal type: input set low to select nonmultiplexed bus operation. set high to select multiplexed bus operation. signal name: d0/ad0 to d7/ad7 signal des cription: data bus [d0 to d7] or address/data bus signal type: input/output in nonmultiplexed bus operation (mux = 0), it serves as the data bus. in multiplexed bus operation (mux = 1), it serves as an 8 - bit, multiplexed address/data bus. signal name: a 0 to a6 signal description: address bus signal type: input in nonmultiplexed bus operation (mux = 0), it serves as the address bus. in multiplexed bus operation (mux = 1), these pins are not used and should be tied low. signal name: bts s ignal description: bus type select signal type: input strap high to select motorola bus timing; strap low to select intel bus timing. this pin controls the function of the rd*(ds*), a7/ale(as), and wr*(r/w*) pins. if bts = 1, then these pins assume the f unction listed in parenthesis (). signal name: rd* (ds* ) signal description: read input - data strobe signal type: input rd* and ds* are active - low signals. ds active high when mux = 0. see bus timing diagrams. signal name: cs1 * signal description: chip select for transceiver #1 signal type: input must be low to read or write to transceiver #1 of the device. cs1* is an active - low signal. signal name: cs2 * signal description: chip select for transceiver #2 signal type: input must be low to read or write to transceiver #2 of the device. cs2* is an active - low signal. signal name: cs3 * signal description: chip select for transceiver #3 signal type: input must be low to read or write to transc eiver #3 of the device. cs3* is an active - low signal. signal name: cs4 * signal description: chip select for transceiver #4 signal type: input must be low to read or write to transceiver #4 of the device. cs4* is an active - low signal.
product preview DS21Q55 20 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . si gnal name: a7/ale (as ) signal description: a7 or address latch enable(address strobe) signal type: input in nonmultiplexed bus operation (mux = 0), it serves as the upper address bit. in multiplexed bus operation (mux = 1), it serv es to demultiplex the bus on a positive - going edge. signal name: wr* (r/w* ) signal description: write input(read/write) signal type: input wr* is an active - low signal. 3.4 extended system information bus signal name: esibs0 x signal description: extended system information bus select 0 signal type: input/output used to group two DS21Q55s into a bus - sharing mode for alarm and status reporting. see extended system information bus (esib) for more details. signal name : esibs1 x signal description: extended system information bus select 1 signal type: input/output used to group two DS21Q55s into a bus - sharing mode for alarm and status reporting. see extended system information bus (esib) for more detai ls. signal name: esibrd x signal description: extended system information bus read signal type: input/output used to group two DS21Q55s into a bus - sharing mode for alarm and status reporting. see extended system information bus (esib) fo r more details. 3.5 jtag test access port pins signal name: jtrst signal description: ieee 1149.1 test reset signal type: input jtrst is used to asynchronously reset the test access port controller. after power - up, jtrst must be toggled from low to high. this action will set the device into the jtag device id mode. normal device operation is restored by pulling jtrst low. jtrst is pulled high internally via a 10k resistor operation. signal name: jtms signal description: ieee 1 149.1 test mode select signal type: input this pin is sampled on the rising edge of jtclk and is used to place the test - access port into the various defined ieee 1149.1 states. this pin has a 10k pullup resistor.
product preview DS21Q55 21 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . signal name: jtclk signa l description: ieee 1149.1 test clock signal signal type: input this signal is used to shift data into jtdi on the rising edge and out of jtdo on the falling edge. signal name: jtdi signal description: ieee 1149.1 test data input signal type: input test instructions and data are clocked into this pin on the rising edge of jtclk. this pin has a 10k pullup resistor. signal name: jtdo signal description: ieee 1149.1 test data output signal type: output test instructions an d data are clocked out of this pin on the falling edge of jtclk. if not used, this pin should be left unconnected. 3.6 line interface pins signal name: mclk1 signal description: master clock input for transceivers 1 & 2 signal type: input a (5 0ppm) clock source. this clock is used internally for both clock/data recovery and for the jitter attenuator for both t1 and e1 modes. a quartz crystal of 2.048mhz can be applied across mclk and xtald instead of the clock source. the clock rate can be 16.3 84mhz, 8.192mhz, 4.096mhz, or 2.048mhz. when using the DS21Q55 in t1 - only operation a 1.544mhz (50ppm) clock source can be used. mclk1 and mclk2 may be driven from a common clock. signal name: mclk2 signal description: master clock input fo r transceivers 3 & 4 signal type: input a (50ppm) clock source. this clock is used internally for both clock/data recovery and for the jitter attenuator for both t1 and e1 modes. a quartz crystal of 2.048mhz can be applied across mclk and xtald instead o f the clock source. the clock rate can be 16.384mhz, 8.192mhz, 4.096mhz, or 2.048mhz. when using the DS21Q55 in t1 - only operation a 1.544mhz (50ppm) clock source can be used. mclk1 and mclk2 may be driven from a common clock. signal name: liuc signal description: line interface connect signal type: input tie low to separate the line interface circuitry from the framer/formatter circuitry and activate the tposi/tnegi/tclki/rposi/rnegi/rclki pins. tie high to connect the line interface circu itry to the framer/formatter circuitry and deactivate the tposi/tnegi/tclki/rposi/rnegi/rclki pins. when liuc is tied high, the tposi/tnegi/tclki/ rposi/rnegi/rclki pins should be tied low. signal name: rtip x and rring x signal description: receive tip and ring signal type: input analog inputs for clock recovery circuitry. these pins connect via a 1:1 transformer to the network. see line interface unit for details.
product preview DS21Q55 22 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . signal name: ttip x and tring x si gnal description: transmit tip and ring signal type: output analog line driver outputs. these pins connect via a 1:2 step - up transformer to the network. see line interface unit for details. 3.7 supply pins signal name: dv dd signal description: digital posi tive supply signal type: supply 3.3v 5%. should be tied to the rv dd and tv dd pins. signal name: rv dd signal description: receive analog positive supply signal type: supply 3.3v 5%. should be tied to the dv dd and tv dd pins. signal name: tv dd sign al description: transmit analog positive supply signal type: supply 3.3v 5% should be tied to the rv dd and dv dd pins. signal name: dv ss signal description: digital signal ground signal type: supply should be tied to the rv ss and tv ss pins. signal n ame: rv ss signal description: receive analog signal ground signal type: supply 0.0v. should be tied to dv ss and tv ss . signal name: tv ss signal description: transmit analog signal ground signal type: supply 0.0v. should be tied to dv ss and rv ss .
product preview DS21Q55 23 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 3.8 pinout DS21Q55 pin description table 5 - 1 note: signal is common to all transceivers unless otherwise stated pin symbol type description u3 a0 i address bus bit 0 (lsb). l17 a1 i address bus bit 1. v2 a2 i address bus bit 2. t4 a3 i address bus bit 3. v8 a4 i address bus bit 4. h4 a5 i address bus bit 5. u8 a6 i address bus bit 6. p4 a7/ale(as) i address bus bit 7 (msb) / address latch enable. m1 bpclk1 o back plane clock, transceiver # 1. h17 bpclk2 o back plane clock, transceiver # 2. f4 bp clk3 o back plane clock, transceiver # 3. v13 bpclk4 o back plane clock, transceiver # 4. p2 bts i bus type select (0 = intel / 1 = motorola), p3 cs1* i chip select, transceiver # 1. a14 cs2* i chip select, transceiver # 2. b5 cs3* i chip select, tran sceiver # 3. k17 cs4* i chip select, transceiver # 4. u11 d0/ad0 i/o data bus bit 0/ address/data bus bit 0 (lsb). j19 d1/ad1 i/o data bus bit 1/ address/data bus bit 1. w15 d2/ad2 i/o data bus bit 2/address/data bus bit 2. u7 d3/ad3 i/o data bus bit 3/address/data bus bit 3. u9 d4/ad4 i/o data bus bit 4/address/data bus bit 4. u5 d5/ad5 i/o data bus bit 5/address/data bus bit 5. v4 d6/ad6 i/o data bus bit 6/address/data bus bit 6. u4 d7/ad7 i/o data bus bit 7/address/data bus bit 7 (msb). j3 dvdd 1 ? digital positive supply. n4 dvdd1 ? digital positive supply. u2 dvdd1 ? digital positive supply. v5 dvdd1 ? digital positive supply. b12 dvdd2 ? digital positive supply. c12 dvdd2 ? digital positive supply. c16 dvdd2 ? digital positive supply. d 18 dvdd2 ? digital positive supply. a9 dvdd3 ? digital positive supply. b3 dvdd3 ? digital positive supply. b6 dvdd3 ? digital positive supply. c4 dvdd3 ? digital positive supply. g20 dvdd4 ? digital positive supply. m17 dvdd4 ? digital positive supp ly. m20 dvdd4 ? digital positive supply. p18 dvdd4 ? digital positive supply. h3 dvss1 ? digital signal ground. u6 dvss1 ? digital signal ground. w8 dvss1 ? digital signal ground. a17 dvss2 ? digital signal ground.
product preview DS21Q55 24 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . pin symbol type description a20 dvss2 ? digital signal ground. b11 dvss2 ? digital signal ground. a5 dvss3 ? digital signal ground. b7 dvss3 ? digital signal ground. b9 dvss3 ? digital signal ground. h20 dvss4 ? digital signal ground l20 dvss4 ? digital signal ground n17 dvss4 ? digital signal ground j4 esibr d1 ? extended system information bus read, transceiver # 1. c13 esibrd2 ? extended system information bus read, transceiver # 2. c3 esibrd3 ? extended system information bus read, transceiver # 3. u13 esibrd4 ? extended system information bus read, tran sceiver # 4. w6 esibs0_1 i/o extended system information bus 0, transceiver # 1. f18 esibs0_2 i/o extended system information bus 0, transceiver # 2. d7 esibs0_3 i/o extended system information bus 0, transceiver # 3. t20 esibs0_4 i/o extended system i nformation bus 0, transceiver # 4. v9 esibs1_1 i/o extended system information bus 1, transceiver # 1. b17 esibs1_2 i/o extended system information bus 1, transceiver # 2. a6 esibs1_3 i/o extended system information bus 1, transceiver # 3. j20 esibs1_4 i/o extended system information bus 1, transceiver # 4. u1 int* o interrupt. y15 jtclk i jtag clock. n1 jtdi i jtag data input, transceiver #1 v19 jtdo o jtag data output. transceiver #4 w13 jtms i jtag test mode select. v18 jtrst* i jtag reset. k2 liuc i line interface connect. t1 mclk1 i master clock, transceiver #1 and, transceiver #3. w20 mclk2 i master clock, transceiver #2 and, transceiver #4. u10 mux i mux bus select. m2 rchblk1 o receive channel block, transceiver #1. g17 rchblk2 o rece ive channel block, transceiver #2. g4 rchblk3 o receive channel block, transceiver #3. y12 rchblk4 o receive channel block, transceiver #4. j1 rchclk1 o receive channel clock, transceiver #1. d14 rchclk2 o receive channel clock, transceiver #2. f3 rch clk3 o receive channel clock, transceiver #3. u14 rchclk4 o receive channel clock, transceiver #4. n3 rclk1 o receive clock output from the framer, transceiver #1. b13 rclk2 o receive clock output from the framer, transceiver #2. e3 rclk3 o receive clo ck output from the framer, transceiver #3. m18 rclk4 o receive clock output from the framer, transceiver #4. m4 rclki1 i receive clock input for the liu, transceiver #1. a15 rclki2 i receive clock input for the liu, transceiver #2. a4 rclki3 i receive clock input for the liu, transceiver #3. r17 rclki4 i receive clock input for the liu, transceiver #4. m3 rclko1 o receive clock output from the liu, transceiver #1. c14 rclko2 o receive clock output from the liu, transceiver #2. b4 rclko3 o receive cl ock output from the liu, transceiver #3. t17 rclko4 o receive clock output from the liu, transceiver #4. n2 rd*(ds*) i read input (data strobe) k4 rfsync1 o receive frame sync (before the receive elastic store), transceiver
product preview DS21Q55 25 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . pin symbol type description #1. d17 rfsync2 o receive fr ame sync (before the receive elastic store), transceiver #2. a2 rfsync3 o receive frame sync (before the receive elastic store), transceiver #3. v14 rfsync4 o receive frame sync (before the receive elastic store), transceiver #4. f1 rlclk1 o receive lin k clock, transceiver #1. a12 rlclk2 o receive link clock, transceiver #2. d3 rlclk3 o receive link clock, transceiver #3. k18 rlclk4 o receive link clock, transceiver #4. g2 rlink1 o receive link data, transceiver #1. a13 rlink2 o receive link data, t ransceiver #2. a3 rlink3 o receive link data, transceiver #3. u12 rlink4 o receive link data, transceiver #4. h2 rlos/lotc1 o receive loss of sync / loss of transmit clock, transceiver #1. e17 rlos/lotc2 o receive loss of sync / loss of transmit clock, transceiver #2. e1 rlos/lotc3 o receive loss of sync / loss of transmit clock, transceiver #3. v11 rlos/lotc4 o receive loss of sync / loss of transmit clock, transceiver #4. l1 rmsync1 o receive multiframe sync, transceiver #1. d16 rmsync2 o receive multiframe sync, transceiver #2. f2 rmsync3 o receive multiframe sync, transceiver #3. w16 rmsync4 o receive multiframe sync, transceiver #4. r3 rnegi1 i receive negative data for the framer, transceiver #1. d13 rnegi2 i receive negative data for the f ramer, transceiver #2. a1 rnegi3 i receive negative data for the framer, transceiver #3. p17 rnegi4 i receive negative data for the framer, transceiver #4. l3 rnego1 o receive negative data from the liu, transceiver #1. b15 rnego2 o receive negative da ta from the liu, transceiver #2. c2 rnego3 o receive negative data from the liu, transceiver #3. u17 rnego4 o receive negative data from the liu, transceiver #4. r4 rposi1 i receive positive data for the framer, transceiver #1. b14 rposi2 i receive pos itive data for the framer, transceiver #2. b2 rposi3 i receive positive data for the framer, transceiver #3. v15 rposi4 i receive positive data for the framer, transceiver #4. l4 rposo1 o receive positive data from the liu, transceiver #1. a16 rposo2 o receive positive data from the liu, transceiver #2. b1 rposo3 o receive positive data from the liu, transceiver #3. u15 rposo4 o receive positive data from the liu, transceiver #4. y11 rring1 i receive analog ring input, transceiver #1. y14 rring2 i r eceive analog ring input, transceiver #2. y17 rring3 i receive analog ring input, transceiver #3. y20 rring4 i receive analog ring input, transceiver #4. j2 rser1 o receive serial data, transceiver #1. d15 rser2 o receive serial data, transceiver #2. e2 rser3 o receive serial data, transceiver #3. w17 rser4 o receive serial data, transceiver #4. l2 rsig1 o receive signaling output, transceiver #1. b16 rsig2 o receive signaling output, transceiver #2. c1 rsig3 o receive signaling output, transceiver #3. y18 rsig4 o receive signaling output, transceiver #4. k1 rsigf1 o receive signaling freeze output, transceiver #1. c15 rsigf2 o receive signaling freeze output, transceiver #2.
product preview DS21Q55 26 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . pin symbol type description d2 rsigf3 o receive signaling freeze output, transceiver #3. v16 rsig f4 o receive signaling freeze output, transceiver #4. g1 rsync1 i/o receive sync, transceiver #1. d12 rsync2 i/o receive sync, transceiver #2. d1 rsync3 i/o receive sync, transceiver #3. v12 rsync4 i/o receive sync, transceiver #4. h1 rsysclk1 i recei ve system clock, transceiver #1. f17 rsysclk2 i receive system clock, transceiver #2. g3 rsysclk3 i receive system clock, transceiver #3. w14 rsysclk4 i receive system clock, transceiver #4. y10 rtip1 i receive analog tip input, transceiver #1. y13 rt ip2 i receive analog tip input, transceiver #2. y16 rtip3 i receive analog tip input, transceiver #3. y19 rtip4 i receive analog tip input, transceiver #4. p1 rvdd1 ? receive analog positive supply. j17 rvdd2 ? receive analog positive supply. e4 rvdd3 ? receive analog positive supply. w18 rvdd4 ? receive analog positive supply. r2 rvss1 ? receive analog signal ground t2 rvss1 ? receive analog signal ground h19 rvss2 ? receive analog signal ground j18 rvss2 ? receive analog signal ground d4 rvss3 ? receive analog signal ground d5 rvss3 ? receive analog signal ground v20 rvss4 ? receive analog signal ground w19 rvss4 ? receive analog signal ground w1 tchblk1 o transmit channel block, transceiver #1. f20 tchblk2 o transmit channel block, transce iver #2. c11 tchblk3 o transmit channel block, transceiver #3. u20 tchblk4 o transmit channel block, transceiver #4. v10 tchclk1 o transmit channel clock, transceiver #1. a18 tchclk2 o transmit channel clock, transceiver #2. b8 tchclk3 o transmit chan nel clock, transceiver #3. l18 tchclk4 o transmit channel clock, transceiver #4. y9 tclk1 i transmit clock, transceiver #1. b19 tclk2 i transmit clock, transceiver #2. b10 tclk3 i transmit clock, transceiver #3. m19 tclk4 i transmit clock, transceiver #4. v6 tclki1 i transmit clock input for the liu, transceiver #1. d19 tclki2 i transmit clock input for the liu, transceiver #2. c8 tclki3 i transmit clock input for the liu, transceiver #3. p20 tclki4 i transmit clock input for the liu, transceiver # 4. w7 tclko1 o transmit clock output from the framer, transceiver #1. e18 tclko2 o transmit clock output from the framer, transceiver #2. a7 tclko3 o transmit clock output from the framer, transceiver #3. p19 tclko4 o transmit clock output from the fra mer, transceiver #4. v3 tlclk1 o transmit link clock, transceiver #1. e20 tlclk2 o transmit link clock, transceiver #2. d6 tlclk3 o transmit link clock, transceiver #3. t18 tlclk4 o transmit link clock, transceiver #4. w5 tlink1 i transmit link data, transceiver #1. e19 tlink2 i transmit link data, transceiver #2.
product preview DS21Q55 27 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . pin symbol type description c6 tlink3 i transmit link data, transceiver #3. t19 tlink4 i transmit link data, transceiver #4. r1 tnegi1 i transmit negative data input for the liu, transceiver #1. f19 tnegi2 i transm it negative data input for the liu, transceiver #2. d8 tnegi3 i transmit negative data input for the liu, transceiver #3. r20 tnegi4 i transmit negative data input for the liu, transceiver #4. t3 tnego1 o transmit negative data output from framer, trans ceiver #1. b20 tnego2 o transmit negative data output from framer, transceiver #2. d9 tnego3 o transmit negative data output from framer, transceiver #3. n20 tnego4 o transmit negative data output from framer, transceiver #4. w3 tposi1 i transmit posit ive data input for the liu, transceiver #1. c20 tposi2 i transmit positive data input for the liu, transceiver #2. a8 tposi3 i transmit positive data input for the liu, transceiver #3. r19 tposi4 i transmit positive data input for the liu, transceiver # 4. v7 tposo1 o transmit positive data output from framer, transceiver #1. c19 tposo2 o transmit positive data output from framer, transceiver #2. c9 tposo3 o transmit positive data output from framer, transceiver #3. n19 tposo4 o transmit positive data output from framer, transceiver #4. y2 tring1 o transmit analog ring output, transceiver #1. y4 tring2 o transmit analog ring output, transceiver #2. y6 tring3 o transmit analog ring output, transceiver #3. y8 tring4 o transmit analog ring output, tra nsceiver #4. w9 tser1 i transmit serial data, transceiver #1. c17 tser2 i transmit serial data, transceiver #2. c10 tser3 i transmit serial data, transceiver #3. k20 tser4 i transmit serial data, transceiver #4. w10 tsig1 i transmit signaling input, t ransceiver #1. c18 tsig2 i transmit signaling input, transceiver #2. a10 tsig3 i transmit signaling input, transceiver #3. l19 tsig4 i transmit signaling input, transceiver #4. w12 tssync1 i transmit system sync, transceiver #1. b18 tssync2 i transmit system sync, transceiver #2. d10 tssync3 i transmit system sync, transceiver #3. k19 tssync4 i transmit system sync, transceiver #4. u16 tstrst i test/reset v1 tsync1 i/o transmit sync, transceiver #1. d20 tsync2 i/o transmit sync, transceiver #2. c 7 tsync3 i/o transmit sync, transceiver #3. r18 tsync4 i/o transmit sync, transceiver #4. w11 tsysclk1 i transmit system clock, transceiver #1. a19 tsysclk2 i transmit system clock, transceiver #2. a11 tsysclk3 i transmit system clock, transceiver #3. n18 tsysclk4 i transmit system clock, transceiver #4. y1 ttip1 o transmit analog tip output, transceiver #1. y3 ttip2 o transmit analog tip output, transceiver #2. y5 ttip3 o transmit analog tip output, transceiver #3. y7 ttip4 o transmit analog tip o utput, transceiver #4. w2 tvdd1 ? transmit analog positive supply. g19 tvdd2 ? transmit analog positive supply. d11 tvdd3 ? transmit analog positive supply. u19 tvdd4 ? transmit analog positive supply. w4 tvss1 ? transmit analog signal ground.
product preview DS21Q55 28 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . pin symbol type description g18 tv ss2 ? transmit analog signal ground. c5 tvss3 ? transmit analog signal ground. u18 tvss4 ? transmit analog signal ground. k3 wr* (r/w*) i write input (read/write).
product preview DS21Q55 29 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 3.9 package DS21Q55 pin diagram, 27mm bga figure 5 - 1 the diagram shown below is the l ead pattern that will be placed on the target pcb. this is the same pattern that would be seen as viewed from the top. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a rnegi 3 rfsync 3 rlink 3 rclki 3 dvss 3 esibs1 3 tclko 3 tposi 3 dvdd 3 tsig 3 t sysclk 3 rlclk 2 rlink 2 cs 2* rclki 2 rposo 2 dvss 2 tchclk 2 tsysclk 2 dvss 2 b rposo 3 rposi 3 dvdd 3 rclko 3 cs 3* dvdd 3 dvss 3 tchclk 3 dvss 3 tclk 3 dvss 2 dvdd 2 rclk 2 rposi 2 rnego 2 rsig 2 esibs1 2 tssync 2 tclk 2 tnego 2 c rsig 3 rnego 3 eisb rd 3 dvdd 3 tvss 3 tlink 3 tsync 3 tclki 3 tposo 3 tser 3 tchblk 3 dvdd 2 eisbrd 2 rclko 2 rsigf 2 dvdd 2 tser 2 tsig 2 tposo 2 tposi 2 d rsync 3 rsigf 3 rlclk 3 rvss 3 rvss 3 tlclk 3 esibs0 3 tnegi 3 tnego 3 tssync 3 tvdd 3 rsync 2 rnegi 2 rchclk 2 rser 2 rmsync 2 rfsync 2 dvdd 2 tclki 2 tsync 2 e rlos 3 rser 3 rclk 3 rvdd 3 rlos 2 tclko 2 tlink 2 tlclk 2 f rlclk 1 rmsync 3 rchclk 3 bpclk 3 rsysclk 2 esibs0 2 tnegi 2 tchblk 2 g rsync 1 rlink 1 rsysclk 3 rchblk 3 rchb lk 2 tvss 2 tvdd 2 dvdd 4 h rsysclk 1 rlos 1 dvss 1 a5 bpclk 2 nc rvss 2 dvss 4 j rchclk 1 rser 1 dvdd 1 eisbrd 1 rvdd 2 rvss 2 d1/ ad1 esibs1 4 k rsigf 1 liuc wr* rfsync 1 cs 4* rlclk 4 tssync 4 tser 4 l rmsync 1 rs ig 1 rnego 1 rposo 1 a1 tchclk 4 tsig 4 dvss 4 m bpclk 1 rchblk 1 rclko 1 rclki 1 dvdd 4 rclk 4 tclk 4 dvdd 4 n jtdi rd* rclk 1 dvdd 1 dvss 4 tsys clk4 tposo 4 tnego 4 p rvdd 1 bts cs 1* a7/al e(as) rnegi 4 dvdd 4 tclko 4 tclki 4 r tnegi 1 rvss 1 rnegi 1 rposi 1 rclki 4 tsync 4 tposi 4 tnegi 4 t mclk 1 rvss 1 tnego 1 a3 rclko 4 tlclk 4 tlink 4 esibs0 4 u int* dvdd 1 a0 d7/ ad7 d5/ ad5 dvss 1 d3/ ad3 a6 d4/ ad4 mux d0/ ad0 rlink 4 e isbrd 4 rchclk 4 rposo 4 tstrst rnego 4 tvss 4 tvdd 4 tchblk 4 v tsync 1 a2 tlclk 1 d6/ ad6 dvdd 1 tclki 1 tposo 1 a4 esibs1 1 tchclk 1 rlos 4 rsync 4 bpclk 4 rfsync 4 rposi 4 rsigf 4 nc jtrst* jtdo rvss 4 w tchblk 1 tvdd 1 tposi 1 tvss 1 tlink 1 esibs0 1 tclko 1 dvss 1 tser 1 tsig 1 tsysclk 1 tssync 1 jtms rsysclk 4 d2/ ad2 rmsync 4 rser 4 rvdd 4 rvss 4 mclk 2 y ttip 1 tring 1 ttip 2 tring 2 ttip 3 tring 3 ttip 4 tring 4 tclk 1 rtip 1 rring 1 rchblk 4 rtip 2 rring 2 jtclk rtip 3 rring 3 rsig 4 rtip 4 rr ing 4 note: locations c3, c13, j4, and u13 are used for the extended system information bus (esib). these pin locations on the ds21q352, ds21q354, DS21Q552, and DS21Q554 are connected to ground. when replacing a ds21qx5y with a DS21Q55b, these signals sh ould be routed to control logic in order to gain access to the esib. if these pins remain connected to ground, the esib function will be disabled.
product preview DS21Q55 30 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 4. parallel port the DS21Q55 is controlled via a nonmultiplexed (mux = 0) or a multiplexed (mux = 1) bus b y an external microcontroller or microprocessor. the DS21Q55 can operate with either intel or motorola bus timing configurations. if the bts pin is tied low, intel timing will be selected; if tied high, motorola timing will be selected. all motorola bus si gnals are listed in parenthesis (). see the timing diagrams in the ac electrical characteristics for more details. each of the four transceivers has a complete register set as shown below. there are four individual chip select signals (cs1*, cs2*, cs3*, cs4*) that are used select one of the four transceivers. 4.1 register map register map sorted by address table 6 - 1 address r/w register name register abbreviation page 00 master mode register mstrreg * 01 i/o configuration register 1 iocr1 * 02 i/o conf iguration register 2 iocr2 * 03 t1 receive control register 1 t1rcr1 * 04 t1 receive control register 2 t1rcr2 * 05 t1 transmit control register 1 t1tcr1 * 06 t1 transmit control register 2 t1tcr2 * 07 t1 common control register 1 t1ccr1 * 08 software signaling insertion enable 1 ssie1 * 09 software signaling insertion enable 2 ssie2 * 0a software signaling insertion enable 3 ssie3 * 0b software signaling insertion enable 4 ssie4 * 0c t1 receive digital milliwatt enable register 1 t 1rdmr1 * 0d t1 receive digital milliwatt enable register 2 t1rdmr2 * 0e t1 receive digital milliwatt enable register 3 t1rdmr3 * 0f device identification register idr * 10 information register 1 info1 * 11 information register 2 info2 * 12 info rmation register 3 info3 * 13 test register test * 14 interrupt information register 1 iir1 * 15 interrupt information register 2 iir2 * 16 status register 1 sr1 * 17 interrupt mask register 1 imr1 * 18 status register 2 sr2 * 19 interrupt ma sk register 2 imr2 * 1a status register 3 sr3 * 1b interrupt mask register 3 imr3 * 1c status register 4 sr4 * 1d interrupt mask register 4 imr4 * 1e status register 5 sr5 * 1f interrupt mask register 5 imr5 * 20 status register 6 sr6 * 21 interrupt mask register 6 imr6 * 22 status register 7 sr7 * 23 interrupt mask register 7 imr7 * 24 status register 8 sr8 * 25 interrupt mask register 8 imr8 *
product preview DS21Q55 31 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . address r/w register name register abbreviation page 26 status register 9 sr9 * 27 interrupt mask register 9 imr9 * 28 per - channel point er register pcpr * 29 per - channel data register 1 pcdr1 * 2a per - channel data register 2 pcdr2 * 2b per - channel data register 3 pcdr3 * 2c per - channel data register 4 pcdr4 * 2d information register 4 info4 * 2e information register 5 info5 * 2f information register 6 info6 * 30 information register 7 info7 * 31 hdlc #1 receive control h1rc * 32 hdlc #2 receive control h2rc * 33 e1 receive control register 1 e1rcr1 * 34 e1 receive control register 2 e1rcr2 * 35 e1 transmit contro l register 1 e1tcr1 * 36 e1 transmit control register 2 e1tcr2 * 37 boc control register bocc * 38 receive signaling change of state information 1 rsinfo1 * 39 receive signaling change of state information 2 rsinfo2 * 3a receive signaling chang e of state information 3 rsinfo3 * 3b receive signaling change of state information 4 rsinfo4 * 3c receive signaling change of state interrupt enable 1 rscse1 * 3d receive signaling change of state interrupt enable 2 rscse2 * 3e receive signaling c hange of state interrupt enable 3 rscse3 * 3f receive signaling change of state interrupt enable 4 rscse4 * 40 signaling control register sigcr * 41 error count configuration register ercnt * 42 line code violation count register 1 lcvcr1 * 43 li ne code violation count register 2 lcvcr2 * 44 path code violation count register 1 pcvcr1 * 45 path code violation count register 2 pcvcr2 * 46 frames out of sync count register 1 foscr1 * 47 frames out of sync count register 2 foscr2 * 48 e - bit count register 1 ebcr1 * 49 e - bit count register 2 ebcr2 * 4a loopback control register lbcr * 4b per - channel loopback enable register 1 pclr1 * 4c per - channel loopback enable register 2 pclr2 * 4d per - channel loopback enable register 3 pclr3 * 4e per - channel loopback enable register 4 pclr4 * 4f elastic store control register escr * 50 transmit signaling register 1 ts1 * 51 transmit signaling register 2 ts2 * 52 transmit signaling register 3 ts3 * 53 transmit signaling register 4 ts4 * 54 transmit signaling register 5 ts5 * 55 transmit signaling register 6 ts6 * 56 transmit signaling register 7 ts7 * 57 transmit signaling register 8 ts8 * 58 transmit signaling register 9 ts9 * 59 transmit signaling register 10 ts10 *
product preview DS21Q55 32 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . address r/w register name register abbreviation page 5a transmit signaling register 11 ts11 * 5b transmit signaling register 12 ts12 * 5c transmit signaling register 13 ts13 * 5d transmit signaling register 14 ts14 * 5e transmit signaling register 15 ts15 * 5f transmit signaling register 16 ts16 * 60 receive signaling register 1 rs1 * 61 receive signaling register 2 rs2 * 62 receive signaling register 3 rs3 * 63 receive signaling register 4 rs4 * 64 receive signaling register 5 rs5 * 65 receive signaling register 6 rs6 * 66 receive signal ing register 7 rs7 * 67 receive signaling register 8 rs8 * 68 receive signaling register 9 rs9 * 69 receive signaling register 10 rs10 * 6a receive signaling register 11 rs11 * 6b receive signaling register 12 rs12 * 6c receive signaling regist er 13 rs13 * 6d receive signaling register 14 rs14 * 6e receive signaling register 15 rs15 * 6f receive signaling register 16 rs16 * 70 common control register 1 ccr1 * 71 common control register 2 ccr2 * 72 common control register 3 ccr3 * 73 common control register 4 ccr4 * 74 transmit channel monitor select tds0sel * 75 transmit ds0 monitor register tds0m * 76 receive channel monitor select rds0sel * 77 receive ds0 monitor register rds0m * 78 line interface control 1 lic1 * 79 l ine interface control 2 lic2 * 7a line interface control 3 lic3 * 7b line interface control 4 lic4 * 7c test register test * 7d transmit line build - out control tlbc * 7e idle array address register iaar * 7f per - channel idle code value register pcicr * 80 transmit idle code enable register 1 tcice1 * 81 transmit idle code enable register 2 tcice2 * 82 transmit idle code enable register 3 tcice3 * 83 transmit idle code enable register 4 tcice4 * 84 receive idle code enable register 1 rc ice1 * 85 receive idle code enable register 2 rcice2 * 86 receive idle code enable register 3 rcice3 * 87 receive idle code enable register 4 rcice4 * 88 receive channel blocking register 1 rcbr1 * 89 receive channel blocking register 2 rcbr2 * 8a receive channel blocking register 3 rcbr3 * 8b receive channel blocking register 4 rcbr4 * 8c transmit channel blocking register 1 tcbr1 * 8d transmit channel blocking register 2 tcbr2 *
product preview DS21Q55 33 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . address r/w register name register abbreviation page 8e transmit channel blocking register 3 tcbr3 * 8f tran smit channel blocking register 4 tcbr4 * 90 hdlc #1 transmit control h1tc * 91 hdlc #1 fifo control h1fc * 92 hdlc #1 receive channel select 1 h1rcs1 * 93 hdlc #1 receive channel select 2 h1rcs2 * 94 hdlc #1 receive channel select 3 h1rcs3 * 95 hdlc #1 receive channel select 4 h1rcs4 * 96 hdlc #1 receive time slot bits/sa bits select h1rtsbs * 97 hdlc #1 transmit channel select1 h1tcs1 * 98 hdlc #1 transmit channel select 2 h1tcs2 * 99 hdlc #1 transmit channel select 3 h1tcs3 * 9a hdlc #1 transmit channel select 4 h1tcs4 * 9b hdlc #1 transmit time slot bits/sa bits select h1ttsbs * 9c hdlc #1 receive packet bytes available h1rpba * 9d hdlc #1 transmit fifo h1tf * 9e hdlc #1 receive fifo h1rf * 9f hdlc #1 transmit fifo buffer a vailable h1tfba * a0 hdlc #2 transmit control h2tc * a1 hdlc #2 fifo control h2fc * a2 hdlc #2 receive channel select 1 h2rcs1 * a3 hdlc #2 receive channel select 2 h2rcs2 * a4 hdlc #2 receive channel select 3 h2rcs3 * a5 hdlc #2 receive channe l select 4 h2rcs4 * a6 hdlc #2 receive time slot bits/sa bits select h2rtsbs * a7 hdlc #2 transmit channel select 1 h2tcs1 * a8 hdlc #2 transmit channel select 2 h2tcs2 * a9 hdlc #2 transmit channel select 3 h2tcs3 * aa hdlc #2 transmit channel s elect 4 h2tcs4 * ab hdlc #2 transmit time slot bits/sa bits select h2ttsbs * ac hdlc #2 receive packet bytes available h2rpba * ad hdlc #2 transmit fifo h2tf * ae hdlc #2 receive fifo h2rf * af hdlc #2 transmit fifo buffer available h2tfba * b0 extend system information bus control register 1 esibcr1 * b1 extend system information bus control register 2 esibcr2 * b2 extend system information bus register 1 esib1 * b3 extend system information bus register 2 esib2 * b4 extend system infor mation bus register 3 esib3 * b5 extend system information bus register 4 esib4 * b6 in - band code control register ibcc * b7 transmit code definition register 1 tcd1 * b8 transmit code definition register 2 tcd2 * b9 receive up code definition re gister 1 rupcd1 * ba receive up code definition register 2 rupcd2 * bb receive down code definition register 1 rdncd1 * bc receive down code definition register 2 rdncd2 * bd in - band receive spare control register rscc * be receive spare code def inition register 1 rscd1 * bf receive spare code definition register 2 rscd2 * c0 receive fdl register rfdl * c1 transmit fdl register tfdl *
product preview DS21Q55 34 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . address r/w register name register abbreviation page c2 receive fdl match register 1 rfdlm1 * c3 receive fdl match register 2 rfdlm2 * c4 test register tes t * c5 interleave bus operation control register iboc * c6 receive align frame register raf * c7 receive nonalign frame register rnaf * c8 receive si align frame rsiaf * c9 receive si nonalign frame rsinaf * ca receive remote alarm bits rra * cb receive sa4 bits rsa4 * cc receive sa5 bits rsa5 * cd receive sa6 bits rsa6 * ce receive sa7 bits rsa7 * cf receive sa8 bits rsa8 * d0 transmit align frame register taf * d1 transmit nonalign frame register tnaf * d2 transmit si align fra me tsiaf * d3 transmit si nonalign frame tsinaf * d4 transmit remote alarm bits tra * d5 transmit sa4 bits tsa4 * d6 transmit sa5 bits tsa5 * d7 transmit sa6 bits tsa6 * d8 transmit sa7 bits tsa7 * d9 transmit sa8 bits tsa8 * da transmit sa bit control register tsacr * db bert alternating word count rate bawc * dc bert repetitive pattern set register 1 brp1 * dd bert repetitive pattern set register 2 brp2 * de bert repetitive pattern set register 3 brp3 * df bert repetitive pattern set register 4 brp4 * e0 bert control register 1 bc1 * e1 bert control register 2 bc2 * e2 test register test * e3 bert bit count register 1 bbc1 * e4 bert bit count register 2 bbc2 * e5 bert bit count register 3 bbc3 * e6 bert bit count reg ister 4 bbc4 * e7 bert error count register 1 bec1 * e8 bert error count register 2 bec2 * e9 bert error count register 3 bec3 * ea bert interface control register bic * eb error rate control register erc * ec number of errors 1 noe1 * ed num ber of errors 2 noe2 * ee number of errors left 1 noel1 * ef number of errors left 2 noel2 * f0 test register test * f1 test register test * f2 test register test * f3 test register test * f4 test register test * f5 test register test *
product preview DS21Q55 35 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . address r/w register name register abbreviation page f6 test register test * f7 test register test * f8 test register test * f9 test register test * fa test register test * fb test register test * fc test register test * fd test register test * fe test register test * ff test register test * * test1 to test16 registers are used only by the factory.
product preview DS21Q55 36 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 5. special per - channel register operation some of the features described in the data sheet that operate on a per - channel basis use a special method for channel selection. the registers involved are t he per - channel pointer registers (pcpr) and per - channel data registers 1 to 4 (pcdr1 ? 4). the user selects the function(s) that are to be applied on a per - channel basis by setting the appropriate bit(s) in the pcpr register. the user then writes to the pcdr registers to select the channels for that function. the following is an example of mapping the transmit and receive bert function to channels 9, 10, 11, 12, 20, and 21: write 11h to pcpr write 00h to pcdr1 write 0fh to pcdr2 write 18h to pcdr3 write 00h to pcdr4 more information about how to use these per - channel features can be found in their respective sections in the data sheet. register name: pcpr register description: per - channel pointer register register address: 28 h bit # 7 6 5 4 3 2 1 0 name rsaoics rsrcs rfcs brcs thscs peics tfcs btcs default 0 0 0 0 0 0 0 0 bit 0/bert transmit channel select (btcs). bit 1/transmit fractional channel select (tfcs). bit 2/payload error insert channel select (peics). bit 3/transmit hardw are signaling channel select (thscs). bit 4/bert receive channel select (brcs). bit 5/receive fractional channel select (rfcs). bit 6/receive signaling reinsertion channel select (rsrcs). bit 7/receive signaling all ones insertion channel select (rsaoi cs).
product preview DS21Q55 37 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: pcdr1 register description: per - channel data register 1 register address: 29 h bit # 7 6 5 4 3 2 1 0 name default ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 register name: pcdr2 register description : per - channel data register 2 register address: 2a h bit # 7 6 5 4 3 2 1 0 name default ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 register name: pcdr3 register description: per - channel data register 3 register address: 2b h bit # 7 6 5 4 3 2 1 0 name default ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 register name: pcdr4 register description: per - channel data register 4 register address: 2c h bit # 7 6 5 4 3 2 1 0 name default ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25
product preview DS21Q55 38 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 6. programming model the DS21Q55 register map is divided into three groups: t1 specific features, e1 specific features, and common features. the typical programming sequence begins with issuing a reset to the device, selecting t1 or e1 operation in the master mode register, enabling t1 or e1 functions, and enabling the common functions. the act of resetting the device automatically clears all configuration and status registers. therefore, it is not necessary to load unused registers with zeros. programming sequence figure 8 - 1 power - on issue reset select t1 or e1 operation in master mode reg ister program t1 specific registers program e1 specific registers program common registers DS21Q55 operational
product preview DS21Q55 39 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 6.1 power - up sequence the DS21Q55 contains an on - chip power - up reset function, which automatically clears the writeable register space immediately after power is supplied to the device. the user can issue a chip reset at any time. issuing a reset will disrupt traffic until the device is reprogrammed. the reset can be issued through hardware using the tstrst pin or through software using the sftrst function in the master mode register. the lirst (lic2.6) sh ould be toggled from zero to one to reset the line interface circuitry. (it will take the DS21Q55 about 40ms to recover from the lirst bit being toggled.) finally, after the tsysclk and rsysclk inputs are stable, the receive and transmit elastic stores sho uld be reset (this step can be skipped if the elastic stores are disabled). 6.1.1 master mode register register name: mstrreg register description: master mode register register address: 00h bit # 7 6 5 4 3 2 1 0 name - - - - test1 test0 t1 /e1 sftrst default 0 0 0 0 0 0 0 0 bit 0/software issued reset (sftrst). a 0 to 1 transition causes the register space to be cleared. a reset clears all configuration and status registers. the bit automatically clears itself when the reset has complete d. bit 1/operating mode (t1/e1). used to select the operating mode of the framer/formatter (digital) portion of the 21q55. the operating mode of the liu must also be programmed. 0 = t1 operation 1 = e1 operation bits 2, 3/test mode bits (test0, test1). test modes are used to force the output pins of the 21q55 into known states. this can facilitate the checkout of assemblies during the manufacturing process and also be used to isolate devices from shared buses. test1 test0 effect on output pins 0 0 ope rate normally 0 1 force all output pins into tristate (including all i/o pins and parallel port pins) 1 0 force all output pins low (including all i/o pins except parallel port pins) 1 1 force all output pins high (including all i/o pins except parallel port pins) bits 4 ? 7/unused, must be set to zero for proper operation.
product preview DS21Q55 40 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 6.2 interrupt handling various alarms, conditions, and events in the DS21Q55 can cause interrupts. for simplicity, these are all referred to as events in this explanation. all status reg isters can be programmed to produce interrupts. each status register has an associated interrupt mask register. for example, sr1 (status register 1) has an interrupt control register called imr1 (interrupt mask register 1). status registers are the only so urces of interrupts. on power - up, all writeable registers are automatically cleared. since bits in the imrx registers have to be set = 1 to allow a particular event to cause an interrupt, no interrupts can occur until the host selects which events are to p roduct interrupts. since there are potentially many sources of interrupts, several features are available to help sort out and identify which event is causing an interrupt. when an interrupt occurs, the host should first read the iir1, iir2, and iir3 regis ters (interrupt information registers) to identify which status register(s) is producing the interrupt. once that is determined, the individual status register or registers can be examined to determine the exact source. in eight port configurations, two ds 21q55s can be connected together via the 3 - wire esib feature. this allows all eight transceivers to be interrogated by a single cpu port read cycle. the host can determine the synchronization status or interrupt status of all eight devices with a single re ad. the esib feature also allows the user to select from various events to be examined via this method. for more information, see the esib section in this data sheet. once an interrupt has occurred, the interrupt handler routine should set the intdis bit (ccr3.6) to stop further activity on the interrupt pin. after all interrupts have been determined and processed, the interrupt hander routine should re - enable interrupts by setting the intdis bit = 0. 6.3 status registers when a particular event or condition has occurred (or is still occurring in the case of conditions), the appropriate bit in a status register will be set to a one. all of the status registers operate in a latched fashion, which means that if an event or condition occurs a bit is set to a one . it will remain set until the user reads that bit. an event bit will be cleared when it is read and it will not be set again until the event has occurred again. condition bits such as rbl, rlos, etc., will remain set if the alarm is still present. the u ser will always proceed a read of any of the status registers with a write. the byte written to the register will inform the DS21Q55 which bits the user wishes to read and have cleared. the user will write a byte to one of these registers, with a one in th e bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. when a one is written to a bit location, the read register will be updated with the latest information. when a zero is wri tten to a bit position, the read register will not be updated and the previous value will be held. a write to the status registers will be immediately followed by a read of the same register. this write - read scheme allows an external microcontroller or mic roprocessor to individually poll certain bits without disturbing the other bits in the register. this operation is key in controlling the DS21Q55 with higher order languages. status register bits are divided into two groups, condition bits and event bits. condition bits are typically network conditions such as loss of sync, or all ones detect. event bits are typically markers such as the one - second timer, elastic store slip, etc. each status register bit is labeled as a condition or event bit. some of th e status registers have bits for both the detection of a condition and the clearance of the condition. for example, sr2 has a bit that is set when the device goes into a loss of sync state (sr2.0, a condition bit) and a bit that is set (sr2.4, an event bit ) when the loss of sync condition clears (goes in sync). some of the status register bits (condition bits) do not have a separate bit for the ?condition clear? event but rather the status bit can produce interrupts on both edges, setting, and clearing. th ese bits are
product preview DS21Q55 41 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . marked as ?double interrupt bits.? an interrupt will be produced when the condition occurs and when it clears. 6.4 information registers information registers operate the same as status registers except they cannot cause interrupts. they are all latched except for info7 and some of the bits in info5 and info6. info7 register is a read only register and it reports the status of the e1 synchronizer in real time. info7 and some of the bits in info6 and info5 are not latched and it is no t necessary to precede a read of these bits with a write. 6.5 interrupt information registers the interrupt information registers provide an indication of which status registers (sr1 through sr9) are generating an interrupt. when an interrupt occurs, the host can read iir1 and iir2 to quickly identify which of the 9 status registers are causing the interrupt. register name: iir1 register description: interrupt information register 1 register address: 14h bit # 7 6 5 4 3 2 1 0 name sr8 sr7 s r6 sr5 sr4 sr3 sr2 sr1 default 0 0 0 0 0 0 0 0 register name: iir2 register description: interrupt information register 2 register address: 15h bit # 7 6 5 4 3 2 1 0 name - - - - - - - sr9 default 0 0 0 0 0 0 0 0
product preview DS21Q55 42 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 7. clock map figure 9 - 1 shows the clock map of the DS21Q55. the routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. although there is only one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification and clarity. clock map figure 9 - 1 the tclk mux is dependent on the state of the tcss0 and tcss1 bits in the lic1 register and the state of the tclk pin. tcss1 tcss0 transmit clock source 0 0 the tclk pin (c) is always the source of transmit clock. 0 1 switch to the recovered clock (b) when the signal at the tclk pin fails to transition after 1 channel time. 1 0 use the scaled signal (a) derived from mclk as the transmit clock. the tclk pin is ignored. 1 1 use the recovered clock (b) as the transmit clock. the tclk pin is ignored. transmit formatter receive framer bpclk synth remote loopback framer loopback payload loopback (see notes) ltca ltca jitter attenuator see lic1 register local loopback bpclk rclk tclk mclk rxclk txclk to liu llb = 0 llb = 1 plb = 0 plb = 1 rlb = 1 rlb = 0 flb = 1 flb = 0 jas = 0 and dja = 0 jas = 1 or dja = 1 jas = 0 or dja = 1 jas = 1 and dja = 0 rcl = 1 rcl = 0 dja = 1 dja = 0 8xclk 8 x pll pre-scaler lic4.mps0 lic4.mps1 lic2.3 2.048 to 1.544 synthesizer b a c tclk mux
product preview DS21Q55 43 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 8. t1 framer/formatter control registers the t1 framer portion of the DS21Q55 is configured via a set of nine control registers. typically, the control registers are only accessed when the system is first powered up. once the device has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. there are two receive - control registers (t1rcr1 and t1rcr2), two transmit control registers (t1tcr1 and t1tcr2), and a common control register (t1ccr1). each of these registers is described in this section. 8.1 t1 control registers register name: t1rcr1 register description: t1 receive control register 1 register address: 03h bit # 7 6 5 4 3 2 1 0 name - arc oof1 oof2 syncc synct synce resync default 0 0 0 0 0 0 0 0 bit 0/resynchronize (resync). when toggled from low to high, a resynchronization of the receive side framer is initiated. must be cleared and set again f or a subsequent resync. bit 1/sync enable (synce). 0 = auto resync enabled 1 = auto resync disabled bit 2/sync time (synct). 0 = qualify 10 bits 1 = qualify 24 bits bit 3/sync criteria (syncc). in d4 framing mode. 0 = search for ft pattern, then search for fs pattern 1 = cross couple ft and fs pattern in esf framing mode. 0 = search for fps pattern only 1 = search for fps and verify with crc6 bits 4 to 5/out of frame select bits (oof2, oof1). oof2 oof1 out of frame criteria 0 0 2/4 frame bits in error 0 1 2/5 frame bits in error 1 0 2/6 frame bits in error 1 1 2/6 frame bits in error bit 6/auto resync criteria (arc). 0 = resync on oof or rcl event 1 = resync on oof only bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 44 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: t1r cr2 register description: t1 receive control register 2 register address: 04h bit # 7 6 5 4 3 2 1 0 name - rfm rb8zs rslc96 rzse rzbtsi rjc rd4ym default 0 0 0 0 0 0 0 0 bit 0/receive side d4 yellow alarm select (rd4ym). 0 = zeros in bit 2 of all channels 1 = a one in the s - bit position of frame 12 (j1 yellow alarm mode) bit 1/receive japanese crc6 enable (rjc). 0 = use ansi/at&t/itu crc6 calculation (normal operation) 1 = use japanese standard jt ? g704 crc6 calculation bit 2/receive side zbtsi support enable (rzbtsi). allows zbtsi information to be output on rlink pin. 0 = zbtsi disabled 1 = zbtsi enabled bit 3/receive fdl zero destuffer enable (rzse). set this bit to zero if using the internal hdlc/boc controller instead of the l egacy support for the fdl. see legacy fdl support (t1 mode) for details. 0 = zero destuffer disabled 1 = zero destuffer enabled bit 4/receive slc ? 96 enable (rslc96). only set this bit to a one in slc ? 96 framing applications. see d4/slc ? 96 operation for de tails. 0 = slc ? 96 disabled 1 = slc ? 96 enabled bit 5/receive b8zs enable (rb8zs). 0 = b8zs disabled 1 = b8zs enabled bit 6/receive frame mode select (rfm). 0 = d4 framing mode 1 = esf framing mode bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 45 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: t1tcr1 register description: t1 transmit control register 1 register address: 05h bit # 7 6 5 4 3 2 1 0 name tjc tfpt tcpt tsse gb7s tfdls tbl tyel default 0 0 0 0 0 0 0 0 bit 0/transmit yellow alarm (tyel). 0 = do not transmit yellow alarm 1 = transmit yellow alarm bit 1/transmit blue alarm (tbl). 0 = transmit data normally 1 = transmit an unframed all one?s code at tpos and tneg bit 2/tfdl register select (tfdls). 0 = source fdl or fs bits from the internal tf dl register (legacy fdl support mode) 1 = source fdl or fs bits from the internal hdlc controller or the tlink pin bit 3/global bit 7 stuffing (gb7s). 0 = allow the ssiex registers to determine which channels containing all zeros are to be bit 7 stuffed 1 = force bit 7 stuffing in all zero byte channels regardless of how the ssiex registers are programmed bit 4/transmit software signaling enable (tsse). 0 = do not source signaling data from the tsx registers regardless of the ssiex registers. the ssiex registers still define which channels are to have b7 stuffing preformed 1 = source signaling data as enabled by the ssiex registers bit 5/transmit crc pass through (tcpt). 0 = source crc6 bits internally 1 = crc6 bits sampled at tser during f - bit time bit 6/transmit f - bit pass through (tfpt). 0 = f bits sourced internally 1 = f bits sampled at tser bit 7/transmit japanese crc6 enable (tjc). 0 = use ansi/at&t/itu crc6 calculation (normal operation) 1 = use japanese standard jt ? g704 crc6 calculation
product preview DS21Q55 46 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: t1tcr2 register description: t1 transmit control register 2 register address: 06h bit # 7 6 5 4 3 2 1 0 name tb8zs tslc96 tzse fbct2 fbct1 td4ym tzbtsi tb7zs default 0 0 0 0 0 0 0 0 bit 0/transmit side bit 7 zero supp ression enable (tb7zs). 0 = no stuffing occurs 1 = bit 7 force to a one in channels with all zeros bit 1/transmit side zbtsi support enable (tzbtsi). allows zbtsi information to be input on tlink pin. 0 = zbtsi disabled 1 = zbtsi enabled bit 2/transmit side d4 yellow alarm select (td4ym). 0 = zeros in bit 2 of all channels 1 = a one in the s - bit position of frame 12 bit 3/f - bit corruption type 1. (fbct1). a low - to - high transition of this bit causes the next three consecutive ft (d4 framing mode) or fps (esf framing mode) bits to be corrupted, causing the remote end to experience a loss of synchronization. bit 4/f - bit corruption type 2. (fbct2). setting this bit high enables the corruption of one ft (d4 framing mode) or fps (esf framing mode) bit in ever y 128 ft or fps bits as long as the bit remains set. bit 5/transmit fdl zero stuffer enable (tzse). set this bit to zero if using the internal hdlc controller instead of the legacy support for the fdl. see i/o pin configuration options for details. 0 = ze ro stuffer disabled 1 = zero stuffer enabled bit 6/transmit slc ? 96/fs - bit insertion enable (tslc96). only set this bit to a one in d4 framing and slc - 96 applications. must be set to one to source the fs pattern from the tfdl register. see d4/slc ? 96 operat ion for details. 0 = slc ? 96/fs - bit insertion disabled 1 = slc ? 96/fs - bit insertion enabled bit 7/transmit b8zs enable (tb8zs). 0 = b8zs disabled 1 = b8zs enabled
product preview DS21Q55 47 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: t1ccr1 register description: t1 common control register 1 register address: 07h bit # 7 6 5 4 3 2 1 0 name - - - - - tfm pde tloop default 0 0 0 0 0 0 0 0 bit 0/transmit loop code enable (tloop). see programmable in - band loop codes generation and detection for details. 0 = transmit data normally 1 = repla ce normal transmitted data with repeating code as defined in registers tcd1 and tcd2 bit 1/pulse density enforcer enable (pde). the framer always examines both the transmit and receive data streams for violations of the following rules, which are require d by ansi t1.403: no more than 15 consecutive zeros and at least n ones in each and every time window of 8 x (n +1) bits where n = 1 through 23. violations for the transmit and receive data streams are reported in the info1.6 and info1.7 bits respectively. when this bit is set to one, the device will force the transmitted stream to meet this requirement no matter the content of the transmitted stream. when running b8zs, this bit should be set to zero since b8zs encoded data streams cannot violate the pulse density requirements. 0 = disable transmit pulse density enforcer 1 = enable transmit pulse density enforcer bit 2/transmit frame mode select (tfm). 0 = d4 framing mode 1 = esf framing mode bit 3/unused, must be set to zero for proper operation. bit 4/u nused, must be set to zero for proper operation. bit 5/unused, must be set to zero for proper operation. bit 6/unused, must be set to zero for proper operation. bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 48 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 8.2 t1 transmit transparency the softw are - signaling insertion - enable registers, ssie1 ? ssie4, can be used to select signaling insertion from the transmit - signaling registers, ts1 ? ts12, on a per - channel basis. setting a bit in the ssiex register allows signaling data to be sourced from the signa ling registers for that channel. in transparent mode, bit 7 stuffing and/or robbed - bit signaling is prevented from overwriting the data in the channels. if a ds0 is programmed to be clear, no robbed - bit signaling will be inserted nor will the channel hav e bit 7 stuffing performed. however, in the d4 framing mode, bit 2 will be overwritten by a zero when a yellow alarm is transmitted. also, the user has the option to globally override the ssiex registers from determining which channels are to have bit 7 st uffing performed. if the t1tcr1.3 and t1tcr2.0 bits are set to one, then all 24 t1 channels will have bit 7 stuffing performed on them, regardless of how the ssiex registers are programmed. in this manner, the ssiex registers are only affecting channels th at are to have robbed - bit signaling inserted into them. 8.3 t1 receive - side digital - milliwatt code generation receive - side digital - milliwatt code generation involves using the receive digital - milliwatt registers (t1rdmr1/2/3) to determine which of the 24 t1 channels of the t1 line going to the backplane should be overwritten with a digital - milliwatt pattern. the digital - milliwatt code is an 8 - byte repeating pattern that represents a 1khz sine wave (1e/0b/0b/1e/9e/8b/8b/9e). each bit in the t1rdmrx registers r epresents a particular channel. if a bit is set to a one, then the receive data in that channel will be replaced with the digital - milliwatt code. if a bit is set to zero, no replacement occurs.
product preview DS21Q55 49 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: t1rdmr1 register descriptio n: t1 receive digital milliwatt enable register 1 register address: 0ch bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive digital milliwatt enable for channels 1 to 8 (ch1 to ch8). 0 = do not a ffect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital - milliwatt code register name: t1rdmr2 register description: t1 receive digital milliwatt enable register 2 registe r address: 0dh bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive digital milliwatt enable for channels 9 to 16 (ch9 to ch16). 0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital - milliwatt code register name: t1rdmr3 register description: t1 receive digital milliwatt enable register 3 register address: 0eh bit # 7 6 5 4 3 2 1 0 name ch24 ch 23 ch22 ch21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive digital milliwatt enable for channels 17 to 24 (ch17 to ch24). 0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital - milliwatt code
product preview DS21Q55 50 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 8.4 t1 information register register name: info1 register description: information register 1 register address: 10h bit # 7 6 5 4 3 2 1 0 name rpdv tpdv cofa 8zd 16zd sefe b8zs fbe default 0 0 0 0 0 0 0 0 bit 0/frame bit error event (fbe). set when a ft (d4) or fps (esf) framing bit is received in error. bit 1/b8zs code word detect event (b8zs). set when a b8zs code word is detected at rpos and rneg independent of whether the b8zs mode is selected or not via t1tcr2.7. useful for automatically setting the line coding. bit 2/severely errored framing event (sefe). set when two out of six framing bits (ft or fps) are received in error. bit 3/sixteen zero detect event (16zd). set when a string of at leas t 16 consecutive zeros (regardless of the length of the string) have been received at rposi and rnegi. bit 4/eight zero detect event (8zd). set when a string of at least eight consecutive zeros (regardless of the length of the string) have been received at rposi and rnegi. bit 5/change of frame alignment event (cofa). set when the last resync resulted in a change of frame or multiframe alignment. bit 6/transmit pulse density violation event (tpdv). set when the transmit data stream does not meet the an si t1.403 requirements for pulse density. bit 7/receive pulse density violation event (rpdv). set when the receive data stream does not meet the ansi t1.403 requirements for pulse density.
product preview DS21Q55 51 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . t1 alarm criteria table 10 - 1 alarm set criteria clear criteria blue alarm (ais) (note 1) over a 3ms window, five or fewer zeros are received over a 3ms window, six or more zeros are received yellow alarm (rai) d4 bit - 2 mode (t1rcr2.0 = 0) d4 12th f - bit mode (t1rcr2.0 = 1; this mode is also referred to as the ? japanese yellow alarm?) esf mode bit 2 of 256 consecutive channels is set to zero for at least 254 occurrences 12th framing bit is set to one for two consecutive occurrences 16 consecutive patterns of 00ff appear in the fdl bit 2 of 256 consecutiv e channels is set to zero for less than 254 occurrences 12th framing bit is set to zero for two consecutive occurrences 14 or fewer patterns of 00ff hex out of 16 possible appear in the fdl red alarm (lrcl) (also referred to as loss of signal) 192 con secutive zeros are received 14 or more ones out of 112 possible bit positions are received, starting with the first one received notes: 1) the definition of blue alarm (or alarm indication signal) is an unframed, all - ones signal. blue alarm detectors should be able to operate properly in the presence of a 10e - 3 error rate, and they should not falsely trigger on a framed, all - ones signal. the blue alarm criteria in the DS21Q55 has been set to achieve this performance. it is recommended that the rbl bit be qua lified with the rlos bit. 2) ansi specifications use a different nomenclature than this data sheet does; the following terms are equivalent: rbl = ais rcl = los rlos = lof ryel = rai
product preview DS21Q55 52 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 9. e1 framer/formatter control registers the e1 framer portion of the ds21 q55 is configured via a set of four control registers. typically, the control registers are only accessed when the system is first powered up. once the device has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. there are two receive control registers (e1rcr1 and e1rcr2) and two transmit control registers (e1tcr1 and e1tcr2). there are also four status and information registers. each of these eight registers are described in this secti on. 9.1 e1 control registers register name: e1rcr1 register description: e1 receive control register 1 register address: 33h bit # 7 6 5 4 3 2 1 0 name rserc rsigm rhdb3 rg802 rcrc4 frc synce resync default 0 0 0 0 0 0 0 0 bit 0/resync (resync). when toggled from low to high, a resync is initiated. must be cleared and set again for a subsequent resync. bit 1/sync enable (synce). 0 = auto resync enabled 1 = auto resync disabled bit 2/frame resync criteria (frc). 0 = resync if fas received in error 3 consecutive times 1 = resync if fas or bit 2 of non - fas is received in error three consecutive times bit 3/receive crc4 enable (rcrc4). 0 = crc4 disabled 1 = crc4 enabled bit 4/receive g.802 enable (rg802). see signaling operation for details. 0 = do not force rchblk high during bit 1 of timeslot 26 1 = force rchblk high during bit 1 of timeslot 26 bit 5/receive hdb3 enable (rhdb3). 0 = hdb3 disabled 1 = hdb3 enabled bit 6/receive signaling mode select (rsigm). 0 = cas signaling mode 1 = ccs signaling m ode bit 7/rser control (rserc). 0 = allow rser to output data as received under all conditions 1 = force rser to one under loss of frame alignment conditions
product preview DS21Q55 53 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . e1 sync/resync criteria table 11 - 1 frame or multiframe level sync criteria resync criteria itu spec. fas fas present in frame n and n + 2, and fas not present in frame n + 1 three consecutive incorrect fas received alternate: (e1rcr1.2 = 1) the above criteria is met or three consecutive incorrect bit 2 of non - fas received g.706 4.1.1 4.1.2 crc4 two valid mf alignment words found within 8ms 915 or more crc4 code words out of 1000 received in error g.706 4.2 and 4.3.2 cas valid mf alignment word found and previous timeslot 16 contains code other than all zeros two consecutive mf alignment words r eceived in error g.732 5.2 register name: e1rcr2 register description: e1 receive control register 2 register address: 34h bit # 7 6 5 4 3 2 1 0 name sa8s sa7s sa6s sa5s sa4s - - rcla default 0 0 0 0 0 0 0 0 bit 0/receive carrier loss (rcl) alte rnate criteria (rcla). defines the criteria for a receive carrier loss condition for both the framer and line interface (liu) 0 = rcl declared upon 255 consecutive zeros (125s) 1 = rcl declared upon 2048 consecutive zeros (1ms) bit 1/unused, must be set to zero for proper operation. bit 2/unused, must be set to zero for proper operation. bit 3/sa4 - bit select(sa4s). set to one to have rlclk pulse at the sa4 - bit position; set to zero to force rlclk low during sa4 - bit position. see functional timing diagra ms for details. bit 4/sa5 - bit select(sa5s). set to one to have rlclk pulse at the sa5 - bit position; set to zero to force rlclk low during sa5 - bit position. see functional timing diagrams for details. bit 5/sa6 - bit select(sa6s). set to one to have rlclk p ulse at the sa6 - bit position; set to zero to force rlclk low during sa6 - bit position. see functional timing diagrams for details. bit 6/sa7 - bit select(sa7s). set to one to have rlclk pulse at the sa7 - bit position; set to zero to force rlclk low during sa7 - bit position. see functional timing diagrams for details. bit 7/sa8 - bit select (sa8s). set to one to have rlclk pulse at the sa8 - bit position; set to zero to force rlclk low during sa8 - bit position. see functional timing diagrams for details.
product preview DS21Q55 54 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: e1tcr1 register description: e1 transmit control register 1 register address: 35h bit # 7 6 5 4 3 2 1 0 name tfpt t16s tua1 tsis tsa1 thdb3 tg802 tcrc4 default 0 0 0 0 0 0 0 0 bit 0/transmit crc4 enable (tcrc4). 0 = crc4 disabl ed 1 = crc4 enabled bit 1/transmit g.802 enable (tg802). see functional timing diagrams for details. 0 = do not force tchblk high during bit 1 of timeslot 26 1 = force tchblk high during bit 1 of timeslot 26 bit 2/transmit hdb3 enable (thdb3). 0 = hdb3 d isabled 1 = hdb3 enabled bit 3/transmit signaling all ones (tsa1). 0 = normal operation 1 = force timeslot 16 in every frame to all ones bit 4/transmit international bit select (tsis). 0 = sample si bits at tser pin 1 = source si bits from taf and tnaf r egisters (in this mode, e1tcr1.7 must be set to zero) bit 5/transmit unframed all ones (tua1). 0 = transmit data normally 1 = transmit an unframed all one?s code at tposo and tnego bit 6/transmit timeslot 16 data select (t16s). see transmit signaling fo r details 0 = timeslot 16 determined by the ssiex registers and the thscs function in the pcpr register 1 = source timeslot 16 from ts1 to ts16 registers bit 7/transmit timeslot 0 pass through (tfpt). 0 = fas bits/sa bits/remote alarm sourced internally f rom the taf and tnaf registers 1 = fas bits/sa bits/remote alarm sourced from tser
product preview DS21Q55 55 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: e1tcr2 register description: e1 transmit control register 2 register address: 36h bit # 7 6 5 4 3 2 1 0 name sa8s sa7s sa6s sa5s sa4s ae be aais ara default 0 0 0 0 0 0 0 0 bit 0/automatic remote alarm generation (ara). 0 = disabled 1 = enabled bit 1/automatic ais generation (aais). 0 = disabled 1 = enabled bit 2/automatic e - bit enable (aebe). 0 = e - bits not automatically set in the transmit direction 1 = e - bits automatically set in the transmit direction bit 3/sa4 - bit select (sa4s). set to one to source the sa4 bit from the tlink pin; set to zero to not source the sa4 bit. see functional timing diagrams for details. bit 4/sa5 - bit select (sa5s). set to one to source the sa5 bit from the tlink pin; set to zero to not source the sa5 bit. see functional timing diagrams for details. bit 5/sa6 - bit select (sa6s). set to one to source the sa6 bit from the tlink pin; set to zero to not so urce the sa6 bit. see functional timing diagrams for details. bit 6/sa7 - bit select (sa7s). set to one to source the sa7 bit from the tlink pin; set to zero to not source the sa7 bit. see functional timing diagrams for details. bit 7/sa8 - bit select (sa8s ). set to one to source the sa8 bit from the tlink pin; set to zero to not source the sa8 bit. see functional timing diagrams for details.
product preview DS21Q55 56 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 9.2 automatic alarm generation the device can be programmed to automatically transmit ais or remote alarm. when automat ic ais generation is enabled (e1tcr2.1 = 1), the device monitors the receive side framer to determine if any of the following conditions are present: loss of receive frame synchronization, ais alarm (all ones) reception, or loss of receive carrier (or sign al). if any one (or more) of the above conditions is present, then the framer will either force an ais or remote alarm. when automatic rai generation is enabled (e1tcr2.0 = 1), the framer monitors the receive side to determine if any of the following cond itions are present: loss of receive frame synchronization, ais alarm (all ones) reception, or loss of receive carrier (or signal) or if crc4 multiframe synchronization cannot be found within 128ms of fas synchronization (if crc4 is enabled). if any one (or more) of the above conditions is present, then the framer will transmit a rai alarm. rai generation conforms to ets 300 011 specifications and a constant remote alarm will be transmitted if the DS21Q55 cannot find crc4 multiframe synchronization within 40 0ms as per g.706. note: it is an illegal state to have both automatic ais generation and automatic remote alarm generation enabled at the same time.
product preview DS21Q55 57 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 9.3 e1 information registers register name: info3 register description: information register 3 register address: 12h bit # 7 6 5 4 3 2 1 0 name - - - - - crcrc fasrc casrc default 0 0 0 0 0 0 0 0 bit 0/cas resync criteria met event (casrc). set when two consecutive cas mf alignment words are received in error. bit 1/fas resync criteria me t event (fasrc. set when three consecutive fas words are received in error. bit 2/crc resync criteria met event (crcrc). set when 915/1000 code words are received in error. register name: info7 register description: information register 7 (real time) register address: 30h bit # 7 6 5 4 3 2 1 0 name csc5 csc4 csc3 csc2 csc0 fassa cassa crc4sa default 0 0 0 0 0 0 0 0 bit 0/crc4 mf sync active (crc4sa). set while the synchronizer is searching for the crc4 mf alignment word. bit 1/cas mf sync active (cassa). set while the synchronizer is searching for the cas mf alignment word. bit 2/fas sync active (fassa). set while the synchronizer is searching for alignment at the fas level. bit 3 to 7/crc4 sync counter bits (csc0 and csc2 to csc4 ). the crc4 sync counter increments each time the 8ms - crc4 multiframe search times out. the counter is cleared when the framer has successfully obtained synchronization at the crc4 level. the counter can also be cleared by disabling the crc4 mode (e1rcr1.3 = 0). this counter is useful for determining the amount of time the framer has been searching for synchronization at the crc4 level. itu g.706 suggests that if synchronization at the crc4 level cannot be obtained within 400ms, then the search should be ab andoned and proper action taken. the crc4 sync counter will rollover. csc0 is the lsb of the 6 - bit counter. ( note: the second lsb, csc1, is not accessible. csc1 is omitted to allow resolution to >400ms using 5 bits.)
product preview DS21Q55 58 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . e1 alarm criteria table 11 - 2 alarm s et criteria clear criteria itu spec. rlos an rlos condition exists on power - up prior to initial synchronization, when a re - sync criteria has been met, or when a manual re - sync has been initiated via e1rcr1.0 rcl 255 or 2048 consecutive zeros received as determined by e1rcr2.0 in 255 - bit times, at least 32 ones are received g.775/g.962 rra bit 3 of nonalign frame set to one for three consecutive occasions bit 3 of nonalign frame set to zero for three consecutive occasions o.162 2.1.4 rua1 fewer than three zeros in two frames (512 bits) more than two zeros in two frames (512 bits) o.162 1.6.1.2 rdma bit 6 of timeslot 16 in frame 0 has been set for two consecutive multiframes v52lnk two out of three sa7 bits are zero g.965
product preview DS21Q55 59 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 10. common control and sta tus registers register name: ccr1 register description: common control register 1 register address: 70h bit # 7 6 5 4 3 2 1 0 name - crc4r sie odm dicai tcss1 tcss0 rlosf default 0 0 0 0 0 0 0 0 bit 0/function of the rlos/lotc output (rlosf). 0 = receive loss of sync (rlos) 1 = loss of transmit clock (lotc) bit 1/transmit clock source select bit 0 (tcss0). bit 2/transmit clock source select bit 1 (tcss1). tcss1 tcss0 transmit clock source 0 0 the tclk pin is always the source o f transmit clock. 0 1 switch to the clock present at rclk when the signal at the tclk pin fails to transition after one channel time. 1 0 use the scaled signal present at mclk as the transmit clock. the tclk pin is ignored. 1 1 use the signal present a t rclk as the transmit clock. the tclk pin is ignored. bit 3/disable idle code auto increment (dicai) selects/deselects the auto increment feature for the transmit and receive idle code array address register. 0 = addresses in iaar register automaticall y increment on every read/write operation to the pcicr register 1 = addresses in iaar register do not automatically increment bit 4/output data mode (odm). 0 = pulses at tposo and tnego are one full tclko period wide 1 = pulses at tposo and tnego are 1/2 tclko period wide bit 5/signaling integration enable (sie). 0 = signaling changes of state reported on any change in selected channels 1 = signaling must be stable for three multiframes in order for a change of state to be reported bit 6/crc - 4 recalcul ate (crc4r). (e1 only) 0 = transmit crc - 4 generation and insertion operates in normal mode 1 = transmit crc - 4 generation operates according to g.706 intermediate path recalculation method bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 60 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: idr register description: device identification register register address: 0fh bit # 7 6 5 4 3 2 1 0 name id7 id6 id5 id4 id3 id2 id1 id0 default 1 0 1 1 x x x x bits 0 to 3/chip revision bits (id0 to id3). the lower four bits of the idr are used to display the die revision of the chip. ido is the lsb of a decimal code that represents the chip revision. bits 4 to 7/device id (id4 to id7). the upper four bits of the idr are used to display the device id. register name: sr2 register description: status register 2 register address: 18h bit # 7 6 5 4 3 2 1 0 name ryelc rua1c frclc rlosc ryel rua1 frcl rlos default 0 0 0 0 0 0 0 0 bit 0/receive loss of sync condition (rlos). set when the device is not synchroniz ed to the received data stream. bit 1/framer receive carrier loss condition (frcl). set when 255 (or 2048 if e1rcr2.0 = 1) e1 mode or 192 t1 mode consecutive zeros have been detected at rposi and rnegi. bit 2/receive unframed all ones (t1, blue alarm, e1 , ais) condition (rua1). set when an unframed all ones code is received at rposi and rnegi. bit 3/receive yellow alarm condition (ryel). (t1 only) set when a yellow alarm is received at rposi and rnegi. bit 4/receive loss of sync clear event (rlosc). set when the framer achieves synchronization; will remain set until read. bit 5/framer receive carrier loss clear event (frclc). set when carrier loss condition at rposi and rnegi is no longer detected. bit 6/receive unframed all ones clear event (rua1c). s et when the unframed all ones condition is no longer detected. bit 7/receive yellow alarm clear event (ryelc). (t1 only) set when the yellow alarm condition is no longer detected.
product preview DS21Q55 61 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: imr2 register description: interrupt mask re gister 2 register address: 19h bit # 7 6 5 4 3 2 1 0 name ryelc rua1c frclc rlosc ryel rua1 frcl rlos default 0 0 0 0 0 0 0 0 bit 0/receive loss of sync condition (rlos). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising edge only bit 1/framer receive carrier loss condition (frcl). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising edge only bit 2/receive unframed all ones (blue alarm) condition (rua1). 0 = interrupt masked 1 = interrupt enabled ? interrupts on risin g edge only bit 3/receive yellow alarm condition (ryel). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising edge only bit 4/receive loss of sync clear event (rlosc). 0 = interrupt masked 1 = interrupt enabled bit 5/framer receive carri er loss condition clear (frclc). 0 = interrupt masked 1 = interrupt enabled bit 6/receive unframed all ones condition clear event (rua1c). 0 = interrupt masked 1 = interrupt enabled bit 7/receive yellow alarm clear event (ryelc). 0 = interrupt mask ed 1 = interrupt enabled
product preview DS21Q55 62 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: sr3 register description: status register 3 register address: 1ah bit # 7 6 5 4 3 2 1 0 name lspare ldn lup lotc lorc v52lnk rdma rra default 0 0 0 0 0 0 0 0 bit 0/receive remote al arm condition (rra). (e1 only) set when a remote alarm is received at rposi and rnegi bit 1/receive distant mf alarm condition (rdma). (e1 only) set when bit 6 of timeslot 16 in frame 0 has been set for two consecutive multiframes. this alarm is not disab led in the ccs signaling mode. bit 2/v5.2 link detected condition (v52lnk). (e1 only) set on detection of a v5.2 link identification signal. (g.965). bit 3/loss of receive clock condition (lorc). set when the rclki pin has not transitioned for one chann el time. bit 4/loss of transmit clock condition (lotc). set when the tclk pin has not transitioned for one channel time. will force the lotc pin high if enabled via ccr1.0. bit 5/loop up code detected condition (lup). ( t1 only) set when the loop up code as defined in the rupcd1/2 register is being received. see programmable in - band loop code generation and detection for details. bit 6/loop down code detected condition (ldn). (t1 only) set when the loop down code as defined in the rdncd1/2 register is bei ng received. see programmable in - band loop code generation and detection for details. bit 7/spare code detected condition (lspare). (t1 only) set when the spare code as defined in the rscd1/2 registers is being received. see programmable in - band loop code generation and detection for details.
product preview DS21Q55 63 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: imr3 register description: interrupt mask register 3 register address: 1bh bit # 7 6 5 4 3 2 1 0 name lspare ldn lup lotc lorc v52lnk rdma rra default 0 0 0 0 0 0 0 0 bit 0/receiv e remote alarm condition (rra). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising and falling edges bit 1/receive distant mf alarm condition (rdma). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising and falling edges bit 2/v 5.2 link detected condition (v52lnk). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising and falling edges bit 3/loss of receive clock condition (lorc). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising and falling edges bit 4/loss of transmit clock condition (lotc). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising and falling edges bit 5/loop up code detected condition (lup). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising and falling edges bit 6/loop down code detected condition (ldn). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising and falling edges bit 7/spare code detected condition (lspare). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising and falling ed ges
product preview DS21Q55 64 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: sr4 register description: status register 4 register address: 1ch bit # 7 6 5 4 3 2 1 0 name - rsa1 rsa0 tmf taf rmf rcmf raf default 0 0 0 0 0 0 0 0 bit 0/receive align frame event (raf). (e1 only) set every 250s at the beginning of align frames. used to alert the host that si and sa bits are available in the raf and rnaf registers. bit 1/receive crc4 multiframe event (rcmf). (e1 only) set on crc4 multiframe boundaries; will continue to be set every 2ms on an arbi trary boundary if crc4 is disabled. bit 2/receive multiframe event (rmf) . e1 mode: set every 2ms (regardless if cas signaling is enabled or not) on receive multiframe boundaries. used to alert the host that signaling data is available. t1 mode: set ev ery 1.5ms on d4 mf boundaries or every 3ms on esf mf boundaries. bit 3/transmit align frame event (taf). (e1 only) set every 250s at the beginning of align frames. used to alert the host that the taf and tnaf registers need to be updated. b it 4/transmit multiframe event (tmf). e1 mode: set every 2ms (regardless if crc4 is enabled) on transmit multiframe boundaries. used to alert the host that signaling data needs to be updated. t1 mode: set every 1.5ms on d4 mf boundaries or every 3ms on esf mf boundaries. bit 5/receive signaling all zeros event (rsa0). (e1 only) set when over a full mf, timeslot 16 contains all zeros. bit 6/receive signaling all ones event (rsa1). (e1 only) set when the contents of timeslot 16 contains fewer than three zeros over 16 consecutive frames. this alarm is not disabled in the ccs signaling mode.
product preview DS21Q55 65 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: imr4 register description: interrupt mask register 4 register address: 1dh bit # 7 6 5 4 3 2 1 0 name - rsa1 rsa0 tmf taf rmf rcmf raf default 0 0 0 0 0 0 0 0 bit 0/receive align frame event (raf). 0 = interrupt masked 1 = interrupt enabled bit 1/receive crc4 multiframe event (rcmf). 0 = interrupt masked 1 = interrupt enabled bit 2/receive multiframe event (rmf) . 0 = interrupt masked 1 = interrupt enabled bit 3/transmit align frame event (taf). 0 = interrupt masked 1 = interrupt enabled bit 4/transmit multiframe event (tmf). 0 = interrupt masked 1 = interrupt enabled bit 5/receive signaling all zeros event (rsa0). 0 = int errupt masked 1 = interrupt enabled bit 6/receive signaling all ones event (rsa1). 0 = interrupt masked 1 = interrupt enabled
product preview DS21Q55 66 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 11. i/o pin configuration options register name: iocr1 register description: i/o configuration register 1 registe r address: 01h bit # 7 6 5 4 3 2 1 0 name rsms rsms2 rsms1 rsio tsdw tsm tsio odf default 0 0 0 0 0 0 0 0 bit 0/output data format (odf). 0 = bipolar data at tposo and tnego 1 = nrz data at tposo; tnego = 0 bit 1/tsync i/o select (tsio). 0 = tsync i s an input 1 = tsync is an output bit 2/tsync mode select (tsm). selects frame or multiframe mode for the tsync pin. 0 = frame mode 1 = multiframe mode bit 3/tsync double - wide (tsdw). (t1 only) (note: this bit must be set to zero when iocr1.2 = 1 or when iocr1.1 = 0) 0 = do not pulse double - wide in signaling frames 1 = do pulse double - wide in signaling frames bit 4/rsync i/o select (rsio). (note: this bit must be set to zero when escr.0 = 0) 0 = rsync is an output 1 = rsync is an input (only valid if ela stic store enabled) bit 5/rsync mode select 1(rsms1). selects frame or multiframe pulse when rsync pin is in output mode. in input mode (elastic store must be enabled) multiframe mode is only useful when receive signaling re - insertion is enabled. 0 = fra me mode 1 = multiframe mode bit 6/rsync mode select 2(rsms2). t1 mode: rsync pin must be programmed in the output frame mode (iocr1.5 = 0, iocr1.4 = 0). 0 = do not pulse double wide in signaling frames 1 = do pulse double wide in signaling frames e 1 mode: rsync pin must be programmed in the output multiframe mode (iocr1.5 = 1, iocr1.4 = 0). 0 = rsync outputs cas multiframe boundaries 1 = rsync outputs crc4 multiframe boundaries bit 7/rsync multiframe skip control (rsms). useful in framing format conversions from d4 to esf. this function is not available when the receive - side elastic store is enabled. rsync must be set to output multiframe pulses (iocr1.5 = 1 and iocr1.4 = 0). 0 = rsync will output a pulse at every multiframe 1 = rsync wil l output a pulse at every other multiframe
product preview DS21Q55 67 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: iocr2 register description: i/o configuration register 2 register address: 02h bit # 7 6 5 4 3 2 1 0 name rclkinv tclkinv rsyncinv tsyncinv tssyncinv h100en tsclkm rsclkm defa ult 0 0 0 0 0 0 0 0 bit 0/rsysclk mode select (rsclkm). 0 = if rsysclk is 1.544mhz 1 = if rsysclk is 2.048mhz or ibo enabled (see interleaved pcm bus operation. ) bit 1/tsysclk mode select (tsclkm). 0 = if tsysclk is 1.544mhz 1 = if tsysclk is 2.048mhz o r ibo enabled (see interleaved pcm bus operation. ) bit 2/h.100 sync mode (h100en). 0 = normal operation 1 = sync shift bit 3/tssync invert (tssyncinv). 0 = no inversion 1 = invert bit 4/tsync invert (tsyncinv). 0 = no inversion 1 = invert bit 5/rsync i nvert (rsyncinv). 0 = no inversion 1 = invert bit 6/tclk invert (tclkinv). 0 = no inversion 1 = invert bit 7/rclk invert (rclkinv). 0 = no inversion 1 = invert
product preview DS21Q55 68 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 12. loopback configuration register name: lbcr register description: loopback co ntrol register register address: 4ah bit # 7 6 5 4 3 2 1 0 name - - - liuc llb rlb plb flb default 0 0 0 0 0 0 0 0 bit 0/framer loopback (flb). 0 = loopback disabled 1 = loopback enabled this loopback is useful in testing and debugging application s. in flb, the device will loop data from the transmit side back to the receive side. when flb is enabled, the following will occur: 1) t1 mode: an unframed all ones code will be transmitted at tposo and tnego. e1 mode: normal data will be transmitted at tpo so and tnego. 2) data at rposi and rnegi will be ignored. 3) all receive side signals will take on timing synchronous with tclk instead of rclki. 4) please note that it is not acceptable to have rclk tied to tclk during this loopback because this will cause an unst able condition. bit 1/payload loopback (plb). 0 = loopback disabled 1 = loopback enabled when plb is enabled, the following will occur: 1) data will be transmitted from the tposo and tnego pins synchronous with rclk instead of tclk. 2) all of the receive sid e signals will continue to operate normally. 3) the tchclk and tchblk signals are forced low. 4) data at the tser and tsig pins is ignored. 5) the tlclk signal will become synchronous with rclk instead of tclk. t1 mode: normally, this loopback is only enabled whe n esf framing is being performed but can be enabled also in d4 framing applications. in a plb situation, the device will loop the 192 bits of pay - load data (with bpvs corrected) from the receive section back to the transmit section. the fps framing pattern , crc6 calculation, and the fdl bits are not looped back, they are reinserted by the device. e1 mode: in a plb situation, the device will loop the 248 bits of payload data (with bpvs corrected) from the receive section back to the transmit section. the t ransmit section will modify the payload as if it was input at tser. the fas word, si, sa and e bits, and crc4 are not looped back, they are reinserted by the device. bit 2/remote loopback (rlb). in this loopback, data input via the rposi and rnegi pins will be transmitted back to the tposo and tnego pins. data will continue to pass through the receive side framer of the device as it would normally and the data from the transmit side formatter will be ignored. 0 = loopback disabled 1 = loopback enabled
product preview DS21Q55 69 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . bit 3/local loopback (llb). in this loopback, data will continue to be transmitted as normal through the transmit side of the device. data being received at rtip and rring will be replaced with the data being transmitted. data in this loopback will pass th rough the jitter attenuator. (see figure 1 - 1 line interface unit .) 0 = loopback disabled 1 = loopback enabled bit 4/line interface unit mux control (liuc). this is a software version of the liuc pin. when the liuc pin is connected high the liuc bit has c ontrol. when the liuc pin is connected low the framer and liu are separated and the liuc bit has no effect. 0 = if liuc pin connected high, liu internally connected to framer block and deactivate the tposi/tnegi/tclki/rposi/rnegi/rclki pins. 1 = if liuc p in connected high, disconnect liu from framer block and activate the tposi/tnegi/tclki/rposi/rnegi/rclki pins. liuc pin liuc bit 0 0 liu and framer separated 0 1 liu and framer separated 1 0 liu and framer connected 1 1 liu and framer separated bit 5/unused, must be set to zero for proper operation. bit 6/unused, must be set to zero for proper operation. bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 70 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 12.1 per - channel loopback the per - channel loopback registers (pclrs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the t1 or e1 line. if this loopback is enabled, then transmit and receive clocks and frame syncs must be synchronized. one method to accomplish this would be to tie rclk to tc lk and rfsync to tsync. there are no restrictions on which channels can be looped back or on how many channels can be looped back. each of the bit position in the pclrs (pclr1 /pclr2 /pclr3 /pclr4 ) repr esent a ds0 channel in the outgoing frame. when these bits are set to a one, data from the corresponding receive channel will replace the data on tser for that channel. register name: pclr1 register description: per - channel loopback enable register 1 register address: 4bh bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 to 7/per - channel loopback enable for channels 1 to 8 (ch1 to ch8). 0 = loopback disabled 1 = enable loopback. source data fro m the corresponding receive channel register name: pclr2 register description: per - channel loopback enable register 2 register address: 4ch bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bi ts 0 to 7/per - channel loopback enable for channels 9 to 16 (ch9 to ch16). 0 = loopback disabled 1 = enable loopback. source data from the corresponding receive channel
product preview DS21Q55 71 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: pclr3 register description: per - channel loopback enable register 3 register address: 4dh bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 to 7/per - channel loopback enable for channels 17 to 24 (ch17 to ch24). 0 = loopback disabled 1 = enable loopback. sou rce data from the corresponding receive channel register name: pclr4 register description: per - channel loopback enable register 4 register address: 4eh bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 bits 0 to 7/per - channel loopback enable for channels 25 to 32 (ch25 to ch32). 0 = loopback disabled 1 = enable loopback. source data from the corresponding receive channel
product preview DS21Q55 72 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 13. error count registers the DS21Q55 contains four counters that are used to accumulate line coding errors, path errors, and synchronization errors. counter update options include one second boundaries, 42ms (t1 mode only), 62ms (e1 mode only) or manually. see error counter configuration register (ercnt ). when upd ated automatically, the user can use the interrupt from the timer to determine when to read these registers. all four counters will saturate at their respective maximum counts and they will not rollover ( note : only the line - code violation - count register ha s the potential to overflow but the bit error would have to exceed 10e - 2 before this would occur). register name: ercnt register description: error counter configuration register register address: 41h bit # 7 6 5 4 3 2 1 0 name - mecu e cus eams vcrfs fsbe moscrf lcvcrf default 0 0 0 0 0 0 0 0 bit 0/t1 line code violation count register function select (lcvcrf). 0 = do not count excessive zeros 1 = count excessive zeros bit 1/multiframe out of sync count register function select (mosc rf). 0 = count errors in the framing bit position 1 = count the number of multiframes out of sync bit 2/pcvcr fs - bit error report enable (fsbe). 0 = do not report bit errors in fs - bit position; only ft - bit position 1 = report bit errors in fs - bit position as well as ft - bit position bit 3/e1 line code violation count register function select (vcrfs). 0 = count bipolar violations (bpvs) 1 = count code violations (cvs) bit 4/error accumulation mode select (eams). 0 = ercnt .5 determines accumu lation time 1 = ercnt .6 determines accumulation time bit 5/error counter update select (ecus). t1 mode : 0 = update error counters once a second 1 = update error counters every 42ms (333 frames) e1 mode: 0 = update error counters once a second 1 = update error counters every 62.5ms (500 frames) bit 6/manual error counter update (mecu). when enabled by ercnt .4, the changing of this bit from a zero to a one allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. the user must wait a minimum of 1.5 rclk clock periods before reading the error count registers to allow for proper update. bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 73 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 13.1 line code violation count register (lcvcr) t1 operation t1 code violations are defined as bipolar violations (bpvs) or excessive zeros. if the b8zs mode is set for the receive side, then b8zs code words are not counted. this counter is always enabled; it is not disabled during re ceive loss of synchronization (rlos = 1) conditions (table 15 - 1). t1 line code violation counting options table 15 - 1 count excessive zeros? (ercnt.0) b8zs enabled? (t1rcr2.5) what is counted in the lcvcrs no no bpvs yes no bpvs + 16 consecutive zeros no yes bpvs (b8zs code words not counted) yes yes bpvs + 8 consecutive zeros e1 operation either bipolar violations or code violations can be counted. bipolar violations are defined as consecutive marks of the same polarity. in this mode, if the hdb3 mo de is set for the receive side, then hdb3 code words are not counted as bpvs. if ercnt .3 is set, then the lvc counts code violations as defined in itu o.161. code violations are defined as consecutive bipolar violations of the same polarity. in most applications, the framer should be programmed to count bpvs when receiving ami code and to count cvs when receiving hdb3 code. this counter increments at all times and is not disabled by loss of sync conditions. the counter saturates at 65,535 and will not rollover. the bit error rate on an e1 line would have to be greater than 10** - 2 before the vcr would saturate (table 15 - 2). e1 line code violation counting options table 15 - 2 e1 code violation select (ercnt.3) what is counted in the lcvcrs 0 bp vs 1 cvs
product preview DS21Q55 74 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: lcvcr1 register description: line code violation count register 1 register address: 42h bit # 7 6 5 4 3 2 1 0 name lcvc15 lcvc14 lcvc13 lcvc12 lcvc11 lcvc10 lcvc9 lccv8 default 0 0 0 0 0 0 0 0 bits 0 to 7/ line code violation counter bits 8 to 15 (lcvc8 to lcvc15). lcv15 is the msb of the 16 - bit code violation count. register name: lcvcr2 register description: line code violation count register 2 register address: 43h bit # 7 6 5 4 3 2 1 0 name lcvc7 lcvc6 lcvc5 lcvc4 lcvc3 lcvc2 lcvc1 lcvc0 default 0 0 0 0 0 0 0 0 bits 0 to 7/line code violation counter bits 0 to 7 (lcvc0 to lcvc7). lcv0 is the lsb of the 16 - bit code violation count.
product preview DS21Q55 75 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 13.2 path code violation count register (pcvcr) t1 o peration the path - code violation - count register records either ft, fs, or crc6 errors in t1 frames. when the receive side of a framer is set to operate in the t1 esf framing mode, pcvcr will record errors in the crc6 code words. when set to operate in the t1 d4 framing mode, pcvcr will count errors in the ft framing bit position. via the ercnt .2 bit, a framer can be programmed to also report errors in the fs framing bit position. the pcvcr will be disabled during receive loss of synchronizatio n (rlos = 1) conditions. see table 15 - 3 for a detailed description of exactly what errors the pcvcr counts. t1 path code violation counting arrangements table 15 - 3 framing mode count fs errors? what is counted in the pcvcrs d4 no errors in the ft pattern d4 yes errors in both the ft and fs patterns esf don?t care errors in the crc6 code words e1 operation the pcvcr records crc4 errors. since the maximum crc4 count in a one - second period is 1000, this counter cannot saturate. the counter is disabled du ring loss of sync at either the fas or crc4 level; it will continue to count if loss of multiframe sync occurs at the cas level. the pcvcr1 is the most significant word and pcvcr2 is the least significant word of a 16 - bit counter that records path violat ions (pvs).
product preview DS21Q55 76 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: pcvcr1 register description: path code violation count register 1 register address: 44h bit # 7 6 5 4 3 2 1 0 name pcvc15 pcvc14 pcvc13 pcvc12 pcvc11 pcvc10 pcvc9 pcvc8 default 0 0 0 0 0 0 0 0 bits 0 to 7/ path code violation counter bits 8 to 15 (pcvc8 to pcvc15). pcvc15 is the msb of the 16 - bit path code violation count. register name: pcvcr2 register description: path code violation count register 2 register address: 45h bit # 7 6 5 4 3 2 1 0 name pcvc7 pcvc6 pcvc5 pcvc4 pcvc3 pcvc2 pcvc1 pcvc0 default 0 0 0 0 0 0 0 0 bits 0 to 7/path code violation counter bits 0 to 7 (pcvc0 to pcvc7). pcvc0 is the lsb of the 16 - bit path code violation count. 13.3 frames out of sync count register (fos cr) t1 operation the foscr is used to count the number of multiframes that the receive synchronizer is out of sync. this number is useful in esf applications needing to measure the parameters loss of frame count (lofc) and esf error events as described i n at&t publication tr54016. when the foscr is operated in this mode, it is not disabled during receive loss of synchronization (rlos = 1) conditions. the foscr has alternate operating mode whereby it will count either errors in the ft framing pattern (in t he d4 mode) or errors in the fps framing pattern (in the esf mode). when the foscr is operated in this mode, it is disabled during receive loss of synchronization (rlos = 1) conditions. see table 15 - 4 for a detailed description of what the foscr is capable of counting. t1 frames out of sync counting arrangements table 15 - 4 framing mode (t1rcr1 .3) count mos or f - bit errors (ercnt.1) what is counted in the foscrs d4 mos number of multiframes out of sync d4 f - bit errors in the ft pattern esf m os number of multiframes out of sync esf f - bit errors in the fps pattern e1 operation the foscr counts word errors in the frame alignment signal in timeslot 0. this counter is disabled when rlos is high. fas errors will not be counted when the framer is searching for fas alignment and/or synchronization at either the cas or crc4 multiframe level. since the maximum fas word error count in a one - second period is 4000, this counter cannot saturate.
product preview DS21Q55 77 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . the foscr1 (foscr1 ) is the most significant word and foscr2 is the least significant word of a 16 - bit counter that records frames out of sync.
product preview DS21Q55 78 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: foscr1 register description: frames out of sync count register 1 register address: 46h bit # 7 6 5 4 3 2 1 0 name fos15 fos14 fos13 fos12 fos11 fos10 fos9 fos8 default 0 0 0 0 0 0 0 0 bits 0 to 7/frames out of sync counter bits 8 to 15 (fos8 to fos15). fos15 is the msb of the 16 - bit frames out of sync count. register name: foscr2 registe r description: frames out of sync count register 2 register address: 47h bit # 7 6 5 4 3 2 1 0 name fos7 fos6 fos5 fos4 fos3 fos2 fos1 fos0 default 0 0 0 0 0 0 0 0 bits 0 to 7/frames out of sync counter bits 0 to 7 (fos0 to fos7). fos0 is the lsb of the 16 - bit frames out of sync count. 13.4 e - bit counter register (ebcr) this counter is only available in the e1 mode. ebcr1 (ebcr1 ) is the most significant word and ebcr2 is the least significant word of a 16 - bit counter that recor ds far end block errors (febe), as reported in the first bit of frames 13 and 15 on e1 lines running with crc4 multiframe. these count registers will increment once each time the received e - bit is set to zero. since the maximum e - bit count in a one - second period is 1000, this counter cannot saturate. the counter is disabled during loss of sync at either the fas or crc4 level; it will continue to count if loss of multiframe sync occurs at the cas level. register name: ebcr1 register descript ion: e - bit count register 1 register address: 48h bit # 7 6 5 4 3 2 1 0 name eb15 eb14 eb13 eb12 eb11 eb10 eb9 eb8 default 0 0 0 0 0 0 0 0 bits 0 to 7/e - bit counter bits 8 to 15 (eb8 to eb15). eb15 is the msb of the 16 - bit e - bit count. register na me: ebcr2 register description: e - bit count register 2 register address: 49h bit # 7 6 5 4 3 2 1 0 name eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 default 0 0 0 0 0 0 0 0 bits 0 to 7/e - bit counter bits 0 to 7 (eb0 to eb7). eb0 is the lsb of the 16 - bit e - bit count.
product preview DS21Q55 79 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 14. ds0 monitoring function the DS21Q55 has the ability to monitor one ds0 64kbps channel in the transmit direction and one ds0 channel in the receive direction at the same time. in the transmit direction the user will determine which cha nnel is to be monitored by properly setting the tcm0 to tcm4 bits in the tds0sel register. in the receive direction, the rcm0 to rcm4 bits in the rds0sel register need to be properly set. the ds0 channel pointed to by the tc m0 to tcm4 bits will appear in the transmit ds0 monitor (tds0m ) register and the ds0 channel pointed to by the rcm0 to rcm4 bits will appear in the receive ds0 (rds0m ) register. the tcm4 to tcm0 and rcm4 to rcm0 bits should be p rogrammed with the decimal decode of the appropriate t1 or e1 channel. t1 channels 1 through 24 map to register values 0 through 23. e1 channels 1 through 32 map to register values 0 through 31. for example, if ds0 channel 6 in the transmit direction and d s0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into tds0sel and rds0sel: tcm4 = 0 rcm4 = 0 tcm3 = 0 rcm3 = 1 tcm2 = 1 rcm2 = 1 tcm1 = 0 rcm1 = 1 tcm0 = 1 rcm0 = 0 14.1 transmit ds0 monitor reg isters register name: tds0sel register description: transmit channel monitor select register address: 74h bit # 7 6 5 4 3 2 1 0 name - - - tcm4 tcm3 tcm2 tcm1 tcm0 default 0 0 0 0 0 0 0 0 bits 0 to 4 transmit channel monitor bits ( tcm0 to tcm4). tcm0 is the lsb of a 5 - bit channel select that determines which transmit channel data will appear in the tds0m register. bits 5 to 7/unused, must be set to zero for proper operation. register name: tds0m regi ster description: transmit ds0 monitor register register address: 75h bit # 7 6 5 4 3 2 1 0 name b1 b2 b3 b4 b5 b6 b7 b8 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit ds0 channel bits (b1 to b8). transmit channel data that has been selected by the tr ansmit channel monitor select register. b8 is the lsb of the ds0 channel (last bit to be transmitted).
product preview DS21Q55 80 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 14.2 receive ds0 monitor registers register name: rds0sel register description: receive channel monitor select register address: 76h bit # 7 6 5 4 3 2 1 0 name - - - rcm4 rcm3 rcm2 rcm1 rcm0 default 0 0 0 0 0 0 0 0 bits 0 to 4/receive channel monitor bits (rcm0 to rcm4). rcm0 is the lsb of a 5 - bit channel - select that determines which receive ds0 channel data will appear in the rds0m register. bits 5 to 7/unused, must be set to zero for proper operation. register name: rds0m register description: receive ds0 monitor register register address: 77h bit # 7 6 5 4 3 2 1 0 name b1 b2 b3 b4 b5 b6 b7 b8 defa ult 0 0 0 0 0 0 0 0 bits 0 to 7/receive ds0 channel bits (b1 to b8). receive - channel data that has been selected by the receive - channel monitor - select register. b8 is the lsb of the ds0 channel (last bit to be received).
product preview DS21Q55 81 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 15. signaling operation there are t wo methods to access receive signaling data and provide transmit signaling data: processor - based (i.e., software - based) or hardware - based. processor - based refers to access through the transmit and receive signaling registers, rs1 ? rs16 and ts1 ? ts16 . hardware - based refers to the tsig and rsig pins. both methods can be used simultaneously. 15.1 receive signaling simplified diagram of receive signaling path figure 17 - 1 receive signaling registers change of state indication registers signaling buffers all ones re-insertion control rser rsync rsig t1/e1 data stream per-channel control signaling extraction
product preview DS21Q55 82 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 15.1.1 processor - based receive signaling the robbe d - bit signaling (t1) or ts16 cas signaling (e1) is sampled in the receive data stream and copied into the receive signaling registers, rs1 through rs16 . in t1 mode, only rs1 through rs12 are used. the sign aling information in these registers is always updated on multiframe boundaries. this function is always enabled. 15.1.1.1 change of state in order to avoid constant monitoring of the receive signaling registers, the DS21Q55 can be programmed to alert the host whe n any specific channel or channels undergo a change of their signaling state. rscse1 through rscse4 for e1 and rscse1 through rscse3 for t1 are used to select which channels can cause a change of state indicatio n. the change of state is indicated in status register 5 (sr1 .5). if signaling integration, ccr1 .5, is enabled then the new signaling state must be constant for three multiframes before a change of state indication is indicated. th e user can enable the int pin to toggle low upon detection of a change in signaling by setting the imr1 .5 bit. the signaling integration mode is global and cannot be enabled on a channel by channel basis. the user can identity which channels have undergone a signaling change of state by reading the rsinfo1 through rsinfo4 registers . the information from this registers will tell the user which rsx register to read for the new signaling data. all changes are indicated in the rsinfo1 ? rsinfo4 re gister regardless of the rscse1 ? rscse4 registers. 15.1.2 hardware - based receive signaling in hardware - based signaling the signaling data can be obtained from the rser pin or the rsig pin. rsig is a signaling pcm - stream output on a c hannel - by - channel basis from the signaling buffer. the signaling data, t1 robbed bit or e1 ts16 , is still present in the original data stream at rser. the signaling buffer provides signaling data to the rsig pin and also allows signaling data to be reinserted into the original data stream in a different alignment that is determined by a multiframe signal from the rsync pin. in this mode, the receive elastic store can be enabled or disabled. if the receive elastic store is enabled, then the back plane clock (rsysclk) can be either 1.544mhz or 2.048mhz. in the esf framing mode, the abcd signaling bits are output on rsig in the lower nibble of each channel. the rsig data is updated once a multiframe (3ms) unless a freeze is in effect. in the d4 fram ing mode, the ab signaling bits are output twice on rsig in the lower nibble of each channel. hence, bits 5 and 6 contain the same data as bits 7 and 8 respectively in each channel. the rsig data is updated once a multiframe (1.5ms) unless a freeze is in e ffect. see the functional timing diagrams for some examples. 15.1.2.1 receive - signaling reinsertion at rser in this mode, the user will provide a multiframe sync at the rsync pin and the signaling data will be reinserted based on this alignment. in t1 mode, this re sults in two copies of the signaling data in the rser data stream. the original signaling data based on the fs/esf frame positions and the realigned data based on the user supplied multiframe sync applied at rsync. in voice channels this extra copy of sign aling data is of little consequence. reinsertion can be avoided in data channels since this feature is activated on a per - channel basis. for reinsertion, the elastic store must be enabled; however, the backplane clock can be either 1.544mhz or 2.048mhz. s ignaling reinsertion mode is enabled, on a per - channel basis by setting the rsrcs bit high in the pcpr register. the channels that are to have signaling reinserted are selected by writing to the pcdr1 - pcdr3
product preview DS21Q55 83 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register s for t1 mode and pcdr1 - pcdr4 registers for e1 mode. in e1 mode, the user will generally select all channels when doing reinsertion. 15.1.2.2 force receive signaling all ones in t1 mode, the user can, on a per - channel basis, force the robbed - bit sign aling - bit positions to a one. this is done by using the per - channel register, which is described in the special per - channel operation section. the user sets the btcs bit in the pcpr register. the channels that are to be forced to one are selec ted by writing to the pcdr1 - pcdr3 registers. 15.1.2.3 receive - signaling freeze the signaling data in the four - multiframe signaling buffer will be frozen in a known good state upon either a loss of synchronization (oof event), carrier los s, or frame slip. this action meets the requirements of bellcore tr ? tsy ? 000170 for signaling freezing. to allow this freeze action to occur, the rfe control bit (sigcr .4) should be set high. the user can force a freeze by setting the rff con trol bit (sigcr.3) high. the rsigf output pin provides a hardware indication that a freeze is in effect. the four multiframe buffer provides a three - multiframe delay in the signaling bits provided at the rsig pin (and at the rser pin if receive signaling r einsertion is enabled). when freezing is enabled (rfe = 1), the signaling data will be held in the last known good state until the corrupting error condition subsides. when the error condition subsides, the signaling data will be held in the old state for at least an additional 9ms (or 4.5ms in d4 framing mode) before being allowed to be updated with new signaling data. register name: sigcr register description: signaling control register register address: 40h bit # 7 6 5 4 3 2 1 0 nam e - - - rfe rff - - - default 0 0 0 0 0 0 0 0 bit 0/unused, must be set to zero for proper operation. bit 1/unused, must be set to zero for proper operation. bit 2/unused, must be set to zero for proper operation. bit 3/receive force freeze (rff). fr eezes receive - side signaling at rsig (and rser if receive signaling reinsertion is enabled); will override receive - freeze enable (rfe). see receive signaling freeze. 0 = do not force a freeze event 1 = force a freeze event bit 4/receive freeze enable (rfe ). see receive signaling freeze. 0 = no freezing of receive signaling data will occur 1 = allow freezing of receive signaling data at rsig (and rser if receive signaling reinsertion is enabled). bit 5/unused, must be set to zero for proper operation. bit 6/unused, must be set to zero for proper operation. bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 84 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: rs1 to rs12 register description: receive signaling registers (t1 mode, esf format) register address: 60h to 6bh (msb) (lsb) ch2 - a ch2 - b ch2 - c ch2 - d ch1 - a ch1 - b ch1 - c ch1 - d rs1 ch4 - a ch4 - b ch4 - c ch4 - d ch3 - a ch3 - b ch3 - c ch3 - d rs2 ch6 - a ch6 - b ch6 - c ch6 - d ch5 - a ch5 - b ch5 - c ch5 - d rs3 ch8 - a ch8 - b ch8 - c ch8 - d ch7 - a ch7 - b ch7 - c ch7 - d rs4 ch10 - a ch10 - b ch10 - c ch10 - d ch9 - a ch9 - b ch9 - c ch9 - d rs5 ch12 - a ch12 - b ch12 - c ch12 - d ch11 - a ch11 - b ch11 - c ch11 - d rs6 ch14 - a ch14 - b ch14 - c ch14 - d ch13 - a ch13 - b ch13 - c ch13 - d rs7 ch16 - a ch16 - b ch16 - c ch16 - d ch15 - a ch15 - b ch15 - c ch15 - d rs8 ch18 - a ch18 - b ch18 - c ch18 - d ch17 - a ch17 - b ch17 - c ch17 - d rs9 ch20 - a ch20 - b ch20 - c ch20 - d ch19 - a ch19 - b ch19 - c ch19 - d rs10 ch22 - a ch22 - b ch22 - c ch22 - d c h21 - a ch21 - b ch21 - c ch21 - d rs11 ch24 - a ch24 - b ch24 - c ch24 - d ch23 - a ch23 - b ch23 - c ch23 - d rs12 register name: rs1 to rs12 register description: receive signaling registers (t1 mode, d4 format) regist er address: 60h to 6bh (msb) (lsb) ch2 - a ch2 - b ch2 - a ch2 - b ch1 - a ch1 - b ch1 - a ch1 - b rs1 ch4 - a ch4 - b ch4 - a ch4 - b ch3 - a ch3 - b ch3 - a ch3 - b rs2 ch6 - a ch6 - b ch6 - a ch6 - b ch5 - a ch5 - b ch5 - a ch5 - b rs3 ch8 - a ch8 - b c h8 - a ch8 - b ch7 - a ch7 - b ch7 - a ch7 - b rs4 ch10 - a ch10 - b ch10 - a ch10 - b ch9 - a ch9 - b ch9 - a ch9 - b rs5 ch12 - a ch12 - b ch12 - a ch12 - b ch11 - a ch11 - b ch11 - a ch11 - b rs6 ch14 - a ch14 - b ch14 - a ch14 - b ch13 - a ch13 - b ch13 - a ch13 - b rs7 ch16 - a ch16 - b ch16 - a ch16 - b ch15 - a ch15 - b ch15 - a ch15 - b rs8 ch18 - a ch18 - b ch18 - a ch18 - b ch17 - a ch17 - b ch17 - a ch17 - b rs9 ch20 - a ch20 - b ch20 - a ch20 - b ch19 - a ch19 - b ch19 - a ch19 - b rs10 ch22 - a ch22 - b ch22 - a ch22 - b ch21 - a ch21 - b ch21 - a ch21 - b rs11 ch24 - a ch24 - b ch24 - a ch24 - b ch23 - a ch23 - b ch23 - a ch23 - b rs12 note: in d4 format, ts1 - ts12 contain signaling data for two frames. bold type indicates data fo r second frame.
product preview DS21Q55 85 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: rs1 to rs16 register description: receive signaling registers (e1 mode, cas format) register address: 60h to 6fh (msb) (lsb) 0 0 0 0 x y x x rs1 ch 2 - a ch2 - b ch2 - c ch2 - d ch1 - a ch1 - b ch1 - c ch1 - d rs2 ch4 - a ch4 - b ch4 - c ch4 - d ch3 - a ch3 - b ch3 - c ch3 - d rs3 ch6 - a ch6 - b ch6 - c ch6 - d ch5 - a ch5 - b ch5 - c ch5 - d rs4 ch8 - a ch8 - b ch8 - c ch8 - d ch7 - a ch7 - b ch7 - c ch7 - d rs5 ch10 - a ch10 - b ch10 - c ch10 - d ch9 - a ch9 - b ch9 - c ch9 - d rs6 ch12 - a ch12 - b ch12 - c ch12 - d ch11 - a ch11 - b ch11 - c ch11 - d rs7 ch14 - a ch14 - b ch14 - c ch14 - d ch13 - a ch13 - b ch13 - c ch13 - d rs8 ch16 - a ch16 - b ch16 - c ch16 - d ch15 - a ch15 - b ch15 - c ch15 - d rs9 ch18 - a ch18 - b ch18 - c ch18 - d ch17 - a ch17 - b ch17 - c ch17 - d rs10 ch20 - a ch20 - b ch20 - c ch20 - d ch19 - a ch19 - b ch19 - c ch19 - d rs11 ch22 - a ch22 - b ch22 - c ch22 - d ch21 - a ch21 - b ch21 - c ch21 - d rs12 ch24 - a ch24 - b ch24 - c ch24 - d ch23 - a ch23 - b ch23 - c ch23 - d rs13 ch26 - a ch26 - b ch26 - c ch26 - d ch25 - a ch25 - b ch25 - c ch25 - d rs14 ch28 - a ch28 - b ch28 - c ch28 - d ch27 - a ch27 - b ch27 - c ch27 - d rs15 ch30 - a ch30 - b ch30 - c ch30 - d ch29 - a ch29 - b ch29 - c ch29 - d rs16
product preview DS21Q55 86 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: rscse1 , rscse2 , rscse3 , rscse4 register description: receive signaling change of state interrupt enable register addre ss: 3ch, 3dh, 3eh, 3fh (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 rscse1 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 rscse2 ch24 ch23 ch22 ch21 ch20 ch19 ch1 8 ch17 rscse3 ch30 ch29 ch28 ch27 ch26 ch25 rscse4 setting any of the ch1 through ch30 bits in the rscse1 through rscse4 registers will cause an interrupt when that channel?s signaling data c hanges state. register name: rsinfo1 , rsinfo2 , rsinfo3 , rsinfo4 register description: receive signaling change of state information register address: 38h, 39h, 3ah, 3bh (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 rsinfo1 ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 rsinfo2 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 rsinfo3 ch30 ch29 ch28 ch27 ch26 ch25 rsinfo4 when a channel?s signaling data changes state, the respective bit in registers rsinfo1 - 4 will be set. if the channel was also enabled as an interrupt source by setting the appropriate bit in rscse1 ? 4, an interrupt is generated. the bit will remain set until read.
product preview DS21Q55 87 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 15.2 transmit signaling simplified diagram of transmit signaling path figure 17 - 2 15.2.1 processor - based transmit signaling in processor - based mode, signaling data is loaded into the t ransmit - signaling registers (ts1 ? ts16 ) via the host interface. on multiframe boundaries, the contents of these registers is loaded into a shift register for placement in the appropriate bit position in the outgoing data stream. the user can utilize the transmit multiframe interrupt in status register 4 (sr4 .4) to know when to update the signaling bits. the user need not update any transmit signaling register for which there is no change of state for that register. each transmit signaling register contains the robbed - bit signaling (t1) or ts16 cas signaling (e1) for two timeslots that will be inserted into the outgoing stream if enabled to do so via t1tcr1 .4 (t1 mode) or e1tcr1 .6 (e1 mode). in t1 mode, only ts1 through ts12 are used. signaling data can be sourced from the ts registers on a per - channel basis by utilizing the software - signaling insertion - enable registers, ssie1 through ssie4 . transmit signaling registers signaling buffers per-channel control tser tsig t1/e1 data stream per-channel control ssie1 - ssie4 b7 t1tcr1.4 1 0 0 1 0 1 pcpr.3 only applies to t1 mode
product preview DS21Q55 88 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 15.2.1.1 t1 mode in t1 esf framing mode, there are four signaling bits per channel (a, b, c, and d). ts1 ? ts12 contain a full multiframe of signaling data. in t1 d4 framing mode, there are only two signaling bits per channel ( a and b). in t1 d4 framing mode, the framer uses the c and d bit positions as the a and b bit positions for the next multiframe. in d4 mode, two multiframes of signaling data can be loaded into ts1 ? ts12. the framer will load the contents of ts1 ? ts12 into the outgoing shift register every other d4 multiframe. in d4 mode the host should load new contents into ts1 ? ts12 on every other multiframe boundary and no later than 120s after the boundary. 15.2.1.2 e1 mode in e1 mode, ts16 carries the signaling information. this information can be in either ccs (common channel signaling) or cas (channel associated signaling) format. the 32 time slots are referenced by two different channel number schemes in e1. in channel numbering, ts0 thro ugh ts31 are labeled channels 1 through 32. in phone - channel numbering, ts1 through ts15 are labeled channel 1 through channel 15, and ts17 through ts31 are labeled channel 15 through channel 30. time slot numbering schemes table 17 - 1 ts 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 phone channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2 0 21 22 23 24 25 26 27 28 29 30
product preview DS21Q55 89 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: ts1 to ts16 register description: transmit signaling registers (e1 mode, cas format) register address: 50h to 5fh (msb) (lsb) 0 0 0 0 x y x x t s1 ch2 - a ch2 - b ch2 - c ch2 - d ch1 - a ch1 - b ch1 - c ch1 - d ts2 ch4 - a ch4 - b ch4 - c ch4 - d ch3 - a ch3 - b ch3 - c ch3 - d ts3 ch6 - a ch6 - b ch6 - c ch6 - d ch5 - a ch5 - b ch5 - c ch5 - d ts4 ch8 - a ch8 - b ch8 - c ch8 - d ch7 - a ch7 - b ch7 - c ch7 - d ts5 ch10 - a ch10 - b ch10 - c ch10 - d ch9 - a ch9 - b ch9 - c ch9 - d ts6 ch12 - a ch12 - b ch12 - c ch12 - d ch11 - a ch11 - b ch11 - c ch11 - d ts7 ch14 - a ch14 - b ch14 - c ch14 - d ch13 - a ch13 - b ch13 - c ch13 - d ts8 ch16 - a ch16 - b c h16 - c ch16 - d ch15 - a ch15 - b ch15 - c ch15 - d ts9 ch18 - a ch18 - b ch18 - c ch18 - d ch17 - a ch17 - b ch17 - c ch17 - d ts10 ch20 - a ch20 - b ch20 - c ch20 - d ch19 - a ch19 - b ch19 - c ch19 - d ts11 ch22 - a ch22 - b ch22 - c ch22 - d ch21 - a ch21 - b ch2 1 - c ch21 - d ts12 ch24 - a ch24 - b ch24 - c ch24 - d ch23 - a ch23 - b ch23 - c ch23 - d ts13 ch26 - a ch26 - b ch26 - c ch26 - d ch25 - a ch25 - b ch25 - c ch25 - d ts14 ch28 - a ch28 - b ch28 - c ch28 - d ch27 - a ch27 - b ch27 - c ch27 - d ts15 c h30 - a ch30 - b ch30 - c ch30 - d ch29 - a ch29 - b ch29 - c ch29 - d ts16
product preview DS21Q55 90 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: ts1 to ts16 register description: transmit signaling registers (e1 mode, ccs format) register address: 50h to 5f h (msb) (lsb) 1 2 3 4 5 6 7 8 ts1 17 18 19 20 9 10 11 12 ts2 33 34 35 36 25 26 27 28 ts3 49 50 51 52 41 42 43 44 ts4 65 66 67 68 57 58 59 60 ts5 81 82 83 84 73 74 75 76 ts6 97 98 99 100 89 90 91 92 ts7 113 114 115 116 105 106 107 108 ts8 13 14 15 16 121 122 123 124 ts9 29 30 31 32 21 22 23 24 ts10 45 46 47 48 37 38 39 40 ts11 61 62 63 64 53 54 5 5 56 ts12 77 78 89 80 69 70 71 72 ts13 93 94 95 96 85 86 87 88 ts14 109 110 111 112 101 102 103 104 ts15 125 126 127 128 117 118 119 120 ts16
product preview DS21Q55 91 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: ts1 to ts16 register description: transmit signaling registers (t1 mode, esf format) register address: 50h to 5bh (msb) (lsb) ch2 - a ch2 - b ch2 - c ch2 - d ch1 - a ch1 - b ch1 - c ch1 - d ts1 ch4 - a ch4 - b ch4 - c ch4 - d ch3 - a ch3 - b ch3 - c ch3 - d ts2 ch6 - a ch6 - b ch6 - c ch6 - d ch5 - a ch5 - b ch5 - c ch5 - d ts3 ch8 - a ch8 - b ch8 - c ch8 - d ch7 - a ch7 - b ch7 - c ch7 - d ts4 ch10 - a ch10 - b ch10 - c ch10 - d ch9 - a ch9 - b ch9 - c ch9 - d ts5 ch12 - a ch12 - b c h12 - c ch12 - d ch11 - a ch11 - b ch11 - c ch11 - d ts6 ch14 - a ch14 - b ch14 - c ch14 - d ch13 - a ch13 - b ch13 - c ch13 - d ts7 ch16 - a ch16 - b ch16 - c ch16 - d ch15 - a ch15 - b ch15 - c ch15 - d ts8 ch18 - a ch18 - b ch18 - c ch18 - d ch17 - a ch17 - b ch17 - c c h17 - d ts9 ch20 - a ch20 - b ch20 - c ch20 - d ch19 - a ch19 - b ch19 - c ch19 - d ts10 ch22 - a ch22 - b ch22 - c ch22 - d ch21 - a ch21 - b ch21 - c ch21 - d ts11 ch24 - a ch24 - b ch24 - c ch24 - d ch23 - a ch23 - b ch23 - c ch23 - d ts12
product preview DS21Q55 92 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . r egister name: ts1 to ts16 register description: transmit signaling registers (t1 mode, d4 format) register address: 50h to 5bh (msb) (lsb) ch2 - a ch2 - b ch2 - a ch2 - b ch1 - a ch1 - b ch1 - a ch1 - b ts1 ch4 - a ch4 - b ch4 - a ch4 - b ch3 - a ch3 - b ch3 - a ch3 - b ts2 ch6 - a ch6 - b ch6 - a ch6 - b ch5 - a ch5 - b ch5 - a ch5 - b ts3 ch8 - a ch8 - b ch8 - a ch8 - b ch7 - a ch7 - b ch7 - a ch7 - b ts4 ch10 - a ch10 - b ch10 - a ch10 - b ch9 - a ch9 - b ch9 - a c h9 - b ts5 ch12 - a ch12 - b ch12 - a ch12 - b ch11 - a ch11 - b ch11 - a ch11 - b ts6 ch14 - a ch14 - b ch14 - a ch14 - b ch13 - a ch13 - b ch13 - a ch13 - b ts7 ch16 - a ch16 - b ch16 - a ch16 - b ch15 - a ch15 - b ch15 - a ch15 - b ts8 ch18 - a ch18 - b ch18 - a ch18 - b ch17 - a ch17 - b ch17 - a ch17 - b ts9 ch20 - a ch20 - b ch20 - a ch20 - b ch19 - a ch19 - b ch19 - a ch19 - b ts10 ch22 - a ch22 - b ch22 - a ch22 - b ch21 - a ch21 - b ch21 - a ch21 - b ts11 ch24 - a ch24 - b ch24 - a ch24 - b ch23 - a ch23 - b ch23 - a ch23 - b ts12 note: in d4 format, ts1 ? ts12 contain signaling data for two frames. bold type indicates data for second frame.
product preview DS21Q55 93 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 15.2.2 software signaling insertion enable registers, e1 cas mode in e1 cas mode, the cas si gnaling alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling data. register name: ssie1 register description: software signaling insertion enable 1 register address: 08h bit # 7 6 5 4 3 2 1 0 name ch7 ch6 ch5 ch4 ch3 ch2 ch1 ucaw default 0 0 0 0 0 0 0 0 bit 0/upper cas align/alarm word (ucaw ). selects the upper cas align/alarm pattern (0000) to be sourced from the upper 4 bits of the ts1 register. 0 = do not source the upper cas align/alarm pattern from the ts1 register 1 = source the upper cas align/alarm pattern from the ts1 register bits 1 to 7/software signaling insertion enable for channels 1 to 7 (ch1 to ch7 ). these bits determine which channels are to h ave signaling inserted form the transmit signaling registers. 0 = do not source signaling data from the tsx registers for this channel 1 = source signaling data from the tsx registers for this channel register name: ssie2 register descripti on: software signaling insertion enable 2 register address: 09h bit # 7 6 5 4 3 2 1 0 name ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 default 0 0 0 0 0 0 0 0 bits 0 to 7/software signaling insertion enable for channels 8 to 15 (ch8 to ch15 ) . these bits determine which channels are to have signaling inserted form the transmit signaling registers. 0 = do not source signaling data from the ts registers for this channel 1 = source signaling data from the ts registers for this channel
product preview DS21Q55 94 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: ssie3 register description: software signaling insertion enable 3 register address: 0ah bit # 7 6 5 4 3 2 1 0 name ch22 ch21 ch20 ch19 ch18 ch17 ch16 lcaw default 0 0 0 0 0 0 0 0 bit 0/lower cas align/alarm word (lcaw ). selects the lower cas align/alarm bits (xyxx) to be sourced from the lower 4 bits of the ts1 register. 0 = do not source the lower cas align/alarm bits from the ts1 register 1 = source the lower cas alarm align/bits from the ts1 register bits 1 to 7/software signaling insertion enable for lcaw and channels 16 to 22 (ch16 to ch22 ). these bits determine which channels are to have signaling inserted form the transmit signaling registers. 0 = do not source signaling data from the tsx regis ters for this channel 1 = source signaling data from the tsx registers for this channel register name: ssie4 register description: software signaling insertion enable 4 register address: 0bh bit # 7 6 5 4 3 2 1 0 name ch30 ch29 ch28 ch2 7 ch26 ch25 ch24 ch23 default 0 0 0 0 0 0 0 0 bits 0 to 7/software signaling insertion enable for channels 23 to 30 (ch23 to ch30 ). these bits determine which channels are to have signaling inserted form the transmit signaling registers. 0 = do not source signaling data from the ts registers for this channel 1 = source signaling data from the ts registers for this channel
product preview DS21Q55 95 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 15.2.3 software signaling insertion enable registers, t1 mode in t1 mode, only registers ssie1 through ssie3 are used since t here are only 24 channels in a t1 frame. register name: ssie1 register description: software signaling insertion enable 1 register address: 08h bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 to 7/software signaling insertion enable for and channels 1 to 8 (ch1 to ch8 ). these bits determine what channels are to have signaling inserted form the transmit signaling registers. 0 = do not source signaling data from the tsx registers for this channel 1 = source signaling data from the tsx registers for this channel register name: ssie2 register description: software signaling insertion enable 2 register address: 09h bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch 12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 to 7/software signaling insertion enable for channels 9 to 16 (ch9 to ch16 ). these bits determine what channels are to have signaling inserted form the transmit signaling registers. 0 = do no t source signaling data from the tsx registers for this channel 1 = source signaling data from the tsx registers for this channel register name: ssie3 register description: software signaling insertion enable 3 register address: 0ah bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 to 7/software signaling insertion enable for and channels 17 to 24 (ch17 to ch24 ). these bits determine what channels are to have signaling ins erted form the transmit signaling registers. 0 = do not source signaling data from the tsx registers for this channel 1 = source signaling data from the tsx registers for this channel
product preview DS21Q55 96 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 17.2.4 hardware - based transmit signaling in hardware - based mode, signaling data is input via the tsig pin. this signaling pcm stream is buffered and inserted to the data stream being input at the tser pin. signaling data can be input on a per - channel basis via the transmit - hardware signaling - channel select (ths cs) function. the framer can be set up to take the signaling data presented at the tsig pin and insert the signaling data into the pcm data stream that is being input at the tser pin. the user has the ability to control what channels are to have signaling data from the tsig pin inserted into them on a per - channel basis. see the special per - channel operation section. the signaling insertion capabilities of the framer are available whether the transmit side elastic store is enabled or disabled. if the elastic store is enabled, the backplane clock (tsysclk) can be either 1.544mhz or 2.048mhz.
product preview DS21Q55 97 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 16. per - channel idle code generation channel data can be replaced by an idle code on a per - channel basis in the transmit and receive directions. when operated in the t1 mode, only the first 24 channels are used; the remaining channels, ch25 ? ch32 are not used. the DS21Q55 contains a 64 - byte idle code array accessed by the idle array address register (iaar ) and the per - channel idle code register (pcicr ). the contents of the array contain the idle codes to be substituted into the appropriate transmit or receive channels. this substitution can be enabled and disabled on a per - channel basis by the transmit - channel idle - code enable registers (tcice1 ? 4) and receive - channel idle - code enable registers (rcice1 ? 4). to program idle codes, first select a channel by writing to the iaar register. then write the idle code to the pcicr register. for successive writes there is no need to load the iaar with the next consecutive address. the iaar register will automatically increment after a write to the pcicr register. the auto increment feature can be used for read operations as well. bits 6 and 7 (gtic, gric) of the iaar register can be used to block write a common idle code to all transmit or receive positions in the array with a single write to the pcicr register. the user can use the block write feature to set a common idle code for all transmit and receive channels in the iaar by setting both gtic and gric = 1. when a block write is enabled by gtic or gric, the value placed in the pcicr register will be written to all addresses in the transmit or receive idle array and to whatever address is in the lower 6 bits of the iaar register. therefore, when enabling only one of the block functions, gtic or gric, the user must set the lower 6 bits of the iaar register to any address in that block. bits 6 and 7 of the iaar register must be set = 0 for read operations. the tcice1 ? 4 and rcice1 ? 4 are used to enable idle - code replacement on a per - channel basis. idle code array address mapping table 18 - 1 bits 0 ? 5 of iaar register maps to channel 0 transmit channel 1 1 transmit c hannel 2 2 transmit channel 3 - - 30 transmit channel 31 31 transmit channel 32 32 receive channel 1 33 receive channel 2 34 receive channel 3 - - 62 receive channel 31 63 receive channel 32
product preview DS21Q55 98 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 16.1 idle code programming examples the following e xample sets transmit channel 3 idle code to 7eh: write iaar = 02h ;select channel 3 in the array write pcicr = 7eh ;set idle code to 7eh the following example sets transmit channels 3, 4, 5, and 6 idle code to 7eh and enables t ransmission of idle codes for those channels : write iaar = 02h ;select channel 3 in the array write pcicr = 7eh ;set channel 3 idle code to 7eh write pcicr = 7eh ;set channel 4 idle code to 7eh write pcicr = 7eh ;set channel 5 idle code to 7eh write pcicr = 7eh ;set channel 6 idle code to 7eh write tcice1 = 3ch ;enable transmission of idle codes for channels 3, 4, 5, and 6 the following example sets transmit channels 3, 4, 5, and 6 i dle code to 7eh, eeh, ffh, and 7eh respectively: write iaar = 02h write pcicr = 7eh write pcicr = eeh write pcicr = ffh write pcicr = 7eh the following example sets all transmit idl e codes to 7eh: write iaar = 40h write pcicr = 7eh the following example sets all receive and transmit idle codes to 7eh and enables idle code substitution in all e1 transmit and receive channels: write iaar = c0 h ;enable block write to all transmit and receive positions in the array write pcicr = 7eh ;7eh is idle code write tcice1 = feh ;enable idle code substitution for transmit channels 2 through 8 ;although an idle code was programmed for chann el 1 by the block write ;function above, enabling it for channel 1 would step on the frame ;alignment, alarms, and sa bits write tcice2 = ffh ;enable idle code substitution for transmit channels 9 through 16 write tcice3 = feh ;enable idle code substitut ion for transmit channels 18 through 24 ;although an idle code was programmed for channel 17 by the block write ;function above, enabling it for channel 17 would step on the cas frame ;alignment, and signaling information write tcice4 = ffh ;enable idle c ode substitution for transmit channels 25 through 32 write rcice1 = feh ;enable idle code substitution for receive channels 2 through 8 write rcice2 = ffh ;enable idle code substitution for receive channels 9 through 16 write rcice3 = feh ;enable idle c ode substitution for receive channels 18 through 24 write rcice4 = ffh ;enable idle code substitution for receive channels 25 through 32
product preview DS21Q55 99 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: iaar register description: idle array address register register address: 7eh bit # 7 6 5 4 3 2 1 0 name gric gtic iaa5 iaa4 iaa3 iaa2 iaa1 iaa0 default 0 0 0 0 0 0 0 0 bits 0 to 5/channel pointer address bits (iaa0 to iaa5). iaa0 is the lsb of the 5 - bit channel code. bit 6/global transmit idle code (gtic). setting this bit will cause all transmit idle codes to be set to the value written to the pcicr register. when using this bit, the user must place any transmit address in the iaa0 through iaa5 bits (00h ? 1fh). this bit must be set = 0 for read operations. bit 7/global r eceive idle code (gric). setting this bit will cause all receive idle codes to be set to the value written to the pcicr register. when using this bit, the user must place any receive address in the iaa0 through iaa5 bits (20h ? 3fh). this bit m ust be set = 0 for read operations. register name: pcicr register description: per - channel idle code register register address: 7fh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0 to 7/per - channel i dle code bits (c0 to c7). c0 is the lsb of the code (this bit is transmitted last). the tcice1 /2/3/4 are used to determine which of the 24 t1 or 32 e1 channels from the backplane to the t1 or e1 line should be overwritten with the code plac ed in the per - channel code array . register name: tcice1 register description: transmit channel idle code enable register 1 register address: 80h bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 1 to 8 code insertion control bits (ch1 to ch8). 0 = do not insert data from the idle code array into the transmit data stream 1 = insert data from the idle code array into the transmit data stream register name: tcice2 register description: transmit channel idle code enable register 2 register address: 81h bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 9 to 16 code insertion control b its (ch9 to ch16). 0 = do not insert data from the idle code array into the transmit data stream
product preview DS21Q55 100 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 1 = insert data from the idle code array into the transmit data stream
product preview DS21Q55 101 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: tcice3 register description: transmit channel idle code enable register 3 register address: 82h bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 17 to 24 code insertion control bits (ch17 to ch24). 0 = do not insert data from the id le code array into the transmit data stream 1 = insert data from the idle code array into the transmit data stream register name: tcice4 register description: transmit channel idle code enable register 4 register address: 83h bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 25 to 32 code insertion control bits (ch25 to ch32). 0 = do not insert data from the idle code array into the transmit data stream 1 = inser t data from the idle code array into the transmit data stream the receive - channel idle - code enable registers (rcice1 /2/3/4) are used to determine which of the 24 t1 or 32 e1 channels from the backplane to the t1 or e1 line should be overwri tten with the code placed in the per - channel code array. register name: rcice1 register description: receive channel idle code enable register 1 register address: 84h bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 1 to 8 code insertion control bits (ch1 to ch8). 0 = do not insert data from the idle code array into the receive data stream 1 = insert data from the idle code array into the receive data stream register na me: rcice2 register description: receive channel idle code enable register 2 register address: 85h bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 9 to 16 code in sertion control bits (ch9 to ch16). 0 = do not insert data from the idle code array into the receive data stream 1 = insert data from the idle code array into the receive data stream
product preview DS21Q55 102 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: rcice3 register description: receive ch annel idle code enable register 3 register address: 86h bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 17 to 24 code insertion control bits (ch17 to ch24). 0 = do not insert da ta from the idle code array into the receive data stream 1 = insert data from the idle code array into the receive data stream register name: rcice4 register description: receive channel idle code enable register 4 register address: 87h bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 25 to 32 code insertion control bits (ch25 to ch32). 0 = do not insert data from the idle code array into the receive data stream 1 = insert data from the idle code array into the receive data stream
product preview DS21Q55 103 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 17. channel blocking registers the receive - channel blocking registers (rcbr1 /rcbr2 /rcbr3 /rcbr4 ) and the transmit - channel blocking r egisters (tcbr1 /tcbr2 /tcbr3 /tcbr4 ) control the rchblk and tchblk pins, respectively. the rchblk and tchblk pins are user - programmable outputs that can be forced high or low during individual channels. these outputs can be used to block clocks to a usart or lapd controller in isdn ? pri applications. when the appropriate bits are set to a one, the rchblk and tchblk pin will be held high during the entire corresponding channel time. channels 25 through 32 are ignored when the device is operated in the t1 mode. also, the DS21Q55 can internally generate and output a bursty clock on a per - channel basis (n x 64kbps / 56kbps). see fractional t1/e1 support . register name: rcbr1 register descri ption: receive channel blocking register 1 register address: 88h bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 1 to 8 channel blocking control bits (ch1 to ch8). 0 = force the rchblk pin to remain low during this channel time 1 = force the rchblk pin high during this channel time register name: rcbr2 register description: receive channel blocking register 2 register address: 89h bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 9 to 16 channel blocking control bits (ch9 to ch16). 0 = force the rchblk pin to remain low during this channel time 1 = force the rchblk pin high during this channel time
product preview DS21Q55 104 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: rcbr3 register description: receive channel blocking register 3 register address: 8ah bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 17 to 24 c hannel blocking control bits (ch17 to ch24). 0 = force the rchblk pin to remain low during this channel time 1 = force the rchblk pin high during this channel time register name: rcbr4 register description: receive channel blocking register 4 register address: 8bh bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 bits 0 to 7/receive channels 25 to 32 channel blocking control bits (ch25 to ch32). 0 = force the rchblk pin to remain low during thi s channel time 1 = force the rchblk pin high during this channel time register name: tcbr1 register description: transmit channel blocking register 1 register address: 8ch bit # 7 6 5 4 3 2 1 0 name ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 def ault 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 1 to 8 channel blocking control bits (ch1 to ch8). 0 = force the tchblk pin to remain low during this channel time 1 = force the tchblk pin high during this channel time register name: tcbr2 register description: transmit channel blocking register 2 register address: 8dh bit # 7 6 5 4 3 2 1 0 name ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 9 to 16 channel blocking control bits (ch9 t o ch16). 0 = force the tchblk pin to remain low during this channel time 1 = force the tchblk pin high during this channel time
product preview DS21Q55 105 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: tcbr3 register description: transmit channel blocking register 3 register address: 8eh bit # 7 6 5 4 3 2 1 0 name ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit channels 17 to 24 channel blocking control bits (ch17 to ch24). 0 = force the tchblk pin to remain low during this channel time 1 = force the tch blk pin high during this channel time register name: tcbr4 register description: transmit channel blocking register 4 register address: 8fh bit # 7 6 5 4 3 2 1 0 name ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 default 0 0 0 0 0 0 0 0 b its 0 to 7/transmit channels 25 to 32 channel blocking control bits (ch25 to ch32). 0 = force the tchblk pin to remain low during this channel time 1 = force the tchblk pin high during this channel time
product preview DS21Q55 106 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 18. elastic stores operation the DS21Q55 contains dual t wo - frame, fully independent elastic stores, one for the receive direction and one for the transmit direction. the transmit - and receive - side elastic stores can be enabled/disabled independent of each other. also, each elastic store can interface to either a 1.544mhz or 2.048mhz/4.096mhz/8.192mhz/16.384mhz backplane without regard to the backplane rate the other elastic store is interfacing to. the elastic stores have two main purposes. first, they can be used for rate conversion. when the device is in the t1 mode, the elastic stores can rate - convert the t1 data stream to a 2.048mhz backplane. in e1 mode, the elastic store can rate - convert the e1 data stream to a 1.544mhz backplane. second, they can be used to absorb the differences in frequency and phase be tween the t1 or e1 data stream and an asynchronous (not locked) backplane clock (which can be 1.544mhz or 2.048mhz). in this mode, the elastic stores will manage the rate difference and perform controlled slips, deleting or repeating frames of data in orde r to manage the difference between the network and the backplane. the elastic stores can also be used to multiplex t1 or e1 data streams into higher backplane rates. see interleaved pcm bus operation.
product preview DS21Q55 107 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: escr register descripti on: elastic store control register register address: 4fh bit # 7 6 5 4 3 2 1 0 name tesalgn tesr tesmdm tese resalgn resr resmdm rese default 0 0 0 0 0 0 0 0 bit 0/receive elastic store enable (rese). 0 = elastic store is bypassed 1 = elastic store is enabled bit 1/receive elastic store minimum delay mode (resmdm). see minimum delay mode. 0 = elastic stores operate at full two frame depth 1 = elastic stores operate at 32 ? bit depth bit 2/receive elastic store reset (resr). setting this bit from a ze ro to a one forces the read and write pointers into opposite frames, maximizing the delay through the receive elastic store. should be toggled after rsysclk has been applied and is stable. see elastic stores initialization for details. do not leave this bit set high. bit 3/receive elastic store align (resalgn). setting this bit from a zero to a one will force the receive elastic store?s write/read pointers to a minimum separation of half a frame. no action will be taken if the pointer separation is al ready greater or equal to half a frame. if pointer separation is less than half a frame, the command will be executed and the data will be disrupted. should be toggled after rsysclk has been applied and is stable. must be cleared and set again for a subseq uent align. see elastic stores initialization for details. bit 4/transmit elastic store enable (tese). 0 = elastic store is bypassed 1 = elastic store is enabled bit 5/transmit elastic store minimum delay mode (tesmdm). see minimum delay mode for details . 0 = elastic stores operate at full two frame depth 1 = elastic stores operate at 32 - bit depth bit 6/transmit elastic store reset (tesr). setting this bit from a zero to a one forces the read and write pointers into opposite frames, maximizing the delay through the transmit elastic store. transmit data is lost during the reset. should be toggled after tsysclk has been applied and is stable. see elastic stores initialization for details. do not leave this bit set high. bit 7/transmit elastic store align (tesalgn). setting this bit from a zero to a one will force the transmit elastic store?s write/read pointers to a minimum separation of half a frame. no action will be taken if the pointer separation is already greater or equal to half a frame. if pointe r separation is less than half a frame, the command will be executed and the data will be disrupted. should be toggled after tsysclk has been applied and is stable. must be cleared and set again for a subsequent align. see elastic stores initialization fo r details.
product preview DS21Q55 108 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: sr5 register description: status register 5 register address: 1eh bit # 7 6 5 4 3 2 1 0 name - - tesf tesem tslip resf resem rslip default 0 0 0 0 0 0 0 0 bit 0/receive elastic store slip occurrence event (rs lip). set when the receive elastic store has either repeated or deleted a frame. bit 1/receive elastic store empty event (resem). set when the receive elastic store buffer empties and a frame is repeated. bit 2/receive elastic store full event (resf). se t when the receive elastic store buffer fills and a frame is deleted. bit 3/transmit elastic store slip occurrence event (tslip). set when the transmit elastic store has either repeated or deleted a frame. bit 4/transmit elastic store empty event (tesem) . set when the transmit elastic store buffer empties and a frame is repeated. bit 5/transmit elastic store full event (tesf). set when the transmit elastic store buffer fills and a frame is deleted. register name: imr5 register description : interrupt mask register 5 register address: 1fh bit # 7 6 5 4 3 2 1 0 name - - tesf tesem tslip resf resem rslip default 0 0 0 0 0 0 0 0 bit 0/receive elastic store slip occurrence event (rslip). 0 = interrupt masked 1 = interrupt enabled bit 1/r eceive elastic store empty event (resem). 0 = interrupt masked 1 = interrupt enabled bit 2/receive elastic store full event (resf). 0 = interrupt masked 1 = interrupt enabled bit 3/transmit elastic store slip occurrence event (tslip). 0 = interrupt maske d 1 = interrupt enabled bit 4/transmit elastic store empty event (tesem). 0 = interrupt masked 1 = interrupt enabled bit 5/transmit elastic store full event (tesf). 0 = interrupt masked 1 = interrupt enabled
product preview DS21Q55 109 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information .
product preview DS21Q55 110 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 18.1 receive side see the iocr1 and iocr2 registers for information on clock and i/o configurations. if the receive - side elastic store is enabled, then the user must provide either a 1.544mhz or 2.048mhz clock at the rsysclk pin. for higher rate system - clock applications, see the interleaved pcm bus operation section. the user has the option of either providing a frame/multiframe sync at the rsync pin or having the rsync pin provide a pulse on frame/multiframe boundaries. if signaling reinsertion is enabled, signaling data in ts16 is realigned to the multiframe - sync input on rsync. otherwise, a multiframe - sync input on rsync is treated as a simple frame boundary by the elastic store. the framer will always indicate frame boundaries on the network side of the elasti c store via the rfsync output whether the elastic store is enabled or not. multiframe boundaries will always be indicated via the rmsync output. if the elastic store is enabled, then rmsync will output the multiframe boundary on the backplane side of the e lastic store. 18.1.1 t1 mode if the user selects to apply a 2.048mhz clock to the rsysclk pin, then the data output at rser will be forced to all ones every fourth channel and the f - bit will be passed into the msb of ts0. hence, channels 1 (bits 1 ? 7), 5, 9, 13, 1 7, 21, 25, and 29 (timeslots 0 (bits 1 - 7), 4, 8, 12, 16, 20, 24, and 28) will be forced to a one. also, in 2.048mhz applications, the rchblk output will be forced high during the same channels as the rser pin. this is useful in t1 to e1 conversion applicat ions. if the two - frame elastic buffer either fills or empties, a controlled slip will occur. if the buffer empties, then a full frame of data will be repeated at rser and the sr5 .0 and sr5.1 bits will be set to a one. if the buffer fills, then a full frame of data will be deleted and the sr5.0 and sr5.2 bits will be set to a one. 18.1.2 e1 mode if the elastic store is enabled, then either cas or crc4 multiframe boundaries will be indicated via the rmsync output. if the user selects to apply a 1.544mhz clock to the rsysclk pin, then every fourth channel of the received e1 data will be deleted and a f - bit position (which will be forced to one) will be inserted. hence, c hannels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) wil l be deleted from the received e1 data stream. also, in 1.544mhz applications, the rchblk output will not be active in channels 25 through 32 (or in other words, rcbr4 is not active). if the two - frame elastic buffer either fills or empties, a controlled slip will occur. if the buffer empties, then a full frame of data will be repeated at rser and the sr5 .0 and sr5.1 bits will be set to a one. if the buffer fills, then a full frame of data will be deleted and the sr5.0 and sr5.2 bit s will be set to a one.
product preview DS21Q55 111 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 18.2 transmit side see the iocr1 and iocr2 registers for information on clock and i/o configurations. the operation of the transmit elastic store is very similar to the receive side. if the transmit - side ela stic store is enabled a 1.544mhz or 2.048mhz clock can be applied to the tsysclk input. for higher rate system - clock applications, see the interleaved pcm bus operation section. controlled slips in the transmit elastic store are reported in the sr5 .3 bit and the direction of the slip is reported in the sr5.4 and sr5.5 bits. 18.2.1 t1 mode if the user selects to apply a 2.048mhz clock to the tsysclk pin, then the data input at tser will be ignored every fourth channel. hence, channels 1, 5, 9, 13, 17, 2 1, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be ignored. the user can supply frame or multiframe sync pulse to the tssync input. also, in 2.048mhz applications, the tchblk output will be forced high during the channels ignored by the fram er. 18.2.2 e1 mode a 1.544mhz or 2.048mhz clock can be applied to the tsysclk input. the user must supply a frame - sync pulse or a multiframe - sync pulse to the tssync input. 18.3 elastic stores initialization there are two elastic - store initializations that can be use d to improve performance in certain applications, elastic store reset and elastic store align. both of these involve the manipulation of the elastic store?s read and write pointers and are useful primarily in synchronous applications (rsysclk/tsysclk are l ocked to rclk/tclk, respectively). see table below for details. elastic store delay after initialization table 20 - 1 initialization register bit delay receive elastic store reset transmit elastic store reset e scr .2 escr .6 8 clocks < delay < 1 frame 1 frame < delay < 2 frames receive elastic store align transmit elastic store align escr .3 escr .7 ? frame < delay < 1 ? frames ? frame < delay < 1 ? frames 18.4 minimum - delay mode elastic store minimum - delay mode can be used when the elastic store?s system clock is locked to its network clock (e.g., rclk locked to rsysclk for the receive side and tclk locked to tsysclk for the transmit side). escr .5 and escr.1 enable the transmit and receive elastic store minimum - delay modes. when enabled the elastic stores will be forced to a maximum depth of 32 bits instead of the normal two - frame depth. this feature is useful primarily in applications that interfac e to a 2.048mhz bus. certain restrictions apply when minimum delay mode is used. in addition to the restriction mentioned above, rsync must be configured as an output when the receive elastic store is in minimum delay mode and tsync must be configured as a n output when transmit minimum delay mode is enabled. in a typical application rsysclk and tsysclk are locked to rclk, and rsync (frame output mode) is connected to tssync (frame input mode). all of the slip contention logic in the framer is disabled (sinc e slips cannot occur). on power - up, after the rsysclk and tsysclk signals have locked to their
product preview DS21Q55 112 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . respective network clock signals, the elastic store reset bits (escr.2 and escr.6) should be toggled from a zero to a one to ensure proper operation.
product preview DS21Q55 113 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 19. g.706 int ermediate crc - 4 updating (e1 mode only) the DS21Q55 can implement the g.706 crc - 4 recalculation at intermediate path points. when this mode is enabled, the data stream presented at tser will already have the fas/nfas, crc multiframe alignment word, and crc - 4 checksum in timeslot 0. the user can modify the sa bit positions; this change in data content will be used to modify the crc - 4 checksum. the modification, however, will not corrupt any error information the original crc - 4 checksum might contain. in this mode of operation, tsync must be configured to multiframe mode. the data at tser must be aligned to the tsync signal. if tsync is an input then the user must assert tsync aligned at the beginning of the multiframe relative to tser. if tsync is an output, the user must multiframe - align the data presented to tser. crc - 4 recalculate method figure 21 - 1 tser xor crc-4 calculator extract old crc-4 code insert new crc-4 code modify sa bit positions new sa bit data + tposo/tnego
product preview DS21Q55 114 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 20. t1 bit oriented code (boc) controller the DS21Q55 contains a boc generator on the transmit side and a boc detector on the receive side. the boc function i s available only in t1 mode. 20.1 transmit boc bits 0 through 5 in the tfdl register contain the boc message to be transmitted. setting bocc .0 = 1 causes the transmit boc controller to immediately begin inserting the boc sequence int o the fdl bit position. the transmit boc controller automatically provides the abort sequence. boc messages will be transmitted as long as bocc.0 is set. to transmit a boc, use the following: 1) write 6 - bit code into the tfdl register. 2) set sboc bit in bocc register = 1 . 20.2 receive boc the receive boc function is enabled by setting bocc .4 = 1. the rfdl register will now operate as the receive boc message and information register. the lower six bits of the rfdl register (boc message bits) are preset to all ones. when the boc bits change state, the boc change of state indicator, sr8.0 will alert the host. the host will then read the rfdl register to get the boc message. a change of state will occur when either a new boc code has been present for time determined by the receive boc filter bits, rbf0 and rbf1, in the bocc register. to receive a boc, use the following: 1) set integration time via bocc .1 and bocc.2. 2) enable the receive boc function (bocc .4 = 1). 3) enable interrupt (imr8.0 = 1). 4) wait for interrupt to occur. 5) read the rfdl register. 6) the lower six bits of the rfdl register is the message.
product preview DS21Q55 115 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: bocc register description: boc control r egister register address: 37h bit # 7 6 5 4 3 2 1 0 name - - - rboce rbr rbf1 rbf0 sboc default 0 0 0 0 0 0 0 0 bit 0/send boc (sboc). set = 1 to transmit the boc code placed in bits 0 to 5 of the tfdl register. bits 1 to 2/receive boc filter bits (rbf0, rbf1). the boc filter sets the number of consecutive patterns that must be received without error prior to an indication of a valid message. rbf1 rbf0 consecutive boc codes for valid sequence identification 0 0 none 0 1 3 1 0 5 1 1 7 bit 3/receive boc reset (rbr). a 0 to 1 transition will reset the boc circuitry. must be cleared and set again for a subsequent reset. bit 4/receive boc enable (rboce). enables the receive boc function. the rfdl register will report the received boc code. 0 = receive boc function disabled 1 = receive boc function enabled. the rfdl register will report boc messages bit 5/unused, must be set to zero for proper operation. bit 6/unused, must be set to zero for proper operation . bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 116 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: rfdl (rfdl register bit usage when bocc .4 = 1) register description: receive fdl register register address: c0h bit # 7 6 5 4 3 2 1 0 n ame - - rboc5 rboc4 rboc3 rboc2 rboc1 rboc0 default 0 0 0 0 0 0 0 0 bit 0 / boc bit 0 (rboc0). bit 1/boc bit 1 (rboc1). bit 2 / boc bit 2 (rboc2). bit 3/boc bit 3 (rboc3). bit 4/boc bit 4 (rboc4). bit 5/boc bit 5 (rboc5). bit 6/this bit position is unused when bocc.4 = 1. bit 7/this bit position is unused when bocc.4 = 1. register name: sr8 register description: status register 8 register address: 24h bit # 7 6 5 4 3 2 1 0 name - - bocc rfdlad rfdlf tfdle rmtch rboc default 0 0 0 0 0 0 0 0 bit 0/receive boc detector change of state event (rboc). set whenever the boc detector sees a change of state to a valid boc. the setting of this bit prompts the user to read the rfdl register. bit 1/receive fdl match event (rm tch). set whenever the contents of the rfdl register matches rfdlm1 or rfdlm2 . bit 2/tfdl register empty event(tfdle). set when the transmit fdl buffer (tfdl) empties. bit 3/rfdl regist er full event (rfdlf). set when the receive fdl buffer (rfdl) fills to capacity. bit 4/rfdl abort detect event (rfdlad). set when eight consecutive ones are received on the fdl. bit 5/boc clear event (bocc). set when 30 fdl bits occur withou t an abort sequence.
product preview DS21Q55 117 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: imr8 register description: interrupt mask register 8 register address: 25h bit # 7 6 5 4 3 2 1 0 name - - bocc rfdlad rfdlf tfdle rmtch rboc default 0 0 0 0 0 0 0 0 bit 0/receive boc detector chan ge of state event (rboc). 0 = interrupt masked 1 = interrupt enabled bit 1/receive fdl match event (rmtch). 0 = interrupt masked 1 = interrupt enabled bit 2/tfdl register empty event (tfdle). 0 = interrupt masked 1 = interrupt enabled bit 3/rfdl register full event (rfdlf). 0 = interrupt masked 1 = interrupt enabled bit 4/rfdl abort detect event (rfdlad). 0 = interrupt masked 1 = interrupt enabled bit 5/boc clear event (bocc). 0 = interrupt masked 1 = interrupt e nabled
product preview DS21Q55 118 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 21. additional (sa) and international (si) bit operation (e1 only) the DS21Q55, when operated in the e1 mode, provides for access to both the sa and the si bits via three different methods. the first method is via a hardware scheme using the rlink/rlc lk and tlink/tlclk pins. the second method involves using the internal raf /rnaf and taf /tnaf registers. the third method involves an expanded version of the second method. 21.1 hardware scheme (method 1) on the receive side, all of the received data is reported at the rlink pin. using the e1rcr2 register the user can control the rlclk pin to pulse during any combination of sa bits. this allows the user to create a clock that can be used to capture the needed sa bits. if rsync is programmed to output a frame boundary, it will identify the si bits. on the transmit side, the individual sa bits can be either sourced from the internal tnaf register or externally from the tlink pin. using t he e1tcr2 register the framer can be programmed to source any combination of the sa bits from the tlink pin. si bits can be sampled through the tser pin if by setting e1tcr1 .4 = 0. 21.2 internal register scheme based on double - fram e (method 2) on the receive side, the raf and rnaf registers will always report the data as it received in the sa and si bit locations. the raf and rnaf registers are updated on align frame boundaries. the setting of the receive al ign frame bit in status register 4 (sr4 .0) will indicate that the contents of the raf and rnaf have been updated. the host can use the sr4.0 bit to know when to read the raf and rnaf registers. the host has 250s to retrieve the data before it is lost. on the transmit side, data is sampled from the taf and tnaf registers with the setting of the transmit align frame bit in status register 4 (sr4 .3). the host can use the sr4.3 bit to know when to update the ta f and tnaf registers. it has 250s to update the data or else the old data will be retransmitted . if the taf an tnaf registers are only being used to source the align frame and nonalign frame - sync patterns, then the host need only write once to these regis ters . data in the si bit position will be overwritten if the framer is programmed: (1) to source the si bits from the tser pin, (2) in the crc4 mode, or (3) with automatic e - bit insertion enabled. data in the sa bit position will be overwritten if any of t he e1tcr2 .3 to e1tcr2.7 bits are set to one.
product preview DS21Q55 119 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: raf register description: receive align frame register register address: c6h bit # 7 6 5 4 3 2 1 0 name si 0 0 1 1 0 1 1 default 0 0 0 0 0 0 0 0 bit 0/frame al ignment signal bit (1). bit 1/frame alignment signal bit (1). bit 2/frame alignment signal bit (0). bit 3/frame alignment signal bit (1). bit 4/frame alignment signal bit (1). bit 5/frame alignment signal bit (0). bit 6/frame alignment signal bit (0) . bit 7/international bit (si). register name: rnaf register description: receive nonalign frame register register address: c7h bit # 7 6 5 4 3 2 1 0 name si 1 a sa4 sa5 sa6 sa7 sa8 default 0 0 0 0 0 0 0 0 bit 0/additional bit 8 (sa 8). bit 1/additional bit 7 (sa7). bit 2/additional bit 6 (sa6). bit 3/additional bit 5 (sa5). bit 4/additional bit 4 (sa4). bit 5 / remote alarm (a). bit 6/frame nonalignment signal bit (1). bit 7/international bit (si).
product preview DS21Q55 120 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: taf register description: transmit align frame register register address: d0h bit # 7 6 5 4 3 2 1 0 name si 0 0 1 1 0 1 1 default 0 0 0 1 1 0 1 1 bit 0/frame alignment signal bit (1). bit 1/frame alignment signal bit (1). bit 2/frame alignment signal bit (0). bit 3/frame alignment signal bit (1). bit 4/frame alignment signal bit (1). bit 5/frame alignment signal bit (0). bit 6/frame alignment signal bit (0). bit 7/international bit (si). register name: tnaf register descrip tion: transmit nonalign frame register register address: d1h bit # 7 6 5 4 3 2 1 0 name si 1 a sa4 sa5 sa6 sa7 sa8 default 0 1 0 0 0 0 0 0 bit 0/additional bit 8 (sa8). bit 1/additional bit 7 (sa7). bit 2/additional bit 6 (sa6). bit 3/additional bit 5 (sa5). bit 4/additional bit 4 (sa4). bit 5/remote alarm (used to transmit the alarm a). bit 6/frame nonalignment signal bit (1). bit 7/international bit (si).
product preview DS21Q55 121 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 21.3 internal register scheme based on crc4 multiframe (method 3) on the receive side, the re is a set of eight registers (rsiaf , rsinaf , rra , rsa4 to rsa8 ) that report the si and sa bits as they are received. these registers are updated with the setting of the receive crc4 multi frame bit in status register 2 (sr4 .1). the host can use the sr4.1 bit to know when to read these registers. the user has 2ms to retrieve the data before it is lost. the msb of each register is the first received. please see the following regis ter descriptions for more details. on the transmit side, there is also a set of eight registers (tsiaf , tsinaf , tra , tsa4 to tsa8 ) that via the transmit sa bit control register (tsacr), c an be programmed to insert both si and sa data. data is sampled from these registers with the setting of the transmit multiframe bit in status register 2 (sr4 .4). the host can use the sr4.4 bit to know when to update these registers. it has 2ms to update the data or else the old data will be retransmitted. the msb of each register is the first bit transmitted. see the following register descriptions for details. register name: rsiaf register description: receive si bits of the al ign frame register address: c8h bit # 7 6 5 4 3 2 1 0 name sif0 sif2 sif4 sif6 sif8 sif10 sif12 sif14 default 0 0 0 0 0 0 0 0 bit 0/si bit of frame 14(sif14). bit 1/si bit of frame 12(sif12). bit 2/si bit of frame 10(sif10). bit 3/si bit of frame 8(sif8). bit 4/si bit of frame 6(sif6). bit 5/si bit of frame 4(sif4). bit 6/si bit of frame 2(sif2). bit 7/si bit of frame 0(sif0).
product preview DS21Q55 122 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: rsinaf register description: receive si bits of the nonalign frame register address: c9h bit # 7 6 5 4 3 2 1 0 name sif1 sif3 sif5 sif7 sif9 sif11 sif13 sif15 default 0 0 0 0 0 0 0 0 bit 0/si bit of frame 15(sif15). bit 1/si bit of frame 13(sif13). bit 2/si bit of frame 11(sif11). bit 3/si bit of frame 9(sif9). bit 4/si bit of f rame 7(sif7). bit 5/si bit of frame 5(sif5). bit 6/si bit of frame 3(sif3). bit 7/si bit of frame 1(sif1). register name: rra register description: receive remote alarm register address: cah bit # 7 6 5 4 3 2 1 0 name rraf1 rraf3 rraf 5 rraf7 rraf9 rraf11 rraf13 rraf15 default 0 0 0 0 0 0 0 0 bit 0/remote alarm bit of frame 15(rraf15). bit 1/remote alarm bit of frame 13(rraf13). bit 2/remote alarm bit of frame 11(rraf11). bit 3/remote alarm bit of frame 9(rraf9). bit 4/remote ala rm bit of frame 7(rraf7). bit 5/remote alarm bit of frame 5(rraf5). bit 6/remote alarm bit of frame 3(rraf3). bit 7/remote alarm bit of frame 1(rraf1).
product preview DS21Q55 123 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: rsa4 register description: receive sa4 bits register address: cbh bit # 7 6 5 4 3 2 1 0 name rsa4f1 rsa4f3 rsa4f5 rsa4f7 rsa4f9 rsa4f11 rsa4f13 rsa4f15 default 0 0 0 0 0 0 0 0 bit 0/sa4 bit of frame 15(rsa4f15). bit 1/sa4 bit of frame 13(rsa4f13). bit 2/sa4 bit of frame 11(rsa4f11). bit 3/sa4 bit of frame 9(rsa4f9 ). bit 4/sa4 bit of frame 7(rsa4f7). bit 5/sa4 bit of frame 5(rsa4f5). bit 6/sa4 bit of frame 3(rsa4f3). bit 7/sa4 bit of frame 1(rsa4f1). register name: rsa5 register description: receive sa5 bits register address: cch bit # 7 6 5 4 3 2 1 0 name rsa5f1 rsa5f3 rsa5f5 rsa5f7 rsa5f9 rsa5f11 rsa5f13 rsa5f15 default 0 0 0 0 0 0 0 0 bit 0/sa5 bit of frame 15(rsa5f15). bit 1/sa5 bit of frame 13(rsa5f13). bit 2/sa5 bit of frame 11(rsa5f11). bit 3/sa5 bit of frame 9(rsa5f9). bit 4/sa5 bit of frame 7(rsa5f7). bit 5/sa5 bit of frame 5(rsa5f5). bit 6/sa5 bit of frame 3(rsa5f3). bit 7/sa5 bit of frame 1(rsa5f1).
product preview DS21Q55 124 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: rsa6 register description: receive sa6 bits register address: cdh bit # 7 6 5 4 3 2 1 0 na me rsa6f1 rsa6f3 rsa6f5 rsa6f7 rsa6f9 rsa6f11 rsa6f13 rsa6f15 default 0 0 0 0 0 0 0 0 bit 0/sa6 bit of frame 15(rsa6f15). bit 1/sa6 bit of frame 13(rsa6f13). bit 2/sa6 bit of frame 11(rsa6f11). bit 3/sa6 bit of frame 9(rsa6f9). bit 4/sa6 bit of fram e 7(rsa6f7). bit 5/sa6 bit of frame 5(rsa6f5). bit 6/sa6 bit of frame 3(rsa6f3). bit 7/sa6 bit of frame 1(rsa6f1). register name: rsa7 register description: receive sa7 bits register address: ceh bit # 7 6 5 4 3 2 1 0 name rsa7f1 rsa 7f3 rsa7f5 rsa7f7 rsa7f9 rsa7f11 rsa7f13 rsa7f15 default 0 0 0 0 0 0 0 0 bit 0/sa7 bit of frame 15(rsa7f15). bit 1/sa7 bit of frame 13(rsa7f13). bit 2/sa7 bit of frame 11(rsa7f11). bit 3/sa7 bit of frame 9(rsa7f9). bit 4/sa7 bit of frame 7(rsa7f7). bit 5/sa7 bit of frame 5(rsa7f5). bit 6/sa7 bit of frame 3(rsa7f3). bit 7/sa7 bit of frame 1(rsa4f1).
product preview DS21Q55 125 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: rsa8 register description: receive sa8 bits register address: cfh bit # 7 6 5 4 3 2 1 0 name rsa8f1 rsa8f3 rsa8f5 rsa8f7 rsa8f9 rsa8f11 rsa8f13 rsa8f15 default 0 0 0 0 0 0 0 0 bit 0/sa8 bit of frame 15(rsa8f15). bit 1/sa8 bit of frame 13(rsa8f13). bit 2/sa8 bit of frame 11(rsa8f11). bit 3/sa8 bit of frame 9(rsa8f9). bit 4/sa8 bit of frame 7(rsa8f7). bit 5/sa8 bit of frame 5(rsa8f5). bit 6/sa8 bit of frame 3(rsa8f3). bit 7/sa8 bit of frame 1(rsa8f1).
product preview DS21Q55 126 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: tsiaf register description: transmit si bits of the align frame register address: d2h bit # 7 6 5 4 3 2 1 0 name tsif0 tsif2 t sif4 tsif6 tsif8 tsif10 tsif12 tsif14 default 0 0 0 0 0 0 0 0 bit 0/si bit of frame 14(tsif14). bit 1/si bit of frame 12(tsif12). bit 2/si bit of frame 10(tsif10). bit 3/si bit of frame 8(tsif8). bit 4/si bit of frame 6(tsif6). bit 5/si bit of fram e 4(tsif4). bit 6/si bit of frame 2(tsif2). bit 7/si bit of frame 0(tsif0).
product preview DS21Q55 127 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: tsinaf register description: transmit si bits of the nonalign frame register address: d3h bit # 7 6 5 4 3 2 1 0 name tsif1 tsif3 tsif5 tsif7 tsif9 tsif11 tsif13 tsif15 default 0 0 0 0 0 0 0 0 bit 0/si bit of frame 15(tsif15). bit 1/si bit of frame 13(tsif13). bit 2/si bit of frame 11(tsif11). bit 3/si bit of frame 9(tsif9). bit 4/si bit of frame 7(tsif7). bit 5/si bit of frame 5(tsif5) . bit 6/si bit of frame 3(tsif3). bit 7/si bit of frame 1(tsif1). register name: tra register description: transmit remote alarm register address: d4h bit # 7 6 5 4 3 2 1 0 name traf1 traf3 traf5 traf7 traf9 traf11 traf13 traf15 defau lt 0 0 0 0 0 0 0 0 bit 0/remote alarm bit of frame 15(traf15). bit 1/remote alarm bit of frame 13(traf13). bit 2/remote alarm bit of frame 11(traf11). bit 3/remote alarm bit of frame 9(traf9). bit 4/remote alarm bit of frame 7(traf7). bit 5/remote a larm bit of frame 5(traf5). bit 6/remote alarm bit of frame 3(traf3). bit 7/remote alarm bit of frame 1(traf1).
product preview DS21Q55 128 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: tsa4 register description: transmit sa4 bits register address: d5h bit # 7 6 5 4 3 2 1 0 name tsa4f1 tsa4f 3 tsa4f5 tsa4f7 tsa4f9 tsa4f11 tsa4f13 tsa4f15 default 0 0 0 0 0 0 0 0 bit 0/sa4 bit of frame 15(tsa4f15). bit 1/sa4 bit of frame 13(tsa4f13). bit 2/sa4 bit of frame 11(tsa4f11). bit 3/sa4 bit of frame 9(tsa4f9). bit 4/sa4 bit of frame 7(tsa4f7). b it 5/sa4 bit of frame 5(tsa4f5). bit 6/sa4 bit of frame 3(tsa4f3). bit 7/sa4 bit of frame 1(tsa4f1). register name: tsa5 register description: transmit sa5 bits register address: d6h bit # 7 6 5 4 3 2 1 0 name tsa5f1 tsa5f3 tsa5f5 tsa 5f7 tsa5f9 tsa5f11 tsa5f13 tsa5f15 default 0 0 0 0 0 0 0 0 bit 0/sa5 bit of frame 15(tsa5f15). bit 1/sa5 bit of frame 13(tsa5f13). bit 2/sa5 bit of frame 11(tsa5f11). bit 3/sa5 bit of frame 9(tsa5f9). bit 4/sa5 bit of frame 7(tsa5f7). bit 5/sa5 bit of frame 5(tsa5f5). bit 6/sa5 bit of frame 3(tsa5f3). bit 7/sa5 bit of frame 1(tsa5f1).
product preview DS21Q55 129 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: tsa6 register description: transmit sa6 bits register address: d7h bit # 7 6 5 4 3 2 1 0 name tsa6f1 tsa6f3 tsa6f5 tsa6f7 tsa6f9 tsa6f11 tsa6f13 tsa6f15 default 0 0 0 0 0 0 0 0 bit 0/sa6 bit of frame 15(tsa6f15). bit 1/sa6 bit of frame 13(tsa6f13). bit 2/sa6 bit of frame 11(tsa6f11). bit 3/sa6 bit of frame 9(tsa6f9). bit 4/sa6 bit of frame 7(tsa6f7). bit 5/sa6 bit of frame 5(tsa6f5). bit 6/sa6 bit of frame 3(tsa6f3). bit 7/sa6 bit of frame 1(tsa6f1). register name: tsa7 register description: transmit sa7 bits register address: d8h bit # 7 6 5 4 3 2 1 0 name tsa7f1 tsa7f3 tsa7f5 tsa7f7 tsa7f9 tsa7f11 tsa 7f13 tsa7f15 default 0 0 0 0 0 0 0 0 bit 0/sa7 bit of frame 15(tsa7f15). bit 1/sa7 bit of frame 13(tsa7f13). bit 2/sa7 bit of frame 11(tsa7f11). bit 3/sa7 bit of frame 9(tsa7f9). bit 4/sa7 bit of frame 7(tsa7f7). bit 5/sa7 bit of frame 5(tsa7f5). bit 6/sa7 bit of frame 3(tsa7f3). bit 7/sa7 bit of frame 1(tsa4f1).
product preview DS21Q55 130 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: tsa8 register description: transmit sa8 bits register address: d9h bit # 7 6 5 4 3 2 1 0 name tsa8f1 tsa8f3 tsa8f5 tsa8f7 tsa8f9 tsa8f11 tsa8f13 tsa8f1 5 default 0 0 0 0 0 0 0 0 bit 0/sa8 bit of frame 15(tsa8f15). bit 1/sa8 bit of frame 13(tsa8f13). bit 2/sa8 bit of frame 11(tsa8f11). bit 3/sa8 bit of frame 9(tsa8f9). bit 4/sa8 bit of frame 7(tsa8f7). bit 5/sa8 bit of frame 5(tsa8f5). bit 6/sa8 b it of frame 3(tsa8f3). bit 7/sa8 bit of frame 1(tsa8f1).
product preview DS21Q55 131 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: tsacr register description: transmit sa bit control register register address: dah bit # 7 6 5 4 3 2 1 0 name siaf sinaf ra sa4 sa5 sa6 sa7 sa8 default 0 0 0 0 0 0 0 0 bit 0/additional bit 8 insertion control bit (sa8). 0 = do not insert data from the tsa8 register into the transmit data stream 1 = insert data from the tsa8 register into the transmit data stream bit 1/additional bit 7 insertion control bit (sa7). 0 = do not insert data from the tsa7 register into the transmit data stream 1 = insert data from the tsa7 register into the transmit data stream bit 2/additional bit 6 insertion control bit (sa6). 0 = do not insert data from the tsa6 register into the transmit data stream 1 = insert data from the tsa6 register into the transmit data stream bit 3/additional bit 5 insertion control bit (sa5). 0 = do not insert data from the tsa 5 register into the transmit data stream 1 = insert data from the tsa5 register into the transmit data stream bit 4/additional bit 4 insertion control bit (sa4). 0 = do not insert data from the tsa4 register into the transmit data stream 1 = insert data from the tsa4 register into the transmit data stream bit 5/remote alarm insertion control bit (ra). 0 = do not insert data from the tra register into the transmit data stream 1 = insert data f rom the tra register into the transmit data stream bit 6/international bit in nonalign frame insertion control bit (sinaf). 0 = do not insert data from the tsinaf register into the transmit data stream 1 = insert data from the t sinaf register into the transmit data stream bit 7/international bit in align frame insertion control bit (siaf). 0 = do not insert data from the tsiaf register into the transmit data stream 1 = insert data from the tsiaf register into the transmit data stream
product preview DS21Q55 132 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22. hdlc controllers this device has two enhanced hdlc controllers, hdlc #1 and hdlc #2. each controller is configurable for use with time slots, or sa4 to sa8 bits (e1 mode) or the fdl (t1 mode). each hdlc c ontroller has 128 byte buffers in both the transmit and receive paths. when used with time slots, the user can select any time slot or multiple time slots, contiguous or noncontiguous, as well as any specific bits within the time slot(s) to assign to the h dlc controllers. the user must take care to not map both transmit hdlc controllers to the same sa bits, time slots or, in t1 mode, map both controllers to the fdl. hdlc #1 and hdlc #2 are identical in operation and therefore the following operational des cription refers only to a singular controller. the hdlc controller performs all the necessary overhead for generating and receiving performance report messages (prm) as described in ansi t1.403 and the messages as described in at&t tr54016. the hdlc contr oller automatically generates and detects flags, generates and checks the crc check sum, generates and detects abort sequences, stuffs and de - stuffs zeros, and byte aligns to the data stream. the 128 - byte buffers in the hdlc controller are large enough to allow a full prm to be received or transmitted without host intervention. 22.1 basic operation details to allow the framer to properly source/receive data from/to the hdlc controllers, the legacy fdl circuitry (see the legacy fdl support (t1 mode) section.) sh ould be disabled. the hdlc registers are divided into four groups: control/configuration, status/information, mapping, and fifos. table 24 - 1 lists these registers by group.
product preview DS21Q55 1 33 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . hdlc controller registers table 24 - 1 name function control/configuration h1tc , hdlc #1 transmit control register h2tc , hdlc #2 transmit control register general control over the transmit hdlc controllers h1rc , hdlc #1 receive control register h2rc , hdlc #2 receive control registe r general control over the receive hdlc controllers h1fc , hdlc #1 fifo control register h2fc , hdlc #2 fifo control register sets high watermark for receiver and low watermark for transmitter status/information sr6 , hdlc #1 status register sr7 , hdlc #2 status register key status information for both transmit and receive directions imr6 , hdlc #1 interrupt mask register imr7 , hdlc #2 interrupt mask register selects which bits in s tatus registers (sr7 and sr8 ) will cause interrupts info4 , hdlc #1 & #2 information register info5 , hdlc #1 information register info6 , hdlc #2 information register information on hdlc cont roller h1rpba , hdlc #1 receive packet bytes available register h2rpba , hdlc #2 receive packet bytes available register indicates the number of bytes that can be read from the receive fifo h1tfba , hdlc #1 trans mit fifo buffer available register h2tfba , hdlc #2 transmit fifo buffer available register indicates the number of bytes that can be written to the transmit fifo mapping h1rcs1 , h1rcs2 , h1rcs3 , h1rcs4 , hdlc #1 receive channel select registers h2rcs1 , h2rcs2 , h2rcs3 , h2rcs4 , hdlc #2 receive channel select registers selects which channels will be mapped to the receive hdlc controller h1rtsbs , hdlc #1 receive ts/sa bit select register h2rtsbs , hdlc #2 receive ts/sa bit select register selects which bits in a channel will be used or which sa bits will be used by the receive hdlc controller h 1tcs1 , h1tcs2 , h1tcs3 , h1tcs4 , hdlc #1 transmit channel select registers h2tcs1 , h2tcs2 , h2tcs3 , h2tcs4 , hdlc #2 transmit channel selec t registers selects which channels will be mapped to the transmit hdlc controller h1ttsbs , hdlc # 1 transmit ts/sa bit select register h2ttsbs , hdlc # 2 transmit ts/sa bit select register selects which bits in a channel wil l be used or which sa bits will be used by the transmit hdlc controller fifos h1rf , hdlc #1 receive fifo register h2rf , hdlc #2 receive fifo register access to 128 - byte receive fifo h1tf , hdlc #1 transmit fifo re gister h2tf , hdlc #2 transmit fifo register access to 128 - byte transmit fifo
product preview DS21Q55 134 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.2 hdlc configuration basic configuration of the hdlc controllers is accomplished via the hxtc and hxrc registers. operating features such as crc generation, zero stuffer, transmit and receive hdlc mapping options, and idle flags are selected here. also, the hdlc controllers are reset via these registers. register name: h1tc , h2tc register description: hdlc #1 transmit control, hdlc #2 transmit control register address: 90h, a0h bit # 7 6 5 4 3 2 1 0 name nofs teoml thr thms tfs teom tzsd tcrcd default 0 0 0 0 0 0 0 0 bit 0/transmit crc defeat (tcrcd). a 2 - byte crc code is automatically appended to the outbound message. this bit can be used to disable the crc function. 0 = enable crc generation (normal operation) 1 = disable crc generation bit 1/transmit zero stuffer defeat (tzsd). the zero stuffer function automatically inserts a zero in the message field (between the flags) after five consecutive ones to prevent the emulation of a flag or abort sequence by the data pattern. the receiver automatically removes (de - stuffs) any zero after five ones in the message field. 0 = enable the zero stuffer (normal operation) 1 = disable t he zero stuffer bit 2/transmit end of message (teom). should be set to a one just before the last data byte of an hdlc packet is written into the transmit fifo at hxtf. if not disabled via tcrcd, the transmitter will automatically append a 2 - byte crc cod e to the end of the message. bit 3/transmit flag/idle select (tfs). this bit selects the inter - message fill character after the closing and before the opening flags (7eh). 0 = 7eh 1 = ffh bit 4/transmit hdlc mapping select (thms). 0 = transmit hdlc assi gned to channels 1 = transmit hdlc assigned to fdl (t1 mode), sa bits (e1 mode) bit 5/transmit hdlc reset (thr). will reset the transmit hdlc controller and flush the transmit fifo. an abort followed by 7eh or ffh flags/idle will be transmitted until a ne w packet is initiated by writing new data into the fifo. must be cleared and set again for a subsequent reset. 0 = normal operation 1 = reset transmit hdlc controller and flush the transmit fifo bit 6/transmit end of message and loop (teoml). to loop on a message, should be set to a one just before the last data byte of an hdlc packet is written into the transmit fifo. the message will repeat until the user clears this bit or a new message is written to the transmit fifo. if the host clears the bit, th e looping message will complete then flags will be transmitted until new message is written to the fifo. if the host terminates the loop by writing a new message to the fifo the loop will terminate, one or two flags will be transmitted and the new message will start. if not disabled via tcrcd, the transmitter will automatically append a 2 - byte crc code to the end of all messages. this is useful for transmitting consecutive ss7 fisus without host intervention. bit 7/number of flags select (nofs). 0 = send one flag between consecutive messages 1 = send two flags between consecutive messages
product preview DS21Q55 135 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: h1rc , h2rc register description: hdlc #1 receive control, hdlc #2 receive control register address: 31h, 32h bit # 7 6 5 4 3 2 1 0 name rhr rhms - - - - - rsfd default 0 0 0 0 0 0 0 0 bit 0/receive ss7 fill in signal unit delete (rsfd). 0 = normal operation. all fisus are stored in the receive fifo and reported to the host. 1 = when a consecutive fisu having the same bsn the previous fisu is detected, it is deleted without host intervention. bit 1/unused, must be set to zero for proper operation. bit 2/unused, must be set to zero for proper operation. bit 3/unused, must be set to zero for proper operation. bit 4/un used, must be set to zero for proper operation. bit 5/unused, must be set to zero for proper operation. bit 6/receive hdlc mapping select (rhms) . 0 = receive hdlc assigned to channels 1 = receive hdlc assigned to fdl (t1 mode), sa bits (e1 mode) bit 7/ receive hdlc reset (rhr). will reset the receive hdlc controller and flush the receive fifo. must be cleared and set again for a subsequent reset. 0 = normal operation 1 = reset receive hdlc controller and flush the receive fifo
product preview DS21Q55 136 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.2.1 fifo control control of the transmit and receive fifos is accomplished via the fifo control (hxfc). the fifo control register sets the watermarks for both the transmit and receive fifo. bits 3 ? 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. when the transmit fifo empties below the low watermark, the tlwm bit in the appropriate hdlc status register sr6 or sr7 will be set. tlwm is a real - time bit and will remain set as long as the transmit fifo?s read pointer is below the watermark. if enabled, this condition can also cause an interrupt via the *int pin. when the receive fifo fills above the high watermark, the rhwm bit in the appropriate hdlc status register will be set. rhwm is a real - time bit and will remain set as long as the receive fifo?s write pointer is above the watermark. if enabled, this condition can also cause an interrupt via the *int pin. register name: h1fc , h2fc register description: hdlc # 1 fifo control, hdlc # 2 fifo control register address: 91h , a1h bit # 7 6 5 4 3 2 1 0 name - - tflwm2 tflwm 1 tflwm0 rfhwm2 rfhwm1 rfhwm0 default 0 0 0 0 0 0 0 0 bits 0 to 2/receive fifo high watermark select (rfhwm0 to rfhwm2). rfhwm2 rfhwm1 rfhwm0 receive fifo watermark (bytes) 0 0 0 4 0 0 1 16 0 1 0 32 0 1 1 48 1 0 0 64 1 0 1 80 1 1 0 96 1 1 1 112 bits 3 to 5/transmit fifo low watermark select (tflwm0 to tflwm2). tflwm2 tflwm1 tflwm0 transmit fifo watermark (bytes) 0 0 0 4 0 0 1 16 0 1 0 32 0 1 1 48 1 0 0 64 1 0 1 80 1 1 0 96 1 1 1 112 bit 6/unused, must be set to zero for proper operation. bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 137 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.3 hdlc mapping 22.3.1 receive the hdlc controllers need to be assigned a space in the t1/e1 bandwidth in which they will transmit a nd receive data. the controllers can be mapped to either the fdl (t1), sa bits (e1), or to channels. if mapped to channels, then any channel or combination of channels, contiguous or not, can be assigned to an hdlc controller. when assigned to a channel(s) any combination of bits within the channel(s) can be avoided. the hxrcs1 ? hxrcs4 registers are used to assign the receive controllers to channels 1 ? 24 (t1) or 1 ? 32 (e1) according to the following table. register channels hxrcs1 1 ? 8 hxrcs2 9 ? 16 hxrcs3 17 ? 24 hxrcs4 25 ? 32 register name: h1rcs1 , h1rcs2 , h1rcs3 , h1rcs4 h2rcs1 , h2rcs2 , h2rcs3 , h2rcs4 register description: hdlc # 1 rec eive channel select x hdlc # 2 receive channel select x register address: 92h, 93h, 94h, 95h a2h, a3h, a4h, a5h bit # 7 6 5 4 3 2 1 0 name rhcs7 rhcs6 rhcs5 rhcs4 rhcs3 rhcs2 rhcs1 rhcs0 default 0 0 0 0 0 0 0 0 bit 0/receive hdlc channel select bit 0 (rhcs0). select channel 1, 9, 17, or 25. bit 1/receive hdlc channel select bit 1 (rhcs1). select channel 2, 10, 18, or 26. bit 2/receive hdlc channel select bit 2 (rhcs2). select channel 3, 11, 19, or 27. bit 3/receive hdlc channel select bit 3 (rhcs3 ). select channel 4, 12, 20, or 28. bit 4/receive hdlc channel select bit 4 (rhcs4). select channel 5, 13, 21, or 29. bit 5/receive hdlc channel select bit 5 (rhcs5). select channel 6, 14, 22, or 30. bit 6/receive hdlc channel select bit 6 (rhcs6). sele ct channel 7, 15, 23, or 31. bit 7/receive hdlc channel select bit 7 (rhcs7). select channel 8, 16, 24, or 32.
product preview DS21Q55 138 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: h1rtsbs , h2rtsbs register description: hdlc # 1 receive time slot bits/sa bits select hdlc # 2 receive time slot bits/sa bits select register address: 96h, a6h bit # 7 6 5 4 3 2 1 0 name rcb8se rcb7se rcb6se rcb5se rcb4se rcb3se rcb2se rcb1se default 0 0 0 0 0 0 0 0 bit 0/receive channel bit 1 suppress enable/sa8 bit enable (rcb1se ). lsb of the channel. set to one to stop this bit from being used when the hdlc is mapped to time slots. set to one to enable the use of sa8 bit when hdlc mapped is sa bits. bit 1/receive channel bit 2 suppress enable/sa7 bit enable (rcb2se). set to one to stop this bit from being used when the hdlc is mapped to time slots. set to one to enable the use of sa8 bit when hdlc mapped is sa bits. bit 2/receive channel bit 3 suppress enable/sa6 bit enable (rcb3se). set to one to stop this bit from being used when the hdlc is mapped to time slots. set to one to enable the use of sa8 bit when hdlc mapped is sa bits. bit 3/receive channel bit 4 suppress enable/sa5 bit enable (rcb4se). set to one to stop this bit from being used when the hdlc is mapped to time slots. set to one to enable the use of sa8 bit when hdlc mapped is sa bits. bit 4/receive channel bit 5 suppress enable/sa4 bit enable (rcb5se). set to one to stop this bit from being used when the hdlc is mapped to time slots. set to one to enable the use of sa8 b it when hdlc mapped is sa bits. bit 5/receive channel bit 6 suppress enable (rcb6se). set to one to stop this bit from being used. bit 6/receive channel bit 7 suppress enable (rcb7se). set to one to stop this bit from being used. bit 7/receive channel b it 8 suppress enable (rcb8se). msb of the channel. set to one to stop this bit from being used.
product preview DS21Q55 139 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.3.2 transmit the hxtcs1 ? hxtcs4 registers are used to assign the transmit controllers to channels 1 ? 24 (t1) or 1 ? 32 (e1), according to the following table. reg ister channels hxtcs1 1 ? 8 hxtcs2 9 ? 16 hxtcs3 17 ? 24 hxtcs4 25 ? 32 register name: h1tcs1 , h1tcs2 , h1tcs3 , h1tcs4 h2tcs1 , h2tcs2 , h2tcs3 , h2tcs4 register description: hdlc # 1 transmit channel select hdlc # 2 transmit channel select register address: 97h, 98h, 99h, 9ah a7h, a8h, a9h, aah bit # 7 6 5 4 3 2 1 0 name thcs7 thcs6 thcs5 thcs4 thcs3 thcs2 thcs1 thcs0 default 0 0 0 0 0 0 0 0 bit 0/transmit hdlc channel select bit 0 (thcs0). select channel 1, 9, 17, or 25. bit 1/transmit hdlc channel select bit 1 (thcs1). select channel 2, 10, 18, or 26. bit 2/transmit hdlc channel select bit 2 (thcs2). select channel 3, 11, 19, or 27. bit 3/transmit hdlc channel select bit 3 (thcs3). select channel 4, 12, 20, or 28. bit 4/transmit hdlc channel select bit 4 (thcs4). select channel 5, 13, 21, or 29. bit 5/transmit hdlc channel select bit 5 (thcs5). select channel 6, 14, 22, or 30. bi t 6/transmit hdlc channel select bit 6 (thcs6). select channel 7, 15, 23, or 31. bit 7/transmit hdlc channel select bit 7 (thcs7). select channel 8, 16, 24, or 32.
product preview DS21Q55 140 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: h1ttsbs , h2ttsbs register description: h dlc # 1 transmit time slot bits/sa bits select hdlc # 2 transmit time slot bits/sa bits select register address: 9bh, abh bit # 7 6 5 4 3 2 1 0 name tcb8se tcb7se tcb6se tcb5se tcb4se tcb3se tcb2se tcb1se default 0 0 0 0 0 0 0 0 bit 0/transmit chann el bit 1 suppress enable / sa8 bit enable (tcb1se). lsb of the channel. set to one to stop this bit from being used. bit 1/transmit channel bit 2 suppress enable/ sa7 bit enable (tcb1se). set to one to stop this bit from being used. bit 2/transmit channe l bit 3 suppress enable/sa6 bit enable (tcb1se). set to one to stop this bit from being used. bit 3/transmit channel bit 4 suppress enable/sa5 bit enable (tcb1se). set to one to stop this bit from being used. bit 4/transmit channel bit 5 suppress enable/ sa4 bit enable (tcb1se). set to one to stop this bit from being used. bit 5/transmit channel bit 6 suppress enable (tcb1se). set to one to stop this bit from being used. bit 6/transmit channel bit 7 suppress enable (tcb1se). set to one to stop this bit f rom being used. bit 7/transmit channel bit 8 suppress enable (tcb1se). msb of the channel. set to one to stop this bit from being used.
product preview DS21Q55 141 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: sr6 , sr7 register description: hdlc #1 status register 6 hdlc #2 status regi ster 7 register address: 20h, 22h bit # 7 6 5 4 3 2 1 0 name - tmend rpe rps rhwm rne tlwm tnf default 0 0 0 0 0 0 0 0 bit 0/transmit fifo not full condition (tnf). set when the transmit 128 - byte fifo has at least one byte available. bit 1/transmi t fifo below low watermark condition (tlwm). set when the transmit 128 - byte fifo empties beyond the low watermark as defined by the transmit low watermark register (tlwmr). bit 2/receive fifo not empty condition (rne). set when the receive 128 - byte fifo h as at least one byte available for a read. bit 3/receive fifo above high watermark condition (rhwm). set when the receive 128 - byte fifo fills beyond the high watermark as defined by the receive high - watermark register (rhwmr). bit 4/receive packet star t event (rps) . set when the hdlc controller detects an opening byte. this is a latched bit and will be cleared when read. bit 5/receive packet end event (rpe). set when the hdlc controller detects either the finish of a valid message (i.e., crc check comp lete) or when the controller has experienced a message fault such as a crc checking error, or an overrun condition, or an abort has been seen. this is a latched bit and will be cleared when read. bit 6/transmit message end event (tmend). set when the tran smit hdlc controller has finished sending a message. this is a latched bit and will be cleared when read.
product preview DS21Q55 142 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: imr6 , imr7 register description: hdlc # 1 interrupt mask register 6 hdlc # 2 interrupt mask register 7 register address: 21h, 23h bit # 7 6 5 4 3 2 1 0 name - tmend rpe rps rhwm rne tlwm tnf default 0 0 0 0 0 0 0 0 bit 0/transmit fifo not full condition (tnf). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising edge only bit 1/transmit f ifo below low watermark condition (tlwm). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising edge only bit 2/receive fifo not empty condition (rne). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising edge only bit 3/receive fi fo above high watermark condition (rhwm). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising edge only bit 4/receive packet start event (rps) . 0 = interrupt masked 1 = interrupt enabled bit 5/receive packet end event (rpe). 0 = interrupt masked 1 = interrupt enabled bit 6/transmit message end event (tmend). 0 = interrupt masked 1 = interrupt enabled
product preview DS21Q55 143 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: info5 , info6 register description: hdlc #1 information register hdlc #2 information register register address: 2eh, 2fh bit # 7 6 5 4 3 2 1 0 name - - tempty tfull rempty ps2 ps1 ps0 default 0 0 0 0 0 0 0 0 bits 0 to 2/receive packet status (ps0 to ps2) . these are real - time bits indicating the status as of the last read of the receive fifo. ps2 ps1 ps0 packet status 0 0 0 in progress: end of message has not yet been reached 0 0 1 packet ok: packet ended with correct crc code word 0 1 0 crc error: a closing flag was detected, preceded by a corrupt crc code word 0 1 1 abort: packet ended because an abort signal was detected (seven or more ones in a row) 1 0 0 overrun: hdlc controller terminated reception of packet because receive fifo is full 1 0 1 message too short: three or fewer bytes including crc bit 3/receive fifo empty (rempty) . a real - time bit that is set high when the receive fifo is empty. bit 4/transmit fifo full (tfull). a real - time bit that is set high when the fifo is full. bit 5/transmit fifo empty (tempty). a real - time bit that is set high when the fifo is empty. re gister name: info4 register description: hdlc event information register #4 register address: 2dh bit # 7 6 5 4 3 2 1 0 name h2udr h2obt h1udr h1obt default 0 0 0 0 0 0 0 0 bit 0/hdlc #1 opening byte event (h1obt). set when the ne xt byte available in the receive fifo is the first byte of a message. bit 1/hdlc #1 transmit fifo underrun event (h1udr). set when the transmit fifo empties out without having seen the tmend bit set. an abort is automatically sent. this bit is latched and will be cleared when read. bit 2/hdlc #2 opening byte event (h2obt). set when the next byte available in the receive fifo is the first byte of a message. bit 3/hdlc #2 transmit fifo underrun event (h2udr). set when the transmit fifo empties out without having seen the tmend bit set. an abort is automatically sent. this bit is latched and will be cleared when read.
product preview DS21Q55 144 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.3.3 fifo information the transmit fifo buffer - available register indicates the number of bytes that can be written into the transmit fifo. the count from this register informs the host as to how many bytes can be written into the transmit fifo without overflowing the buffer. register name: h1tfba , h2tfba register description: hdlc # 1 transmit fifo buffer availab le hdlc # 2 transmit fifo buffer available register address: 9fh, afh bit # 7 6 5 4 3 2 1 0 name tfba7 tfba6 tfba5 tfba4 tfba3 tfba2 tfba1 tfba0 default 0 0 0 0 0 0 0 0 bits 0 to 7/transmit fifo bytes available (tfbao to tfba7). tfba0 is the lsb. 22.3.4 r eceive packet bytes available the lower 7 bits of the receive packet bytes available register indicate the number of bytes (0 through 127) that can be read from the receive fifo. the value indicated by this register (lower 7 bits) informs the host as to ho w many bytes can be read from the receive fifo without going past the end of a message. this value will refer to one of four possibilities: the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet. after rea ding the number of bytes indicated by this register, the host then checks the hdlc information register for detailed message status. if the value in the hxrpba register refers to the beginning portion of a message or continuation of a message then the msb of the hxrpba register will return a value of 1. this indicates that the host can safely read the number of bytes returned by the lower 7 bits of the hxrpba register but there is no need to check the information register since the packet has not yet termi nated (successfully or otherwise). register name: h1rpba , h2rpba register description: hdlc # 1 receive packet bytes available hdlc # 2 receive packet bytes available register address: 9ch, ach bit # 7 6 5 4 3 2 1 0 name ms rpba6 rpba5 rpba4 rpba3 rpba2 rpba1 rpba0 default 0 0 0 0 0 0 0 0 bits 0 to 6/receive fifo packet bytes available count (rpba0 to rpba6). rpba0 is the lsb. bit 7/message status (ms). 0 = bytes indicated by rpba0 through rpba6 are the end of a mess age. host must check the info5 or info6 register for details. 1 = bytes indicated by rpba0 through rpba6 are the beginning or continuation of a message. the host does not need to check the info5 or info6 register.
product preview DS21Q55 145 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.3.5 hdlc fifos register name: h1tf , h2tf register description: hdlc # 1 transmit fifo, hdlc # 2 transmit fifo register address: 9dh, adh bit # 7 6 5 4 3 2 1 0 name thd7 thd6 thd5 thd4 thd3 thd2 thd1 thd0 default 0 0 0 0 0 0 0 0 bit 0/transmit hdlc data bit 0 (thd0). lsb of a hdlc packet data byte. bit 1/transmit hdlc data bit 1 (thd1). bit 2/transmit hdlc data bit 2 (thd2). bit 3/transmit hdlc data bit 3 (thd3). bit 4/transmit hdlc data bit 4 (thd4). bit 5 /transmit hdlc data bit 5 (thd5). bit 6/transmit hdlc data bit 6 (thd6). bit 7/transmit hdlc data bit 7 (thd7). msb of a hdlc packet data byte. register name: h1rf , h2rf register description: hdlc # 1 receive fifo, hdlc # 2 r eceive fifo register address: 9eh, aeh bit # 7 6 5 4 3 2 1 0 name rhd7 rhd6 rhd5 rhd4 rhd3 rhd2 rhd1 rhd0 default 0 0 0 0 0 0 0 0 bit 0/receive hdlc data bit 0 (rhd0). lsb of a hdlc packet data byte. bit 1/receive hdlc data bit 1 (rhd1). bit 2/rec eive hdlc data bit 2 (rhd2). bit 3/receive hdlc data bit 3 (rhd3). bit 4/receive hdlc data bit 4 (rhd4). bit 5/receive hdlc data bit 5 (rhd5). bit 6/receive hdlc data bit 6 (rhd6). bit 7/receive hdlc data bit 7 (rhd7). msb of a hdlc packet data byte.
product preview DS21Q55 146 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.4 receive hdlc code example below is an example of a receive hdlc routine for controller #1. 1) reset receive hdlc controller 2) set hdlc mode, mapping, and high watermark 3) start new message buffer 4) enable rpe and rhwm interrupts 5) wait for interrupt 6) disable rpe and rhwm interrupts 7) read hxrpba register. n = hxrpba (lower 7 bits are byte count, msb is status) 8) read (n and 7fh) bytes from receive fifo and store in message buffer 9) read info5 register 10) if ps2, ps1, ps0 = 000, then go to step 4 11) if ps2, ps1, ps0 = 001, then p acket terminated ok, save present message buffer 12) if ps2, ps1, ps0 = 010, then packet terminated with crc error 13) if ps2, ps1, ps0 = 011, then packet aborted 14) if ps2, ps1, ps0 = 100, then fifo overflowed 15) go to step 3 22.5 legacy fdl support (t1 mode) in order to pr ovide backward compatibility to the older ds21x52 t1 device, the DS21Q55 maintains the circuitry that existed in the previous generation of the t1 framer. in new applications, it is recommended that the hdlc controllers and boc controller are used. 22.5.1 receiv e section in the receive section, the recovered fdl bits or fs bits are shifted bit - by - bit into the receive fdl register (rfdl ). since the rfdl is 8 bits in length, it will fill up every 2ms (8 x 250s). the framer will signal an external micr ocontroller that the buffer has filled via the sr8.3 bit. if enabled via imr8.3, the int pin will toggle low indicating that the buffer has filled and needs to be read. the user has 2ms to read this data before it is lost. if the byte in the rfdl matches e ither of the bytes programmed into the rfdlm1 or rfdlm2 registers, then the sr8.1 bit will be set to a one and the int pin will toggled low if enabled via imr8.1. this feature allows an external microcontroller to ignore the f dl or fs pattern until an important event occurs. the framer also contains a zero destuffer, which is controlled via the t1rcr2 .3 bit. in both ansi t1.403 and tr54016, communications on the fdl follows a subset of a lapd protocol. the lapd pr otocol states that no more than five ones should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abort signal (11111111). if enabled via t1rcr2.3, the device will automatically look for five ones in a row, followed by a zero. if it finds such a pattern, it will automatically remove the zero. if the zero destuffer sees six or more ones in a row followed by a zero, the zero is not removed. the t1rcr2.3 bit should always be set to a one when the device is extracting the fdl. more on how to use the DS21Q55 in fdl applications in this legacy support mode is covered in a separate application note.
product preview DS21Q55 147 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: rfdl register description: receive fdl register register address: c0h bit # 7 6 5 4 3 2 1 0 name rfdl7 rfdl6 rfdl5 rfdl4 rfdl3 rfdl2 rfdl1 rfdl0 default 0 0 0 0 0 0 0 0 bit 0/receive fdl bit 0 (rfdl0). lsb of the received fdl code. bit 1/receive fdl bit 1 (rfdl1). bit 2/receive fdl bit 2 (rfdl2). bit 3/receive fdl bit 3 (rfdl3 ). bit 4/receive fdl bit 4 (rfdl4). bit 5/receive fdl bit 5 (rfdl5). bit 6/receive fdl bit 6 (rfdl6). bit 7/receive fdl bit 7 (rfdl7). msb of the received fdl code. the receive fdl register (rfdl ) reports the incoming facility data link ( fdl) or the incoming fs bits. the lsb is received first. register name: rfdlm1 , rfdlm2 register description: receive fdl match register 1 receive fdl match register 2 register address: c2h, c3h bit # 7 6 5 4 3 2 1 0 na me rfdlm7 rfdlm6 rfdlm5 rfdlm4 rfdlm3 rfdlm2 rfdlm1 rfdlm0 default 0 0 0 0 0 0 0 0 bit 0/receive fdl match bit 0 (rfdlm0). lsb of the fdl match code. bit 1/receive fdl match bit 1 (rfdlm1 ). bit 2/receive fd l match bit 2 (rfdlm2 ). bit 3/receive fdl match bit 3 (rfdlm3). bit 4/receive fdl match bit 4 (rfdlm4). bit 5/receive fdl match bit 5 (rfdlm5). bit 6/receive fdl match bit 6 (rfdlm6). bit 7/receive fdl match bit 7 (rfdlm7). msb of the f dl match code.
product preview DS21Q55 148 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.5.2 transmit section the transmit section will shift out into the t1 data stream, either the fdl (in the esf framing mode) or the fs bits (in the d4 framing mode) contained in the transmit fdl register (tfdl ). when a new value is written to the tfdl, it will be multiplexed serially (lsb first) into the proper position in the outgoing t1 data stream. after the full eight bits has been shifted out, the framer will signal the host microcontroller that the buffer is empty and that more data is needed by setting the sr8.2 bit to a one. the int will also toggle low if enabled via imr8.2. the user has 2ms to update the tfdl with a new value. if the tfdl is not updated, the old value in the tfdl will be transmitted once again. the framer al so contains a zero stuffer which is controlled via the t1tcr2 .5 bit. in both ansi t1.403 and tr54016, communications on the fdl follows a subset of a lapd protocol. the lapd protocol states that no more than five ones should be transmitted i n a row so that the data does not resemble an opening or closing flag (01111110) or an abort signal (11111111). if enabled via t1tcr2.5, the framer will automatically look for 5 ones in a row. if it finds such a pattern, it will automatically insert a zero after the five ones. the t1tcr2.5 bit should always be set to a one when the framer is inserting the fdl. register name: tfdl register description: transmit fdl register register address: c1h bit # 7 6 5 4 3 2 1 0 name tfdl7 tfdl6 tfdl 5 tfdl4 tfdl3 tfdl2 tfdl1 tfdl0 default 0 0 0 0 0 0 0 0 (note: also used to insert fs framing pattern in d4 framing mode) bit 0/transmit fdl bit 0 (tfdl0). lsb of the transmit fdl code. bit 1/transmit fdl bit 1 (tfdl1). bit 2/transmit fdl bit 2 (tfdl2 ). bit 3/transmit fdl bit 3 (tfdl3). bit 4/transmit fdl bit 4 (tfdl4). bit 5/transmit fdl bit 5 (tfdl5). bit 6/transmit fdl bit 6 (tfdl6). bit 7/transmit fdl bit 7 (tfdl7). msb of the transmit fdl code. the transmit fdl register (tfdl ) c ontains the facility data link (fdl) information that is to be inserted on a byte basis into the outgoing t1 data stream. the lsb is transmitted first. 22.6 d4/slc ? 96 operation in the d4 framing mode, the framer uses the tfdl register to insert th e fs framing pattern. to allow the device to properly insert the fs framing pattern, the tfdl register at address c1h must be programmed to 1ch and the following bits must be programmed as shown: t1tcr1 .2 = 0 (source fs data from the tfdl re gister) t1tcr2 .6 = 1 (allow the tfdl register to load on multiframe boundaries). since the slc ? 96 message fields share the fs - bit position, the user can access these message fields via the tfdl and rfdl registers. please see the separate application note for a detailed description of how to implement a slc ? 96 function.
product preview DS21Q55 149 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23. line interface unit (liu) the liu in the DS21Q55 contains three sections: the receiver, which handles clock and data recovery; the transmitter, whic h wave - shapes and drives the network line; and the jitter attenuator. these three sections are controlled by the line interface control registers (lic1 ? lic4 ), which are described below. the liu has its own t1/e1 mode select bit an d can operate independently of the framer function. the DS21Q55 can switch between t1 or e1 networks without changing any external components on either the transmit or receive side. figure 25 - 1 shows a network connection using minimal components. in this configuration the device can connect to t1, j1, or e1 (75o or 120o) without any component change. the receiver can adjust the 120o termination to 100o or 75o. the transmitter can adjust its output impedance to provide high return loss characteristics for 1 20o, 100o, and 75o lines. other components may be added to this configuration in order to meet safety and network protection requirements. this is covered in recommended circuits . basic network connections figure 25 - 1 ttip tring rtip rring DS21Q55 transmit line receive line 1f 60 60 0.01f backplane connections 1:1 2:1
product preview DS21Q55 150 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23.1 liu operation the analog ami/hdb 3 waveform off of the e1 line or the ami/b8zs waveform off of the t1 line is transformer coupled into the rtip and rring pins of the DS21Q55. the user has the option to use internal termination, software selectable for 75o/100o/120o applications, or extern al termination. the liu recovers clock and data from the analog signal and passes it through the jitter attenuation mux outputting the received line clock at rclko and bipolar or nrz data at rposo and rnego. the DS21Q55 contains an active filter that recon structs the analog received signal for the nonlinear losses that occur in transmission. the receive circuitry also is configurable for various monitor applications. the device has a usable receive sensitivity of 0db to - 43db for e1 and 0db to - 36db for t1, which allows the device to operate on 0.63mm (22awg) cables up to 2.5km (e1) and 6k feet (t1) in length. data input at tposi and tnegi is sent via the jitter attenuation mux to the wave shaping circuitry and line driver. the DS21Q55 will drive the e1 or t 1 line from the ttip and tring pins via a coupling transformer. the line driver can handle both cept 30/isdn - pri lines for e1 and long - haul (csu) or short - haul (dsx - 1) lines for t1. 23.2 liu receiver the DS21Q55 contains a digital clock recovery system. the d evice couples to the receive e1 or t1 twisted pair (or coaxial cable in 7 5o e1 applications) via a 1:1 transformer. see table 25 - 1 for transformer details. the DS21Q55 has the option of using software - selectable termination requiring only a single, fixed pair of termination resistors. the DS21Q55?s liu is designed to be fully software selectable for e1 and t1 without the need to change any external resistors for the receive - side. the receive - side will allow the user to configure the device for 75o, 100o, or 120o receive termination by setting the rt1 (lic4 .1) and r t0 (lic4.0) bits. when using the internal termination feature, the resistors labeled r in figure should be 60o each. if external termination is required, rt1 and rt0 should be set to zero and the resistors labeled r i n figure will need to be 37.5o, 50o, or 60o each depending on the line impedance. there are two ranges of receive sensitivity for both t1 and e1, which is selectable by the user. the egl bit of lic1 (lic 1.4) selects the full or limited sensitivity. the resultant e1 or t1 clock derived from mclk is multiplied by 16 via an internal pll and fed to the clock recovery system. the clock recovery system uses the clock from the pll circuit to form a 16 times over - sampler, which is used to recover the clock and data. this over - sampling technique offers outstanding performance to meet jitter tolerance specifications shown in . normally, the clock that is output at the rclk pin is the recovered clock from the e1 ami/hdb3 or t1 ami/b8zs waveform presented at the rtip and rring inputs. if the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the rclk to an appr oximate 50% duty cycle. if the jitter attenuator is either placed in the transmit path or is disabled, the rclk output can exhibit slightly shorter high cycles of the clock. this is due to the highly over - sampled digital clock recovery circuitry. see rece ive ac timing characteristics for more details. when no signal is present at rtip and rring, a receive carrier loss (rcl) condition will occur and the rclk will be derived from the jaclk source.
product preview DS21Q55 151 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23.2.1 receive level indicator and threshold interrupt the ds21 q 55 reports the signal strength at rtip and rring in 2.5db increments through rl3 ? rl0 located in information register 2 (info2 ). this feature is helpful when trouble - shooting line - performance problems. the ds2155 can initiate an interrupt whenev er the input falls below a certain level through the input - level under - threshold indicator (sr1.7). using the rlt0 ? rlt4 bits of the ccr4 register, the user can set a threshold in 2.5db increments. the sr1.7 bit is set whenever the input level at rtip and r ring falls below the threshold set by the value in rlt0 ? rlt4. the level must remain below the programmed threshold for approximately 50ms for this bit to be set. 23.2.2 receive g.703 synchronization signal (e1 mode) the DS21Q55 is capable of receiving a 2.048mh z square - wave synchronization clock as specified in section 13 of itu g.703 10/98. in order to use this mode, set the receive synchronization clock enable (lic3 .2) = 1. 23.2.3 monitor mode monitor applications in both e1 and t1 require various flat g ain settings for the receive - side circuitry. the DS21Q55 can be programmed to support these applications via the monitor mode control bits mm1 and mm0 in the lic3 register (figure 25 - 2). typical monitor application figure 25 - 2 primary t1/e1 terminating device monitor port jack t1/e1 line x f m r DS21Q55 rt rm rm secondary t1/e1 terminating device
product preview DS21Q55 152 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23.3 liu transm itter the DS21Q55 uses a phase - lock loop along with a precision digital - to - analog converter (dac) to create the waveforms that are transmitted onto the e1 or t1 line. the waveforms created by the transmitter meet the latest etsi, itu, ansi, and at&t specif ications. the user will select which waveform is to be generated by setting the ets bit (lic2 .7) for e1 or t1 operation, then programming the l2/l1/l0 bits in register lic1 for the appropriate application. a 2.048mhz or 1.544mhz clock is required at tclki for transmitting data presented at tposi and tnegi. normally these pins are connected to tclko, tposo and tnego. however, the liu may operate in an independent fashion. itu specification g.703 requires an accuracy of 50ppm for b oth t1 and e1. tr62411 and ansi specs require an accuracy of 32ppm for t1 interfaces. the clock can be sourced internally from rclk or jaclk. see lic2 .3, lic4.4 and lic4.5 for details. due to the nature of the design of the transmitter, very little jitter (less than 0.005 uipp broadband from 10hz to 100khz) is added to the jitter present on tclk. also, the waveforms created are independent of the duty cycle of tclk. the transmitter couples to the e1 or t1 transmit twisted pair (or coaxial cabl e in some e1 applications) via a 1:2 step - up transformer. in order for the device to create the proper waveforms, the transformer used must meet the specifications listed in table 25 - 1. the DS21Q55 has the option of using software - selectable transmit termi nation. the transmit line drive has two modes of operation: fixed gain or automatic gain. in the fixed gain mode, the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude. in the automatic gain mode, the transmit ter adjusts its output level to compensate for slight variances in the network load. see the transmit line build - out control (tlbc) register for details. 23.3.1 transmit short - circuit detector/limiter the DS21Q55 has automatic short - circuit limiter which limits t he source current to 50ma (rms) into a 1 ohm load. this feature can be disabled by setting the scld bit (lic2 .1) = 1. tcle (info2 .5) provides a real time indication of when the current limiter is activated. if the current limite r is disabled, tcle will indicate that a short - circuit condition exist. status register sr1 .2 provides a latched version of the information, which can be used to activate an interrupt when enable via the imr1 register. when set low , the tpd bit (lic1 .0) will power - down the transmit line driver and tristate the ttip and tring pins. 23.3.2 transmit open - circuit detector the DS21Q55 can also detect when the ttip or tring outputs are open circuited. tocd (info2 .4) wi ll provide a real - time indication of when an open circuit is detected. sr1 provides a latched version of the information (sr1.1), which can be used to activate an interrupt when enable via the imr1 register. 23.3.3 transmit bpv error inse rtion when ibpv (lic2 .5) is transitioned from a zero to a one, the device waits for the next occurrence of three consecutive ones to insert a bpv. ibpv must be cleared and set again for another bpv error insertion. 23.3.4 transmit g.703 synchronizat ion signal (e1 mode) the DS21Q55 can transmit the 2.048mhz square - wave synchronization clock as defined in section 13 of itu g.703 10/98. in order to transmit the 2.048mhz clock, when in e1 mode, set the transmit synchronization clock enable (lic3 .1) = 1.
product preview DS21Q55 153 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23.4 mclk prescaler a 16.384mhz, 8.192mhz, 4.096mhz, 2.048mhz, or 1.544mhz clock must be applied at mclk. itu specification g.703 requires an accuracy of 50ppm for both t1 and e1. tr62411 and ansi specs require an accuracy of 32ppm for t1 interfa ces. a prescaler will divide the 16mhz, 8mhz, or 4mhz clock down to 2.048mhz. there is an onboard pll for the jitter attenuator that will convert the 2.048mhz clock to a 1.544mhz rate for t1 applications. setting jamux (lic2 .3) to a logic 0 by passes this pll. 23.5 jitter attenuator the DS21Q55 contains an onboard jitter attenuator that can be set to a depth of either 32 bits or 128 bits via the jabds bit (lic1 .2). the 128 - bit mode is used in applications where large excursions of wander are expected. the 32 - bit mode is used in delay - sensitive applications. the characteristics of the attenuation are shown in figure 14. the jitter attenuator can be placed in either the receive path or the transmit path by appropriately setting or clearing the jas bit (lic1.3). also, the jitter attenuator can be disabled (in effect, removed) by setting the dja bit (lic1.1). onboard circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the tclk pin to create a smooth jitter free clock which is used to clock data out of the jitter attenuator fifo. it is acceptable to provide a gapped/bursty clock at the tclk pin if the jitter attenuator is placed on the transmit side. if the incoming jitter exceeds either 120 uipp (buffer depth is 128 bits) or 28uipp (buffer depth is 32 bits), then the jitter attenuator will divide the internal nominal 32.768mhz (e1) or 24.704mhz (t1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. when th e device divides by either 15 or 17, it also sets the jitter attenuator limit trip (jalt) bit in status register 1 (sr1.4). 23.6 cmi (code mark inversion) option the DS21Q55 provides a cmi interface for connection to optical transports. this interface is a unip olar 1t2b type of signal. ones are encoded as either a logical one or zero level for the full duration of the clock period. zeros are encoded as a zero - to - one transition at the middle of the clock period. cmi coding figure 25 - 3 transmit and receive cm i is enabled via lic4 .7. when this register bit is set, the ttip pin will output cmi coded data at normal levels. this signal can be used to directly drive an optical interface. when cmi is enable, the user can also use hdb3/b8zs coding. when this register bit is set, the rtip pin will become a unipolar cmi input. the cmi signal will be processed to extract and align the clock with data. 0 1 1 1 0 0 1 clock data cmi
product preview DS21Q55 154 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23.7 liu control registers register name: lic1 register description: line interface control 1 register address: 78h bit # 7 6 5 4 3 2 1 0 name l2 l1 l0 egl jas jabds dja tpd default 0 0 0 0 0 0 0 0 bit 0/transmit power - down (tpd). 0 = powers down the transmitter and tristates the ttip and tring pins 1 = normal transmitter operation bit 1/d isable jitter attenuator (dja). 0 = jitter attenuator enabled 1 = jitter attenuator disabled bit 2/jitter attenuator buffer depth select (jabds). 0 = 128 bits 1 = 32 bits (use for delay sensitive applications) bit 3/jitter attenuator select (jas). 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side bit 4/receive equalizer gain limit (egl). this bit controls the sensitivity of the receive equalizer. t1 mode: 0 = - 36db (long haul) 1 = - 15db (limited long haul) e1 mode: 0 = - 15db (short haul) 1 = - 43db (long haul) bits 5 to 7/line build - out select (l0 to l2). when using the internal termination the user needs only to select 000 for 75o operation or 001 for 120o operation below. this selects the pr oper voltage levels for 75o or 120o operation. using tt0 and tt1 of the licr4 register, users can then select the proper internal source termination. line build - outs 100 and 101 are for backwards compatibility with older products only.
product preview DS21Q55 155 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . e1 mode l2 l1 l0 a pplication n (1) return loss rt (1) 0 0 0 75o normal 1:2 nm 0 0 0 1 120o normal 1:2 nm 0 1 0 0 75o with high return loss* 1:2 21db 6.2o 1 0 1 120o with high return loss* 1:2 21db 11.6o * tt0 and tt1 of lic4 register must be set to zero i n this configuration. t1 mode l2 l1 l0 application n (1) return loss rt (1) 0 0 0 dsx - 1 (0 to 133 feet)/0db csu 1:2 nm 0 0 0 1 dsx - 1 (133 to 266 feet) 1:2 nm 0 0 1 0 dsx - 1 (266 to 399 feet) 1:2 nm 0 0 1 1 dsx - 1 (399 to 533 feet) 1:2 nm 0 1 0 0 dsx - 1 (533 to 655 feet) 1:2 nm 0 1 0 1 - 7.5db csu 1:2 nm 0 1 1 0 - 15db csu 1:2 nm 0 1 1 1 - 22.5db csu 1:2 nm 0
product preview DS21Q55 156 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: tlbc register description: transmit line build - out control register address: 7dh bit # 7 6 5 4 3 2 1 0 name - a gce gc5 gc4 gc3 gc2 gc1 gc0 default 0 0 0 0 0 0 0 0 bit 0 ? 5 gain control bits 0 ? 5 (gc0 ? gc5 ). the gc0 through gc5 bits control the gain setting for the nonautomatic gain mode. use the tables below for setting the recommended values. the lb (line build - o ut) column refers to the value in the l0 ? l2 bits in lic1 (line interface control 1) register. network mode lb gc5 gc4 gc3 gc2 gc1 gc0 0 1 0 0 1 1 0 1 0 1 1 0 1 1 2 0 1 1 0 1 0 3 1 0 0 0 0 0 4 1 0 0 1 1 1 5 1 0 0 1 1 1 6 0 1 0 0 1 1 t1, impedance match off 7 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 2 0 1 0 1 0 1 3 0 1 1 0 1 0 4 1 0 0 0 1 0 5 1 0 0 0 0 0 6 0 0 1 1 0 0 t1, impedance match on 7 1 1 1 1 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 1 4 1 0 1 0 1 0 e1, impedance match off 5 1 0 1 0 0 0 1 0 1 1 0 1 0 e1, impedance match on 2 0 1 1 0 1 0 bit 6/automatic gain control enable (agce). 0 = use transmit agc, tlbc bits 0 ? 5 are ?don?t care? 1 = do not use transmit agc, tlbc bits 0 ? 5 set nominal level bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 157 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: lic2 register description: line interface control 2 register address: 79h bit # 7 6 5 4 3 2 1 0 name ets lirst ibpv tua1 jamux - scld clds default 0 0 0 0 0 0 0 0 bit 0 custom line driver select ( clds ). setting this bit to a one will redefine the operation of the transmit line driver. when this bit is set to a one and lic1 .5 = lic1.6 = lic1.7 = 0, then the device will generate a square wave at the ttip and tring outputs instead of a normal waveform. when this bit is set to a one and lic1.5 = lic1.6 = lic1.7 1 0, then the device will force ttip and tring outputs to become open - drain drivers instead of their normal push - pull operation. this bit should be set to zero for normal ope ration of the device. bit 1/short circuit limit disable (ets = 1) (scld). controls the 50ma (rms) current limiter. 0 = enable 50ma current limiter 1 = disable 50ma current limiter bit 2/unused, must be set to zero for proper operation. bit 3/jitter att enuator mux (jamux). controls the source for jaclk. 0 = jaclk sourced from mclk (2.048mhz or 1.544mhz at mclk) 1 = jaclk sourced from internal pll (2.048mhz at mclk) bit 4/transmit unframed all ones (tua1). the polarity of this bit is set such that the device will transmit an all ones pattern on power - up or device reset. this bit must be set to a one to allow the device to transmit data. the transmission of this data pattern is always timed off of the jaclk. 0 = transmit all ones at ttip and tring 1 = tr ansmit data normally bit 5/insert bpv (ibpv). a zero - to - one transition on this bit will cause a single bpv to be inserted into the transmit data stream. once this bit has been toggled from a zero to a one, the device waits for the next occurrence of three consecutive ones to insert the bpv. this bit must be cleared and set again for a subsequent error to be inserted. bit 6/line interface reset (lirst). setting this bit from a zero to a one will initiate an internal reset that resets the clock recovery sta te machine and recenters the jitter attenuator. normally this bit is only toggled on power - up. must be cleared and set again for a subsequent reset. bit 7/e1/t1 select (ets). 0 = t1 mode selected 1 = e1 mode selected
product preview DS21Q55 158 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: lic3 register description: line interface control 3 register address: 7ah bit # 7 6 5 4 3 2 1 0 name - tces rces mm1 mm0 rsclke tsclke taoz default 0 0 0 0 0 0 0 0 bit 0/transmit alternate ones and zeros (taoz). transmit a ?101010? pattern (customer di sconnect indication signal) at ttip and tring. the transmission of this data pattern is always timed off of tclk. 0 = disabled 1 = enabled bit 1/transmit synchronization g.703 clock enable (tsclke). 0 = disable 1.544 (t1)/2.048 (e1)mhz transmit synchron ization clock 1 = enable 1.544 (t1)/2.048 (e1)mhz transmit synchronization clock bit 2/receive synchronization g.703 clock enable (rsclke). 0 = disable 1.544 (t1)/2.048 (e1)mhz synchronization receive mode 1 = enable 1.544 (t1)/2.048 (e1)mhz synchroniz ation receive mode bits 3 to 4/monitor mode (mm0 to mm1). mm1 mm0 internal linear gain boost (db) 0 0 normal operation (no boost) 0 1 20 1 0 26 1 1 32 bit 5/receive clock edge select (rces). selects which rclko edge to update rposo and rnego. 0 = update rposo and rnego on rising edge of rclko 1 = update rposo and rnego on falling edge of rclko bit 6/transmit clock edge select (tces). selects which tclki edge to sample tposi and tnegi. 0 = sample tposi and tnegi on falling edge of tclki 1 = sa mple tposi and tnegi on rising edge of tclki bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 159 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: lic4 register description: line interface control 4 register address: 7bh bit # 7 6 5 4 3 2 1 0 name cmie cmii mps1 mps 0 tt1 tt0 rt1 rt0 default 0 0 0 0 0 0 0 0 bits 0 to 1/receive termination select (rt0 to rt1) . rt1 rt0 internal receive termination configuration 0 0 internal receive - side termination disabled 0 1 internal receive - side 75o enabled 1 0 internal receive - side 100o enabled 1 1 internal receive - side 120o enabled bits 2 to 3/transmit termination select (tt0 to tt1). tt1 tt0 internal transmit termination configuration 0 0 internal transmit - side termi nation disabled 0 1 internal transmit - side 75o enabled 1 0 internal transmit - side 100o enabled 1 1 internal transmit - side 120o enabled bits 4 and 5/mclk prescaler for t1 mode. mclk (mhz) mps1 mps0 jamux (lic2 .3) 1.544 0 0 0 3.088 0 1 0 6.176 1 0 0 12.352 1 1 0 2.048 0 0 1 4.096 0 1 1 8.192 1 0 1 16.384 1 1 1 bits 4 and 5/mclk prescaler for e1 mode. mclk (mhz) mps1 mps0 jamux (lic2 .3) 2.048 0 0 0 4.096 0 1 0 8.192 1 0 0 16.384 1 1 0 bit 6/cmi invert (cmii). 0 = cmi normal at ttip and rtip 1 = invert cmi signal at ttip and rtip bit 7/cmi enable (cmie). 0 = disable cmi mode 1 = enable cmi mode
product preview DS21Q55 160 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: info2 register description: information register 2 register address: 11h bit # 7 6 5 4 3 2 1 0 name bsync - tcle tocd rl3 rl2 rl1 rl0 default 0 0 0 0 0 0 0 0 bits 0 to 3/receive level bits (rl0 to rl3). real - time bits rl3 rl2 rl1 rl0 receive level (db) 0 0 0 0 greater than - 2.5 0 0 0 1 - 2.5 to - 5.0 0 0 1 0 - 5.0 to - 7.5 0 0 1 1 - 7.5 to - 10.0 0 1 0 0 - 10.0 to - 12.5 0 1 0 1 - 12.5 to - 15.0 0 1 1 0 - 15.0 to - 17.5 0 1 1 1 - 17.5 to - 20.0 1 0 0 0 - 20.0 to - 22.5 1 0 0 1 - 22.5 to - 25.0 1 0 1 0 - 25.0 to - 27.5 1 0 1 1 - 27.5 to - 30.0 1 1 0 0 - 30.0 to ? 32.5 1 1 0 1 - 32.5 to - 35.0 1 1 1 0 - 35.0 to - 37.5 1 1 1 1 less than - 37.5 bit 4/transmit open circuit detect. (tocd) a real - time bit set when the device detects that the ttip and tring outputs are open - circuited. bit 5/transmit current limit exceeded. (tcle) a real - time bit set when the 50ma (rms) current limiter is activated, whether the current limiter is enabled or not. bit 6/unused. bit 7/bert real - time synchronization status (bsync). real - time status of the synchronizer (this bit is not latched). will be set when the incom ing pattern matches for 32 consecutive bit positions. will be cleared when six or more bits out of 64 are received in error. refer to bsync in the bert status register, sr9 , for an interrupt generating version of this signal.
product preview DS21Q55 161 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: ccr4 register description: common control register 4 register address: 73h bit # 7 6 5 4 3 2 1 0 name rlt3 rlt2 rlt1 rlt0 ? ? ? ? default 0 0 0 0 0 0 0 0 bit 0 /unused, must be set to zero for proper operation. bit 1 /unused, must be s et to zero for proper operation. bit 2 /unused, must be set to zero for proper operation. bit 3 /unused, must be set to zero for proper operation. bits 4 to 7/receive level threshold bits (rlt0 to rlt3) rlt3 rlt2 rlt1 rlt0 receive level (db) 0 0 0 0 gre ater than - 2.5 0 0 0 1 - 2.5 0 0 1 0 - 5.0 0 0 1 1 - 7.5 0 1 0 0 - 10.0 0 1 0 1 - 12.5 0 1 1 0 - 15.0 0 1 1 1 - 17.5 1 0 0 0 - 20.0 1 0 0 1 - 22.5 1 0 1 0 - 25.0 1 0 1 1 - 27.5 1 1 0 0 - 30.0 1 1 0 1 - 32.5 1 1 1 0 - 35.0 1 1 1 1 less than - 37.5
product preview DS21Q55 162 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . regi ster name: sr1 register description: status register 1 register address: 16h bit # 7 6 5 4 3 2 1 0 name ilut timer rscos jalt lrcl tcle tocd lolitc default 0 0 0 0 0 0 0 0 bit 0/loss of line interface transmit clock condition (lolitc) . set when tclki has not transitioned for one channel time. bit 1/transmit open circuit detect condition (tocd). set when the device detects that the ttip and tring outputs are open - circuited. bit 2/transmit current limit exceeded condition (tcle). set whe n the 50ma (rms) current limiter is activated whether the current limiter is enabled or not. bit 3/line interface receive carrier loss condition (lrcl). set when the carrier signal is lost. bit 4/jitter attenuator limit trip event (jalt). set when the j itter attenuator fifo reaches to within 4 bits of its useful limit. will be cleared when read. useful for debugging jitter - attenuation operation. bit 5/receive signaling change of state event (rscos). set when any channel selected by the receive - signaling change - of - state interrupt - enable registers (rscse1 through rscse4 ) changes signaling state. bit 6/timer event (timer). follows the error counter update interval as determined by the ecus bit in the error counter configuratio n register (ercnt ). t1 mode: set on increments of one second or 42ms based on rclk. e1 mode: set on increments of one second or 62.5ms based on rclk. bit 7/input level under threshold (ilut). this bit is set whenever the input level at rti p and rring falls below the threshold set by the value in ccr4.4 through ccr4.7. the level must remain below the programmed threshold for approximately 50ms for this bit to be set. this is a double interrupt bit.
product preview DS21Q55 163 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: imr1 registe r description: interrupt mask register 1 register address: 17h bit # 7 6 5 4 3 2 1 0 name - timer rscos jalt lrcl tcle tocd lolitc default 0 0 0 0 0 0 0 0 bit 0/loss of transmit clock condition (lolitc) . 0 = interrupt masked 1 = interrupt enabled ? generates interrupts on rising and falling edges bit 1/transmit open circuit detect condition (tocd). 0 = interrupt masked 1 = interrupt enabled ? generates interrupts on rising and falling edges bit 2/transmit current limit exceeded condition (tcle). 0 = interrupt masked 1 = interrupt enabled ? generates interrupts on rising and falling edges bit 3/line interface receive carrier loss condition (lrcl). 0 = interrupt masked 1 = interrupt enabled ? generates interrupts on rising and falling edges bit 4/ji tter attenuator limit trip event (jalt). 0 = interrupt masked 1 = interrupt enabled bit 5/receive signaling change of state event (rscos). 0 = interrupt masked 1 = interrupt enabled bit 6/timer event (timer). 0 = interrupt masked 1 = interrupt enabled
product preview DS21Q55 164 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23.8 recommended circuits basic interface figure 25 - 4 notes: 1) all resistor values are 1%. 2) resistors r should be set to 60o each if the internal receive - side termination feature is enabled. when this feature is disabled, r = 37.5o for 75o coaxial e1 lines, 60o for 120o twisted pair e1 lines, or 50o for 100o twisted pair t1 lines. 3) c = 1f ceramic. ttip tring rtip rring dv dd tv dd rv dd v dd dv ss tv ss rv ss DS21Q55 r r 2:1 1:1 c 0.1f 0.1f 0.1f .01f transmit line receive line 0.1f 10f 10f + +
product preview DS21Q55 165 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . protected interfac e using internal receive termination figure 25 - 5 notes: 1) all resistor values are 1%. 2) x1 and x2 are very low dcr transformers 3) c1 = 1f ceramic. 4) s1 and s2 are 6v transient suppressers. 5) d1 to d8 are schottky diodes. 6) the fuse s, f1 ? f4, are optional to prevent ac power - line crosses from compromising the transformers. 7) the 68 m f is used to keep the local power - plane potential within tolerance during a surge. ttip tring rtip rring dv dd tv dd rv dd v dd v dd dv ss tv s s rv ss DS21Q55 68f 2:1 1:1 d1 d2 d3 d4 c1 f1 f2 f3 f4 s1 0.1f 0.1f 0.1f .01 f x1 x2 transmit line receiv e line 0.1f 10f 10f + + + 0.1f s2 60 60 v dd d5 d6 d7 d8 0.1f
product preview DS21Q55 166 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23.9 component specifications transformer specifications table 25 - 1 specific ation recommended value turns ratio 3.3v applications 1:1 (receive) and 1:2 (transmit) 2% primary inductance 600 m h minimum leakage inductance 1.0 m h maximum intertwining capacitance 40pf maximum transmit transformer dc resistance primary (device side ) secondary 1.0 o maximum 2.0o maximum receive transformer dc resistance primary (device side) secondary 1.2o maximum 1.2o maximum
product preview DS21Q55 167 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . e1 transmit pulse template figure 25 - 6 t1 transmit pulse template figure 25 - 7 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 time (ns) scaled amplitude 50 100 150 200 250 -50 -100 -150 -200 -250 269ns 194ns 219ns (in 75 ohm systems, 1.0 on the scale = 2.37vpeak in 120 ohm systems, 1.0 on the scale = 3.00vpeak) g.703 template 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 -500 -300 -100 0 300 500 700 -400 -200 200 400 600 100 time (ns) normalized amplitude t1.102/87, t1.403, cb 119 (oct. 79), & i.431 template -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05 ui time amp. maximum curve ui time amp. minimum curve
product preview DS21Q55 168 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . jitter tolerance (t1 mode) figure 25 - 8 jitter tole rance (e1 mode) figure 25 - 9 frequency (hz) unit intervals (uipp) 1k 100 10 1 0.1 10 100 1k 10k 100k DS21Q55 tolerance 1 tr 62411 (dec. 90) itu-t g.823 frequency (hz) unit intervals (uipp) 1k 100 10 1 0.1 1 0 100 1k 10k 100k DS21Q55 tolerance 1 minimum tolerance level as per itu g.823 40 1.5 0.2 20 2.4k 18k
product preview DS21Q55 169 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . jitter attenuation (t1 mode) figure 25 - 10 jitter attenuation (e1 mode) figure 25 - 11 frequency (hz) 0db -20db -40db -60db 1 10 100 1k 10k jitter attenuation (db) 100k tr 62411 (dec. 90) prohibited area curve b curve a DS21Q55 t1 mode frequency (hz) 0db -20db -40db -60db 1 10 100 1k 10k jitter attenuation (db) 100k itu g.7xx prohibited area tbr12 prohibited area DS21Q55 e1 mode
product preview DS21Q55 170 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 24. programmable in - band loop code generation and detection the DS21Q55 has the ability to generate and detect a repeating bit pattern from 1 bit to 8 bits or 16 bits in length. this function is available only in t1 mode . to transmit a pattern, the user will load the pattern to be sent into the transmit code definition registers (tcd1 and tcd2 ) and select the pro per length of the pattern by setting the tc0 and tc1 bits in the in - band code - control (ibcc ) register. when generating a 1 - , 2 - , 4 - , 8 - , or 16 - bit pattern both transmit code - definition registers (tcd1 and tcd2) must be filled with the proper c ode. generation of a 3 - , 5 - , 6 - , and 7 - bit pattern only requires tcd1 to be filled. once this is accomplished, the pattern will be transmitted as long as the tloop control bit (t1ccr1 .0) is enabled. normally (unless the transmit formatter is programmed to not insert the f - bit position) the framer will overwrite the repeating pattern once every 193 bits to allow the f - bit position to be sent. an example: to transmit the standard loop - up code for channel service units (csus), which is a repea ting pattern of ...10000100001..., set tcd1 = 80h, ibcc = 0 and t1ccr1 .0 = 1. the framer has three programmable pattern detectors. typically, two of the detectors are used for loop - up and loop - down code detection. the user will program the codes to be detected in the receive - up code - definition (rupcd1 and rupcd2 ) registers and the receive - down code - definition (rdncd1 and rdncd2 ) registers and the length of each pattern will be selected via the ibcc register. a third detector (spare) is defined and controlled via the rscd1 /rscd2 and rscc registers. both receive code - definition registers are used together t o form a 16 - bit register when detecting a 16 - bit pattern. both receive code - definition registers will be filled with the same value for 8 - bit patterns. detection of a 1 - , 2 - , 3 - , 4 - , 5 - , 6 - , and 7 - bit pattern only requires the first receive code - definition register to be filled. the framer will detect repeating pattern codes in both framed and unframed circumstances with bit error rates as high as 10e - 2. the detectors are capable of handling both f - bit inserted and f - bit overwrite patterns. writing the leas t significant byte of the receive code - definition register resets the integration period for that detector. the code detector has a nominal integration period of 36ms. hence, after about 36ms of receiving a valid code, the proper status bit (lup at sr3 .5, ldn at sr3.6, and lspare at sr3.7 ) will be set to a one. normally codes are sent for a period of five seconds. it is recommended that the software poll the framer every 50ms to 1000ms until five seconds has elapsed to ensure that the code is c ontinuously present.
product preview DS21Q55 171 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: ibcc register description: in - band code control register register address: b6h bit # 7 6 5 4 3 2 1 0 name tc1 tc0 rup2 rup1 rup0 rdn2 rdn1 rdn0 default 0 0 0 0 0 0 0 0 bits 0 to 2/receive - down cod e length definition bits (rdn0 to rdn2). rdn2 rdn1 rdn0 length selected (bits) 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8/16 bits 3 to 5/receive - up code length definition bits (rup0 to rup2). rup2 rup1 rup0 length sele cted (bits) 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8/16 bits 6 to 7/transmit code length definition bits (tc0 to tc1). tc1 tc0 length selected (bits) 0 0 5 0 1 6/3 1 0 7 1 1 16/8/4/2/1
product preview DS21Q55 172 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: tcd1 register description: transmit code definition register 1 register address: b7h bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bit 0/transmit code definition bit 0 (c0). a ?don?t care? if a 5 - , 6 - , or 7 - bit lengt h is selected. bit 1/transmit code definition bit 1 (c1). a ?don?t care? if a 5 - bit or 6 - bit length is selected. bit 2/transmit code definition bit 2 (c2). a ?don?t care? if a 5 - bit length is selected. bit 3/transmit code definition bit 3 (c3). bit 4/t ransmit code definition bit 4 (c4). bit 5/transmit code definition bit 5 (c5). bit 6/transmit code definition bit 6 (c6). bit 7/transmit code definition bit 7 (c7). first bit of the repeating pattern. register name: tcd2 register descrip tion: transmit code definition register 2 register address: b8h bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 note: least significant byte of 16 - bit codes bit 0/transmit code definition bit 0 (c0). a ?don?t care? if a 5 - , 6 - , or 7 - bit length is selected. bit 1/transmit code definition bit 1 (c1). a ?don?t care? if a 5 - , 6 - , or 7 - bit length is selected. bit 2/transmit code definition bit 2 (c2). a ?don?t care? if a 5 - , 6 - , or 7 - bit length is selected. bit 3/transmit co de definition bit 3 (c3). a ?don?t care? if a 5 - , 6 - , or 7 - bit length is selected. bit 4/transmit code definition bit 4 (c4). a ?don?t care? if a 5 - , 6 - , or 7 - bit length is selected. bit 5/transmit code definition bit 5 (c5). a ?don?t care? if a 5 - , 6 - , or 7 - bit length is selected. bit 6/transmit code definition bit 6 (c6). a ?don?t care? if a 5 - , 6 - , or 7 - bit length is selected. bit 7/transmit code definition bit 7 (c7). a ?don?t care? if a 5 - , 6 - , or 7 - bit length is selected.
product preview DS21Q55 173 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: rupcd1 register description: receive - up code definition register 1 register address: b9h bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 note: writing this register resets the detector?s integration period. bit 0/ receive - up code definition bit 0 (c0). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 1/receive - up code definition bit 1 (c1). a ?don?t care? if a 1 - bit to 6 - bit length is selected. bit 2/receive - up code definition bit 2 (c2). a ?don?t care? if a 1 - bit to 5 - bit length is selected. bit 3/receive - up code definition bit 3 (c3). a ?don?t care? if a 1 - bit to 4 bit length is selected. bit 4/receive - up code definition bit 4 (c4). a ?don?t care? if a 1 - bit to 3 - bit length is selected. bit 5/receive - up code definition bit 5 (c5). a ?don?t care? if a 1 - bit or 2 - bit length is selected. bit 6/receive - up code definition bit 6 (c6). a ?don?t care if a 1 - bit length is selected. bit 7/receive - up code definition bit 7 (c7). first bit of the repeating patte rn. register name: rupcd2 register description: receive - up code definition register 2 register address: bah bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bit 0/receive - up code definition bit 0 (c0). a ? don?t care? if a 1 - bit to 7 - bit length is selected. bit 1/receive - up code definition bit 1 (c1). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 2/receive - up code definition bit 2 (c2). a ?don?t care? if a 1 - bit to 7 - bit length is selected. b it 3/receive - up code definition bit 3 (c3). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 4/receive - up code definition bit 4 (c4). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 5/receive - up code definition bit 5 (c5). a ?don?t c are? if a 1 - bit to 7 - bit length is selected. bit 6/receive - up code definition bit 6 (c6). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 7/receive - up code definition bit 7 (c7). a ?don?t care? if a 1 - bit to 7 - bit length is selected.
product preview DS21Q55 174 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . regist er name: rdncd1 register description: receive - down code definition register 1 register address: bbh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 note: writing this register resets the detector?s integra tion period. bit 0/receive - down code definition bit 0 (c0). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 1/receive - down code definition bit 1 (c1). a ?don?t care? if a 1 - bit to 6 - bit length is selected. bit 2/receive - down code definition b it 2 (c2). a ?don?t care? if a 1 - bit to 5 - bit length is selected. bit 3/receive - down code definition bit 3 (c3). a ?don?t care? if a 1 - bit to 4 - bit length is selected. bit 4/receive - down code definition bit 4 (c4). a ?don?t care? if a 1 - bit to 3 - bit leng th is selected. bit 5/receive - down code definition bit 5 (c5). a ?don?t care? if a 1 - bit or 2 - bit length is selected. bit 6/receive - down code definition bit 6 (c6). a ?don?t care? if a 1 - bit length is selected. bit 7/receive - down code definition bit 7 ( c7). first bit of the repeating pattern.
product preview DS21Q55 175 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: rdncd2 register description: receive - down code definition register 2 register address: bch bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bit 0/ receive - down code definition bit 0 (c0). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 1/receive - down code definition bit 1 (c1). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 2/receive - down code definition bit 2 (c2). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 3/receive - down code definition bit 3 (c3). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 4/receive - down code definition bit 4 (c4). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 5/receive - down code definition bit 5 (c5). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 6/receive - down code definition bit 6 (c6). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 7/receive - down code definition bit 7 (c7). a ?don ?t care? if a 1 - bit to 7 - bit length is selected. register name: rscc register description: in - band receive spare control register register address: bdh bit # 7 6 5 4 3 2 1 0 name - - - - - rsc2 rsc1 rsc0 default 0 0 0 0 0 0 0 0 bits 0 to 2/receive spare code length definition bits (rsc0 to rsc2). rsc2 rsc1 rsc0 length selected (bits) 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8/16 bit 3/unused, must be set to zero for proper operation. bit 4/unu sed, must be set to zero for proper operation. bit 5/unused, must be set to zero for proper operation. bit 6/unused, must be set to zero for proper operation. bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 176 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: rscd1 register description: receive - spare code definition register 1 register address: beh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 note: writing this register resets the detector?s integration period. bit 0/receive - spar e code definition bit 0 (c0). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 1/receive - spare code definition bit 1 (c1). a ?don?t care? if a 1 - bit to 6 - bit length is selected. bit 2/receive - spare code definition bit 2 (c2). a ?don?t care? if a 1 - bit to 5 - bit length is selected. bit 3/receive - spare code definition bit 3 (c3). a ?don?t care? if a 1 - bit to 4 - bit length is selected bit 4/receive - spare code definition bit 4 (c4). a ?don?t care? if a 1 - bit to 3 - bit length is selected. bit 5/recei ve - spare code definition bit 5 (c5). a ?don?t care? if a 1 - bit or 2 - bit length is selected. bit 6/receive - spare code definition bit 6 (c6). a ?don?t care? if a 1 - bit length is selected. bit 7/receive - spare code definition bit 7 (c7). first bit of the rep eating pattern. register name: rscd2 register description: receive - spare code definition register 2 register address: bfh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bit 0/receive - spare code definition bit 0 (c0). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 1/receive - spare code definition bit 1 (c1). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 2/receive - spare code definition bit 2 (c2). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 3/receive - spare code definition bit 3 (c3). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 4/receive - spare code definition bit 4 (c4). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 5/receive - spare code de finition bit 5 (c5). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 6/receive - spare code definition bit 6 (c6). a ?don?t care? if a 1 - bit to 7 - bit length is selected. bit 7/receive - spare code definition bit 7 (c7). a ?don?t care? if a 1 - bit t o 7 - bit length is selected.
product preview DS21Q55 177 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 25. bert function the bert (bit error rate tester) block can generate and detect both pseudorandom and repeating - bit patterns. it is used to test and stress data - communication links. the bert block is capable of generating and de tecting the following patterns: the pseudorandom patterns 2e7, 2e11, 2e15, and qr ss a repetitive pattern from 1 to 32 bits in length alternating (16 - bit) words that flip every 1 to 256 words daly pattern the bert function is assigned on a per - channel bas is for both the transmitter and receiver. this is accomplished by using the special per - channel function. using this function, the bert pattern can be transmitted and/or received in single or across multiple ds0s, contiguous or broken. transmit and receive bandwidth assignments are independent of each other. the bert receiver has a 32 - bit bit counter and a 24 - bit error counter. the bert receiver will report three events: a change in receive - synchronizer status, a bit error detection, and if either the bit counter or the error counter overflows. each of these events can be masked within the bert function via the bert control register 1 (bc1 ). if the software detects that the bert has reported an event, then the software must read the bert informa tion register (bir) to determine which event(s) has occurred. to activate the bert block, the host must configure the bert multiplexer via the bic register. sr9 contains the status information on the bert function. the host can be alerted when there is a change of state of the bert via this register. a major change of state is defined as either a change in the receive synchronization (i.e., the bert has gone into or out of receive synchronization), a bit error has been detected, or an overflow has occurred in either the bit counter or the error counter. the host must read sr9 to determine the change of state.
product preview DS21Q55 178 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 25.1 bert register description register name: bc1 register description: bert control register 1 register address: e0h bit # 7 6 5 4 3 2 1 0 name tc tinv rinv ps2 ps1 ps0 lc resync default 0 0 0 0 0 0 0 0 bit 0/force resynchronization (resync). a low - to - high transition will force the receive bert synchronizer to resynchronize to the incoming data stream. this bi t should be toggled from low to high whenever the host wishes to acquire synchronization on a new pattern. must be cleared and set again for a subsequent resynchronization. bit 1/load bit and error counters (lc). a low - to - high transition latches the curre nt bit and error counts into the registers bbc1/bbc2 /bbc3 /bbc4 and bec1/bec2 /bec3 and clears the internal count. this bit should be toggled from low to high whenever the host wishes to begin a new acquisition period. must be cleared and set again for a subsequent loads. bits 2 to 4/pattern select bits (ps0 to ps2) ps2 ps1 ps0 pattern definition 0 0 0 pseudorandom 2e7 ? 1 0 0 1 pseudorandom 2e11 ? 1 0 1 0 pseudorandom 2e15 ? 1 0 1 1 pseudorando m pattern qr ss . a 2 20 - 1 pattern with 14 consecutive zero estriction. 1 0 0 repetitive pattern 1 0 1 alternating word pattern 1 1 0 modified 55 octet (daly) pattern the daly pattern is a repeating 55 octet pattern that is byte - aligned into the active d s0 timeslots. the pattern is defined in an atis (alliance for telecommunications industry solutions) committee t1 technical report number 25 (november 1993). 1 1 1 reserved bit 5/receive invert data enable (rinv). 0 = do not invert the incoming data str eam 1 = invert the incoming data stream bit 6/transmit invert data enable (tinv). 0 = do not invert the outgoing data stream 1 = invert the outgoing data stream bit 7/transmit pattern load (tc). a low - to - high transition loads the pattern generator with t he pattern that is to be generated. this bit should be toggled from low to high whenever the host wishes to load a new pattern. must be cleared and set again for a subsequent loads.
product preview DS21Q55 179 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: bc2 register description: bert control regi ster 2 register address: e1h bit # 7 6 5 4 3 2 1 0 name eib2 eib1 eib0 sbe rpl3 rpl2 rpl1 rpl0 default 0 0 0 0 0 0 0 0 bits 0 to 3/repetitive pattern length bit 3 (rpl0 to rpl3). rpl0 is the lsb and rpl3 is the msb of a nibble that describes the ho w long the repetitive pattern is. the valid range is 17 (0000) to 32 (1111). these bits are ignored if the receive bert is programmed for a pseudorandom pattern. to create repetitive patterns less than 17 bits in length, the user must set the length to an integer number of the desired length that is less than or equal to 32. for example, to create a 6 - bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30 (1101). length (bits) rpl3 rpl2 rpl1 rpl0 17 0 0 0 0 18 0 0 0 1 19 0 0 1 0 20 0 0 1 1 21 0 1 0 0 22 0 1 0 1 23 0 1 1 0 24 0 1 1 1 25 1 0 0 0 26 1 0 0 1 27 1 0 1 0 28 1 0 1 1 29 1 1 0 0 30 1 1 0 1 31 1 1 1 0 32 1 1 1 1 bit 4/single bit error insert (sbe). a low - to - high transition will create a single bit error. must be cleared and set again for a subsequent bit error to be inserted. bits 5 to 7/error insert bits 0 to 2 (eib0 to eib2). will automatically insert bit errors at the prescribed rate into the generated data pattern. can be used for verifying error detection features. eib2 eib1 eib0 error rate inserted 0 0 0 no errors automatically inserted 0 0 1 10e - 1 0 1 0 10e - 2 0 1 1 10e - 3 1 0 0 10e - 4 1 0 1 10e - 5 1 1 0 10e - 6 1 1 1 10e - 7
product preview DS21Q55 180 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: bic register description: ber t interface control register register address: eah bit # 7 6 5 4 3 2 1 0 name - rfus - tbat tfus - bertdir berten default 0 0 0 0 0 0 0 0 bit 0/bert enable (berten). 0 = bert disabled 1 = bert enabled bit 1/bert direction (bertdir). 0 = network 1 = system bit 2/unused, must be set to zero for proper operation. bit 3/transmit framed/unframed select (tfus). for t1 mode only. 0 = bert will not source data into the f - bit position (framed) 1 = bert will source data into the f - bit position (unframed) b it 4/transmit byte align toggle (tbat). a zero - to - one transition will force the bert to byte align its pattern with the transmit formatter. this bit must be transitioned in order to byte - align the daly pattern. bit 5/unused, must be set to zero for proper operation. bit 6/receive framed/unframed select (rfus). for t1 mode only. 0 = bert will not sample data from the f - bit position (framed) 1 = bert will sample data from the f - bit position (unframed) bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 181 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: sr9 register description: status register 9 register address: 26h bit # 7 6 5 4 3 2 1 0 name - bbed bbco bec0 bra1 bra0 brlos bsync default 0 0 0 0 0 0 0 0 bit 0/bert in synchronization condition (bsync). will be set when the incoming pattern matches for 32 consecutive bit positions. refer to bsync in info2 register for a real - time version of this bit. bit 1/bert receive loss of synchronization condition (brlos). a latched bit that is set whenever the r eceive bert begins searching for a pattern. the bert will lose sync after receiving six errored bits out of 63 bits. synchronization is lost when six errors are received in 63 bits. once synchronization is achieved, this bit will remain set until read. bi t 2/bert receive all zeros condition (bra0). a latched bit that is set when 32 consecutive zeros are received. allowed to be cleared once a one is received. bit 3/bert receive all ones condition (bra1). a latched bit that is set when 32 consecutive ones are received. allowed to be cleared once a zero is received. bit 4/bert error counter overflow (beco) event (beco). a latched bit that is set when the 24 - bit bert error counter (bec) overflows. cleared when read and will not be set again until another ove rflow occurs. bit 5/bert bit counter overflow event (bbco). a latched bit that is set when the 32 - bit bert bit counter (bbc) overflows. cleared when read and will not be set again until another overflow occurs. bit 6/bert bit error detected (bed) event (bbed). a latched bit that is set when a bit error is detected. the receive bert must be in synchronization for it detect bit errors. cleared when read.
product preview DS21Q55 182 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: imr9 register description: interrupt mask register 9 register addres s: 27h bit # 7 6 5 4 3 2 1 0 name - bbed bbco bec0 bra1 bra0 brlos bsync default 0 0 0 0 0 0 0 0 bit 0/bert in synchronization condition (bsync). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising and falling edges bit 1/receive loss of synchronization condition (brlos). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising and falling edges bit 2/receive all zeros condition (bra0). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising and falling edges bit 3/re ceive all ones condition (bra1). 0 = interrupt masked 1 = interrupt enabled ? interrupts on rising and falling edges bit 4/bert error counter overflow event (beco). 0 = interrupt masked 1 = interrupt enabled bit 5/bert bit counter overflow event (bbco). 0 = interrupt masked 1 = interrupt enabled bit 6/bit error detected event (bbed). 0 = interrupt masked 1 = interrupt enabled bert alternating word count rate. when the bert is programmed in the alternating word mode, the words will repeat for the coun t loaded into this register then flip to the other word and again repeat for the number of times loaded into this register register name: bawc register description: bert alternating word count rate register address: dbh bit # 7 6 5 4 3 2 1 0 name acnt7 acnt6 acnt5 acnt4 acnt3 acnt2 acnt1 acnt0 default 0 0 0 0 0 0 0 0 bits 0 to 7/alternating word count rate bits 0 to 7 (acnt0 to acnt7). acnt0 is the lsb of the 8 - bit alternating word count rate counter.
product preview DS21Q55 183 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 25.2 bert repetitive pattern set these registers must be properly loaded for the bert to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern, or a daly pattern. for a repetitive pattern that is less than 32 bits, the pattern should be repeated so that all 32 bits are used to describe the pattern. for example, if the pattern was the repeating 5 - bit pattern ?01101? (where the right - most bit is the one sent first and received first) then brp1 should be loaded with adh, brp2 w ith b5h, brp3 with d6h, and brp4 should be loaded with 5ah. for a pseudorandom pattern, all four registers should be loaded with all ones (i.e., ffh). for an alternating word pattern, one word should be placed into brp1 and brp2 a nd the other word should be placed into brp3 and brp4. for example, if the dds stress pattern ?7e? is to be described, the user would place 00h in brp1, 00h in brp2, 7eh in brp3, and 7eh in brp4, and the alternating word counter would be set to 50 (decimal ) to allow 100 bytes of 00h followed by 100 bytes of 7eh to be sent and received. register name: brp1 register description: bert repetitive pattern set register 1 register address: dch bit # 7 6 5 4 3 2 1 0 name rpat7 rpat6 rpat5 rpat4 r pat3 rpat2 rpat1 rpat0 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert repetitive pattern set bits 0 to 7 (rpat0 to rpat7). rpat0 is the lsb of the 32 - bit repetitive pattern set. register name: brp2 register description: bert repetitive pattern set register 2 register address: ddh bit # 7 6 5 4 3 2 1 0 name rpat15 rpat14 rpat13 rpat12 rpat11 rpat10 rpat9 rpat8 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert repetitive pattern set bits 8 to 15 (rpat8 to rpat15). register name: brp3 register description: bert repetitive pattern set register 3 register address: deh bit # 7 6 5 4 3 2 1 0 name rpat23 rpat22 rpat21 rpat20 rpat19 rpat18 rpat17 rpat16 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert repetitive pattern set bits 16 to 23 (rpa t16 to rpat23). register name: brp4 register description: bert repetitive pattern set register 4 register address: dfh bit # 7 6 5 4 3 2 1 0 name rpat31 rpat30 rpat29 rpat28 rpat27 rpat26 rpat25 rpat24 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert repetitive pattern set bits 24 to 31 (rpat24 to rpat31). rpat31 is the lsb of the 32 - bit repetitive pattern set.
product preview DS21Q55 184 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 25.3 bert bit counter once bert has achieved synchronization, this 32 - bit counter will increment for each data bit (i.e., clock) received . toggling the lc control bit in bc1 can clear this counter, which saturates when full and will set the bbco status bit. register name: bbc1 register description: bert bit count register 1 register address: e3h bit # 7 6 5 4 3 2 1 0 name bbc7 bbc6 bbc5 bbc4 bbc3 bbc2 bbc1 bbc0 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert bit counter bits 0 to 7 (bbc0 to bbc7). bbc0 is the lsb of the 32 - bit counter. register name: bbc2 regis ter description: bert bit count register 2 register address: e4h bit # 7 6 5 4 3 2 1 0 name bbc15 bbc14 bbc13 bbc12 bbc11 bbc10 bbc9 bbc8 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert bit counter bits 8 to 15 (bbc8 to bbc15). register name: bbc3 register description: bert bit count register 3 register address: e5h bit # 7 6 5 4 3 2 1 0 name bbc23 bbc22 bbc21 bbc20 bbc19 bbc18 bbc17 bbc16 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert bit counter bits 16 to 23 (bbc16 to bbc23). registe r name: bbc4 register description: bert bit count register 4 register address: e6h bit # 7 6 5 4 3 2 1 0 name bbc31 bbc30 bbc29 bbc28 bbc27 bbc26 bbc25 bbc24 default 0 0 0 0 0 0 0 0 bits 0 to 7/bert bit counter bits 24 to 31 (bbc24 to bbc31). bbc31 is the msb of the 32 - bit counter.
product preview DS21Q55 185 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 25.4 bert error counter once bert has achieved synchronization, this 24 - bit counter will increment for each data bit received in error. toggling the lc control bit in bc1 can clear this counter. this counter sa turates when full and will set the beco status bit. register name: bec1 register description: bert error count register 1 register address: e7h bit # 7 6 5 4 3 2 1 0 name ec7 ec6 ec5 ec4 ec3 ec2 ec1 ec0 default 0 0 0 0 0 0 0 0 bits 0 to 7/error counter bits 0 to 7 (ec0 to ec7). ec0 is the lsb of the 24 - bit counter. register name: bec2 register description: bert error count register 2 register address: e8h bit # 7 6 5 4 3 2 1 0 name ec15 ec14 ec13 ec12 ec11 ec10 ec9 ec8 default 0 0 0 0 0 0 0 0 bits 0 to 7/error counter bits 8 to 15 (ec8 to ec15). register name: bec3 register description: bert error count register 3 register address: e9h bit # 7 6 5 4 3 2 1 0 name ec23 ec22 ec21 ec20 ec19 ec18 e c17 ec16 default 0 0 0 0 0 0 0 0 bits 0 to 7/error counter bits 16 to 23 (ec16 to ec23). ec23 is the msb of the 24 - bit counter.
product preview DS21Q55 186 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 26. payload error insertion function an error - insertion function is available in the DS21Q55 and is used to create errors in t he payload portion of the t1 frame in the transmit path. errors can be inserted over the entire frame or on a per - channel basis. the user can select all ds0s or any combination of ds0s. see special per - channel registration operation for information on usin g the per - channel function. errors are created by inverting the last bit in the count sequence. for example, if the error rate 1 in 16 is selected, the 16 th bit is inverted. f - bits are excluded from the count and are never corrupted. error rate changes occ ur on frame boundaries. error - insertion options include continuous and absolute number with both options supporting selectable - insertion rates. transmit error insertion setup sequence table 28 - 1 step action 1 enter desired error rate in the erc register. note: if er3 through er0 = 0, no errors will be generated even if the constant error insertion feature is enabled. 2a or 2b for constant error insertion set ce = 1 (erc .4). for a defined number of errors: - set ce = 0 (erc .4) - load noe1 and noe2 with the number of errors to be inserted - toggle wnoe (erc .7) from 0 to 1, to begin error insertion
product preview DS21Q55 187 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: erc register description: error rate control register regist er address: ebh bit # 7 6 5 4 3 2 1 0 name wnoe - - ce er3 er2 er1 er0 default 0 0 0 0 0 0 0 0 bits 0 to 3/error insertion rate select bits (er0 to er3). er3 er2 er1 er0 error rate 0 0 0 0 no errors inserted 0 0 0 1 1 in 16 0 0 1 0 1 in 32 0 0 1 1 1 in 64 0 1 0 0 1 in 128 0 1 0 1 1 in 256 0 1 1 0 1 in 512 0 1 1 1 1 in 1024 1 0 0 0 1 in 2048 1 0 0 1 1 in 4096 1 0 1 0 1 in 8192 1 0 1 1 1 in 16384 1 1 0 0 1 in 32768 1 1 0 1 1 in 65536 1 1 1 0 1 in 131072 1 1 1 1 1 in 262144 bit 4/cons tant errors (ce). when this bit is set high (and the er0 to er3 bits are not set to 0000), the error insertion logic will ignore the number of error registers (noe1, noe2) and generate errors constantly at the selected insertion rate. when ce is set to zer o, the noex registers determine how many errors are to be inserted. bit 5/unused, must be set to zero for proper operation. bit 6/unused, must be set to zero for proper operation. bit 7/write noe registers (wnoe). if the host wishes to update to the noe x registers, this bit must be toggled from a zero to a one after the host has already loaded the prescribed error count into the noex registers. the toggling of this bit causes the error count loaded into the noex registers to be loaded into the error inse rtion circuitry on the next clock cycle. subsequent updates require that the wnoe bit be set to zero and then one once again.
product preview DS21Q55 188 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 26.1 number of error registers the number of error registers determine how many errors will be generated. up to 1023 errors can be gen erated. the host will load the number of errors to be generated into the noe1 and noe2 registers. the host can also update the number of errors to be created by first loading the prescribed value into the noe registers and then toggling the wnoe bit in the error rate control registers. error insertion examples table 28 - 2 value write read 000h do not create any errors no errors left to be inserted 001h create a single error one error left to be inserted 002h create two errors two errors left to be insert ed 3ffh create 1023 errors 1023 errors left to be inserted register name: noe1 register description: number of errors 1 register address: ech bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0 to 7/nu mber of errors counter bits 0 to 7 (c0 to c7). bit c0 is the lsb of the 10 - bit counter. register name: noe2 register description: number of errors 2 register address: edh bit # 7 6 5 4 3 2 1 0 name - - - - - - c9 c8 default 0 0 0 0 0 0 0 0 bits 0 to 1/number of errors counter bits 8 to 9 (c8 to c9). bit c9 is the msb of the 10 - bit counter.
product preview DS21Q55 189 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 26.1.1 number of errors left register the host can read the noelx registers at any time to determine how many errors are left to be inserted. register name: noel1 register description: number of errors left 1 register address: eeh bit # 7 6 5 4 3 2 1 0 name c7 c6 c5 c4 c3 c2 c1 c0 default 0 0 0 0 0 0 0 0 bits 0 to 7/number of errors left counter bits 0 to 7 (c0 to c7). bit c0 is th e lsb of the 10 - bit counter. register name: noel2 register description: number of errors left 2 register address: efh bit # 7 6 5 4 3 2 1 0 name - - - - - - c9 c8 default 0 0 0 0 0 0 0 0 bits 0 to 1/number of errors left counter bits 8 to 9 (c8 to c9). bit c9 is the msb of the 10 - bit counter.
product preview DS21Q55 190 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 27. interleaved pcm bus operation in many architectures, the pcm outputs of individual framers are combined into higher speed pcm buses to simplify transport across the system backplane. the DS21Q55 can be con figured to allow pcm data to be multiplexed into higher speed buses eliminating external hardware, saving board space and cost. the DS21Q55 can be configured for channel or frame interleave. the interleaved pcm bus option (ibo) supports three bus speeds. the 4.096mhz bus speed allows two pcm data streams to share a common bus. the 8.192mhz bus speed allows four pcm data streams to share a common bus. the 16.384mhz bus speed allows eight pcm data streams to share a common bus. see figure 30 - 1 for an exampl e of four transceivers sharing a common 8.192mhz pcm bus. the receive elastic stores of each transceiver must be enabled. via the ibo register the user can configure each transceiver for a specific bus position. for all ibo bus configurations each transcei ver is assigned an exclusive position in the high - speed pcm bus. the 8khz frame sync can be generated from the system backplane or from the first device on the bus. all other devices on the bus must have their frame syncs configured as inputs. relative to this common frame sync, the devices will await their turn to drive or sample the bus according to the settings of the da0, da1, and da2 bits of the iboc register. 27.1 channel interleave mode in channel interleave mode, data is output to the pcm d ata - out bus one channel at a time from each of the connected devices until all channels of frame n from each device has been placed on the bus. this mode can be used even when the DS21Q55s are operating asynchronous to each other. the elastic stores will m anage slip conditions. 27.2 frame interleave mode in frame interleave mode, data is output to the pcm data - out bus one frame at a time from each of the devices. this mode is used only when all connected devices are operating in a synchronous fashion (all inboun d t1 or e1 lines are synchronous) and are synchronous with the system clock (system clock derived from t1 or e1 line). in this mode, slip conditions are not allowed.
product preview DS21Q55 191 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: iboc register description: interleave bus operation control register register address: c5h bit # 7 6 5 4 3 2 1 0 name - ibs1 ibs0 ibosel iboen da2 da1 da0 default 0 0 0 0 0 0 0 0 bits 0 to 2/device assignment bits (da0 to da2). da2 da1 da0 device position 0 0 0 1 st device on bus 0 0 1 2 nd device on bus 0 1 0 3 rd device on bus 0 1 1 4 th device on bus 1 0 0 5 th device on bus 1 0 1 6 th device on bus 1 1 0 7 th device on bus 1 1 1 8 th device on bus bit 3/interleave bus operation enable (iboen). 0 = interleave bus operation disabled 1 = interleave bus o peration enabled bit 4/interleave bus operation select (ibosel). this bit selects channel - or frame - interleave mode. 0 = channel interleave 1 = frame interleave bits 5 to 6/ibo bus size bit 1 (ibs0 to ibs1). indicates how many devices on the bus. ib s1 ibs0 bus size 0 0 two devices on bus 0 1 four devices on bus 1 0 eight devices on bus 1 1 reserved for future use bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 192 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . ibo example figure 29 - 1 rsysclk tsysclk rsync tssync rsig tsig tser rser rsysclk tsyscl k rsig tsig tser rser rsysclk tsysclk rsig tsig tser rser rsysclk tsysclk rsig tsig tser rser 8.192mhz system clock in system 8khz frame sync in pcm data out pcm data in pcm signaling out pcm signaling in rsync tssync rsync ts sync rsync tssync DS21Q55 #1 DS21Q55 #2 DS21Q55 #4 DS21Q55 #3
product preview DS21Q55 193 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 28. extended system information bus (esib) the esi b allows two DS21Q55s to share an 8 - bit cpu bus for the purpose of reporting alarms and interrupt status as a group. with a single bus read, the host can be updated with alarm or interrupt status from all members of the group. there are two control registe rs, esibcr1 and esibcr2, and four information registers, esib1, esib2 , esib3, and esib4 . as an example, eight DS21Q55s can be grouped into an esib group. a single read of the esib1 register of any m ember of the group will yield the interrupt status of all eight DS21Q55s. therefore the host can determine which device or devices are causing an interrupt without polling all eight devices. via esib2 the host can gather synchronization status on all membe rs of the group. esib3 and esib4 can be programmed to report various alarms on a device by device basis. there are three device pins involved in forming a esib group. these are esibs0, esibs1, and esibrd. a 10k pullup resistor must be provided on esibs0, esibs1, and esibrd. esib group of four DS21Q55s figure 30 - 1 esib0 esib1 esibrd cpu i/f DS21Q55 # 1 esib0 esib1 esibrd cpu i/f DS21Q55 # 2 esib0 esib1 esibrd cpu i/f DS21Q55 # 3 esib0 esib1 esibrd cpu i/f DS21Q55 # 4 v dd 10k (3)
product preview DS21Q55 194 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: esibcr1 register description: extended system information bus control register 1 register address: b0h bit # 7 6 5 4 3 2 1 0 name - - - - esibsel2 esibse l1 esibsel0 esien default 0 0 0 0 0 0 0 0 bit 0/extended system information bus enable (esien). 0 = disabled 1 = enabled bits 1 to 3/output data bus line select (esibsel0 to esibsel2). these bits tell the device which data bus bit to output the esib da ta on when one of the esib information registers is accessed. each member of the esib group must have a unique bit selected. esibsel2 esibsel1 esibsel0 bus bit driven 0 0 0 ad0 0 0 1 ad1 0 1 0 ad2 0 1 1 ad3 1 0 0 ad4 1 0 1 ad5 1 1 0 ad6 1 1 1 ad7 bit 4/unused, must be set to zero for proper operation. bit 5/unused, must be set to zero for proper operation. bit 6/unused, must be set to zero for proper operation. bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 195 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: esibcr2 r egister description: extended system information bus control register 2 register address: b1h bit # 7 6 5 4 3 2 1 0 name - esi4sel2 esi4sel1 esi4sel0 - esi3sel2 esi3sel1 esi3sel0 default 0 0 0 0 0 0 0 0 bits 0 to 2/address esi3 data output select (e si3sel0 to esi3sel2). these bits select what status is to be output when the device decodes an esi3 address during a bus read operation. esi3sel2 esi3sel1 esi3sel0 status output (t1 mode) status output (e1 mode) 0 0 0 rbl rua1 0 0 1 ryel rra 0 1 0 lup rdma 0 1 1 ldn v52lnk 1 0 0 sigchg sigchg 1 0 1 esslip esslip 1 1 0 - - 1 1 1 - - bit 3 / unused, must be set to zero for proper operation. bits 4 to 6/address esi4 data output select (esi4sel0 to esi4sel2). these bits select what status is to be output when the device decodes an esi4 address during a bus - read operation. esi4sel2 esi4sel1 esi4sel0 status output (t1 mode) status output (e1 mode) 0 0 0 rbl rua1 0 0 1 ryel rra 0 1 0 lup rdma 0 1 1 ldn v52lnk 1 0 0 sigchg sig chg 1 0 1 esslip esslip 1 1 0 - - 1 1 1 - - bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 196 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register name: esib1 register description: extended system information bus register 1 register address: b2h bit # 7 6 5 4 3 2 1 0 name disn disn disn disn disn disn disn disn default 0 0 0 0 0 0 0 0 bits 0 to 7/device interrupt status (disn). causes all devices participating in the esib group to output their interrupt status on the appropriate data bus line selected by the esibse l0 to esibsel2 bits of the esibcr1 register. register name: esib2 register description: extended system information bus register 2 register address: b3h bit # 7 6 5 4 3 2 1 0 name drlosn drlosn drlosn drlosn drlosn drlosn drlosn drlosn default 0 0 0 0 0 0 0 0 bits 0 to 7/device receive loss of sync (drlosn). causes all devices participating in the esib group to output their frame synchronization status on the appropriate data bus line selected by the esibsel0 to esibsel2 bits of the esibcr1 register. register name: esib3 register description: extended system information bus register 3 register address: b4h bit # 7 6 5 4 3 2 1 0 name ust1n ust1n ust1n ust1n ust1n ust1n ust1n ust1n default 0 0 0 0 0 0 0 0 bits 0 to 7/user - sele cted status 1 (ust1n). causes all devices participating in the esib group to output status or alarms as selected by the esi3sel0 to esi3sel2 bits in the esibcr2 configuration register on the appropriate data bus line selected by the esibsel0 to esibsel2 bi ts of the esibcr2 register. register name: esib4 register description: extended system information bus register 4 register address: b5h bit # 7 6 5 4 3 2 1 0 name ust2n ust2n ust2n ust2n ust2n ust2n ust2n ust2n default 0 0 0 0 0 0 0 0 bits 0 to 7/user - selected status 2 (ust2n). causes all devices participating in the esib group to output status or alarms as selected by the esi4sel0 to esi4sel2 bits in the esibcr2 configuration register on the appropriate data bus line selected by the esibsel0 to esibsel2 bits of the esibcr2 register.
product preview DS21Q55 197 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 29. programmable backplane clock synthesizer the DS21Q55 contains an on - chip clock synthesizer that generates a user - selectable clock referenced to the recovered receive clock (rclk). the synthesizer uses a phase - locke d loop to generate low - jitter clocks. common applications include generation of port and back plane system clocks. register name: ccr2 register description: common control register 2 register address: 71h bit # 7 6 5 4 3 2 1 0 name - - - - - bpcs1 bpcs0 bpen default 0 0 0 0 0 0 0 0 bit 0/back plane clock enable (bpen). 0 = disable bpclk pin (pin held at logic 0) 1 = enable bpclk pin bits 1 to 2/back plane clock selects (bpcs0, bpcs1). bpcs1 bpcs0 bpclk frequency (mhz) 0 0 16.384 0 1 8.192 1 0 4.096 1 1 2.048 bit 3/unused, must be set to zero for proper operation. bit 4/unused, must be set to zero for proper operation. bit 5/unused, must be set to zero for proper operation. bit 6/unused, must be set to zero for proper operat ion. bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 198 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 30. fractional t1/e1 support the DS21Q55 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a usart or lapd controller in fractional t1/e1 or isdn - pri applications. this is accomplished by assigning an alternate function to the rchclk and tchclk pins. when the gapped clock feature is enabled, a gated clock is output on the rchclk and/or tchclk pins. the channel selection is controlled via the special per - channel control registers. no clock is generated at the f - bit position. the receive and transmit paths have independent enables. channel formats supported include 56kbps and 64kbps. when 56kbps mode is selected, the cloc k corresponding to the data/control bit in the channel is omitted. only the seven most significant bits of the channel have clocks. register name: ccr3 register description: common control register 3 register address: 72h bit # 7 6 5 4 3 2 1 0 name - - - - tdatfmt tgpcken rdatfmt rgpcken default 0 0 0 0 0 0 0 0 bit 0/receive gapped - clock enable (rgpcken). 0 = rchclk functions normally 1 = enable gapped - bit clock output on rchclk bit 1/receive channel - data format (rdatfmt). 0 = 64kbp s (data contained in all 8 bits) 1 = 56kbps (data contained in 7 out of the 8 bits) bit 2/transmit gapped - clock enable (tgpcken). 0 = tchclk functions normally 1 = enable gapped - bit clock output on tchclk bit 3/transmit channel - data format (tdatfmt). 0 = 64kbps (data contained in all 8 bits) 1 = 56kbps (data contained in 7 out of the 8 bits) bit 4/unused, must be set to zero for proper operation. bit 5/unused, must be set to zero for proper operation. bit 6/unused, must be set to zero for proper operat ion. bit 7/unused, must be set to zero for proper operation.
product preview DS21Q55 199 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 31. jtag - boundary - scan architecture and test - access port the DS21Q55 is an mcm consisting of 4 ds2155s. each device has its on jtag state machine and therefore is treated as 4 separate devices wh en testing. the following description refers to the ds2155 jtag function. the ds2155 ieee 1149.1 design supports the standard instruction codes sample/preload, bypass, and extest. optional public instructions included are high - z, clamp, and idcode (figur e 21). the DS21Q55 contains the following as required by ieee 1149.1 standard test - access port and boundary - scan architecture: test access port (tap) tap controller instruction register bypass register boundary scan register device identification register the test access port has the necessary interface pins: jtrst, jtclk, jtms, jtdi, and jtdo. see the pin descriptions for details. jtag functional block diagram figure 34 - 1 +v boundary scan register identification register bypass register instruction register jtdi jtms jtclk jtrst jtdo +v +v test access port controller mux 10 k 10k 10k select output enable
product preview DS21Q55 200 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . tap controller state machine the tap controller is a finite state machine t hat responds to the logic level at jtms on the rising edge of jtclk (figure 34 - 2) . test - logic - reset upon power - up, the tap controller will be in the test - logic - reset state. the instruction register will contain the idc ode instruction. all system logic of the device will operate normally. run - test - idle the run - test - idle is used between scan operations or during specific tests. the instruction register and test registers will remain idle. select - dr - scan all test regi sters retain their previous state. with jtms low, a rising edge of jtclk moves the controller into the capture - dr state and will initiate a scan sequence. jtms high during a rising edge on jtclk moves the controller to the select - ir - scan state. capture - dr data can be parallel - loaded into the test - data registers selected by the current instruction. if the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. on the rising edge of jtclk, the controller will go to the shift - dr state if jtms is low or it will go to the exit1 - dr state if jtms is high. shift - dr the test - data register selected by the current instruction will be connected between jtdi and jtdo and w ill shift data one stage towards its serial output on each rising edge of jtclk. if a test register selected by the current instruction is not placed in the serial path, it will maintain its previous state. exit1 - dr while in this state, a rising edge on j tclk will put the controller in the update - dr state, which terminates the scanning process, if jtms is high. a rising edge on jtclk with jtms low will put the controller in the pause - dr state. pause - dr shifting of the test registers is halted while in thi s state. all test registers selected by the current instruction will retain their previous state. the controller will remain in this state while jtms is low. a rising edge on jtclk with jtms high will put the controller in the exit2 - dr state. exit2 - dr a r ising edge on jtclk with jtms high while in this state will put the controller in the update - dr state and terminate the scanning process. a rising edge on jtclk with jtms low will enter the shift - dr state. update - dr a falling edge on jtclk while in the up date - dr state will latch the data from the shift register path of the test registers into the data output latches. this prevents changes at the parallel output due to changes in the shift register.
product preview DS21Q55 201 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . select - ir - scan all test registers retain their previous state. the instruction register will remain unchanged during this state. with jtms low, a rising edge on jtclk moves the controller into the capture - ir state and will initiate a scan sequence for the instruction register. jtms high during a rising edge o n jtclk puts the controller back into the test - logic - reset state. capture - ir the capture - ir state is used to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of jtclk. if jtms is high on the r ising edge of jtclk, the controller will enter the exit1 - ir state. if jtms is low on the rising edge of jtclk, the controller will enter the shift - ir state. shift - ir in this state, the shift register in the instruction register is connected between jtdi a nd jtdo and shifts data one stage for every rising edge of jtclk towards the serial output. the parallel register as well as all test registers remain at their previous states. a rising edge on jtclk with jtms high will move the controller to the exit1 - ir state. a rising edge on jtclk with jtms low will keep the controller in the shift - ir state while moving data one stage thorough the instruction shift register. exit1 - ir a rising edge on jtclk with jtms low will put the controller in the pause - ir state. if jtms is high on the rising edge of jtclk, the controller will enter the update - ir state and terminate the scanning process. pause - ir shifting of the instruction shift register is halted temporarily. with jtms high, a rising edge on jtclk will put the con troller in the exit2 - ir state. the controller will remain in the pause - ir state if jtms is low during a rising edge on jtclk. exit2 - ir a rising edge on jtclk with jtms low will put the controller in the update - ir state. the controller will loop back to sh ift - ir if jtms is high during a rising edge of jtclk in this state. update - ir the instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of jtclk as the controller enters this state. once latch ed, this instruction becomes the current instruction. a rising edge on jtclk with jtms low, will put the controller in the run - test - idle state. with jtms high, the controller will enter the select - dr - scan state.
product preview DS21Q55 202 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . tap controller state diagram figure 34 - 2 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 select dr-scan capture dr shift dr exit dr pause dr exit2 dr update dr select ir-scan capture ir shift ir exit ir pause ir exit2 ir update ir test logic reset run test/ idle 0
product preview DS21Q55 203 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 31.1 instruction register the instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. when the tap controller enters the shift - ir state, the instruction shift register will be connected between jtdi and j tdo. while in the shift - ir state, a rising edge on jtclk with jtms low will shift the data one stage towards the serial output at jtdo. a rising edge on jtclk in the exit1 - ir state or the exit2 - ir state with jtms high will move the controller to the update - ir state. the falling edge of that same jtclk will latch the data in the instruction shift register to the instruction parallel output. instructions supported by the ds2155 and its respective operational binary codes are shown in table 34 - 1. instruction codes for ieee 1149.1 architecture table 34 - 1 instruction selected register instruction codes sample/preload boundary scan 010 bypass bypass 111 extest boundary scan 000 clamp bypass 011 high - z bypass 100 idcode device identification 001
product preview DS21Q55 204 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . sample/p reload this is a mandatory instruction for the ieee 1149.1 specification that supports two functions. the digital i/os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the captu re - dr state. sample/preload also allows the device to shift data into the boundary scan register via jtdi using the shift - dr state. bypass when the bypass instruction is latched into the parallel instruction register, jtdi connects to jtdo through the one - bit bypass test register. this allows data to pass from jtdi to jtdo not affecting the device?s normal operation. extest this allows testing of all interconnections to the device. when the extest instruction is latched in the instruction register, the f ollowing actions occur. once enabled via the update - ir state, the parallel outputs of all digital output pins will be driven. the boundary scan register will be connected between jtdi and jtdo. the capture - dr will sample all digital inputs into the bounda ry scan register. clamp all digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass register between jtdi and jtdo. the outputs will not change during the clamp instruction. high - z all digital ou tputs of the device will be placed in a high impedance state. the bypass register will be connected between jtdi and jtdo. idcode when the idcode instruction is latched into the parallel instruction register, the identification test register is selected. the device identification code will be loaded into the identification register on the rising edge of jtclk following entry into the capture - dr state. shift - dr can be used to shift the identification code out serially via jtdo. during test - logic - reset, the identification code is forced into the instruction register?s parallel output. the id code will always have a 1 in the lsb position. the next 11 bits identify the manufacturer?s jedec number and number of continuation bytes followed by 16 bits for the devi ce and 4 bits for the version (table 34 - 2). table 34 - 3 lists the device id codes for the devices. id code structure table 34 - 2 msb lsb version contact factory device id jedec 1 4 bits 16 bits 00010100001 1 device id codes table 34 - 3 device 16 - bit id ds2155 0010h ds21354 0005h ds21554 0003h ds21352 0004h
product preview DS21Q55 205 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . ds21552 0002h 31.2 test registers ieee 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. an optional test register has been included with the ds2155 design. this test register is the identification register and is used with the idcode instruction and the test - logic - reset state of the tap controller. 31.3 boundary scan register this register contains both a shift register path and a latched parallel output for all control cells and digital i/o cells and is n bits in length. see table 34 - 4 for all of the cell bit locations and definitions. 31.4 bypass register this is a single 1 - bit shift register used with the bypass, clamp, and high - z instructions that prov ides a short path between jtdi and jtdo. 31.5 identification register the identification register contains a 32 - bit shift register and a 32 - bit latched parallel output. this register is selected during the idcode instruction and when the tap controller is in t he test - logic - reset state. see tables 34 - 2 and 34 - 3 for more information about bit usage.
product preview DS21Q55 206 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . boundary scan control bits table 34 - 4 nxa = not externally available bit pin symbol type control bit description 2 1 rchblk o 2 jtms i 1 3 bpclk o 4 jtclk i 5 jtrst i 0 6 rcl (nxa) o 7 jtdi i 77 8 uop0 (nxa) o 76 9 uop1 (nxa) o 10 jtdo o 75 11 bts i 74 12 liuc i 73 13 8xclk (nxa) o 72 14 tstrst i 71 15 uop2 (nxa) o 16 rtip i 17 rring i 18 rv dd ? 19 rv ss ? 20 rv ss ? 21 mclk i 22 xtald (nxa) o 70 23 uop3 (nxa) o 24 rv ss ? 69 25 int o 26 n/c ? 27 n/c ? 28 n/c ? 29 ttip o 30 tv ss ? 31 tv dd ? 32 tring o 68 33 tchblk o 67 34 tlclk o 66 35 tlink i 65 - esibs0.cntl - 0 = esibs0 is an in put; 1 = esibs0 is an output 64 36 esibs0 i/o 63 ? tsync.cntl ? 0 = tsync is an input; 1 = tsync is an output 62 37 tsync i/o 61 38 tposi i 60 39 tnegi i 59 40 tclki i 58 41 tclko o 57 42 tnego o 56 43 tposo o 44 dv dd ? 45 dv ss ? 55 46 tclk i 54 47 tser i
product preview DS21Q55 207 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . bit pin symbol type control bit description 53 48 tsig i 52 49 teso (nxa) o 51 50 tdata (nxa) i 50 51 tsysclk i 49 52 tssync i 48 53 tchclk o 47 - esibs1.cntl - 0 = esibs1 is an input; 1 = esibs1 is an output 46 54 esibs1 i/o 45 55 mux i 44 ? bus.cntl ? 0 = d0 - d7/ad0 - ad7 are inputs; 1 = d0 ? d7/ad0 ? ad7 are outputs 43 56 d0/ad0 i/o 42 57 d1/ad1 i/o 41 58 d2/ad2 i/o 40 59 d3/ad3 i/o 60 dv ss ? 61 dv dd ? 39 62 d4/ad4 i/o 38 63 d5/ad5 i/o 37 64 d6/ad6 i/o 36 65 d7/ad7 i/o 35 66 a0 i 34 6 7 a1 i 33 68 a2 i 32 69 a3 i 31 70 a4 i 30 71 a5 i 29 72 a6 i 28 73 a7/ale(as) i 27 74 rd*(ds*) i 26 75 cs* i 25 - esibrd.cntl - 0 = esibrd is an input;1 = esibrd is an output 24 76 esibrd i/o 23 77 wr*(r/w*) i 22 78 rlink o 21 79 rlclk o 80 dv ss ? 81 dv dd 20 82 rclk o 83 dv dd ? 84 dv ss ? 19 85 rdata (nxa) o 18 86 rposi i 17 87 rnegi i 16 88 rclki i 15 89 rclko o 14 90 rnego o 13 91 rposo o 12 92 rchclk o 11 93 rsigf o 10 94 rsig o 9 95 rser o 8 96 rmsync o
product preview DS21Q55 208 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . bit pin symbol type control bit description 7 97 rfsync o 6 ? rsync.cntl ? 0 = rsync is an input; 1 = rsync is an output 5 98 rsync i/o 4 99 rlos/lotc o 3 100 rsysclk i 32. functional timing diagrams 32.1 t1 mode receive side d4 timing figure 35 - 1 notes: 1) rsync in the frame m ode (iocr1.5 = 0) and double - wide frame sync is not enabled (iocr1.6 = 0). 2) rsync in the frame mode (iocr1.5 = 0) and double - wide frame sync is enabled (iocr1.6 = 1). 3) rsync in the multiframe mode (iocr1.5 = 1). 4) rlink data (fs - bits) is updated one bit prior to even frames and held for two frames. frame# 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 4 rlink rlclk 3 rsync 1 rsync rfsync 2 rsync
product preview DS21Q55 209 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . receive side esf timing figure 35 - 2 notes: 1) rsync in frame mode (iocr1.4 = 0) and double wide frame sync is not enabled (iocr1.6 = 0). 2) rsync in frame mode (iocr1.4 = 0) and double wide frame sync is enabled (io cr1.6 = 1). 3) rsync in multiframe mode (iocr1.4 = 1). 4) zbtsi mode disabled (t1rcr2.2 = 0). 5) rlink data (fdl bits) is updated one bit time before odd frames and held for two frames. 6) zbtsi mode is enabled (t1rcr2.2 = 1). 7) rlink data (z bits) is updated one bit ti me before odd frames and held for four frames. 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 6 rfsync frame# tlclk rsync rsync rsync tlink 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 4 rlclk rlink 5 7
product preview DS21Q55 210 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . receive side boundary timing (with elastic store disabled) figure 35 - 3 notes: 1) rchblk is programmed to block channel 24. 2) shown is rlink/rlclk in the esf framing mode. channel 23 channel 24 channel 1 channel 23 channel 24 channel 1 rclk rser rsync rfsync rsig rchclk rchblk 1 rlclk rlink 2 b a c/a d/b a c/a d/b lsb f msb msb lsb a b
product preview DS21Q55 211 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . receive side 1.544mhz boundary timi ng (with elastic store enabled ) figure 35 - 4 notes: 1) rsync is in the output mode (iocr1.4 = 0). 2) rsync is in the input mode (iocr1.4 = 1). 3) rchblk is programmed to block channel 24. rser channel 23 channel 24 channel 1 rchclk rchblk rsysclk rsync 2 3 rsync 1 rmsync rsig lsb f msb msb lsb channel 23 channel 24 channel 1 b a c/a d/b a c/a d/b a b
product preview DS21Q55 212 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . receive side 2.048mhz boundary timing (with elastic store enabled) figur e 35 - 5 notes: 1) rser data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to one. 2) rsync is in the output mode (iocr1.4 = 0). 3) rsync is in the input mode (iocr1.4 = 1). 4) rchblk is forced to one in the same channels as rser (note 1). 5) the f - bit positio n is passed through the receive - side elastic store. rser channel 1 rchclk rchblk rsysclk rsync channel 31 channel 32 1 3 4 rsync 2 rmsync rsig channel 31 channel 32 b a c/a d/b c/a d/b a b channel 1 lsb msb lsb
product preview DS21Q55 213 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . transmit side d4 timing figure 35 - 6 notes: 1) tsync in the frame mode (iocr1.2 = 0) and double - wide frame sync is not enabled (iocr1.1 = 0). 2) tsync in the frame mode (iocr1.2 = 0) and double - wide frame sync is enabled (iocr1.1 = 1). 3) tsync in the multiframe mode (iocr1.2 = 1). 4) tlink data (fs - bits) is sampled during the f - bit position of even frames for insertion into the outgoing t1 stream when enabled via t1tcr1.2. 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 1 2 3 4 tssync frame# tlclk tsync tsync tsync tlink
product preview DS21Q55 214 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . transmit side esf timing figure 35 - 7 notes: 1) tsync in frame mode (iocr1.2 = 0) and double - wide frame sync is not enabled (iocr1.3 = 0). 2) tsync in frame mode (iocr1.2 = 0) and double - wide frame sync is enabled (iocr1.3 = 1). 3) tsync in multiframe mode (iocr1.2 = 1). 4) tlink data (fdl bits) sampl ed during the f - bit time of odd frame and inserted into the outgoing t1 stream if enabled via tcr1.2. 5) zbtsi mode is enabled (t1tcr2.1 = 1). 6) tlink data (z bits) sampled during the f - bit time of frames 1, 5, 9, 13, 17, and 21 and inserted into the outgoing s tream if enabled via t1tcr1.2. 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 6 tssync frame# tlclk tsync tsync tsync tlink 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 4 tlclk tlink 5
product preview DS21Q55 215 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . transmit side boundary timing (with elastic store disabled) figure 35 - 8 notes: 1) tsync is in the output mode (iocr1.1 = 1). 2) tsync is in the input mode (iocr1.1 = 0). 3) tchblk is programmed to block channel 2. 4) shown is tli nk/tlclk in the esf framing mode. lsb f msb lsb msb lsb msb channel 1 channel 2 channel 1 channel 2 a b c/a d/b a b c/a d/b tclk tser tsync tsync tsig tchclk tchblk tlclk tlink d/b 1 2 3 4 don't care
product preview DS21Q55 216 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . transmit side 1.544mhz boundary timing (with elastic store enabled) figure 35 - 9 note: 1) tchblk is programmed to block channel 24 (if the tpcsi bit is set, then the signaling data at tsig will be ignored during channel 24). lsb f msb lsb msb channel 1 channel 24 a b c/a d/b a b c/a d/b tsysclk tser tssync tsig tchclk tchblk channel 23 a channel 23 channel 24 channel 1 1
product preview DS21Q55 217 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . transmit side 2.048mhz boundary timing (with elastic store enabled) figure 35 - 11 notes: 1) tser data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored. 2) tchblk is programmed to block channel 31 (if the tpcsi bit is set, then the signaling data at tsig will be ignored). 3) tchblk is forced to one in the same channels as tser is ignored (note 1). 4) the f - bit position for the t1 frame is sampled and passed through the transmit side elastic store into the msb bit position of channel 1. (normally the tra nsmit side formatter overwrites the f - bit position unless the formatter is programmed to pass - through the f - bit position). lsb f lsb msb channel 1 channel 32 a b c/a d/b a b c/a d/b tsysclk tser tssync tsig tchclk tchblk channel 31 a channel 31 channel 32 channel 1 1 4 2,3
product preview DS21Q55 218 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 32.2 e1 mode receive side timing figure 35 - 11 notes: 1) rsync in frame mode (iocr1.5 = 0). 2) rsync in multiframe mode (iocr1.5 = 1). 3) rl clk is programmed to output just the sa bits. 4) rlink will always output all five sa bits as well as the rest of the receive data stream. 5) this diagram assumes the cas mf begins in the raf frame. frame# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 4 rlink rlclk 3 rsync 1 rsync rfsync 2
product preview DS21Q55 219 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . receive side boundary timing (with elastic store disabled) fi gure 35 - 12 notes: 1) rchblk is programmed to block channel 1. 2) rlclk is programmed to mark the sa4 bit in rlink. 3) shown is a rnaf frame boundary. 4) rsig normally contains the cas multiframe - alignment nibble (0000) in channel 1. channel 32 channel 1 channel 2 channel 32 channel 1 channel 2 rclk rser rsync rfsync rsig rchclk rchblk 1 rlclk rlink 2 c d a lsb msb a b si 1 a sa4 sa5 sa6 sa7 sa8 sa4 sa5 sa6 sa7 sa8 b note 4
product preview DS21Q55 220 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . receive side boundary timing, r sysclk = 1.544mhz (with elastic store enabled) figure 35 - 13 notes: 1) data from the e1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the e1 link is mapped to channel 1 of the t1 link, etc.) and the f - bit position is added (forced to one). 2) rsync in the output mode (iocr1.4 = 0). 3) rsync in the input mode (iocr1.4 = 1). 4) rchblk is programmed to block channel 24. rser channel 23/31 channel 24/32 channel 1/2 rchclk rchblk rsysclk rsync 2 3 rsync 1 rmsync lsb f msb msb lsb 4
product preview DS21Q55 221 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . receive side boundary timing, rsysclk = 2.048mhz (with elastic store enabled) figure 35 - 14 notes: 1) rsync is in the output m ode (iocr1.4 = 0). 2) rsync is in the input mode (iocr1.4 = 1). 3) rchblk is programmed to block channel 1. 4) rsig normally contains the cas multiframe - alignment nibble (0000) in channel 1. rser channel 1 rchclk rchblk rsysclk rsync channel 31 channel 32 1 3 rsync 2 rmsync rsig channel 31 channel 32 c d a b channel 1 lsb msb lsb msb c d b a note 4
product preview DS21Q55 222 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . receive ibo channel interleave mode timing figure 35 - 15 notes: 1) 4. 096mhz bus configuration. 2) 8.192mhz bus configuration. 3) 16.384mhz bus configuration. 4) rsync is in the input mode (iocr1.4 = 0). rser lsb rsysclk rsync framer2, channel 32 msb lsb framer 1, channel 1 rsig framer2, channel 32 framer 1, channel 1 msb lsb framer2, channel 1 framer2, channel 1 4 rser rsync rsig rser rsig f3 32 f4 32 f1 c1 f2 c1 f3 c1 f4 c1 f1 c2 f2 c2 f3 c2 f4 c2 1 1 2 2 bit level detail (4.096mhz bus configurtation) f2 c32 f1 c1 f2 c1 f1 c2 f2 c2 f2 c32 f1 c1 f2 c1 f1 c2 f2 c2 f3 c32 f4 c32 f1 c1 f2 c1 f3 c1 f4 c1 f1 c2 f2 c2 f3 c2 f4 c2 a b c d a b c d a b c d rser rsig 3 3 f1 c1 f2 c1 f3 c1 f4 c1 f5 c1 f6 c1 f7 c1 f8 c1 f1 c2 f2 c2 f3 c2 f4 c2 f5 c2 f6 c2 f7 c2 f8 c2 f5 c32 f6 c32 f7 c32 f8 c32 f1 c1 f2 c1 f3 c1 f4 c1 f5 c1 f6 c1 f7 c1 f8 c1 f1 c2 f2 c2 f3 c2 f4 c2 f5 c2 f6 c2 f7 c2 f8 c2 f5 c32 f6 c32 f7 c32 f8 c32 framer #1, channel #1
product preview DS21Q55 223 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . receive ibo frame interleave mode timing figure 35 - 16 notes: 1) 4.096mhz bus configuration. 2) 8.192mhz bus configuration. 3) 16.384m hz bus configuration 4) rsync is in the input mode (iocr1.4 = 0). rser lsb rsysclk rsync framer2, channel 32 msb lsb framer 1, channel 1 rsig framer2, channel 32 framer 1, channel 1 msb lsb framer1, channel 2 framer1, channel 2 4 rser rsync rsig rser rsig f3 f4 f1 f2 f3 f4 f1 f2 f3 f4 1 1 2 2 bit level detail (4.096mhz bus configurtation) f2 f1 f2 f1 f2 f2 f1 f2 f1 f2 f3 f4 f1 f2 f3 f4 f1 f2 f3 f4 a b c d a b c d a b c d rser rsig 3 3 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f5 f6 f7 f8 framer #1, channels 1 through 32
product preview DS21Q55 224 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . g.802 timing, e1 mode only figure 35 - 17 note: 1) rchblk or tchblk programmed to pulse high during timeslots 1 through 15, 17 through 25, and bit 1 of timeslot 26. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 31 32 ts # rsync tsync rchclk tchclk rchblk tchblk channel 26 channel 25 lsb msb rclk / rsysclk tclk / tsysclk rser / tser rchclk / tchclk rchblk / tchblk 1 2 0
product preview DS21Q55 225 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . transmit side timing fig ure 35 - 18 notes: 1) tsync in frame mode (iocr1.2 = 0). 2) tsync in multiframe mode (iocr1.2 = 1). 3) tlink is programmed to source just the sa4 bit. 4) this diagram assumes both the cas mf and the crc4 mf begin with the taf frame. 5) tlink and tlclk are not synchron ous with tssync. 1 2 3 4 5 6 7 8 9 10 11 12 1 3 tssync frame# tsync tsync 13 14 15 16 1 2 3 4 5 tlclk tlink 14 15 16 6 7 8 9 10 3 2
product preview DS21Q55 226 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . transmit side boundary timing (with elastic store disabled) figure 35 - 19 notes: 1) tsync is in the output mode (iocr1.1 = 1.) 2) tsync is in the input mode (iocr1.1 = 0). 3) tchblk is programmed to block channel 2. 4) tlink is programmed to s ource the sa4 bit. 5) the signaling data at tsig during channel 1 is normally overwritten in the transmit formatter with the cas multiframe - alignment nibble (0000). 6) shown is a tnaf frame boundary. lsb msb lsb msb channel 1 channel 2 channel 1 channel 2 a b c d tclk tser tsync tsync tsig tchclk tchblk tlclk tlink 1 2 3 4 don't care si 1 a sa4 sa5 sa6 sa7 sa8 d don't care 4
product preview DS21Q55 227 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . transmit side boundary timing, tsysclk = 1.544mhz (with elas tic store enabled) figure 35 - 20 notes: 1) the f - bit position in the tser data is ignored. 2) tchblk is programmed to block channel 24. lsb f msb lsb msb channel 1 channel 24 tsysclk tser tssync tchclk tchblk channel 23 1 2
product preview DS21Q55 228 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . transmit side boundary timing, tsysclk = 2.048mhz (with elastic store enabled) figure 35 - 21 note: 1) tchblk is programme d to block channel 31. lsb f lsb msb channel 1 channel 32 a b c d a b tsysclk tser tssync tsig tchclk tchblk channel 31 a channel 31 channel 32 channel 1 1 4 2,3 c d
product preview DS21Q55 229 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . transmit ibo channel interleave mode timing figure 35 - 22 notes: 1) 4.096mhz bus configuration. 2) 8.192mhz bus configuration. 3) 16.384mhz bus configuration 4) tsync is in input mode tser lsb tsysclk tsync framer2, channel 32 msb lsb framer 1, channel 1 tsig framer2, channel 32 framer 1, channel 1 msb lsb framer2, channel 1 framer2, channel 1 4 tser tssync trsig tser tsig f3 32 f4 32 f1 c1 f2 c1 f3 c1 f4 c1 f1 c2 f2 c2 f3 c2 f4 c2 1 1 2 2 bit level detail (4.096mhz bus configurtation) f2 c32 f1 c1 f2 c1 f1 c2 f2 c2 f2 c32 f1 c1 f2 c1 f1 c2 f2 c2 f3 c32 f4 c32 f1 c1 f2 c1 f3 c1 f4 c1 f1 c2 f2 c2 f3 c2 f4 c2 a b c d a b c d a b c d tser tsig 3 3 f1 c1 f2 c1 f3 c1 f4 c1 f5 c1 f6 c1 f7 c1 f8 c1 f1 c2 f2 c2 f3 c2 f4 c2 f5 c2 f6 c2 f7 c2 f8 c2 f5 c32 f6 c32 f7 c32 f8 c32 f1 c1 f2 c1 f3 c1 f4 c1 f5 c1 f6 c1 f7 c1 f8 c1 f1 c2 f2 c2 f3 c2 f4 c2 f5 c2 f6 c2 f7 c2 f8 c2 f5 c32 f6 c32 f7 c32 f8 c32 framer #1, channel #1
product preview DS21Q55 230 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . transmit ibo frame interleave mode timing figure 35 - 23 notes: 1) 4.096mhz bus configuration. 2) 8.192mhz bus configuration. 3) 16.384mhz bus configuration 4) tsync is in input mode tser lsb tsysclk tsync framer2, channel 32 msb lsb framer 1, channel 1 tsig framer2, channel 32 framer 1, channel 1 msb lsb framer1, channel 2 framer1, channel 2 4 tser tssync tsig tser tsig f3 f4 f1 f2 f3 f4 f1 f2 f3 f4 1 1 2 2 bit level detail (4.096mhz bus configurtation) f2 f1 f2 f1 f2 f2 f1 f2 f1 f2 f3 f4 f1 f2 f3 f4 f1 f2 f3 f4 a b c d a b c d a b c d tser tsig 3 3 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f5 f6 f7 f8 framer #1, channels 1 through 32
product preview DS21Q55 231 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 33. operating parameters absolute maximum ratings* voltage range on any pin relative to ground - 1.0v to +6.0v operating temperature range for DS21Q55 0 c to +70 c operating temperature range for DS21Q55n - 40 c to +85 c storage temperature range - 55 c to +125 c soldering temperature see j - std - 20a * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time can affect reliability. thermal characteristics parameter min typ max n otes ambient temperature - 40 c - +85 c 1 junction temperature - - +125 c theta - ja ( q ja ) in still air for 100 - pin lqfp - - 2 theta - ja ( q ja ) in still air for 10mm csbga pin lqfp - - 2 notes: 1) the package is mounted on a four - layer jedec standard test board. 2) theta - ja ( q ja ) is the junction to ambient thermal resistance, when the package is mounted on a four - layer jedec standard test board. theta - ja ( q ja ) vs airflow forced air (meters per second) theta - ja ( q ja ) 100 - pin lqfp theta - ja ( q ja ) 10mm cs bga 0 1 2.5
product preview DS21Q55 232 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . recommended dc operating conditions (0 c to +70 c for DS21Q55; - 40 c to +85 c for DS21Q55n) parameter symbol min typ max units notes logic 1 v ih 2.0 5.5 v logic 0 v il - 0.3 +0.8 v supply v dd 3.135 3.3 3.465 v 1 capacitanc e (t a = +25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf dc characteristics (0 c to +70 c; v dd = 3.3v 5% for DS21Q55; - 40 c to +85 c; v dd = 3.3v 5% for DS21Q55n) parameter s ymbol min typ max units notes supply current i dd 380 ma 2 input leakage i il - 1.0 +1.0 m a 3 output leakage i lo 1.0 m a 4 output current (2.4v) i oh - 1.0 ma output current (0.4v) i ol +4.0 ma notes: 1) applies to rv dd , tv dd , and dv dd . 2) tclk = t clki = rclki = tsysclk = rsysclk = mclk1 = mclk2 = 1.544mhz; outputs open circuited. 3) 0.0v < v in < v dd . 4) applied to int* when 3 - stated.
product preview DS21Q55 233 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 34. ac timing parameters and diagrams capacitive test loads are 40pf for bus signals, 20pf for all others. 34.1 multipexed bus ac characteristics ac characteristics ? multiplexed parallel port (mux = 1) (0 c to +70 c; v dd = 3.3v 5% for DS21Q55; - 40 c to +85 c; v dd = 3.3v 5% for DS21Q55n) parameter symbol min typ max units notes cycle time t cyc 200 ns pulse width, ds low or rd* high pw el 100 ns pulse width, ds high or rd* low pw eh 100 ns input rise/fall times t r , t f 20 ns r/w* hold time t rwh 10 ns r/w* setup time before ds high t rws 50 ns cs* setup time before ds, wr* or rd* active t cs 20 ns cs* hold t ime t ch 0 ns read data hold time t dhr 10 50 ns write data hold time t dhw 5 ns muxed address valid to as or ale fall t asl 15 ns muxed address hold time t ahl 10 ns delay time ds, wr*, or rd* to as or ale rise t asd 20 ns pulse width as or ale high pw ash 30 ns delay time, as or ale to ds, wr* or rd* t ased 10 ns output data delay time from ds or rd* t ddr 80 ns data setup time t dsw 50 ns see figures 37 - 1 to 37 - 3
product preview DS21Q55 234 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . intel bus read timing (bts = 0 / mux = 1) figure 37 - 1 intel bus write timing (bts = 0 / mux = 1) figure 37 - 2 ash pw t cyc t asd t asd pw pw eh el t t t t t t ahl ch cs asl ased cs* ad0-ad7 dhr t ddr ale rd* wr* ash pw t cyc t asd t asd pw pw eh el t t t t t t t ahl dsw dhw ch cs asl ased cs* ad0-ad7 rd* wr* ale
product preview DS21Q55 235 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . motorola bus timing (bts = 1 / mux = 1) figure 37 - 3 t asd ash pw t t asl ahl t cs t asl t t t dsw dhw t ch t t t ddr dhr rwh t ased pw eh t rws ahl pw el t cyc as ds ad0-ad7 (write) ad0-ad7 (read) r/w* cs*
product preview DS21Q55 236 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 34.2 nonmultiplexed bus ac characteristics ac characteristics ? nonmultiplexed parallel port (mux = 0) (0 c to +70 c; v dd = 3.3v 5% for DS21Q55; - 40 c to +85 c; v dd = 3.3v 5% for DS21Q55n) parameter symbol min typ max units notes setup time for a0 to a7, valid to cs* active t1 0 ns setup time for cs* active to either rd*, wr*, or ds* active t2 0 ns delay time from either rd* or ds* active to d ata valid t3 75 ns hold time from either rd*, wr*, or ds* inactive to cs* inactive t4 0 ns hold time from cs* inactive to data bus 3 - state t5 5 20 ns wait time from either wr* or ds* activate to latch data t6 75 ns data setup time to either wr* or ds* inactive t7 10 ns data hold time from either wr* or ds* inactive t8 10 ns address hold from either wr* or ds* inactive t9 10 ns see figures 37 - 4 to 37 - 7
product preview DS21Q55 237 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . intel bus read timing (bts = 0 / mux = 0) figure 37 - 4 intel bus write timing (bts = 0 / mux = 0) figure 37 - 5 address valid data valid a0 to a7 d0 to d7 wr* cs* rd* 0ns min. 0ns min. 75ns max. 0ns min. 5ns min. / 20ns max. t1 t2 t3 t4 t5 address valid a0 to a7 d0 to d7 rd* cs* wr* 0ns min. 0ns min. 75ns min. 0ns min. 10ns min. 10ns min. t1 t2 t6 t4 t7 t8
product preview DS21Q55 238 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . motorola bus read timing (bts = 1 / mux = 0) figure 37 - 6 motorola bus write timing (bts = 1 / mux = 0) figure 37 - 7 address valid data valid a0 to a7 d0 to d7 r/w* cs* ds* 0ns min. 0ns min. 75ns max. 0ns min. 5ns min. / 20ns max. t1 t2 t3 t4 t5 address valid a0 to a7 d0 to d7 r/w* cs* ds* 0ns min. 0ns min. 75ns min. 0ns min. 10ns min. 10ns min. t1 t2 t6 t4 t7 t8
product preview DS21Q55 239 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 34.3 receive side ac characteristics ac characteristics ? receive side (0 c to +70 c; v dd = 3.3v 5% for DS21Q55; - 40 c to +85 c; v dd = 3.3v 5% for DS21Q55n) parameter symbol min typ max units notes rclko period t lp 488 (e1) 648 (t1) ns ns rclko pulse width t lh t ll 200 200 .5 t lp .5 t lp ns ns 1 1 rclko pulse width t lh t ll 150 150 .5 t lp .5 t lp ns ns 2 2 rclki period t cp 488 (e1) 648 (t1) ns rclki pulse width t ch t cl 20 20 .5 t cp .5 t cp ns ns rsysclk period t sp t sp t sp t sp t sp 648 488 244 122 61 ns ns 3 4 5 6 7 rsysclk pulse width t sh t sl 20 20 .5 t sp .5 t sp ns ns rsync setup to rsysclk falling t su 20 ns rsync pulse width t pw 50 ns rposi/rnegi setup to rclki falling t su 20 ns rposi/rnegi hold from rclki falling t hd 20 ns rsysclk, rclki rise and fall times t r , t f 22 ns delay rclko to rposo, rnego valid t dd 50 ns delay rclk to rser, rdata, rsig, rlink valid t d1 50 ns delay rclk to rchclk, rsync, rchblk, rfsync, rlclk t d2 50 ns delay rsysclk to rser, rsig valid t d3 22 ns delay rsysclk to rchclk, rchblk, rmsync, rsync t d4 22 ns see figures 37 - 8 to 37 - 10
product preview DS21Q55 240 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . notes: 1) jitter attenuator enabled in the receive path. 2) jitter attenuator disabled or enabled in the transmit path. 3) rsysclk = 1.544mhz. 4) rsysclk = 2.048mhz. 5) rsysclk = 4.096mhz. 6) rsysclk = 8.192mhz. 7) rsysclk = 16.384mhz. receive side timing (t1 m ode) figure 37 - 8 t d1 1 t d2 rser / rdata / rsig rchclk rchblk rsyn c rlclk rlink t d1 notes: 1) rsync is in the output mode. 2) shown is rlink/rlclk in the esf framing mode. 3) no relationship between rchclk and rchblk and other signals is implied. rclk rfsync / rmsy nc f bit 2 t d2 t d2 t d2 t d2
product preview DS21Q55 241 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . receive side timing, elastic store enabled (t1 mode) figure 37 - 9 notes: 1) rsync is in the output mode. 2) rsync is in the input mode. 3) f - bit when ccr1.3 = 0, msb of ts0 when ccr1.3 = 1. f t t r t d3 t d4 t d4 t d4 t t su hd rser / rsig rchclk rchblk 1 rsync 2 rsync rsysclk sl t t sp sh t t d4 rmsync see note 3
product preview DS21Q55 242 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . receive line interface timi ng figure 37 - 10 t f t r rposi, rnegi rclki cl t t cp ch t t su t hd t dd rposo, rnego rclko ll t t lp lh t
product preview DS21Q55 243 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 34.4 transmit ac characteristics ac characteristics ? transmit side (0 c to +70 c; v dd = 3.3v 5% for DS21Q55; - 40 c to +85 c; v dd = 3.3v 5% for DS21Q55n) parameter symbol min typ (e1) max units notes tclk period t cp 488 (e1) 648 (t1) ns tclk pulse width t ch t cl 20 20 .5 t cp .5 t cp ns ns tclki period t lp 488 (e1) 648 (t1) ns tclki pulse width t lh t ll 20 20 .5 t lp .5 t lp ns ns tsysclk period t sp t sp t sp t sp t sp 648 448 244 122 61 ns ns ns ns ns 1 2 3 4 5 tsysclk pulse wid th t sp t sp 20 20 .5 t sp .5 t sp ns ns tsync or tssync setup to tclk or tsysclk falling t su 20 ns tsync or tssync pulse width t pw 50 ns tser, tsig, tlink, tposi, tnegi set up to tclk, tsysclk, tclki falling t su 20 ns tser, tsig, tlink hold fro m tclk or tsysclk, falling t hd 20 ns tposi, tnegi hold from tclki falling t hd 20 ns tclk, tclki or tsysclk rise and fall times t r , t f 25 ns delay tclko to tposo, tnego valid t dd 50 ns delay tclk to tchblk, tchclk, tsync, tlclk t d2 50 ns delay tsysclk to tchclk, tchblk t d3 22 ns see figures 37 - 11 to 37 - 13 notes: 1) tsysclk = 1.544mhz. 2) tsysclk = 2.048mhz. 3) tsysclk = 4.096mhz.
product preview DS21Q55 244 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 4) tsysclk = 8.192mhz. 5) tsysclk = 16.384mhz transmit side timing figure 37 - 11 4) tchclk and tchblk are synchronous with tclk when the transmit - side elastic store is disabled. notes: 1) tsync is in the output mode (tcr2.2 = 1). 2) tsync is in the input mode (tcr2.2 = 0). 3) tser is sampled on the falling edge of tclk when the transmit - side elastic store is disabled. 5) tlink is only sampled during f - bit lo cations. 6) no relationship between tchclk and tchblk and the other signals is implied. t f t r 1 tclk tser / tsig / tdata tchclk t t cl t ch cp tsync tsync tlink tlclk tchblk t d2 t d2 t d2 t t t t t t hd su d2 su hd d1 t hd 2 5 teso t su
product preview DS21Q55 245 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . transmit side timing, el astic store enabled figure 37 - 12 t f t r tsysclk tser tchclk t t sl t sh sp tssync tchblk t d3 t d3 t t t su hd su t hd notes: 1) tser is only sampled on the falling edge of tsysclk when the transmit - side elastic store is enabled. 2) tchclk and tchblk are sy nchronous with tsysclk when the transmit - side elastic store is enabled.
product preview DS21Q55 246 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . transmit line interface timing figure 37 - 13 tclko tposo, tnego t dd t f t r tclki tposi, tnegi t t ll t lh lp t hd t su
product preview DS21Q55 247 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 35. mechanical descriptions
product preview DS21Q55 248 of 248 0121 03 please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information .

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