spt5100 8-bit, 20 mwps dual channel video dac signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 block diagram features ? 8-bit dual channel video digital-to-analog converter ? 20 mwps operation ? low power: 70 mw ? internal voltage reference ? 5 v monolithic cmos ? 32-lead qfp package (7 mm by 7 mm, 0.8 mm pitch) applications ? high-speed digital-to-analog conversion ? y/ c, s-video processing ? desktop video processing ? digital tv ? satellite tv decoders ? digital vcrs current. the differential linearity errors of the dacs are guaranteed to be a maximum of 0.5 lsb over the full temperature range. the device is available in a 32-lead qfp package in the commercial temperature range. general description the spt5100 is an 8-bit, 20 mwps, dual channel video digital- to-analog converter specifically designed for video process- ing applications including digital tv decoders and digital vcrs. a single external resistor controls the full-scale output c urr en t swit ch cel l ar ray ( cel l 4) v cs v ref c urr en t swit ch cel l ar ray ( cel l 4) current swi tch ce ll ar ray (ce l l 6 3) la t ch de co d er la t ch y ou t av dd i oy (lsb) y y1 y2 y3 y4 y5 y6 (msb) y7 clky v cs v ref current swi tch ce ll ar ray (ce l l 6 3) la t ch de co d er la t ch c out av dd i oc (ls b) c c1 c2 c3 c4 c5 c6 (msb ) c7 clkc av ss av ss av dd av dd
spt 2 3/14/97 spt5100 electrical specifications f clk = 20 mwps, av dd = 5.0 v, output pull-up load = 240 w , t a = 25 c, av ss = 0.0 v test test parameters conditions level min typ max units dc electrical characteristics dc performance resolution 8.0 bits differential linearity t a = t min to t max i 0.25 0.5 lsb integral linearity i 0.5 1.0 lsb analog outputs output voltage range v cs = +1.25 v i 4.0 5.0 v conversion rate i 20 mwps output offset voltage i 14 25 mv signal-to-noise ratio i 41 45 db differential phase v 1.2 degrees differential gain v 2 % glitch energy v 80 pv-s settling time i 31 26 ns propagation delay (t pd ) v 10 12 ns crosstalk i -47 db fs control voltage (v cs ) iv 1.0 1.4 v digital inputs and timing input current, logic high v ih = 5 v i 5 m a logic low v il = 0 v i -5 m a set-up time, data and controls (t s )i5 ns hold time, data and controls (t h ) i 10 ns clock pulse width (low) i 25 ns clock pulse width (high) i 25 ns power supply requirements supply voltage i 4.75 5.25 v supply current i 14 ma power dissipation i 70 mw absolute maximum rating (beyond which damage may occur) 1 supply voltages av dd (measured to av ss ) ........................... -0.3 to 7.0 v input voltage clock and data ......................................... av ss to av dd output current i out ............................................................................. 0 to 8 ma temperature operating, ambient ........................................ 0 to +70 c storage .................................................... -55 to + 125 c note : 1. operation at any absolute maximum ratings is not implied. see electrical specifications for proper nominal applied conditions in typical applications.
spt 3 3/14/97 spt5100 interface considerations figure 1 shows a typical interface circuit of the spt5100 in normal circuit operation. supply and ground considerations spt suggests that all power supply pins (av dd ) be tied together and decoupled using a 0.1 m f ceramic capacitor in parallel with a 10 m f tantalum capacitor. internal reference voltage (v ref ) voltage reference is internally generated. connect a 0.1 m f bypass capacitor as close to the pin as possible. full-scale adjust control (v cs ) connect a 0.1 m f bypass capacitor with the shortest possible lead length between v cs and av ss . a resistor connected between this pin and av dd controls the magnitude of the full- scale video signal. the output voltage range of the spt5100 can be kept constant and stable by keeping the value of v cs to ground constant. the full-scale voltage changes according to v cs. (see figure 2.) current outputs the y channel and c channel current outputs should have a load resistor connected to av dd . the resistors are typically 240 w and should be kept in the 150 w to 250 w range. latch-up considerations in order to prevent a possible latch-up condition, spt sug- gests that a 100 w resistor be placed in series with each clock input pin. table i - binary codes 1 lsb = 3.91 mv, v cs = 1.25 v digital input analog step a7 a6 a5 a4 a3 a2 a1 a0 out (v) (msb) (lsb) 0 00000000 4.0000 1 00000001 4.0039 2 00000010 4.0078 3 00000011 4.0117 . . . . . . . . . 254 11111110 4.9922 255 11111111 4.9961 test level codes all electrical characteristics are subject to the following conditions: all parameters having min/ max specifications are guaranteed. the test level column indicates the specific device test- ing actually performed during production and quality assurance inspection. any blank sec- tion in the data column indicates that the speci- fication is not tested at the specified condition. test level i ii iii iv v vi test procedure 100% production tested at the specified temperature. 100% production tested at t a =25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = 25 c. parameter is guaranteed over specified temperature range.
spt 4 3/14/97 spt5100 figure 1 - typical interface circuit figure 3 - timing diagram figure 2 - typical performance characteristics t h n-data t s 1/2 lsb t pd n-output level 1/2 lsb full scale output voltage v cs (v) 1.4 1.3 1.2 1.1 1.0 0.9 2.5 3.0 3.5 4.0 4.5 5.0 full scale output voltage versus v cs load resistors = 240 ta = +25 ? digital inputs = all 240 w av dd 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 c (lsb) c1 c2 c3 c4 c5 c6 c7 (msb) v ref v cs av ss av dd av dd av ss clkc clky (msb) y7 y6 y5 y4 y3 y2 y1 (lsb) y av dd av dd av ss cout av ss yout av dd av ss 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 240 w av dd 10 k w 5 k w 2 k w 0.1 k w 0.1 k w 0.1 f 0.1 f 0.1 f av dd 0.1 f 0.1 f spt5100 10 f + -
spt 5 3/14/97 spt5100 package outline 32-lead qfp inches millimeters symbol min max min max a 0.339 0.363 8.70 9.30 b 0.261 0.285 6.70 7.30 c 0.339 0.363 8.70 9.30 d 0.261 0.285 6.70 7.30 e 0.023 0.039 0.60 1.00 f 0.012 0.020 0.30 0.50 g 0.056 0.057 1.44 1.46 h 0.002 0.006 0.05 0.15 i 0.039 typ 1.00 typ j 0.004 0.008 0.09 0.20 k0 7 0 7 l 0.016 typ 0.4 typ a b c d e f g h i j k l
spt 6 3/14/97 spt5100 pin assignments pin functions name function c out c channel analog current output y out y channel analog current output c7 - c0 c channel data inputs y7 - y0 y channel data inputs clky y channel clock input clkc c channel clock input v ref voltage reference (a 0.1 m f ceramic capacitor should be used) v cs full-scale adjust control voltage 1 to 1.4 v av ss ground av dd power supply voltage v ref v cs av ss av dd av dd av ss clkc clky (msb) y7 y6 y5 y4 y3 y2 y1 (lsb) y0 av dd av dd av ss c out av ss y out av dd av ss c7 (msb) c6 c5 c4 c3 c2 c1 c0 (lsb) 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 spt5100 ordering information part number temperature range package SPT5100SCT 0 to +70 c 32l qfp signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is hereby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited. warning - life support applications policy - spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty.
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