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"#!! $% &!'(( # ) #* + +* , + '--# + * # # #* - ! apu0594 package type handling code package type w : cog handling code ty : tray e ? ? ? ? ? general-purpose 8-bit mpu interface : allows direct connection with the 80 or 68- family mpu over bus ? ? ? ? ? not designed or rated as radiation hardened ? ? ? ? ? format of font character 5 8 dots including 1 dot which also serves for display a cursor ? ? ? ? ? operating temperature : -30 to +85 c ? ? ? ? ? packaging : chip ( 184 pads ) ? ? ? ? ? cmos silicon gate process ( p-type silicon circuit substrate ) ? ? ? ? ? built-in lcd drive power circuit ? ? ? ? ? built-in booster circuit : enables two or three times higher voltage ? ? ? ? ? built-in voltage conversion circuit : generates lcd drive voltage ( v 0 , v 1 , v 2 , v 3 or v 4 ) based on stepped-up voltage. ? ? ? ? ? bias ratio of built-in power source : 1 / 4, 1 / 5 ? ? ? ? ? built-in electronic control : controllable in 16 steps ? ? ? ? ? built-in cgrom : 240 characters ( 5 8 240 = 9600 bits ) ? ? ? ? ? built-in cgram : 8 characters ( 5 8 8 = 320 bits ) ? ? ? ? ? built-in segram : 80 segments ( 16 7 = 112 bits ) ? ? ? ? ? built-in display data ram : 32 characters ( 32 8 = 256 bits) ? ? ? ? ? power source : supply voltage for logic system : +2.7v to +5.5v lcd drive voltage : +4.0v to +11.0v ? ? ? ? ? allows serial interfacing ( ? i 2 cbus format ) ? ? ? ? ? display duty ratio : 1 / 8, 1 / 9, 1 / 16, 1 / 17 ? ? ? ? ? command features ? ? ? ? ? display of 2 lines by 16 characters ? ? ? ? ? display on / off ? ? ? ? ? normal / reverse display control ? ? ? ? ? busy flag read-out ? ? ? ? ? cursor display ? ? ? ? ? blinking ( per character ) ? ? ? ? ? display double fonts lengthwise ? ? ? ? ? power saving mode ? ! "#!! $% &!'(( ( the apu0594 is a dot matrix lcd driver with a built-in character rom, which can be connected to a microcomputer via a bus. eight-bit or serial data sent by a microcomputer is used to generate lcd drive signals for displaying characters. incorporating the character rom, which has font, characters configured in the format of 5 8 dots and the apu0594 has 80 output pins for a segment driver circuit and 17 output pins for a common driver circuit in a single chip, a display system for 16 characters 2 lines can be implemented easily. because of its lower power consumption and wider operating voltage range, the apu0594 makes itself most suited for a lcd unit on battery-operated portable information-oriented equipment. mpu interface resb csb rs rdb wrb m86 p / s d0 d1 d2 d3 d4/isel d5/sa0 d6/scl test oscillation circuit d7/sda osci osco ck annunciator drive circuit address counter instruction decoder data holder busy segs0 to segs9, coms( ? 2) lcd drive circuit timing control circuit ddram cgram segram latching circuit shift register cgrom p / s conversion circuit cursor blinking control circuit lcd power source cks shl0 shl1 v 0 to v 4 cap1+ cap1- cap2+ cap2- v out vr1 vr2 pmode v ee lp flm m v dd v ss seg0 to seg79 com0 to com15, com( ? 2) ? ! "#!! $% &!'(( . x y ( 0 , 0 ) -x -y b ump size : 78 100 m pad size : 90 119 m b ump height : 18 m die thickness : 625 m u pper_pad pitch : 110 m die size : 9838 2065 ? ! "#!! $% &!'(( / ! " # 1 dummy 4675 917 35 seg31 935 917 69 seg65 -2805 917 2 segs1 4565 917 36 seg32 825 917 70 seg66 -2915 917 3 segs0 4455 917 37 seg33 715 917 71 seg67 -3025 917 4 seg0 4345 917 38 seg34 605 917 72 seg68 -3135 917 5 seg1 4235 917 39 seg35 495 917 73 seg69 -3245 917 6 seg2 4125 917 40 seg36 385 917 74 seg70 -3355 917 7 seg3 4015 917 41 seg37 275 917 75 seg71 -3465 917 8 seg4 3905 917 42 seg38 165 917 76 seg72 -3575 917 9 seg5 3795 917 43 seg39 55 917 77 seg73 -3685 917 10 seg6 3685 917 44 seg40 -55 917 78 seg74 -3795 917 11 seg7 3575 917 45 seg41 -165 917 79 seg75 -3905 917 12 seg8 3465 917 46 seg42 -275 917 80 seg76 -4015 917 13 seg9 3355 917 47 seg43 -385 917 81 seg77 -4125 917 14 seg10 3245 917 48 seg44 -495 917 82 seg78 -4235 917 15 seg11 3135 917 49 seg45 -605 917 83 seg79 -4345 917 16 seg12 3025 917 50 seg46 -715 917 84 segs5 -4455 917 17 seg13 2915 917 51 seg47 -825 917 85 segs6 -4565 917 18 seg14 2805 917 52 seg48 -935 917 86 dummy -4675 917 19 seg15 2695 917 53 seg49 -1045 917 87 dummy -4792 795 20 seg16 2585 917 54 seg50 -1155 917 88 segs7 -4792 685 21 seg17 2475 917 55 seg51 -1265 917 89 segs8 -4792 575 22 seg18 2365 917 56 seg52 -1375 917 90 segs9 -4792 465 23 seg19 2255 917 57 seg53 -1485 917 91 coms -4792 355 24 seg20 2145 917 58 seg54 -1595 917 92 com8 -4792 245 25 seg21 2035 917 59 seg55 -1705 917 93 com9 -4792 135 26 seg22 1925 917 60 seg56 -1815 917 94 com10 -4792 25 27 seg23 1815 917 61 seg57 -1925 917 95 com11 -4792 -84 28 seg24 1705 917 62 seg58 -2035 917 96 com12 -4792 -194 29 seg25 1595 917 63 seg59 -2145 917 97 com13 -4792 -304 30 seg26 1485 917 64 seg60 -2255 917 98 com14 -4792 -414 31 seg27 1375 917 65 seg61 -2365 917 99 com15 -4792 -524 32 seg28 1265 917 66 seg62 -2475 917 100 com1 -4792 -634 33 seg29 1155 917 67 seg63 -2585 917 101 dummy -4792 -744 34 seg30 1045 917 68 seg64 -2695 917 102 dummy -4658 -894 ? ! "#!! $% &!'(( 0 ! " # 103 v 0 -4548 -894 131 ck -1093 -894 159 cap2- 3458 -894 104 v 0 -4438 -894 132 cks -963 -894 160 cap2- 3568 -894 105 v 1 -4303 -894 133 osci -833 -894 161 cap2+ 3703 -894 106 v 1 -4193 -894 134 osco -703 -894 162 cap2+ 3813 -894 107 v 2 -4058 -894 135 lp -397 -894 163 cap2+ 3923 -894 108 v 2 -3948 -894 136 flm -267 -894 164 v out 4058 -894 109 v 3 -3813 -894 137 m 38 -894 165 v out 4168 -894 110 v 3 -3703 -894 138 d0 168 -894 166 v out 4278 -894 111 v 4 -3568 -894 139 d1 474 -894 167 vr1 4412 -894 112 v 4 -3458 -894 140 d2 604 -894 168 vr2 4548 -894 113 v ss -3331 -894 141 d3 910 -894 169 dummy 4658 -894 114 v ss -3221 -894 142 d4 / isel 1040 -894 170 dummy 4792 -744 115 v ss -3111 -894 143 d5 / sa0 1346 -894 171 com7 4792 -634 116 shl0 -2988 -894 144 d6 / scl 1476 -894 172 com6 4792 -524 117 v dd -2858 -894 145 d7 / sda 1782 -894 173 com5 4792 -414 118 v dd -2748 -894 146 v dd 1912 -894 174 com4 4792 -304 119 shl1 -2618 -894 147 v dd 2022 -894 175 com3 4792 -194 120 v ss -2494 -894 148 v dd 2132 -894 176 com2 4792 -84 121 v ss -2384 -894 149 v ee 2283 -894 177 com1 4792 25 122 test -2261 -894 150 v ee 2393 -894 178 com0 4792 135 123 resb -2131 -894 151 v ee 2503 -894 179 comi 4792 245 124 csb -2001 -894 152 cap1- 2638 -894 180 coms 4792 355 125 rs -1872 -894 153 cap1- 2748 -894 181 segs4 4792 465 126 m86 -1742 -894 154 cap1- 2858 -894 182 segs3 4792 575 127 p / s -1612 -894 155 cap1+ 2993 -894 183 segs2 4792 685 128 wrb -1482 -894 156 cap1+ 3103 -894 184 dummy 4792 795 129 rdb -1352 -894 157 cap1+ 3213 -894 130 pmode -1223 -894 158 cap2- 3348 -894 ? ! "#!! $% &!'(( 1 symbol i / o pin description resb i used to reset the apu0594. the apu0594 is reset when ?0? is entered. d0 d1 d2 d3 d4 / isel d5 / sa0 d6 / scl d7 / sda i / o when set to parallel interface mode (p / s = ?h?) used as an 8-bit bi-directional data bus, (d0-d7) which is connected to data bus in 8-bit mpu. when set to serial interface mode (p / s = ?l?) used as serial interface signals (sda, scl, and isel). sda : i / o for the i 2 cbus data line when serial interface is selected. must be connecting to a positive supply via pull-up resistor. scl : input for the i 2 cbus clock signal when serial interface is selected. must be connecting to a positive supply via pull-up resistor. sa0 : used for lsb bit of slave address for i 2 cbus (7 bits width) . must be fixed at ?h? or ?l?. isel : used to identify i 2 cbus. when use i 2 cbus; need to fix ?h?. if isel is set ?l?, apu0594 operation is not warranty. csb i used to enter chip select signal. normally, address bus signal is decoded and then entered. rs i used to identify data sent by mpu at d0 to d7. rdb (e) i when connected to 80-family mpu : used to connect rdb signal for 80-family mpu. when this signal becomes ?l?, data bus in the apu0594 enters the output mode. when connected to 68-family mpu : used to connect enable clock e signal for 68-family mpu. when this signal becomes ?h?, apu0594 is made active. wrb (r / w) i when connected to 80-family mpu : used to connect wrb signal for 80-family mpu. when this signal becomes ?l?, apu0594 is made active and any signal over data bus is captured at leading edge of wrb signal. when connected to 68-family mpu : used to connect read / write control signal for 68-family mpu. r / w = ?h? : read r / w = ?l? : write m86 i used to select mpu interface type. fixed at either m86 = ?h? for 68-family interface or m86 = ?l? for 80-family interface. p / s i used to switch between parallel and serial interface. p / s = ?h? for parallel interface. fixes sda and scl at ?h? or ?l?. p / s = ?l? for serial interface. fixes d7 to d0 at hi -z ; rdb and wrb at ?h? or ?l?. test i used for testing purpose. must be fixed at ?l?. ? ! "#!! $% &!'(( $ symbol i / o pin description lp o used as latch signal output pin for display data. outputs lcd drive signal when lp signal fall. flm o used as lcd sync signal (first line marker) output pin . mo used as alternation signal output pin for lcd drive output . used as common driver output pin for lcd drive (for character display) . among v 0 , v 1 , v 4 , and v ss levels, one level is selected depending on the combination of scanned data and m signal . data m output level hhv ss lhv 1 hlv 0 com0 to com15 o llv 4 used as common output pin for marker display . becomes common output pin when duty + 1 (plus) command is executed . having two output pins for com1, they output same level , it is able to select output pin for com1 when wiring pattern , duty + 1 on duty + 1 off com1 o com1 state com16 (when displaying 2 lines) , com8 (when displaying 1 line) v 0 or v 4 seg0 to seg79 o used as segment driver output pin for lcd drive . among v 0 , v 2 , v 3 , and v ss levels, one level is selected depending on the combination of m signal and display data . coms o used as common driver output pin for static lcd drive (for annunciator display) . having two output pins for coms, they output same level , it is able to select output pin for coms when wiring pattern. when da = ? 0 ? , outputs v ss level . segs0 to segs9 o used as segment driver output pin for static lcd drive (for annunciator display) . among v dd and v ss levels, one level is selected depending on the combination of coms signal and display data . when da = ? 0 ? , outputs v ss level . shl0, shl1 i input pin to control the transfer direction of the segment and common signal output data . shl0 = ? 0 ? : segment data display direction is seg0 to seg79 . shl0 = ? 1 ? : segment data display direction is seg79 to seg0 . shl1 = ? 0 ? : common data display direction is com0 to com15 . shl1 = ? 1 ? : common data display direction is com15 to com0 . m signal display data seg output v 0 1 1 1 0 0 0 v 2 v ss v 3 ? ! "#!! $% &!'(( % & symbol i / o pin description osci i used as oscillation circuit input pin (feedback resistor must be inserted between this pin and osco) . osco o used as oscillation circuit output pin . the ck pin must be fixed at v ss oscillation circuit is used as source oscillation clock . ck i used as external clock input pin . the osci pin must be fixed at v ss if this pin is used for original oscillation input . cks i used as external clock select pin . cks = ? h ? : external clock is input at the ck pin . cks = ? l ? : oscillation circuit using the osci and osco pins is used . symbol i / o pin description v dd power source used as logic system power pin , which must be connected to +2.7 to +5.5 v . v ss power source used as ground pin , which must be connected to 0 v . v 0 v 1 v 2 v 3 v 4 power source used as bias power pin for lcd drive voltage . when using an external power supply , convert impedance by using resistance-division of lcd drive power supply or operation amplifier before adding voltage to the pins . when using the external power supply , maintain the following power supply conditions . v ss < v 4 < v 3 < v 2 < v 1 < v 0 when the power supply circuit is on , lcd drive voltage of v 0 to v 4 are generated by the built in booster and voltage converter . when using the built-in power supply , be sure to connect each capacitor between v 0 to v 4 and v ss . ? ! "#!! $% &!'(( 2 symbol i / o pin description cap1+ o used to connect positive side of capacitor for built-in booster circuit . a capacitor must be connecting between this pin and the cap1- pin . cap1- o used to connect negative side of capacitor for built-in booster circuit . a capacitor must be connecting between this pin and the cap1+pin . cap2+ o used to connect positive side of capacitor for built-in booster circuit . a capacitor must be connecting between this pin and the cap2- pin. cap2- o used to connect negative side of capacitor for built-in booster circuit . a capacitor must be connecting between this pin and the cap2+ pin. v ee power pin used to apply voltage for generating booster voltage . normally this pin must be set at the same level as at the v dd pin. v out power pin used as output pin when built-in booster circuit is used . a capacitor must be connected between this pin and the v ss pin . if only voltage conversion circuit is used , voltage must be input so that the condition of v out > v 0 is satisfied . vr1 i used as input pin for voltage conversion circuit . voltage must be input between the v out and v ss pins by dividing voltage by resistor , and must be input so that the condition of vr1 vr2 > 4.0 v is satisfied . vr2 i used as input pin for voltage conversion circuit . voltage must be input between the v out and v ss pins by dividing voltage by resistor , and must be input so that the condition of vr1 vr2 > 4.0 v is satisfied . pmode i used as lcd power control pin . the operation condition of power circuit must be selected using the combination of the pmode pin and the power circuit on / off command (pon). ' " (a-1) input circuit 1 v dd input signal i v ss (0v) applicable pins : m86, p / s, shl0, shl1, osci, ck, cks, pmode, resb, test ? ! "#!! $% &!'(( (a-2) input circuit 2 input signal i applicable pins : csb, rs, wrb, rdb input control signal v dd v ss (0v) v ss (0v) (b-1) input / output circuit 1 input signal i/o applicable pins : osco input signal output control signal output signal v dd v ss (0v) v dd v ss (0v) ? ! "#!! $% &!'(( (b-2) input / output circuit 2 v dd i/o v ss (0v) applicable pins : d0 to d7 output control signal output signal input signal v ss (0v) v ss (0v) v dd (c) output circuit o output signal applicable pins : lp, flm, m, segs0 to segs9, coms v dd v dd v ss (0v) v ss (0v) (d) lcd output circuit v 0 o v 1 / v 2 output control signal 1 output control signal 3 output control signal 2 output control signal 4 applicable pins : seg0 to seg79, com0 to com15, com v 0 v ss (0v) v ss (0v) v ss (0v) v 4 / v 3 ? ! "#!! $% &!'(( ( ()*+,-+./.0/*-+./) the apu0594 performs data transfer via the 8-bit data bus or the serial data input (the sda or scl pin) . the parallel or serial interface is selected by setting the polarity of the p / s pin to ? h ? or ? l ? . p / s i / f type csb rs rdb wrb m86 sda scl data bus h parallel csb rs rdb wrb m86 ?? d0 to d7 lserial ????? sda scl ? the apu0594 allows parallel data transfer by directly connecting the data bus to an 8-bit mpu if the parallel interface is selected with the p / s pin . for this 8-bit mpu, the 80-family or 68-family mpu type interface can be selected with the m86 pin. m86 mpu type csb rs rdb wrb d0 to d7 h 68-family mpu csb rs e r / w d0 to d7 l 80-family mpu csb rs rdb wrb d0 to d7 % the apu0594 identifies data types over the 8-bit data bus by combinations of rs, rdb, and wrb signals. 80-family rs 68-family r / w rdb wrb function 0 1 0 1 reads out busy flags 0 0 1 0 writes commands 1 1 0 1 reads out ram data 1 0 1 0 writes ram data the serial interface for the apu0594 is i 2 cbus format. i 2 cbus is for bi-directional, two-line communication between different ics or other modules. apu0594 always operated for slave device, sending data start and stop is controlled by start / stop bit, which are sent by master device. ? i 2 cbus is a philips ? s registered trademark ? ! "#!! $% &!'(( . when the busy flag is ? 1 ? , this indicates that the apu0594 is internally operating. in this state, the apu0594 does not accept the next instruction. as shown in the instruction table, the busy flag is output to the data bus d7 when rs is ? 0 ? or r / w is ? 1 ? (for 68-family interface) , and when rs is ? 0 ? or rdb is ? 0 ? (for the 80-family interface) . the busy flag is generated only when the display clear command or the acl command is executed. it must be checked that the busy flag is ? 0 ? before the next instruction can be executed. ' ! # the address counter (ac) is used to address the ddram, or segram. when the addressing instruction is written into the ac, the address information is transferred to the ac. simultaneously, the instruction also determines which ram is to be selected among the ddram, cgram, and segram. after data is written into (read out into) the ddram, cgram , or segram , the ac is automatically counted up or down by one . as shown in the instruction table, the ac outputs data to the data buses d6 to d0 when rs is ? 0 ? or r / w is ? 1 ? (for the 68-family interface) . 1 ! # the ddram stores display data presented with 8-bit character codes. its capacity is 32 characters in the format of 8 bits. 2 3 ! ) the cgram generates 240 different character patterns in the format of 5 8 dots from 8-bit character codes. 3 ! ) the cgram allows you to freely overwrite characters with your program. eight different types of characters can be written by the format of 5 8 dots. ( ) the segram allows you to freely control icons and marks with your program. when the com1 outputs the select signal, the data stored in the segram is read out to display 80 segments. the timing generator circuit generates the timing signals to operate the internal circuits including the ddram, cgrom, cgram, and segram as well as those for segment and common driver outputs. read-out of the display data to the lcd drive circuit is completely independent of mpu. therefore, mpu that has no relationship the read-out operation of the display data can access. ? ! "#!! $% &!'(( / this circuit generates the cursor, the blinking cursor, or the reverse-display cursor. the cursor or the blinking cursor appears in the digit that corresponds to the address in the ddram, which was specified in the address, counter. % this is the cr oscillation circuit, which controls the oscillation frequency with feedback resistor rf. this circuit is used as the source of display timing signals and the boost clock for the booster circuit. if external clock is used, maintain osci pin at v ss and osco pin opens (nc) , and feed the clock to ck pin. the duty cycle of the external clock must be 50%. the cks pin is used to switch between the oscillation circuit and the external clock input. cks oscillation circuit external clock ? l ? enabled disabled ? h ? disabled enabled $ this is the drive circuit, which generates 4-value levels for lcd drive. it consists of 17 common drivers and 80 segment drivers. character data is transferred by 60 bits from the cgrom or the cgram to the segment driver circuit. the combination of the transferred display data and the m signal is used to output lcd drive voltage. among the common outputs, one output (com1) is used to marker display. the common driver circuit has a shift register and sequentially outputs common scan select signals. this is the drive circuit, which generates 2-value levels for static lcd drive. this circuit provides displaying announciators for icons or marks. it consists of common drivers (coms 2) and 10 segment drivers (segs0 to segs9) . among v dd and v ss levels, one level is selected for static lcd drive. when this circuit is not displaying announciator , it outputs v ss level. ' $ $ the voltage conversion circuit incorporates a voltage generation circuit, which divides the electric potential at the v 0 pin with resistors to generate the electric potentials v 0 , v 1 , v 2 , v 3 , and v 4 which are required for lcd drive. the lcd drives voltage bias for the apu0594 is 1 / 4 or 1 / 5. if the built-in power source is used, the capacitor c2 for voltage stabilization must be connected to the lcd power pin. in order to stabilize the input voltages at the vr1 and vr2, the capacitor c2 must be connected for the actual system by selecting its value as appropriate. ? ! "#!! $% &!'(( 0 1 $ 15 16 1 2 3 16 1 2 3 1 32 lp flm m com0 v 1 com1 seg0 seg1 v 0 v 4 v 0 v 4 v 4 v 4 v 1 v 1 v ss v ss v 0 v 4 v 3 v 2 v 0 v 2 v 3 v ss v ss v 3 v 3 v 3 v 2 v 2 v 0 v 1 v ss ? ! "#!! $% &!'(( 1 2 & the power supply circuit generates the voltage required for lcd drive. it consists of a booster circuit, an electronic volume, and a voltage conversion circuit. high voltage boosted by the booster circuit is input to the voltage conversion circuit so that the necessary voltages for lcd drive (v 0 , v 1 , v 2 , v 3 , and v 4 ) are generated. if the number of pixels on your lcd panel is large, i.e., the display capacity is large; the built-in power circuit should not be used for driving that lcd panel. if used, this could greatly deteriorate the display quality. in this case, an external power source should be used. the power circuit is off, the booster circuit and the power circuit on / off command (pon) . when the built-in power circuit is off, the booster circuit and the voltage conversion circuit are also off. if an external power source is used, lcd drive voltages v 0 , v 1 , v 2 , v 3 , and v 4 must be externally supplied with the built-in power circuit off; the cap1+, cap1-, cap2+, cap2-, v out , v ee , vr1, and vr2 pins must be opened; and the pmode pin must be connected to the v ss pin. the function of the power circuit can be selected depending on the status of the pmode pin. some functions of the external power source and the built-in power source can be combined to use together. pon pmode booster circuit voltage conversion circuit external voltage input remarks 0 0 disabled disabled v 0 , v 1 , v 2 , v 3 , and v 4 are supplied ? 1 0 1 disabled disabled v 0 , v 1 , v 2 , v 3 , and v 4 are supplied ? 1 1 0 enabled enabled ? 1 1 disabled enabled v out , vr1, and v 2 are supplied ? 2 ? 1 : the power circuit does not operate . therefore, open the cap1+, cap1-, and cap2+ , cap2-, v out , v ee , vr1, and vr2 pin; and externally supply lcd drive voltages. ? 2 : the booster circuit does not operate . therefore, open the cap1+, cap1-, cap2+, cap2-, and v ee pins; supply power for the voltage conversion circuit at the v out pin; and supply reference voltage for lcd drive at the vr1 and vr2 pins. $ the voltage conversion circuit incorporates an electronic volume, which allows the lcd drive voltage level v 0 to be controlled with a command and also allows the tone of lcd display to be controlled. if 4-bit data is stored in the register of the electronic volume, one level can be selected among 16 voltage values for the lcd drive voltage v 0 . the input voltage determines the voltage control range of the electronic control levels at the vr1 and vr2. this means that the voltage range of (vr1 ? vr2) is the controllable voltage range of the electronic volume. the electric potential relation between the vr1 and vr2 pins must be vr1 > vr2. the input voltage levels at the vr1 and vr2 pins must be selected in accordance with the voltage levels to be obtained with electronic volume. ? ! "#!! $% &!'(( the capacitor c1 is connected between the cap1+ and cap1-, between the cap2+ and cap2- and between the v out and v ss so that the electric potential between the v ee and v ss is tripled and then output at the v out pin. for the doubled electric potential, the capacitor between the cap2+ and cap2- is removed from the above connections and the cap1+ and cap2+ are short-circuited. then the doubled voltage can be obtained at the v out pin. the booster circuit uses the clock signal from the oscillation circuit or the ck pin as the booster signal. this requires that the oscillation circuit is operating or that the clock signal is input at the ck pin. you must take care that the output level at the v out pin does not exceed the recommended maximum operating voltage (11.0 v) when the voltage is doubled or tripled. if this value is exceeded, the operation of the apu0594 is not warranty. v out = 9 v v ee = 3 v v ss = 0 v for tripled voltage v out = 6 v v ee = 3 v v ss = 0 v for doubled voltage $ the boosted voltage at the v out pin is connected to the vr1 and vr2 pins and then the lcd drive volt- ages (v 0 , v 1 , v 2 , v 3 , and v 4 ) are generated via the voltage conversion circuit . the input level at the vr1 and vr2 must meet the electric potential condition of vr1 > vr2. the built-in electric volume divides the electric potential between the vr1 and vr2 into 16 segments. since the vr1 and vr2 pins have high input impedance, the input voltage levels at the vr1 and vr2 are determined by the resistance ratio of r1, r2, and r3. the current flowing between the v out and v ss pins is determined by the combined resis- tance of r1, r2, and r3.therefore, r1, r2, and r3 must be selected in accordance with the above current as well as the input voltage levels at the vr1 and vr2.the boosted voltage at the v out pin origi- nates from the voltage supplied at the v ee pin. thus, the dc path current generated with r1, r2, and r3 connected between the v out and v ss pins is consumed as consumption current at the v ee pin. the electric current value three times large than the dc path current generated between the v out and v ss pins when the voltage is tripled is added as consumption current at the v ee pin (two times larger current is added for doubled voltage). you must take sufficient care that the input levels at the vr1 and vr2 pins do not fluctuate with external noise. ? ! "#!! $% &!'(( v out vr1 vr2 v ss apu0594 r1 r2 r3 example of voltage control circuit setting the resb pin to the ? l ? level can initialize the apu0594. normally, the resb pin is connected to the reset pin on the mpu so that the apu0594 can be initialized together with the mpu. when the apu0594 is turned on, the resetting must be performed. item pin description function set re = 0 : writes to expanded register disabled . be = 0 : segram blink off dub = 0 : normal display mode . (displaying double fonts lengthwise off) bt = 0 : blinking type is normal / reverse display . entry mode set i / d = 1 : increments by one s = 0 : no shift occurs . display mode set nl = 0 : display 2 lines . display control 1 d = 0 : display off c = 0 : cursor off b = 0 : blink off display control 2 plus = 0 : 1 / 16 duty rev = 0 : normal display alon = 0 : normal display power control halt = 0 : power saving off pon = 0 : power circuit off acl = 0 : acl operation off bias : 1 / 5 bias register in electronic volume (1 , 1 , 1 , 1) annunciator control da = 0 : display annunciator off i0 to i7 = (0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0) ram data ddram : not determined cgram : not determined segram : not determined ? ! "#!! $% &!'(( 2 % 4 & cap1+ cap1- cap2+ cap2- v out vr1 vr2 osci osco cks apu0594 v dd external power source when built-in power circuit is not used cap1+ cap1- cap2+ cap2- vr1 vr2 osci osco cks apu0594 c1 v ss c2 v ss c3 v ss r1 r2 r3 c2 c2 c2 c2 c2 rf c1 c1 r1+r2+r3 2.0 to 4.0 m ? rf c2 c1 1.0 to 5.0 f 0.1 f 1m ? recommended values v dd v dd v dd v ee v ee v ss v out v ss v 0 v 1 v 2 v 3 v 4 v 0 v 1 v 2 v 3 v 4 v 0 v 1 v 2 v 3 v 4 v ss v ss v ss ? ! "#!! $% &!'(( ( ! ) since the instructions for the apu0594 are executed which execution cycle time, the mpu can be oper- ated at a high speed without waiting time. the busy state check is only necessary when the display clear command or the acl command is executed. instruction code instruction re rs d7 d6 d5 d4 d3 d2 d1 d0 description display clear 0 / 1000000 0 0 1 specifies address 0 from ddram in ac after clearing all display. cursor home 0 / 1000000 0 1 ? allocates address 0 for ddram in ac and resets shifted display. entry mode set 0 i / d s specifies cursor moving direction and whether or not to shift display. display mode set 1 000000 1 ? nl sets display 2lines or 1line (nl). display control 1 0 dcb turns on / off all display (d); turns on / off cursor (c); or specifies blinking character indicated by cursor (b). display control 2 1 000001 plus rev alon specifies duty + 1 (plus); displays data in reverse display (rev); or turns on all display (alon). cursor / display shift 0 s / c r / l ?? moves cursor and shifts display without changing data in ddram. power control 1 00001 bias halt pon acl specifies power saving (halt); turn on power circuit (pon); or specifies resetting (acl). sets bias ratio (bias). function set 0 / 1 0 0 0 1 be dub re bt ? enables writes to expanded register (re). enables blinking for segram (be). enables display double font lengthwise (dub). sets blinking character type (bt). cgram address set 0 cgram address set segram address set 1 001 ?? segram address set ddram address set 0 ? ddram address set electronic volume set 1 010 ?? electronic volume set 0 i5 i4 i3 i2 i1 i0 annunciator control 1 011 da ? i9 i8 i7 i6 sets data for annunciator (i0 to i9). enables display annunciator (da). busy flag / address read 0 / 1 0 bf ? reads out busy flag and data from ac. ram data write 0 / 1 1 ram data write ram data read 0 / 1 1 ram data read ? ! "#!! $% &!'(( ( 2-1. display clear space code ? 20h ? (for 32 characters) is written to all addresses in the ddram. the address counter specifies ddram address 0. if the display is shifted, it is reset in place. this means that the display is cleared and the cursor or blinking cursor, if displayed , returns to the left end in the first line .set the i / d of the increment mode to ? increment ? , ? s ? will not change. if you start clearing the display, the busy flag is generated. therefore, to execute . instructions after clearing the display, monitor the busy flag and then execute the next instruction after checking that the flag has been released, or allow an waiting period for 34 times the source clock frequency. 2-2. cursor home specify ddram address 0 in the address counter. if the display is shifted, it is reset in place. the data in the ddram remains unchanged .the cursor or the blinking cursor, if displayed, returns to the left end in the first line. 2-3. entry mode set re rs d7 d6 d5 d4 d3 d2 d1 d0 0 / 1000000001 re rs d7 d6 d5 d4 d3 d2 d1 d0 0 / 100000000 ? re rs d7 d6 d5 d4 d3 d2 d1 d0 00000001i / ds ? ! "#!! $% &!'(( (( when the extended register enable bit (re) is ? 0 ? , the following i / s , and s bits are accessed : i / d : when any character code is written into or read out from the ddram , the ddram address is shifted by + 1 (i / d = 1) or +1 (i / d = 0). in case of +1, the cursor or the blinking cursor moves to the right. this is also applicable when any data is written into or read out from the cgram or segram. s : if s = 1 , the entire display is shifted to either the left or right when any character code is written into the ddram. if i / d = 1, the entire display is shifted to the left; or if i / s = 0 , the entire display is shifted to the right . therefore, if i / d = 1, the cursor looks stationary with only the display shifted . when any character code is read out from the ddram, the display is not shifted. if s = 0, the display remains unshifted. when any data is written into or read out from the cgram or segram, the display also remains unshifted. when duty + 1 command is on (plus = 1), if s = 1 and any code is written into ddram, the line that com1 scans is also shifted , so that this command is allowed only duty + 1 command is off (plus = 0) state. 2-4. display mode set when the extended register enable bit (re) is ? 1 ? , the following nl bit is accessed : nl : this command selects the displaying lines . nl = ? 0 ? : displays 2 lines . display duty ratio is 1 / 16. nl = ? 1 ? : displays 1 line . display duty ratio is 1 / 8. 2-5. display control 1 when the extended register enable bit (re) is ? 0 ? , the following d, c, and b bits are accessed : d : turns on the display if d = 1; or turns off the display if d = 0. since the data in the ddram is retained, the display can be resumed by specifying d = 1. c : displays the cursor if c = 1; or hides the cursor if c = 0. even if the cursor is hidden, i / d and other features remain unchanged when the display data is written. the cursor is shown using 5 dots in the 8 th line . b : blinks the character in the cursor position if b = 1. this blinking turns on / off all dots dis- played in reverse. the blinking frequency is ms when f osc = k hz and displays 2lines. this value caries in proportion to the inverse number of f osc . re rs d7 d6 d5 d4 d3 d2 d1 d0 10000001 ? nl re rs d7 d6 d5 d4 d3 d2 d1 d0 0000001dcb ? ! "#!! $% &!'(( (. 2-6. display control 2 when the extended register enable bit (re) is ? 1 ? , the plus , rev , and alon bits are accessed. once the specified values are stored in the register, they are retained even if the re bit is set to ? 0 ? . plus : specifies ? duty + 1 ? . toggles the display duty. the com1 pin functions as the com8 (when displaying 1 line) or com16 (when displaying 2 lines) for marker. when the com1 is scanned, the data in the segram is output as display data from the segment driver. plus = ? 0 ? : sets the display duty to 1 / 8 (when displaying 1 line) or 1 / 16 (when displaying 2 lines). plus = ? 1 ? : sets the display duty to 1 / 9 (when displaying 1 line) or 1 / 17 (when displaying 2 lines). rev : toggles between normal and reverse video for display. rev = ? 0 ? : normal video rev = ? 1 ? : reverse video alon : toggles between normal and full lit-up display regardless the data type in the ddram. the setting of this bit takes priority over that of rev. alon = ? 0 ? : normal display alon = ? 1 ? : full lit-up display 2-7. cursor / display shift when the extended register enable bit (re) is ? 0 ? , the following s / c and r / l bits may be set. the cursor position or the display is shifted to the left or right without writing the display data or reading it out. this may be used to modify or search the display. the cursor movement from the 1 st to 2 nd line occurs after the 16 th digit in the 1 st line. note that all the lines are shifted simultaneously. when duty + 1 command is on (plus = 1), if s = 1 and any code is written into ddram, the line that com1 scans is also shifted, so that this command is allowed only duty + 1 command is off (plus = 0) state. re rs d7 d6 d5 d4 d3 d2 d1 d0 0000001dcb re rs d7 d6 d5 d4 d3 d2 d1 d0 000001s / cr / l ?? ? ! "#!! $% &!'(( (/ 2-8. power control bias : this command selects the displaying bias ratio. bias = ? 0 ? : 1 / 5 bias. bias = ? 1 ? : 1 / 4 bias. halt : turns on / off the power saving mode. when the apu0594 enters the power saving mode, the consumed current can be decreased to nearly the standby current value. halt = ? 0 ? : normal mode. halt = ? 1 ? : power saving mode. the internal state in the power saving mode is decried below ? the oscillation and power circuits are stopped. ? the lcd drive is disabled. the output from the segment and common drivers are made at the v ss level. ? the clock input at the ck pin is inhibited. pon : turns on / off the internal power circuit. pon = ? 0 ? : turns off the power circuit. pon = ? 1 ? : turns on the power circuit. the booster circuit and the voltage conversion circuit become active when the power circuit is turned on. the operating section in the circuits varies depending on the setting of the pmode pin. for further details, see the description of functions. acl : the internal circuit can be initialized. acl = ? 0 ? : normal mode. acl = ? 1 ? : acl operation is on. if you turn on acl command, the busy flag is generated. therefore, to execute an instruction after acl operation, monitor the busy flag and then execute the next period for 2 times the source clock frequency. re rs d7 d6 d5 d4 d3 d2 d1 d0 100001biashaltponacl ? ! "#!! $% &!'(( (0 2-9. function set re : this bit is the enable bit for extended register. if re = ? 1 ? , the extended function setting can be accessed. when setting instruction, it is necessary to follow the state of re bit.(refer to instruction code.) be : when be = ? 1 ? , the information which was stored in the segram using its upper 2 bits may be used to allow for blinking the display data from the segram. dub : this bit is toggled the display double fonts lengthwise. dub = ? 0 ? : display normal mode. dub = ? 1 ? : display double fonts lengthwise. ? note : double fonts lengthwise is able to display only first line. ? note : not using these setting, when displaying 1 line mode. (nl = 1) bt : this command selects the character blinking type. bt = ? 0 ? : displaying normal / reverse per 32 frames. bt = ? 1 ? : displaying normal / black per 32 frames. 2-10. cgram address set if the extended register enable bit (re) is ? 0 ? , cgram addresses may be specified. in the above example, the address had shown in binary number for ? aaaaaa ? is allocated in the address counter. subsequently data is written for read from the mpu by referencing the cgram. 2-11. segram address set if the extended register enable bit (re) is ? 1 ? , segram addresses may be specified. the address had shown in binary number for ? aaaa ? is allocated in the address counter. subsequently data is written or read from the mpu in referencing the scgram. re rs d7 d6 d5 d4 d3 d2 d1 d0 0 / 1 0 0 0 1 be dub re bt ? re rs d7 d6 d5 d4 d3 d2 d1 d0 0001aaaaaa re rs d7 d6 d5 d4 d3 d2 d1 d0 1001 ?? aaaa ? ! "#!! $% &!'(( (1 2-12. ddram address set if the extended register enable bit (re) is ? 0 ? , ddram addresses may be specified. the ddram address had shown in binary number for ? aaaaa ? is allocated in the address counter. subsequently data is written or read from the mpu in referencing to the ddram. 2-13. electronic volume register set the lcd drove voltage v 0 output from the built-in power circuit can be controlled and the display tone on the lcd can be also controlled. the lcd drive voltage v 0 takes one out of 16 voltage values by setting 4 bit data register. if the electronic control is not used, specify (1, 1, 1, and 1) in the 4-bit data register. after the apu0594 is reset, the 4-bit data register is automatically set to (1, 1, 1, 1). 2-14. annunciator control i0 to i9 : these bits are setting data for annunclator. i0 to i9 correspond to segs0 to segs9 for static lcd drive outputs. da : when da = ? 1 ? , outputs pin for static lcd drive (for annunciator display). among v dd and v ss levels, one level is selected depending on the combination of coms signal and display data (i0 to i9). when da = ? 0 ? , outputs v ss level. re rs d7 d6 d5 d4 d3 d2 d1 d0 0010 ? aaaaa re rs d7 d6 d5 d4 d3 d2 d1 d0 1010 ?? msb ???? . lsb msb lsb v 0 0 0 0 0 1 1 1 1 smaller larger .......... ............ ............ re rs d7 d8 d5 d4 d3 d2 d1 d0 0 i5i4i3i2i1i0 1 011 da ? i9 i8 i7 i6 ? ! "#!! $% &!'(( ( "v ss " "v dd " coms segs0 segs1 not lighted lighted display off("da" = "0") display on("da" = "1") 1 frame 1 frame example of outputs for annunciator (da = "1", i0 = "0", i1 = "1") "v ss " "v ss " "v ss " "v ss ""v ss " "v dd " "v dd " 2-15. busy flag / address read ? bf = 1 ? indicates that the apu0594 is internally operating and the next instruction is not accepted until ? bf = 0 ? . the busy flag is only generated when the display clear or the acl command is executed. therefore, any other instruction can be executed without monitoring the busy flag. simultaneously, the address counter value presented in binary number for ? aaaaaa ? is read out. the address counter is used by the ddram, cgram, and segram. the data read out from the rams is determined by specifying a command before this. 2-16. write data to ram writes binary 8-bit data d0 to d7 to the cgram or ddram or segram. whether the cgram or ddram or segram is to be written into is determined by the previous specification of cgram or ddram or segram address setting. after writing, the address automati- cally increments or decrements by 1, in accordance with the entry mode. re rs d7 d6 d5 d4 d3 d2 d1 d0 0 / 1 0 bf ? aaaaaa re rs d7 d6 d5 d4 d3 d2 d1 d0 0 / 11 dddddddd ? ! "#!! $% &!'(( ( 2-17. read data to ram reads binary 8-bit data d0 to d7 from the cgram or dgram or ddram or segram. the most recent set address command determines whether the cgram or ddram or segram is to be read. after writing, the address automatically increments or decrements by 1, in accordance with the entry mode. 2-18. example of instructions vs. display re rs d7 d6 d5 d4 d3 d2 d1 d0 0 / 11 dddddddd instruction no. rs d7 d6 d5 d4 d3 d2 d1 d0 display action power on 1 no display appears. function set 2 0 0 0 1 ? ? 0 0 ? ? 0 ? is written to re bit. display clear 3 0 0 0 0 0 0 0 0 1 display is cleared. display on / off control 4 0 0 0 0 0 1 1 1 0 _ turns on display and cursor. if display clear, display is filled with blank spaces. entry mode set 5 0 0 0 0 0 0 1 1 0 _ counts up address by one and moves cursor to right when data is written to ram. ddram data write 6 1 0 1 0 0 0 0 0 1 a_ writes ? a ? . 7 : : ddram data write 8 1 0 1 0 0 0 0 1 1 anpec_ writes ? c ? . ddram address set 9 0 1 ? ? 1 0 0 0 0 anpec _ set dram address so that cursor is positioned at top of 2nt line. ddram data write 10 1 0 1 0 0 1 1 0 0 anpec l_ writes ? l ? . 11 : : ddram data write 12 1 0 1 0 1 0 0 1 0 anpec lcddriver_ writes ? r ? . 13 : : cursor home 14 0 0 0 0 0 0 0 1 ? anpec lcddriver resets both display and cursor in place (address 0) ? ! "#!! $% &!'(( (2 character codes vs. character patterns low order high order ? ! "#!! $% &!'(( . cgram addresses vs. character codes (ddram) and character patterns (cgram). ? mark shows ? don ? t care ? . upper section : character pattern 1 (y display) lower section : character pattern 2 (h display) note : 1. character code bits d2 to d0 correspond to cgram addresses a5 to a3 (3 bits : 8 types) 2. cgram addressed a2 to a0 correspond to line positions of the character pattern (3 bits : 8 lines) 3. the columns of the character pattern are laid out with bit 0 allocated to the right end. therefore, the pattern of bits 4 to 0 is displayed. 4. if the upper 4 bits (7 to 4) of the character code are zeros, the cgram is selected. since bit d3 are ? don ? t care ? , ? 00h ? and ? 08h ? are the same cgram address. 5. if the cgram data is ? 1 ? data is displayed; if ? 0 ? , data isn ? t displayed. character code d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 a5 a4 a3 a2 a1 a0 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? 1 0 0 0 1 0 0 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 cgram address cgram data (y) (h) ? ? ? 1 0 0 0 1 ? ! "#!! $% &!'(( . segram addresses vs. display patterns segram address segram data a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 b1 b0 ? s0 s1 s2 s3 s4 0 0 0 1 b1 b0 ? s5 s6 s7 s8 s9 0 0 1 0 b1 b0 ? s10 s11 s12 s13 s14 0 0 1 1 b1 b0 ? s15 s16 s17 s18 s19 0 1 0 0 b1 b0 ? s20 s21 s22 s23 s24 0 1 0 1 b1 b0 ? s25 s26 s27 s28 s29 0 1 1 0 b1 b0 ? s30 s31 s32 s33 s34 0 1 1 1 b1 b0 ? s35 s36 s37 s38 s39 1 0 0 0 b1 b0 ? s40 s41 s42 s43 s44 1 0 0 1 b1 b0 ? s45 s46 s47 s48 s49 1 0 1 0 b1 b0 ? s50 s51 s52 s53 s54 1 0 1 1 b1 b0 ? s55 s56 s57 s58 s29 1 1 0 0 b1 b0 ? s60 s61 s62 s63 s64 1 1 0 1 b1 b0 ? s65 s66 s67 s68 s69 1 1 1 0 b1 b0 ? s70 s71 s72 s73 s74 1 1 1 1 b1 b0 ? s75 s76 s77 s78 s79 ? mark shows ? don ? t care ? . blink control pattern displayed (d7 and d6) (d4 to d0) note : 1. data stored in the segram is output for one-line display when com1 is selected. 2. pins s0 to s79 are segment driver pins. these segment physical positions will not be changed when either shl 0 = ?0? or ?1?. 3. after output at pin s79, that at pin s0 is repeated. 4. for segram data, the lower 5 bits are used for display data. 5. if be bit control the blinking of the lower 5-bit pattern. when d7 is set to ? 1 ? , the lower 5-bit display blinks. if bit d6 is ? 1 ? , only the pattern of bit d4 can be blinked. 6. if segram data is ? 1 ? , data is displayed; or if ? 0 ? , data isn ? t displayed. ? ! "#!! $% &!'(( .( display positions vs. display data ram (ddram) addresses the above addressing is used because 16 digits are displayed. the ddram stores data for 32 characters. if the display data is shifted, the ddram addresses are changed as follows : shift to right shift to left note : the memory in the ddram is configured as follows : digit 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th com0 to 7000102030405060708090a0b0c0d0e0f com8 to 15 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f digit 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th com0 to 71f000102030405060708090a0b0c0d0e com8 to 15 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e digit 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th com0 to 70102030405060708090a0b0c0d0e0f10 com8 to 15 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 00 display area (16 characters x 2 line) as shown above, the 2 nd data appears following the end of the data in the 1 st line. notice that the addresses are consecutive. ? ! "#!! $% &!'(( .. apu0594 built-in i 2 cbus format interface. the i 2 cbus is for bi-directional, two-line communication between different ics or modules. i 2 cbus protocol consists of data receiver and data transmitter. the device, which control protocol, is master, the device that is controlled is slave. master controls data translation and provides clock signal. the apu0594 is used as slave receiver or slave receiver slave transmitter. 1-1. data transfer the change of sda-state is allowed during scl is low level. if sda change during scl is high, this action is recognized as start bit or stop bit. 1-2. start signal when the bus is not busy, sda transfer high to low during scl is high. this state is defined as the start condition. 1-3. stop signal when the bus is not busy, sda transfer low to high during scl is high. this state is defined as the stop condition. 1-4. acknowledge acknowledge bit is used to confirm data translation. transmitters (master or slave) release bus lines after receive 8 bit data. during next clock (9 th clock) receiver, put low level on the bus to indicate data receive completely. start signal stop signal scl sda start / stop timing 9 acknowledge scl sda acknowledge timing 12 8 data data data ? ! "#!! $% &!'(( ./ 1-5. device address code after sending start bit, master device must transfer 8bit device address code at first. address code consists of 7bits-slave address and 1 bit r / w. when read operation, r / w bit is ? 1 ? . when write operation, r / w bit is ? 0 ? . 1-6. device addressing bus master must generate start-condition to start data translation between 2 devices. after gener- ate start condition, master puts 8 bit word on sda bus line. apu0594 is fixed higher order bits (corresponding to db7 to db2) for identify device, it is fixed ? 011101 ? . next 1 bit is used to select lcd driver among some devices connecting to same bus. apu0594 can connect to same bus up to 2 chips. sa0 is used for lsb bit for identify device. 8 th bit (r / w bit) define operation mode. r/w = ? 0 ? : write operation r/w = ? 1 ? : read operation slave address(7bits) send data at first cycle r / wack { "0" : slave receiver "1" : slave transmitter sa0 r/w apu0594 slave address 1 0 1 1 1 0 1-7. second transferred data after received start condition, first cycles of 1 byte, when slave receive mode, apu0594 is speci- fied control-byte waiting mode, control-bye consists of 3 bits. these bits are used to specify function mode for operating instruction. co : this bit define translation mode. ? 0 ? : last control byte, only data bytes to follow ? 1 ? : next two bytes are a data byte and another are control byte rs : rs is correspond to ? rs ? signal in instruction table. this bit specified translation data, r/w : this bit specified read/write mode. ? 0 ? : readable mode ? 1 ? : write enable mode. send data at second cycle r/w rs co ? ! "#!! $% &!'(( .0 & 33 ? scl serial clock input pin scl is used for clock of all data i/o ? sda sda is bi-directional pin, which is used to data i/o. sda is open drain pin, so please connect to v dd via pull-up resistor. ? sa0 sa0 is used for lsb bit of slave address (7 bits width). must be fixed at ? h ? or ? l ? externally. ? isel isel select to use i 2 cbus or not when isel is ? h ? , i 2 cbus is enable. if isel is low, i 2 cbus-operation of apu0594 is not warranty. % 4 ! "%# step i 2 c byte display operation 1 i 2 c start initialized. nothing display writing slave address sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/w ack 2 0 1 1 1 0 1 0 0 1 during the acknowledge cycle sda will be pull-downed by uc037 send a control byte co rs r/w ack 3 0 0 0 0 0 0 0 0 1 control bits rs and co and r/w are specified function set d7 d6 d5 d4 d3 d2 d1 d0 ack 4 0 0 1 0 0 0 0 0 1 set re bit ? 0 ? display clear d7 d6 d5 d4 d3 d2 d1 d0 ack 5 0 0 0 0 0 0 0 1 1 display clear display on/off control d7 d6 d5 d4 d3 d2 d1 d0 ack 6 0 0 0 0 1 1 1 0 1 ? display and cursor are on all display are clear by operating display clear entry mode set d7 d6 d5 d4 d3 d2 d1 d0 ack 7 0 0 0 0 0 1 1 0 1 ? entry mode set. when ram writing, address is up by 1 and cursor is shifted right. cgram address set d7 d6 d5 d4 d3 d2 d1 d0 ack 8 0 1 0 0 0 0 0 0 1 ? set address to write into cgram 9 start condition ? set rs bit ? 1 ? and generated start condition for writing send slave address sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/w ack 10 0 1 1 1 0 1 0 0 1 ? ? ! "#!! $% &!'(( .1 4 ! "%# step i 2 c byte display operation send control byte co rs r/w ack 11 0 1 0 0 0 0 0 0 1 ? cgram data write d7 d6 d5 d4 d3 d2 d1 d0 ack 12 0 0 0cg4cg3cg2cg1cg0 1 ? write cgram data 13 : : : 14 start condition ? generated start condition again for setting rs ? 0 ? 15 send condition ? send control byte co rs r/w ack 16 0 0 0 0 0 0 0 0 1 ? set ddram address d7 d6 d5 d4 d3 d2 d1 d0 ack 17 1 0 0 0 0 0 0 0 1 ? setting address for ddram writing 18 start condition ? set rs ? 1 ? and generated start condition again for ddram writing send slave address sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/w ack 19 0 1 1 1 0 1 0 0 1 ? send control byte co rs r/w ack 20 0 0 0 0 0 0 0 0 1 ? write ddram data d7 d6 d5 d4 d3 d2 d1 d0 ack 21 0 1 0 0 0 0 0 1 1 a_ write ? a ? 22 : : send ddram data d7 d6 d5 d4 d3 d2 d1 d0 ack 23 0 1 0 0 0 0 1 1 1 anpec_ write ? c ? 24 start condition anpec_ set rs ? 1 ? and generated start condition again for ddram writing send slave address sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/w ack 25 0 1 1 1 0 1 0 0 1 anpec_ send control byte co rs r/w ack 26 0 0 0 0 0 0 0 0 1 anpec_ send ddram address d7 d6 d5 d4 d3 d2 d1 d0 ack 27 0 0 0 1 0 0 0 0 1 anpec_ set ddram address for cursor set ahead of 2 nd line 28 start condition anpec_ set rs ? 1 ? and generated start condition again for ddram writing ? ! "#!! $% &!'(( . 4 !%"%# step i 2 c byte display operation send slave address sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/w ack 29 0 1 1 1 0 1 0 0 1 anpec_ send control byte co rs r/w ack 30 0 1 0 0 0 0 0 0 1 anpec_ write ddram data d7 d6 d5 d4 d3 d2 d1 d0 ack 31 0 1 0 0 0 0 0 0 1 anpec l_ write ? l ? 32 : : : write ddram data d7 d6 d5 d4 d3 d2 d1 d0 ack 33 0 1 0 1 0 0 1 0 1 anpec lcddriver_ write ? r ? 34 start condition anpec lcddriver_ set rs ? 1 ? and generated start condition again for ddram writing send slave address sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/w ack 35 0 1 1 1 0 1 0 0 1 anpec lcddriver_ send control byte co rs r/w ack 36 1 0 0 0 0 0 0 0 1 anpec lcddriver_ set control bit co ? 1 ? set ddram address d7 d6 d5 d4 d3 d2 d1 d0 ack 37 1 0 0 0 0 0 0 0 1 anpec lcddriver_ set address for read-out ddram data send control byte co rs r/w ack 38 0 1 1 0 0 0 0 0 1 anpec lcddriver _ set control bit rs ? 1 ? and r/w ? 1 ? 39 start condition anpec lcddriver _ set rs ? 1 ? and generated start condition again for ddram writing send slave address sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/w ack 40 0 1 1 1 0 1 0 1 1 anpec lcddriver _ set r/w ? 1 ? for read-out ddram data read out data d7 d6 d5 d4 d3 d2 d1 d0 ack 41 msb ????????? lsb anpec lcddriver _ read-out ddram data from msb to lsb master doing acknowledge 42 : : : read out data d7 d6 d5 d4 d3 d2 d1 d0 ack 43 msb ????????? lsb 1 anpec lcddriver _ as master don ? t acknowledge, data will not be output in next cycle 44 stop condition anpec lcddriver _ generated stop condition and finish ? ! "#!! $% &!'(( . 4 item symbol condition applicable pin rated value unit supply voltage (1) v dd v dd -0.3 to +7.0 v supply voltage (2) v ee v ee -0.3 to +7.0 v supply voltage (3) v out v out -0.3 to +13.0 v supply voltage (3) vr vr -0.3 to +13.0 v supply voltage (3) v 0 v 0 -0.3 to +13.0 v supply voltage (4) v 1 ,v 2 ,v 3 ,v 4 v 1 ,v 2 ,v 3 ,v 4 -0.3 to v 0 +0.3 v input voltage v i relative to v ss (0 v) : ta = + 25 c ? 1 -0.3 to v dd +0.3 v storage temperature tstg -45 to +125 c ? 1 : d0 to d7, csb, rs, m86, rdb, wrb, ck, cks, osci, p/s, resb, pmode, shl0, shl1 and test pins item symbol applicable pin min typ max unit remarks supply voltage v dd v dd 2.7 5.5 v ? 1 v 0 v 0 411v ? 2 recommended operating voltage v out v out 411v operating temperature topr -30 85 c ? 1 : this is the voltage applied to the v ss pin. ? 2 : the voltage relation shall meet the condition of v ss < v 4 < v 3 < v 2 < v 1 < v 0 . anpec electronics corp. head office : 5f, no. 2 li-hsin road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 7f, no. 137, lane 235, pac chiao rd., hsin tien city, taipei hsien, taiwan, r. o. c. tel : 886-2-89191368 fax : 886-2-89191369 )-.((5+*( ? ! "#!! $% &!'(( .2 3 3 unless otherwise specified, v ss = 0v, v dd = +2.7 to +5.5v and ta = -30 to +85 c item symbol applicable condition min typ max unit applicable pin high-level input voltage(1) vih 0.8 v dd v dd v ? 1 low-level input voltage(1) vil 0 0.2 v dd v ? 1 high-level output voltage(1) voh ioh = -0.4 ma v dd -0.4 v ? 2 low-level output voltage(1) vol iol = 0.4 ma 0.4 v ? 2 input leak current ili v i = v ss or v dd -10 10 a ? 3 output leak current ilo v i = v ss or v dd -10 4 10 a ? 4 resistance when lcd driver output is turned on ron1 | von| = 0.5v v 0 = 8v 8 k ? ? 5 resistance when static lcd driver output is turned on ron2 | von| = 0.5v 8 k ? ? 6 v dd =3v 5 standby current istb ck = 0v csb = v dd v dd =5v 10 a ? 7 oscillation frequency fosc rf = ? 2% v dd =3v 46 khz ? 8 booster input voltage v ee 2.4 5.5 v ? 9 8.6 booster output voltage v out when voltage is tripled (v ee = 3v) when voltage is doubled (v ee = 3v) 5.7 v ? 10 current consumption(1) idd1 v 0 = 6v, v dd = 3v (triple voltage) a ? 11 current consumption(2) idd2 v 0 = 5v, v dd = 3v (double voltage) a ? 12 reset ? l ? pulse width trw 10 s ? 13 applicable pins : ? 1 : d0 to d7, csb, rs m86, rdb, wrb, ck, cks, p/s, resb, pmode, shl0, shl1 and test pins. ? 2 : d0 to d7, lp, flm and m pins. ? 3 : csb, rs, m86, rdb, wrb, ck, cks, p/s, resb, pmode, shl0, shl1 and test pins. ? 4 : applicable when d0 to d7 are at high impedance. ? 5 : seg0 to seg79, com0 to com15 and com1 pins. resistance value when 0.5v is applied between each output pin and each power source (v 0 , v 1 , v 2 , v 3 , v 4 or v ss ). applicable when power is supplied at the power bias ratio of 1/7 in the external power supply mode. ? 6 : segs0 to segs9 and coms pins. ? 7 : current at the v d pin when the source oscillation frequency clock is stopped; the chip is not se- lected (csb = v dd ); and no load is used. ? ! "#!! $% &!'(( / ? 8 : oscillation frequency when feedback resistor rf of 1m ? is connected between osci and osco. ? 9 : if the step-up circuit is used, the primary power v ee must be used within the above range. if the drive voltage for the lcd panel you are mounting can boost using the voltage level at the v dd pin, connect to the normal v dd power supply. ? 10 : v out pin applicable when the built-in oscillation circuit (rf = ? ) and power circuit (pmode = ? l ? ) are used. measuring conditions : c1 = 1 f; v out pin is connected only c1 and the lcd driver pin is not loaded. ? 11 : applicable if no access is made by the mpu when the built-in oscillation circuit (rf = ? ) and power circuit (pmode = ? l ? ) are used . the electronic control is not used (the code is ? 1111 ? ). the step-up circuit is used for tripling voltage. the display is full lit-up (alon = ? 1 ? ) and the lcd driver pin is not loaded. measuring conditions : v dd = v ee ; vr1 = vr2; c1 = 1 f; c2 = 0.1 f; r1+r2+r3 = 4m ? ; the current flowing through voltage control resistors (r1, r2 and r3) is included. ? 12 : applicable if no access is made by the mpu when the built-in oscillation circuit (rf = k ? ) and power circuit (pmode = ? l ? ) are used. the electronic control is not used (the code is ? 1111 ? ). the step-up circuit is used for double voltage. the display is full lit-up (alon = ? 1 ? ) and the lcd driver pin is not loaded. measuring conditions : v dd = v ee ; vr1 = vr2; c1 = 1 f; c2 = 0.1f; r1+r2+r3 = 4m ? ; the current flowing through voltage control resistors (r1, r2 and r3) is included. ? 13 : resb pin 3 2-1.system bus read / write timing (80-family mpu) (read timing) (write timing) csb rs rdb (e) d0 to d7 tas8 tah8 trdw8 trdh8 trdd8 tcyc8 csb rs wrb (r-nw) d0 to d7 tas8 tah8 twrw8 tcyc8 tdh8 tds8 ? ! "#!! $% &!'(( / (80-family mpu timing characteristics) (v dd = 4.5 to 5.5v, ta = -30 to +85 c) item symbol measuring condition mix max unit applicable pin address hold time address setup time tah8 tas8 ns csb rs system cycle time read pulse width write pules width tcyc8 trdw8 twrw8 ns wrb rdb data setup time data hold time tds8 tdh8 ns d0 to d7 read data output delay time read data hold time trdd8 trdh8 cl = 15 pf ns d0 to d7 input signal rise and fall time tr, tf ns all of above pins (v dd = 4.5 to 5.5v, ta = -30 to +85 c) item symbol measuring condition mix max unit applicable pin address hold time address setup time tah8 tas8 ns csb rs system cycle time read pulse width write pules width tcyc8 trdw8 twrw8 ns wrb rdb data setup time data hold time tds8 tdh8 ns d0 to d7 read data output delay time read data hold time trdd8 trdh8 cl = 15 pf ns d0 to d7 input signal rise and fall time tr, tf ns all of above pins 2-2. system bus read/write timing (68-family mpu) (read timing) (write timing) e (rdb) r/wb (wrb) csb rs d0 to d7 tcyc6 tew6 tas6 trdd6 tah6 trdh6 e (rdb) r/wb (wrb) csb rs d0 to d7 tcyc6 tew6 tas6 tah6 tdh6 tds6 ? ! "#!! $% &!'(( /( ! ) 3 1. connection to the 80-family mpu a0 v cc (80-family mpu) a1 to a7 iorq d1 to d7 rd wr res gnd rs v dd (apu0594) csb d0 to d7 rdb wrb resb v ss decoder reset input 2.2v to 5.5v 7 8 2. connection to the 68-family mpu a0 v cc (68-family mpu) a1 to a15 vma d0 to d7 e r/w res gnd rs v dd (apu0594) csb d0 to d7 rdb(e) wrb(r/w) resb v ss decoder reset input 2.2v to 5.5v 15 8 item condition min typ max unit basic gate propagation delay time ta = +2 5 c, v ss = 0v, v dd = 5.0v 10 ns 4 3 |
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