IRFL210 features ? surface mount ? available in tape and reel ? dynamic dv/dt rating ? repetitive avalanche rated ? fast switching ? ease of paralleling ? simple drive requirements ? lead (pb)-free available description the sot-223 package is designed for surface-mounting using vapor phase, infrared, or wave soldering techniques. its unique package design allows for easy automatic pick-and-place as with other sot or soic packages but has the added advantage of improved thermal performace due to an enlarged tab for heatsinking. power dissipation of greater than 1.25 w is possible in a typical surface mount application. note a. see device orientation. product summary v ds (v) 200 r ds(on) ( )v gs = 10 v 1.5 q g (max.) (nc) 8.2 q gs (nc) 1.8 q gd (nc) 4.5 configuration single n -channel mosfet g d s sot-223 ordering information package sot-223 sot-223 lead (pb)-free IRFL210pbf IRFL210trpbf a sihfl210-e3 sihfl210t-e3 a snpb IRFL210 IRFL210tr a sihfl210 sihfl210t a absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 200 v gate-source voltage v gs 20 continuous drain current v gs at 10 v t c = 25 c i d 0.96 a t c = 100 c 0.6 pulsed drain current a i dm 7.7 linear derating factor 0.025 w/c linear derating factor (pcb mount) e 0.017 single pulse avalanche energy b e as 50 mj repetitive avalanche current a i ar 0.96 a repetitive avalanche energy a e ar 0.31 mj 2014-8-9 1 www.kersemi.com
notes a. repetitive rating; pulse width limited by maximum junction temper ature (see fig. 11). b. v dd = 50 v, starting t j = 25 c, l = 81 mh, r g = 25 , i as = 0.96 a (see fig. 12). c. i sd 3.3 a, di/dt 70 a/s, v dd v ds , t j 150 c. d. 1.6 mm from case. e. when mounted on 1" square pcb (fr-4 or g-10 material). note a. when mounted on 1" square pcb (fr-4 or g-10 material). maximum power dissipation t c = 25 c p d 3.1 w maximum power dissipation (pcb mount) e t a = 25 c 2.0 peak diode recovery dv/dt c dv/dt 5.0 v/ns operating junction and st orage temperature range t j , t stg - 55 to + 150 c soldering recommendations (peak temperature) for 10 s 300 d thermal resistance ratings parameter symbol min. typ. max. unit maximum junction-to-ambient (pcb mount) a r thja --40 c/w maximum junction-to-case (drain) r thjc --60 absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 200 - - v v ds temperature coefficient v ds /t j reference to 25 c, i d = 1 ma - 0.30 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = 200 v, v gs = 0 v - - 25 a v ds = 160 v, v gs = 0 v, t j = 125 c - - 250 drain-source on-state resistance r ds(on) v gs = 10 v i d = 0.58 a b --1.5 forward transconductance g fs v ds = 50 v, i d = 0.58 a 0.51 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 140 - pf output capacitance c oss -53- reverse transfer capacitance c rss -15- total gate charge q g v gs = 10 v i d = 3.3 a, v ds = 160 v, see fig. 6 and 13 b --8.2 nc gate-source charge q gs --1.8 gate-drain charge q gd --4.5 turn-on delay time t d(on) v dd = 100 v, i d = 3.3 a, r g = 24 , r d = 30 , see fig. 10 b -8.2- ns rise time t r -17- turn-off delay time t d(off) -14- fall time t f -8.9- internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact -4.0- nh internal source inductance l s -6.0- d s g IRFL210 2014-8-9 2 www.kersemi.com
notes a. repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. pulse width 300 s; duty cycle 2 %. typical characteristics 25 c, unless otherwise noted fig. 1 - typical output characteristics, t c = 25 c fig. 2 - typical output characteristics, t c = 150 c fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol showing the integral reverse p - n junction diode - - 0.96 a pulsed diode forward current a i sm --7.7 body diode voltage v sd t j = 25 c, i s = 0.96 a, v gs = 0 v b --2.0v body diode reverse recovery time t rr t j = 25 c, i f = 3.3 a, di/dt = 100 a/s b - 150 310 ns body diode reverse recovery charge q rr - 0.60 1.4 c forward turn-on time t on intrinsic turn-on time is negligib le (turn-on is dominated by l s and l d ) specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit s d g 91193_01 20 s p u lse w idth t c = 25 c 4.5 v 10 1 10 0 10 -1 10 0 10 1 v ds , drain-to-so u rce v oltage ( v ) i d , drain c u rrent (a) 10 -1 bottom to p v gs 15 v 10 v 8 .0 v 7.0 v 6.0 v 5.5 v 5.0 v 4.5 v 91193_02 4.5 v 20 s p u lse w idth t c = 150 c 10 0 10 -1 10 0 10 1 v ds , drain-to-so u rce v oltage ( v ) i d , drain c u rrent (a) 10 -1 bottom to p v gs 15 v 10 v 8 .0 v 7.0 v 6.0 v 5.5 v 5.0 v 4.5 v 91193_03 25 c 150 c 20 s p u lse w idth v ds = 50 v 10 -1 10 0 i d , drain c u rrent (a) v gs , gate-to-so u rce v oltage ( v ) 567 8 910 4 10 -2 91193_04 i d = 3.3 a v gs = 10 v 3.0 0.0 0.5 1.0 1.5 2.0 2.5 - 60 - 40 - 20 0 20 40 60 8 0 100 120 140 160 t j , j u nction temperat u re ( c) r ds(on) , drain-to-so u rce on resistance ( n ormalized) 3.5 IRFL210 2014-8-9 3 www.kersemi.com
fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area 91193_05 300 250 200 150 0 100 10 0 10 1 capacitance (pf) v ds , drain-to-so u rce v oltage ( v ) v gs = 0 v , f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd c iss c rss c oss 50 91193_06 q g , total gate charge (nc) v gs , gate-to-so u rce v oltage ( v ) 20 16 12 8 0 4 02 8 6 4 i d = 3.3 a for test circ u it see fig u re 13 10 v ds = 40 v v ds = 100 v v ds = 160 v 91193_07 10 1 10 0 10 -1 25 c 150 c 0.4 0. 8 1.6 1.2 2.0 v gs = 0 v v sd , so u rce-to-drain v oltage ( v ) i sd , re v erse drain c u rrent (a) 91193_0 8 100 s 1 ms 10 ms operation in this area limited b y r ds(on) t c = 25 c t j = 150 c single p u lse i d , drain c u rrent (a) 10 2 2 5 2 5 2 5 v ds , drain-to-so u rce v oltage ( v ) 10 10 2 25 2 5 0.1 1 10 1 25 10 3 IRFL210 2014-8-9 4 www.kersemi.com
fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case 91193_09 i d , drain c u rrent (a) t c , case temperat u re (c) 25 150 125 100 75 50 0.0 0.4 0.6 0. 8 1.0 0.2 p u lse w idth 1 s d u ty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f 91193_11 thermal response (z thjc ) t 1 , rectang u lar p u lse d u ration (s) 10 -5 10 -4 10 -3 10 -2 0.1 1 10 10 2 10 3 1 0.1 10 -2 10 2 10 0 - 0.5 0.2 0.1 0.05 0.01 single p u lse (thermal response) n otes: 1. d u ty factor, d = t 1 /t 2 2. peak t j = p dm x z thjc + t c 0.02 p dm t 1 t 2 IRFL210 2014-8-9 5 www.kersemi.com
fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit r g i as 0.01 t p d.u.t l v ds + - v dd 10 v v ary t p to o b tain re qu ired i as i as v ds v dd v ds t p 91193_12c 100 0 20 40 60 8 0 25 150 125 100 75 50 starting t j , j u nction temperat u re (c) e as , single p u lse energy (mj) 120 bottom to p i d 0.43 a 0.61 a 0.90 a v dd = 50 v q gs q gd q g v g charge v gs d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v c u rrent reg u lator c u rrent sampling resistors same type as d.u.t. + - IRFL210 2014-8-9 6 www.kersemi.com
fig. 14 - for n-channel p. w . period di/dt diode reco v ery d v /dt ripple 5 % body diode for w ard drop re-applied v oltage re v erse reco v ery c u rrent body diode for w ard c u rrent v gs = 10 v * v dd i sd dri v er gate dri v e d.u.t. i sd w a v eform d.u.t. v ds w a v eform ind u ctor c u rrent d = p. w . period + - + + + - - - * v gs = 5 v for logic le v el de v ices peak diode recovery dv/dt test circuit v dd ? d v /dt controlled b y r g ? dri v er same type as d.u.t. ? i sd controlled b y d u ty factor "d" ? d.u.t. - de v ice u nder test d.u.t circ u it layo u t considerations ? lo w stray ind u ctance ? gro u nd plane ? lo w leakage ind u ctance c u rrent transformer r g IRFL210 2014-8-9 7 www.kersemi.com
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