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toshiba original cmos 8-bit microcontroller tlcs-870/x series TMP88CU74FG semiconductor company
tmp88cu74 i 2008-03-06 document change notification ? ? the purpose of this notification is to inform customers about the launch of the pb-free version of the device. the introduction of a pb-f ree replacement affects the datash eet. please understand that this notification is intended as a temporary su bstitute for a revision of the datasheet. changes to the datasheet may include the following, though not all of them may apply to this particular device. ? 1. part number example: tmpxxxxxxf tmpxxxxxxfg all references to the previous part number were left unchanged in body text. the new part number is indicated on the prelims pages (cover page and this notification). ? 2. package code and package dimensions example: lqfp100-p-1414-0.50c lqfp100-p-1414-0.50f all references to the previous package code and package dimensions were left unchanged in body text. the new ones are indicated on the prelims pages. ? 3. addition of notes on lead solderability now that the device is pb-free, notes on lead solderability have been added. ? 4. restrictions on product use the previous (obsolete) provision might be left unchanged on page 1 of body text. a new replacement is included on the next page. ? 5. publication date of the datasheet the publication date at the lower right corner of the prelims pages applies to the new device.
tmp88cu74 ii 2008-03-06 1. part number 2. package code and dimensions previous part number (in body text) previous packa g e code (in body text) new part number new package code otp tmp88cu74f p-qfp80-1420-0.80b TMP88CU74FG qfp80-p-1420-0.80b tmp88pu74fg * : for the dimensions of the new package, see the attached package dimensions diagram. 3. addition of notes on lead solderability the following solderability test is conducted on the new device. lead solderability of pb-free devices (with the g suffix) te st te s t c o n d i t i o n s r e m a r k solderability (1) use of lead (pb) solder bath temperature = 230c dipping time = 5 seconds the number of times = once use of r-type flux (2) use of lead (pb)-free solder bath temperature = 245c dipping time = 5 seconds the number of times = once use of r-type flux leads with over 95% solder coverage till lead forming are acceptable. 4. restrictions on product use the following replaces the ?restrictions on product use? on page 1 of body text. 5. publication date of the datasheet the publication date of this datasheet is printed at the lower right corner of this notification. restrictions on product use 20070701-en ? the information contained herein is subject to change without notice. ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in his document shall be made at the customer?s own risk. ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. ? please contact your sales representative for product-by-product details in this document regarding rohs compatibility. please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. ? for a discussion of how the reliability of microcontrollers can be predicted, please refer to section 1.3 of the chapter entitled quality and reliability assurance/handling precautions.
tmp88cu74 iii 2008-03-06 (annex) package dimensions qfp80-p-1420-0.80b unit: mm ?

tmp88cu74 2003-02-17 88cu74-2 ? time base timer divider output function watchdog timer ? interrupt source/reset output (programmable) 8-bit serial interface: 1 channel ? with 8 bytes transm it/receive data buffer ? internal/external serial clock, and 4/8-bit mode serial bus interface ? 8-bit sio/i 2 c bus mode 8-bit successive approximate type ad converter with sample and hold ? analog inputs: 12 channels conversion time: 23 s at 8 mhz (high-speed conversion mode), 59 s at 12.5 mhz (low-speed conversion mode) vacuum fluorescent tube driver (automatic display) ? high breakdown voltage ports (max 40 v 37 bits) ? programmable grid scan output dual clock operation ? single/dual-clock mode (selection) five power saving operating modes ? stop mode: oscillation stops. battery/capacito r back-up. release by stop pin input. ? slow mode: low power consumption operation using low-frequency clock. ? idle1 mode: cpu stops, and peripherals operate using high-frequency clock. release by interrupts. ? idle2 mode: cpu stops, and peripherals operate using high-and low-frequency clock. release by interrupts. ? sleep mode: cpu stops, and peripherals operate using low-frequency clock. release by interrupts. wide operating voltage: 2.7 to 5.5 v at 32.8 khz, 4.5 to 5.5 v at 12.5 mhz/32.8 khz emulation pod: bm88cu74f0a 2007-10-19
tmp88cu74 2003-02-17 88cu74-3 pin assignments (top view) p-qfp80-1420-0.80b p32 )0 sck ( p86 (v22) p85 (v21) p84 (v20) p83 (v19) p82 (v18) p81 (v17) p80 (v16) p77 (v15) p76 (v14) p75 (v13) p74 (v12) p73 (v11) p72 (v10) p71 (v9) p70 (v8) p67 (v7) p66 (v6) p65 (v5) p64 (v4) p63 (v3) p62 (v2) p61 (v1) p87 (v23) p60 (v0) (v24) p90 ( v25 ) p91 (v26) p92 (v27) p93 ( v28 ) p94 (v29) p95 (v30) p96 ( v31 ) p97 (v32) pd0 (v33) pd1 (v34) pd2 (v35) pd3 (v36) pd4 vkk ( 1 sck ) p00 (si1) p01 (so1) p02 p03 p04 p05 p06 p07 vss xout xin reset (xtout) p22 (xtin) p21 test (stop/int5) p20 (int0) p10 (int1) p11 (tc2/ppg) p12 (dvo) p13 (pdo/pwm) p14 (tc1/int3) p15 (int2) p16 (int4/tc3) p17 (scl/si0) p30 (sda/so0) p31 vdd varef p53 (ain11) p52 ( ain10 ) p51 (ain9) p50 (ain8) p47 ( ain7 ) p46 (ain6) p45 (ain5) p44 ( ain4 ) p43 (ain3) p41 ( ain1 ) p42 (ain2) vass 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 38 37 36 35 34 33 32 31 30 29 28 27 26 25 40 39 p40 (ain0) 2007-10-19
tmp88cu74 2003-02-17 88cu74-4 block diagram p22 to p20 reset i/o pin test pin xin xout vft power supply power supply xtal connecting pins i/o port test reset vkk vdd vss p6 p7 p8 p9 pd vacuum fluorescent tube driver circuit address/data bus system controller stanby controller timing generator high frequ low frequ clock generator tlcs-870/x cpu core data memory (ram) program memory (rom) interrupt control circuit time base timer watchdog timer 16-bit timer/counters tc1 tc2 8-bit timer/counters tc3 tc4 serial bus interfaces sio1 i 2 c bus i/o por t analog reference voltage (analog inputs) i/o port varef vass p47 (ain7) to p40 (ain0) p17 to p10 p53 (ain11) to p50 (ain8) p07 to p00 p32 to p30 p97 to p90 pd4 to pd0 p77 to p70 p87 to p80 p67 to p60 p2 8 bit ad converter p4 p5 p1 p0 p3 2007-10-19
tmp88cu74 2003-02-17 88cu74-5 pin functions (1/2) pin name input/output function p07 to p03 i/o p02 (so1) i/o (output) sio1 serial data output p01 (si1) i/o (input) sio1 serial data input p00 ( 1 sck ) i/o (i/o) sio1 serial clock input/output p17 (int4/tc3) external interrupt 4 input or timer counter 3 input p16 (int2) external interrupt 2 input p15 (int3/tc1) i/o (input) external interrupt 3 input or timer counter 1 input p14 ( pdo / pwm ) i/o (output) pwm output or programmable divider output p13 ( dvo ) i/o (output) divider output p12 (tc2/ ppg ) i/o (i/o) timer counter input 2 or programmable pulse generator output p11 (int1) external interrupt input 1 p10 ( 0 int ) i/o (input) two 8-bit programmable input/output ports (tri-state). each bit of these ports can be individually configured as an input or an output under software control. during reset, all bits are configured as inputs. when used as a ppg output or a divider output, the output latch must be set to 1. external interrupt input 0 p22 (xtout) i/o (output) p21 (xtin) resonator connecting pins (32.8 khz). for inputting external clock, xtin is used and xtout is opened. p20 ( 5 int / stop ) i/o (input) 3-bit input/output port with latch. when used as an input port, a resonator connecting pin, an external interrupt input, or a stop mode release input, the output latch must be set to 1. external interrupt input 5 or stop mode release signal input p32 ( 0 sck ) i/o (input) sio0 clock input/output p31 (sda/so0) i/o (i/o/output) i 2 c bus data input/output or sio0 data output p30 (scl/si0) i/o (i/o/input) 3-bit programmable input/output port (tri-state/programmable open drain). each bit of the port can be individully configured as an input or an output under software control. when used as a serial interface output, the output latch must be set to 1. i 2 c bus clock input/output or sio0 data input p47 (ain7) to p40 (ain0) i/o (input) p53 (ain13) to p50 (ain8) i/o (input) 8/4-bit programmable input/output port (tri-state). each bit of the port can be individually configured as an input or output under software control. when used as an analog input set to input mode. ad converter analog inputs p67 (v7) to p60 (v0) p77 (v15) to p70 (v8) p87 (v23) to p80 (v16) p97 (v31) to p90 (v24) 8-bit high breakdown voltage output ports with the latch. when used as an vacuum fluorescent tube driver output, the output latch must be cleared to 0. pd4(v36) to pd0 (v32) i/o (output) 5-bit high breakdown voltage output ports with the latch. when used as an vacuum fluorescent tube driver output, the latch must be cleared to 0. vtf output 2007-10-19
tmp88cu74 2003-02-17 88cu74-6 pin functions (2/2) pin name input/output function xin, xout input/output resonator connecting pins for high-frequency clock. for inputting external clock, xin is used an xout is opened. reset input/output reset signal input or watchdog timer output/address-reset output/system clock reset output. test input test pin for out-going teset. be tied to low. vdd, vss +5 v, 0 v (gnd) vkk vacuum fluore scent tube driver voltage pin. varef, vass power supply analog reference voltage input (high, low) 2007-10-19
tmp88cu74 2003-02-17 88cu74-7 operational description 1. cpu core functions the cpu core consists of a cpu, a system clock controller, an interrupt controller, and a watchdog timer. this section provides a description of the cpu core, the program memory (rom), the data memory (ram), and the reset circuit. 1.1 memory address map tlcs-870/x series, the memory is organized 4 address spaces (rom, ram, sfr, and dbr). figure 1.1.1 shows the memory address maps of the tmp88cu74. it uses a memory mapped i/o system, and all i/o registers are ma pped in the sfr/dbr address spaces. there are 16 banks of general-purpose registers. figure 1.1.1 memory address maps 1.2 program memory (rom) the tmp88cu74 has a 96 kbytes (addresses 04000h to 1bfffh) and 256 bytes (addresses fff00h to fffffh) of program memory (mask programmed rom). figure 1.1.1 shown in memory address maps. addresses fff00h to fffffh in the progra m memory can also be used for spec ial purposes. 64 bytes 00000h 0003f 1920 bytes sfr ram 128 bytes 00040 000bf 000c0 0083f register banks (8 registers 16 banks) rom: read only memory includes: program memory vector table ram: random access memory includes: data memory stack general-purpose register banks sfr: special function register includes: i/o ports peripheral control registers peripheral status registers system control registers interrupt control registers program status word dbr: data buffer register includes: sio data buffer vft display data buffer 128 bytes 00f80 00fff 04000 1bfff 98304 bytes 64 bytes 64 bytes 64 bytes 64 bytes fff00 fff3f fff40 fff7f fff80 fffbf fffc0 fffff dbr rom tmp88cu74 vector table for interrupts/ reset (16 vectors) vector table for vector call instructions (16 vectors) 2007-10-19
tmp88cu74 2003-02-17 88cu74-8 1.3 data memory (ram) the tmp88cu74 has 2 kbytes of static ram (address 00040h to 0083fh). the first 128 bytes (00040h to 000bfh) of the internal ram are also used as general-purpose register banks. the data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. example: clears ram to 00h except the bank 0. ld hl, 00048h ; sets start address to hl register pair ld a, h ; sets initial data (00h) to a register ld bc, 03f7h ; sets number of byte to bc register pair sramclr: ld (hl + ), a dec bc jrs f, sramclr note: the general-purpose registers are mapped in the ram; therefore, do not clear ram at the current bank addresses. 1.4 system clock controller the system clock controller consists of a clock generator, a timing generator, and a stand-by controller. figure 1.4.1 system clock controller 1.4.1 clock generator the clock generator generates the basic clock which provides the system clocks supplied to the cpu core and peripheral hardware. it contains two oscillation circuits: one for the high-frequency clock and one for the low-frequency clock. power consumption can be reduced by switching of the system clock controller to low-power operation based on the low-frequency clock. the high-frequency (fc) and low-frequency (fs) clocks can easily be obtained by connecting a resonator between the xin/xout and xtin/xtout pins, respectively. clock input from an external oscillator is also possible. in this case, external clock is applied to xin/xtin pin with xout/xtout pin not connected. the tmp88cu74 are not provided an rc oscillation. timing generator control register clock generator high-frequency clock oscillator low-frequency clock oscillator timing generator stand-by controller system clocks clock generator control system control registers xin xout xtin xtout tbtcr 00036h fc fs 00038h 00039h syscr1 syscr2 2007-10-19
tmp88cu74 2003-02-17 88cu74-9 figure 1.4.2 examples of resonator connection note: accurate adjustment of the oscillation frequency although no hardware to externally and directly monitor the basic clock pulse is not provided, the oscillation frequency can be adjusted by making the program to output fixed frequency pulse to the port with disabling all interrupts and watchdog timers, and monitoring this pulse. with a system requiring adjustment of the oscillation frequency, the adjusting program must be created beforehand. 1.4.2 timing generator the timing generator generates the various system clocks supplied to the cpu core and peripheral hardware from the basic clock (fc or fs). the timing generator provides the following functions. 1. generation of main system clock (fm) 2. generation of divider output ( dvo ) pulses 3. generation of source clocks for time base timer 4. generation of source clocks for watchdog timer 5. generation of internal source clocks for timer/counters tc1-tc6 6. generation of internal clocks for serial interfaces sio and hso 7. generation of source clocks for vft driver circuit 8. generation of warm-up clocks for releasing stop mode 9 generation of a clock for releasing reset output (1) configuration of timing generator the timing generator consists of a 3-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. the clock fc/4 or fc/8, that is output from the 2nd stage or the 3rd stage of the prescaler, can be selected as the clock to input to the 1st stage of the divider by dv1ck (bit 5 in cgcr). inputting fc/8 to the 1st stage of the divider operates the peripheral circuit without the setting change when the operation clock is multiplied by 2. (example: 8 mhz to 12.5 mhz) the dv1ck should be set the peripheral circuit prior to starting the peripheral circuits. do not change the set value after setting. an input clock to the 7th stage of the divider depends on the operating mode, dv1ck (bit 5 in dvcr), and dv7ck(bit 4 in tbtcr), that is shown in table 1.4.1. as reset and stop mode started/canceled, the prescale r and the divider are cleared to 0. (a) crystal/ceramic resonator (b) external oscillator (c) crystal (d) external oscillator high-frequency clock low-frequency clock xin xout xin xout (open) xtin xtout xtin xtout (open) 2007-10-19
tmp88cu74 2003-02-17 88cu74-10 table 1.4.1 input clock to 7th stage of the divider single-clock mode ? dual-clock mode ? normal1, idle1 mode normal2, idle2 mode (sysck = 0) dv7ck = 0 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 dv7ck = 1 slow, sleep mode (sysck = 1) fc/2 8 fc/2 9 fc/2 8 fc/2 9 fs fs note 1: do not set dv7ck to 1 in the single clock mode. note 2: in slow and sleep mode, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. figure 1.4.3 configuration of timing generator low-frequency clock fs high-frequency clock 0 1 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 main system clock generator machine cycle counters fm sysck dv7ck dv1ck prescaler divider divider selector selector s a y b s a y b timer/counters serial interface vacuum fluorescent tube driver circuit s b0 b1 a0 y0 a1 y1 selector stand-by controller watchdog timer time base timer divider output note: fm = fc or fs fc fc 2007-10-19
tmp88cu74 2003-02-17 88cu74-11 7 6 5 4 3 2 1 0 dvcr (00030h) 0 0 dv1ck (initial value: **0 * ****) dv1ck selection of input clock to the 1st stage of the divider 0: fc/4 1: fc/8 r/w note 1: fc: high-frequency clock [hz], * : don't care note 2: bit 4 to 0 in cgcr is always read in as 1 when a read instruction is executed. figure 1.4.4 clock gear control register 7 6 5 4 3 2 1 0 tbtcr (00036h) (dvoen) (dvock) dv7ck (tbten) (tbtck) (initial value: 0 **0 0*** ) dv7ck selection of input clock to the 7 th stage of the divide 0: fc/2 8 or fc/2 9 [hz] 1: fs r/w note 1: fc: high-frequency clock [hz], * : don't care note 2: do not set dv7ck to 1 in the single clock mode. note 3: do not set dv7ck to 1 before low-frequency clock is stable in the dual-clock mode. figure 1.4.5 timing generator control register (2) machine cycle instruction execution and peripheral hardware operation are synchronized with the main system clock. the minimum inst ruction execution unit is called an machine cycle. there are a total of 15 different types of instructions for the tlcs-870/x series: ranging from 1-cycle instructions which require one machine cycle for execution to 15-cycle instructions which require 15 machine cycles for execution. a machine cycle consists of 4 states (s0 to s3), and each state consists of one main system clock. figure 1.4.6 machine cycle 1.4.3 stand-by controller the stand-by controller starts and stops the oscillation circuits for the high-frequency and low-frequency clocks, and switches the main system clock. there are two operating modes: single-clock and dual-clock. these modes are controlled by the system control registers (syscr1and syscr2). figure 1.4.7 shows the operating mode transition diagram and figure 1.4.8 shows the system control registers. (1) single-clock mode only the oscillation circuit for the high-frequency clock is used, and p21 (xtin) and p22 (xtout) pins are used as input/output ports. in the single-clock mode, the machine cycle time is 4/fc [s] (0.32 s at fc = 12.5 mhz). main system clock (fm) state 0.32 s at fc = 12.5 mhz 122 s at fs = 32.8 khz s0 1/fc or 1/fs [s] s1 s2 s3 s0 s1 s2 s3 machine cycle 2007-10-19
tmp88cu74 2003-02-17 88cu74-12 1. normal1 mode in this mode, both the cpu core and on-chip peripherals operate using the high-frequency clock. the tmp88cu74 is placed in this mode after reset. 2. idle1 mode in this mode, the internal oscillation circuit remains active. the cpu and the watchdog timer are halted; however on-chip peripherals remain active (operate using the high-frequency clock). idle1 mode is started by the system control register 2 (syscr2), and idle1 mode is released to normal1 mode by an interrupt request from the on-chip peripherals or external interrupt inputs. when the imf (interrupt master enable flag) is 1 (interrupt enable), the execution will resume with the acceptance of the interrupt, and the operation will return to normal after the interrupt service is comp leted. when the imf is 0 (interrupt disable), the execution will resume with the instruction which follows the idle1 mode start instruction. 3. stop1 mode in this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. the internal status immediately prior to the halt is held with a lowest power consumption during stop1 mode. stop1 mode is started by the system control register 1 (syscr1), and stop1 mode is released by an inputting (either level-sensitive or edge-sensitive can be programmably selected) to the stop pin. after the warming-up period is completed, the execution resumes with the instruction which follows the stop1 mode start instruction. (2) dual-clock mode both the high-frequency and lo w-frequency oscillation circuits are used in this mode. p21 (xtin) and p22 (xtout) pins cannot be used as input/output ports. the main system clock is obtained from the high-frequency clock in normal2 and idle2 modes, and is obtained from the low-frequency clock in slow and sleep modes. the machine cycle time is 4/fc [s] in the no rmal2 and idle2 modes, and 4/fs [s] (122 s at fs = 32.8 khz) in the slow and sleep modes. the tlcs-870/x is placed in the sign al-clock mode during reset. to use the dual-clock mode, the low-frequency oscillator should be turned on by executing [set (syscr2), xten] instruction. 1. normal2 mode in this mode, the cpu core operates using the high-frequency clock. on-chip peripherals operate using the high-frequency clock and/or low-frequency clock. 2. slow mode this mode can be used to reduce power-consumption by turning off oscillation of the high-frequency clock. the cpu core and on-chip peripherals operate using the low-frequency clock. switching back and fo rth between normal2 and slow modes are performed by the system control register 2 (syscr2). 3. idle2 mode in this mode, the internal oscillation circuit remain active. the cpu and the watchdog timer are halted; however, on-chip peripherals remain active (operate using the high-frequency clock and/or the low-frequency clock). starting and releasing of idle2 mode are the same as for idle1 mode, except that operation returns to normal2 mode. 2007-10-19
tmp88cu74 2003-02-17 88cu74-13 4. sleep mode in this mode, the internal oscillation circuit of the low-frequency clock remains active. the cpu, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (operate using the low-frequency clock). starting and releasing of sleep mode are the same as for idle1 mode, except that operation returns to slow mode. 5. stop2 mode as in stop1 mode, all system operations are halted in this mode. as in normal2 mode at the start, the operating mode returns to normal2 mode, and as in slow mode at the start, it returns to slow mode after release. (a) single-clock mode (b) dual-clock mode note: normal1 and normal2 modes are generically called normal; stop1 and stop2 are called stop; and idle1, idle2 and sleep are called idle. frequency operating mode high- frequency low- frequency cpu core on-chip peripherals machine cycle time reset1 reset reset normal1 operate idle1 turning on oscillation operate 4/fc [s] single-clock stop1 turning off oscillation turning off oscillation halt halt ? normal2 high-frequency idle2 turning on oscillation halt operate (high and/or low) 4/fc [s] slow low-frequency sleep turning on oscillation low-frequency 4/fs [s] dual-clock stop2 turning off oscillation turning off oscillation halt halt ? figure 1.4.7 operating mode transition diagram reset normal1 mode normal2 mode slow mode idle1 mode idle2 mode sleep mode stop1 mode stop2 mode instruction instruction instruction instruction instruc- tion release input interrupt release input reset release instruction instruction interrupt instruction interrupt 2007-10-19
tmp88cu74 2003-02-17 88cu74-14 system control register 1 7 6 5 4 3 2 1 0 syscr1 (00038h) stop relm retm 1 wut (initial value: 0000 00 **) stop stop mode start 0: cpu core and peripherals remain active 1: cpu core and peripherals are halted (start stop mode) relm release method for stop mode 0: edge-sensitive release 1: level-sensitive release retm operating mode after stop mode 0: return to normal mode 1: return to slow mode return to normal mode dv1ck = 0 dv1ck = 1 return to slow mode 00 3 2 16 /fc 3 2 17 /fc 3 2 13 /fc 01 2 16 /fc 2 17 /fc 2 13 /fc 10 3 2 14 /fc 3 2 15 /fc ? wut warming-up time at releasing stop mode 11 2 14 /fc 2 15 /fc ? r/w note 1: always set retm to 0 when transiting from normal mode to stop mode. always set retm to 1 when transiting from slow mode to stop mode. note 2: when stop mode is released with reset pin input, a return is made to normal mode regardless of the retm contents. note 3: fc: high-frequency clock [hz] fs: low-frequency clock [hz] * : dont care note 4: bits 1 and 0 in syscr1 are read in as undefined data when a read instruction is executed. note 5: always set bit 4 in syscr1 to 1 when stop mode is started. system control register 2 7 6 5 4 3 2 1 0 syscr2 (00039h) xen xten sysck idle (initial value: 1000 ****) xen high-frequency oscillator control 0: turn off oscillation 1: turn on oscillation xten low-frequency oscillator control 0: turn off oscillation 1: turn on oscillation sysck main system clock select (write)/main system clock monitor (read) 0: high-frequency clock 1: low-frequency clock idle idle mode start 0: cpu and watchdog timer remain active 1: cpu and watchdog timer are stopped (start idle1 mode) r/w note 1: xen and sysck are automatically overwritten in accordance with the contents of retm (bit 5 in syscr1) when stop mode is released. retm operating mode after stop mode xten sysck 0 1 normal 1/2 mode slow mode 1 0 0 1 note 2: do not clear xen to 0 when sysck = 0, and do not clear xten to 0 when sysck = 1. note 3: a reset is applied ( reset pin output goes low) if both xen and xten are cleared to 0. note 4: * : dont care note 5: bits 3 to 0 in syscr2 are always read in as 1 when a read instruction is executed. figure 1.4.8 system control registers 2007-10-19
tmp88cu74 2003-02-17 88cu74-15 1.4.4 operating mode control (1) stop mode (stop1, stop2) stop mode is controlled by the system control register 1 (syscr1) and the stop pin input. the stop pin is also used both as a port p20 and an int5 (external interrupt input 5) pin. stop mode is started by setting stop (bit 7 in syscr1) to 1. during stop mode, the following status is maintained. 1. oscillations are turned off, and all internal operations are halted. 2. the data memory, registers, the program status word and port output latches are all held in the status in effect before stop mode was entered. 3. the prescaler and the divider of the timing generator are cleared to 0. 4. the program counter holds the address of the instruction but one to the instruction (e.g.[set (syscr1).7]) which started stop mode. stop mode includes a level-sensitive release mode and an edge-sensitive release mode, either of which can be selected with the relm (bit 6 in syscr1). a. level-sensitive release mode (relm = 1) in this mode, stop mode is released by setting the stop pin high. this mode is used for capacitor back-up when the main power supply is cut off and long term battery back-up. when the stop pin input is high, executing an instruction which starts stop mode will not place in stop mode but instead will immediately start the release sequence (warm-up). t hus, to start stop mode in th e level-sensitive release mode, it is necessary for the program to first confirm that the stop pin input is low. the following two methods can be used for confirmation. 1. testing a port p20. 2. using an external interrupt input int5 ( int5 is a falling edge-sensitive input). example 1: starting stop mode from normal mode by testing a port p20. ld (syscr1), 01010000b ; sets up the level-sensitive release mode sstoph: test (p2). 0 ; wait until the stop pin input goes low level jrs f, sstoph set (syscr1). 7 ; starts stop mode example 2: starting stop mode from normal mode with an int5 interrupt. pint5: test (p2). 0 ; to reject noise, stop mode does not start if port p20 is at high jrs f, sint5 ld (syscr1), 01010000b ; sets up the level-sensitive release mode. set (syscr1). 7 ; starts stop mode sint5: reti 2007-10-19
tmp88cu74 2003-02-17 88cu74-16 figure 1.4.9 level-sensitive release mode note 1: even if the stop pin input is low after warming up start, the stop mode is not restarted. note 2: in this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the stop pin input is detected. b. edge-sensitive release mode (relm = 0) in this mode, stop mode is released by a rising edge of the stop pin input. this is used in applications where a relatively short program is executed repeatedly at periodic intervals. this periodic signal (for example, a clock from a low-power consumption oscillator) is input to the stop pin. in the edge-sensitive release mode, stop mode is started even when the stop pin input is high level. example: starting stop mode from normal mode ld (syscr1), 10010000b ; starts after specified to the edge-sensitive release mode figure 1.4.10 edge-sensitive release mode stop mode is released by the following sequence. 1. in the dual-clock mode , when returning to normal2, both th e high-frequency and low-frequency clock oscillators are turned on; when returning to slow mode, only the low-frequency clock oscillator is turned on. in the signal-clock mode, only the high-frequency clock oscillator is turned on. 2. a warming-up period is inserted to allow oscillation time to stabilize. during warm-up, all internal operations remain halted. four different warming-up times can be selected with the wut (bits 2 and 3 in syscr1) in accordance with the resonator characteristics. stop pin xout pin normal operation confirm by program that the stop pin input is low and start stop mode. v ih stop mode is released by the hardware. always released if the stop pin input is high. normal operation stop operation warm-up stop pin normal operation stop mode started by the program. xout pin stop mode is released by the hardware at the rising edge of stop pin input. v ih warm-up normal operation stop operation stop operation 2007-10-19
tmp88cu74 2003-02-17 88cu74-17 3. when the warming-up time has elapsed, normal operation resumes with the instruction following the stop mode start instruction (e.g. [set (syscr1). 7]). the start is made after the prescaler an d the divider of the timing generator are cleared to 0. table 1.4.2 warming-up time example (at fc = 12.5 mhz, fs = 32.8 khz) warming-up time [ms] return to normal mode wut dv1ck = 0 dv1ck = 1 return to slow mode 00 01 10 11 15.729 5.243 3.932 1.311 31.457 10.486 7.864 2.621 750 250 ? ? note: the warming-up time is obtained by dividing the basic clock by the divider: therefore, the warming-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when stop mode is released. thus, the warming-up time must be considered an approximate value. stop mode can also be released by inputting low level on the reset pin, which immediately performs the normal reset operation. note: when stop mode is released with a low hold voltage, the following cautions must be observed. the power supply voltage must be at the operating voltage level before releasing stop mode. the reset pin input must also be h level, rising together with the power supply voltage. in this case, if an external time constant circuit has been connected, the reset pin input voltage will increase at a slower pace than the power supply voltage. at this time, there is a danger that a reset may occur if input voltage level of the reset pin drops below the non-inverting high-level input voltage (hysteresis input). 2007-10-19
tmp88cu74 2003-02-17 88cu74-18 figure 1.4.11 stop mode start/release instruction at address a + 4 a + 6 3 instruction at address a + 3 2 a + 5 instruction at address a + 2 1 a + 4 (b) stop mode release count up 0 a + 3 turn on stop pin input halt 0 turn off a + 2 n turn on (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) warming up n + 1 set (syscr1). 7 n + 2 a + 3 n + 3 0 n + 4 turn off halt oscillator circuit main system clock program counter instruction execution divider oscillator circuit main system clock program counter instruction execution divider 2007-10-19
tmp88cu74 2003-02-17 88cu74-19 (2) idle mode (idle1, idle2, sleep) idle mode is controlled by the system control register 2 (syscr2) and maskable interrupts. the following status is maintained during idle mode. 1. operation of the cpu and watchdog timer (wdt) is halted. on-chip peripherals continue to operate. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before idle mode was entered. 3. the program counter holds the address of the second instruction after the instruction which starts idle mode. example: starting idle mode. set (syscr2). 4 ; idle 1 figure 1.4.12 idle mode idle mode includes a normal release mode and an interrupt release mode. selection is made with the interrupt master enable flag (imf). releasing idle mode returns from idle1 to normal1, from idle2 to normal2, and from sleep to slow mode. interrupt request imf = 1 interrupt processing execution of the instruction which follows the idle mode start instruction (normal release mode) no no reset (interrupt release mode) yes yes no yes starting idle mode by instruction cpu, wdt are halted reset input 2007-10-19
tmp88cu74 2003-02-17 88cu74-20 (i) normal release mode (imf = 0) idle mode is released by any interrupt source enabled by the individual interrupt enable flag (ef) or an external interrupt 0 ( int0 pin) request. execution resumes with the instruction following the idle mode start instruction (e.g. [set (syscr2), 4]. the interrupt latches (il) of the interrupt source used for releasing must be cleared to 0 by load instructions. (ii) interrupt release mode (imf = 1) idle mode is released and interrupt processing is started by any interrupt source enabled with the indi vidual interrupt enable flag (ef) or an external interrupt 0 ( int0 pin) request. after the interrupt is processed, the execution resumes from the instruction following the instruction which starts idle mode. idle mode can also be released by inputting low level on the reset pin, which immediately performs the reset operation. after reset, the tmp88cu74 is placed in normal 1 mode. note: when a watchdog timer interrupt is generated immediately before idle mode is started, the watchdog timer interrupt will be processed but idle mode will not be started. 2007-10-19
tmp88cu74 2003-02-17 88cu74-21 figure 1.4.13 idle mode start/release acceptance of interrupt operate (b) idle mode release operate (i) normal release mode a + 3 halt halt halt halt a + 4 instruction at address a + 2 a + 3 set (syscr2).4 (a) idle mode start (example: starting with the set instruction located at address a) main system clock a + 2 operate a + 3 halt interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer (ii) interrupt release mode 2007-10-19
tmp88cu74 2003-02-17 88cu74-22 (3) slow mode slow mode is controlled by the system control register 2 (syscr2) and the timer/counter 2 (tc2). a. switching from normal2 mode to slow mode first, set sysck (bit 5 in syscr2) to switch the main system clock to the low-frequency clock. next, clear xen (bit 7 in syscr2) to turn off high-frequency oscillation. note: the high frequency clock can be continued oscillation in order to return to normal2 mode from slow mode quickly. always turn off oscillation of high frequency clock when switching from slow mode to stop mode. when the low-frequency clock oscillation is unstable, wait until oscillation stabilizes before performing the above operations. the timer/counter 2 (tc2) can conveniently be used to confirm that low-frequency clock oscillation has stabilized. example 1: switching from normal2 mode to slow mode. set (syscr2). 5 ; sysck 1 (switches the main system clock to the low-frequency clock) clr (syscr2). 7 xen 0 (turns off high-frequency oscillation) example 2: switching to the slow mode after low-frequency clock oscillation has stabilized. ld (tc2cr), 14h ; sets tc2 mode (timer mode, source clock: fs) ldw (treg2), 8000h ; sets warming-up time (according to xtal characteristics) set (eirh). ef14 ; enables inttc2 ld (tc2cr), 34h ; starts tc2 pinttc2: ld (tc2cr), 10h ; stops tc2 set (syscr2). 5 ; sysck 1 (switches the main system clock to the low-frequency clock) clr (syscr2). 7 ; xen 0 (turns off high-frequency oscillation) reti vinttc2: dl pinttc2 ; inttc2 vector table 2007-10-19
tmp88cu74 2003-02-17 88cu74-23 b. switching from slow mode to normal2 mode first, set xen (bit 7 in syscr2) to turn on the high-frequency oscillation. when time for stabilization (warm-up) h as been taken by th e timer/counter 2 (tc2), clear sysck (bit 5 in syscr2) to switch the main system clock to the high-frequency clock. note 1: after sysck is cleared to "0", executing the instructions is continued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. note 2: slow mode can also be released by inputting low level on the reset pin, which immediately performs the reset operation. after reset, the tmp88cu74 is placed in normal1 mode. example: switching from slow mode to normal2 mode (fc = 12.5 mhz, warming-up time is 5.8 ms). set (syscr2). 7 ; xen 1 (turns on high-frequency oscillation) ld (tc2cr), 10h ; sets tc2 mode (timer mode, source clock: fc) ld (treg2 + 1), 0f8h ; sets the warming-up time (according to frequency and xtal characteristics) set (eirh). ef14 ; enables inttc2 ld (tc2cr), 30h ; starts tc2 pinttc2: ld (tc2cr), 10h ; stops tc2 clr (syscr2). 5 ; sysck 0 (switches the main system clock to the high-frequency clock) reti vinttc2: dl pinttc2 ; inttc2 vector table high-frequency clock low-frequency clcok main system clock sysck 2007-10-19
tmp88cu74 2003-02-17 88cu74-24 figure 1.4.14 switching between the normal2 and slow modes high-frequency clock (a) switching to the slow mode mode switching clr (syscr2).7 set (syscr2).5 normal2 mode set (syscr2).7 (b) switching to the normal2 mode clr (syscr2).5 warming up normal2 mode slow mode slow mode turn off low-frequency clock main system clock sysck xen instruction execution high-frequency clock low-frequency clock main system clock sysck xen instruction execution 2007-10-19
tmp88cu74 2003-02-17 88cu74-25 1.5 interrupt controller the tmp88cu74 each have a total of 15 interrupt sources: 6 externals and 9 internals. nested interrupt control with priorities is also possible. two of the internal sources are pseudo non-maskable interrupts; the remainder are all maskable interrupts. interrupt latches (il) that hold the interrupt requests are provided for interrupt sources. each interrupt vector is independent. the interrupt latch is set to 1 when an inte rrupt request is generated and requests the cpu to accept the interrupt. the acceptance of maskable interrupts can be selectively enabled and disabled by the program using the interrupt master enable flag (imf) and the individual interrupt enable flags (ef). when two or more interrupts are generated simultaneously, the interrupt is accepted in the highest priority order as determined by the hardware. figure 1.5.1 shows the interrupt controller. table 1.5.1 interrupt sources interrupt source enable condition interrupt latch vector address priority internal/ external (reset) non-maskable ? ffffch high 0 internal intsw (software interrupt) ? ffff8h 1 internal intwdt (watchdog timer interrupt) pseudo non-maskable il2 ffff4h 2 external int0 (external interrupt 0) imf = 1, int0en = 1 il3 ffff0h 3 internal inttc1 (16-bit tc1 interrupt) imf k ef4 = 1 il4 fffech 4 external int1 (external interrupt 2) imf k ef5 = 1 il5 fffe8h 5 internal inttbt (time base timer interrupt) imf k ef6 = 1 il6 fffe4h 6 external int2 (external interrupt 2) imf k ef7 = 1 il7 fffe0h 7 internal inttc3 (8-bit tc3 interrupt) imf k ef8 = 1 il8 fffdch 8 internal intsio1 (serial interface1 interrupt) imf k ef9 = 1 il9 fffd8h 9 internal inttc4 (8-bit tc4 interrupt) imf k ef10 = 1 il10 fffd4h 10 external int3 (external interrupt 3) imf k ef11 = 1 il11 fffd0h 11 internal intkey (key scan interrupt) imf k ef12 = 1 il12 fffcch 12 internal intsio2 (serial interface2 interrupt) imf k ef13 = 1 il13 fffc8h 13 internal inttc2 (16-bit tc2 interrupt) imf k ef14 = 1 il14 fffc4h 14 external int5 (external interrupt 5) imf k ef15 = 1 il15 fffc0h low 15 note: before you change each enable flag (ef) and/or each interrupt latch (il), be sure to clear the interrupt master enable flag (imf) to 0 (to disable interrupts). a. after a di instruction is executed b. when an interrupt is accepted, imf is automatically cleared to 0. however, to enable nested interrupts, change ef and/or il before setting imf to 1 (to enable interrupts). if the individual enable flags (ef) and interrupt latches (il) are set under conditions other than the above, the proper operation cannot be guaranteed. 2007-10-19
tmp88cu74 2003-02-17 88cu74-26 (1) interrupt latches (il15 to 2) interrupt latches are provided for each source, except for a software interrupt. the latch is set to 1 when an interrupt request is generated, and requests the cpu to accept the interrupt. the latch is cleared to 0 just after the interrupt is accepted. all interrupt latches are initialized to 0 during reset. interrupt latches are assigned to addre sses 003ch and 003dh in the sfr. each latch can be cleared to 0 individu ally by an instruction; h owever, the read-modify-write instruction such as bit manipulation or operation instructions cannot be used. thus, interrupt requests can be canceled and initialized by the program. note that interrupt latches cannot be set to 1 by any instruction. the contents of interrupt latches can be read out by an instruction. therefore, testing interrupt requests by software is possible. example 1: clears interrupt latches ldw (ill), 1110100000111111b ; il12, il10 to il6 0 example 2: reads interrupt latches ld wa, (ill) ; w ilh, a ill example 3: tests an interrupt latch test (il).7 ; if il7 = 1 then jump jr f, sset 2007-10-19
tmp88cu74 2003-02-17 88cu74-27 figure 1.5.1 interrupt controller block diagram edge selection, digital noise reject circuit int5 inttc2 intsio1 int4 int3 inttc4 intsbi inttc3 int2 inttbt int1 inttc1 int0 intwdt intsw eintcr 2 int4es int3es int2es int1nc, int1es int0en external interrupts control register il15 to 3 write data write strobe for il internal reset ef15 to ef4 interrupt enable register instruction which clears imf to 0 [di] instruction priority encoder & vector table address generator non-maskable interrupts maskable interrupts request interrupt request vector table address release idle mode request interrupt acceptance interrupt master enable flag imf q s r il15 q s r il14 q s r il13 q s r il12 q s r il11 q s r il10 q s r il9 q s r il8 q s r il7 q s r il6 q s r il5 q s r il4 q s r il3 q s r il2 q s r interrupt latches [reti] instruction during maskble interrupt service [reti] instruction only when imf was set before interrupt was accepted. [ei] instruction instruction which sets imf to 1 edge selection, digital noise reject circuit edge selection, digital noise reject circuit edge selection, digital noise reject circuit 2007-10-19
tmp88cu74 2003-02-17 88cu74-28 (2) interrupt enable register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except for the pseudo non-maskable interrupts (software and watc hdog timer interrupts). pseudo non-maskable interrupts are accepted regardless of the contents of the eir; however, the pseudo non-maskable interrupts cannot be nested more than once at the same time. for example, the watchdog timer inte rrupt is not accepted during the software interrupt service. the eir consists of an interrupt master enable flag (imf) and the individual interrupt enable flags (ef). this register is assigned to addresses 0003ah and 0003bh in the sfr, and can be read and written by an instructi on (including read-modify-write instructions such as bit manipulation instructions). 1. interrupt master enable flag (imf) the interrupt master enable flag (imf) enables and disables the acceptance of all interrupts, except for pseudo non-maskable interrupts. clearing this flag to 0 disables the acceptance of all maskable interrupts. setting to 1 enables the acceptance of interrupts. when an interrupt is accepted, this flag is cleared to 0 to temporarily disable the acceptance of maskable interrupts. after execution of the interrupt service program, this flag is set to 1 by the maskable interrupt return instruction [reti] to again enable the acceptance of interrupts. if an interrupt request has already been occurred, interrupt service starts immediately after execution of the [reti] instruction. pseudo non-maskable interrupts are returned by the [retn] instruction. in this case, the imf is set to 1 only when pseudo non-maskable interrupt service is started with interrupt acceptance enabled (imf = 1). note that the imf remains 0 when cleared by the interrupt service program. the imf is assigned to bit 0 at address 0003ah in the sfr, and can be read and written by an instruction. the imf is normally set and cleared by the [ei] and [di] instructions, and the imf is in itialized to 0 during reset. 2. individual interrupt enable flags (ef15 to ef4) these flags enable and disable the acceptance of individual maskable interrupts, except for an external interrupt 0. setting the corresponding bit of an individual interrupt enable flag to 1 enables acceptan ce of an interrupt, setting the bit to 0 disables acceptance. example 1: sets ef for individual interrupt enable, and sets imf to 1. ldw (eirl), 1110100010100001b ; ef15 to ef13, ef11, ef7, ef5, imf 1 example 2: sets an individual interrupt enable flag to 1. set (eirh).4 ; ef12 1 2007-10-19
tmp88cu74 2003-02-17 88cu74-29 ? 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 il (0003c, 0003dh) il15 il14 il13 il12 il11 il10 il9 il8 il7 il6 il5 il4 il3 il2 (initial value: 00000000 000000 **) ef15 ef14 ef13 ef12 ef11 ef10 ef9 ef8 ef7 ef6 ef5 ef4 imf eir (0003a, 0003bh) (initial value: 00000000 0000 *** 0) note 1: do not use any read-modify-write instruction such as bit manipulation for clearing il. note 2: do not set imf to 1 during non-maskable interrupt service program. note 3: bits1 and 0 in ill are read in as undefined data when a read instruction is executed. note 4: * : don t care figure 1.5.2 interrupt latch (il) and interrupt enable register (eir) 1.5.1 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to 0 by a reset or an instruction. interrupt acceptance sequence requires 12 machine cycles (3.84 s at fc = 12.5 mhz in the normal mode) after the completion of the current instruction execution. the interrupt service task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for pseudo non-maskable interrupts). figure 1.5.3 shows the timing chart of interrupt acceptance processing. (1) interrupt acceptance interrupt acceptance processing is as follows. 1. the interrupt master enable flag (imf) is cleared to 0 to te mporarily disable the acceptance of any following maskable in terrupts. when a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. the interrupt latch (il) for the interrupt source accepted is cleared to 0. 3. the contents of the program counter (return address) and the program status word (psw) are saved (pushed) on the stack in sequence of pswh, pswl, pce, pch, pcl. the stack pointer (sp) is decremented five times. 4. the entry address of the interrupt service program is read from the vector table, and set to the program counter. 5. the rbs control code is read from the ve ctor table. the lower 4-bit of this code is added to the rbs. 6. the instruction stored at the entry address of the interrupt service program is executed. ilh (0003dh) ill (0003ch) eirl (0003ah) eirh (0003bh) 2007-10-19
tmp88cu74 2003-02-17 88cu74-30 note 1: a: return address, b: entry address, c: address which the reti instruction is stored note 2: the maximum response time from when an il is set until an interrupt acceptance processing starts is 62/fc [s] or 62/fs [s] with interrupt enabled. figure 1.5.3 timing chart of interrupt acceptance and interrupt return instruction imf execution address bus pc sp rbs (b) return from interrupt instruction c c + 1 n ? 4 n ? 3 n ? 2 n ? 1 n a a + 1 a + 2 a c + 2 c + 1 c n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n i k reti instruction a + 1 i n n ? 1n ? 2n ? 3n ? 4n ? 5 k = i + (fffe7). 3 ? 0 a a + 1 a b b + 2 b + 1b + 3 b + 2 b + 1 b n ? 4 n ? 3 n ? 2 n ? 1 n fffe4 a + 1 a instruction interrupt acceptance instruction (a) interrupt acceptance fffe5 fffe6 fffe7 imf execution address bus pc sp rbs il6 il15 inttbt int5 1-machine cycle interrupt service tas k 2007-10-19
tmp88cu74 2003-02-17 88cu74-31 example: correspondence between vector table address for in ttbt and the entry address of the interrupt service program. ? ? ? ? ? ? ? ? a maskable interrupt is not accepted until the imf is set to 1 even if the maskable interrupt higher than the level of current servicing interrupt is occurred. when nested interrupt service is necessary, the imf is set to 1 in the interrupt service program. in this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. however, an acceptance of external interrupt 0 cannot be disabled by the ef; therefore, if disable is necessary, either the external interrupt function of the int0 pin must be disabled with the int0en in the external interrupt control register (eintcr) (the interrupt latch il3 is not set at int0en = 0, therefore, the rising edge of int0 pin input can not be detected.) or an interrupt processing must be avoided by the program. example 1: disables an external interrupt 0 using the int0en ld (eintcr), 00000000b ; int0en 0 example 2: disables the processing of external interrupt 0 under the software control (using bit 0 at address 000f0h as the interrupt processing disable switch) pint0: test (000f0h). 0 ; return without interrupt processing if (000f0h) 0 = 1 jrs t, sint0 reti sint0: interrupt processing reti vint0: dl pint0 (2) saving/restoring general-purpose registers during interrupt acceptance processing, the program counter (pc) and the program status word (psw) are automatically saved on the stack, but not the accumulator and other registers. these registers are saved by the program if necessary. also, when nesting multiple interrupt services, it is necessary to avoid using the same data memory area for saving registers. vector table address entry address fffe4h fffe5h fffe6h fffe7h 43h d2h 0ch 06h cd243h cd244h cd245h cd246h vector rbs control interrupt service program 2007-10-19
tmp88cu74 2003-02-17 88cu74-32 the following method is used to save/restore the general-purpose registers. 1. general-purpose register save/restore by automatic register bank changeover the general-purpose registers can be saved at high-speed by switching to a register bank that is not in use. normally, the bank 0 is used for the main task and the banks 1 to 15 are assigned to interrupt service tasks. to increase the efficiency of data memory utilization, the same bank is assigned for interrupt sources which are not nested. the switched bank is automatically restored by executing an interrupt return instruction [reti] or [retn]. therefore, it is not necessary for a program to save the rbs. example: register bank changeover pintxx: interrupt processing reti vintxx: dp pintxx db 1 ; rbs rbs + 1 2. general-purpose register save/restore by register bank changeover the general-purpose registers can be saved at high-speed by switching to a register bank that is not in use. normally, the bank 0 is used for the main task and the banks 1 to 15 are assigned to interrupt service tasks. example: register bank changeover pintxx: ld rbs, n interrupt processing reti ; restores bank and returns vintxx: dp pintxx ; interrupt service routine entry address db 0 3. general-purpose registers save/restore using push and pop instructions to save only a specific register, and when the same interrupt source occurs more than once, the general-purpose registers can be saved/restored using the push/pop instructions. example: register save/restore using push and pop instructions pintxx: push wa ; save wa register pair interrupt processing pop wa ; restore wa register pair reti ; return 2007-10-19
tmp88cu74 2003-02-17 88cu74-33 address (example) sp 0023ah a 0023b sp w sp 0023c pcl pcl pcl 0023d pch pch pch 0023e pce pce pce 0023f pswl pswl pswl 00240 pswh pswh pswh sp 00241 at acceptance of an interrupt at execution of a push instruction at execution of a pop instruction 4. general-purpose registers save/restore using data transfer instructions data transfer instruction can be used to save only a specific general-purpose register during processing of single interrupt. example: saving/restoring a register using data transfer instructions pintxx: ld (gsava), a ; save a register interrupt processing ld a, (gsava) ; restore a register reti ; return ? ? ? ? ? ? ? ? ? ? ? figure 1.5.4 saving/restoring general-purpose registers at execution of an interrupt return instruction bank m bank n bank m bank m saving registers restoring registers interrupt service task acceptance of interrupt interrupt service task restore to bank m automatically by [reti]/[retn] interrupt return interrupt return switch to bank n by ld, rbs and n instruction switch to bank n automatically time main task main task (a) saving/restoring by register bank changeover (b) saving/restoring using push/pop or data transfer instructions acceptance of interrupt 2007-10-19
tmp88cu74 2003-02-17 88cu74-34 (3) interrupt return the interrupt return instructions [reti]/[retn] perform the following operations. [reti] maskable interrupt return [retn] non-maskable interrupt return 1. the contents of the program counter and the program status word are restored from the stack. 2. the stack pointer is incremented 5 times. 3. the interrupt master enable flag is set to 1. 4. the interrupt nesting counter is decremented, and the interrupt nesting flag is changed. 1. the contents of the program counter and program status word are restored from the stack. 2. the stack pointer is incremented 5 times. 3. the interrupt master enable flag is set to 1 only when a non-maskable interrupt is accepted in interrupt enable status. however, the interrupt master enable flag remains at 0 when so clear by an interrupt service program. 4. the interrupt nesting counter is decremented, and the interrupt nesting flag is changed. interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. note: when the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 1.5.2 software interrupt (intsw) executing the [swi] instruction generates a software interrupt and immediately starts interrupt processing (intsw is highest prioritized interrupt). however, if processing of a non-maskable interrupt is already underway, executing the swi instruction will not generate a software interrupt but will re sult in the same operation as the [nop] instruction. use the [swi] instruction only for detection of the address error or for debugging. note: to use the swi instruction for software break in the development tool, software interrupt always generates even if the non-maskable interrupt is in progress. 1. address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address. code ffh is the swi instruction, so a software interrupt is generated and an address error is detected. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address-trap reset is generated in case that an instruction is fetched from ram or sfr areas. 2. debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. 2007-10-19
tmp88cu74 2003-02-17 88cu74-35 1.5.3 external interrupts the tmp88cu74 has six external interrupt inputs ( int0 , int1, int2, int3, int4, int5 ). four of these are equipped with digital noise reject circuits(pulse inputs of less than a certain time are eliminated as noise). edge selection is also possible with int1 to int4. the int0 /p10 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. edge selection, noise reject control and int0 /p10 pin function selection are performed by the external interrupt control register (eintcr). table 1.5.2 external interrupts source pin secondary function pin enable conditions edge digital noise reject int0 0 int p10 imf = 1, int0en = 1 falling edge ? (hysteresis input) int1 int1 p11 imf k ef5 = 1 pulses of less than 15/fc or 63/fc [s] are eliminated as noise. pulses of 48/fc or 192/fc [s] or more are considered to be signals. int2 int2 p16 imf k ef7 = 1 int3 int3 p15/tc1 imf k ef11 = 1 int4 int4 p17/tc3 imf k ef12 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 24/fc [s] or more are considered to be signals. int5 5 int p20/ stop imf k ef15 = 1 falling edge ? (hysteresis input) note 1: the noise reject function is turned off in slow and sleep modes. also, the noise reject times are not constant for pulses input while transiting between operating modes. note 2: the noise reject function is also affected for timer/counter input (tc1 pin, tc3 pin). note 3: the pulse width (both h and level) for input to the int0 and int5 pins must be over 2 machine cycle. note 4: if a noiseless signal is input to the external interrupt pin in the normal 1/2 or idle 1/2 mode, the maximum time from the edge of input signal until the il is set is as follows: 1. int1 pin 49/fc [s] (int1nc = 1), 193/fc [s] (int1nc = 0) 2. int2 pin 25/fc [s] note 5: even if the falling edge of int0 pin input is detected at int0en = 0, the interrupt latch il3 is not set. t intl t inth 0 int / 5 int input t intl , t inth 2 tcyc (note: tcyc = 4/fm [s]) note: tcyc = 4/fc [s] (in normal1/2, idel1/2 mode) 4/fs (in slow, sleep mode) 2007-10-19
tmp88cu74 2003-02-17 88cu74-36 7 6 5 4 3 2 1 0 eintcr (00037h) int1 nc int0 en int4 es int3 es int2 es int1 es (initial value: 00 * 0 000* ) int1nc noise reject time select 0: pulses of less than 63/fc [s] are eliminated as noise 1: pulses of less than 15/fc [s] are eliminated as noise int0en p10/ int0 pin configuration 0: p10 input/output port 1: int0 pin (port p10 should be set to an input mode) int4es int3es int2es int1es int4 to int1 edge select 0: rising edge 1: falling edge r/w note 1: fc: high-frequency clock [hz], * : dont care note 2: edge detection during switching edge selection is invalid. note 3: do not change eintcr only when imf = 0. after changing eintcr, interrupt latches of external interrupt inputs must be cleared to 0 using load instruction. note 4: in order to change of external interrupt input by rewriting the contents of int2es and int3es and int4es during normal 1/2 mode, clear interrupt latches of external interrupt inputs (int2 and int3 and int4) after 8 machine cycles from the time of rewriting. during slow mode, 3 machine cycles are required. figure 1.5.5 external interrupt control register 2007-10-19
tmp88cu74 2003-02-17 88cu74-37 1.6 reset circuit the tmp88cu74 has four types of reset generation procedures: an external reset input, an address trap reset output, a watchdog timer reset output and a system clock reset output. table 1.6.1 shows on-chip hardware initialization by reset action. the malfunction reset output circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. the reset pin can output level l at the maximum 24/fc [s] (1.92 s at 12.5 mhz) when power is turned on. table 1.6.1 initializing internal status by reset action on-chip hardware initial value on-chip hardwear initial value program counter (pc) (ffffeh to ffffch) stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l) not initialized prescaler and divider of timing generator 0 register bank selector (rbs) 0 jump status flag (jf) 1 watchdog timer enable zero flag (zf) not initialized carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 output latches of i/o ports refer to i/o port circuitry interrupt individinal enable flags (ef) 0 interrupt latchs (il) 0 control registers refer to each of control register 1.6.1 external reset input the reset pin contains a schmitt trigger (hysteresis) with an internal pull-up resistor. when the reset pin is held at l level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within th e operating voltage range and os cillation stable, a reset is applied and the internal state is initialized. when the reset pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses ffffc to ffffeh. figure 1.6.1 reset circuit vdd reset input reset sink open drain watchdog timer reset address trap reset system clock reset malfunction reset output circuit 2007-10-19
tmp88cu74 2003-02-17 88cu74-38 1.6.2 address-trap-reset if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram or the sfr area, an address-trap-reset will be generated. then, the reset pin output will go low. the reset time is about 8/fc to 24/fc [s] (0.64 to 1.92 s at 12.5 mhz). ? ? ? ? ? note 1: address a is in the sfr or on-chip ram space. note 2: during reset release, reset vector r is read out, and an instruction at address r is fetched and decoded. figure 1.6.2 address-trap-reset 1.6.3 watchdog timer reset refer to section 2.4 watchdog timer. 1.6.4 system-clock-reset clearing both xen and xten (bit s 7 and 6 in syscr2) to 0, clearing xen to 0 when sysck = 0, or clearing xen to 0 when sysck = 1 stops system clock, and causes the microcomputer to deadlock. this can be prevented by automatically generating a reset signal whenever xen = xten = 0 is detected to continue the oscillation. then, the reset pin output goes low from high-impedance. the reset time is about 8/fc to 24/fc [s] (0.64 to 1.92 s at 12.5 mhz). jp a instruction execution reset output 8/fc to 24/fc [s] 4/fc to 12/fc [s] 20/fc [s] address-trap is occurred (l output) (h) reset release instruction at address r 2007-10-19
tmp88cu74 2003-02-17 88cu74-39 2. on-chip peripheral functions 2.1 special function registers (sfr) the tmp88cu74 uses the memory mapped i/o system, and all peripheral control and data transfers are performed through the special function registers (sfr). the sfr are mapped to addresses 00000h to 0003fh, and dbr are mapped to address 00f80h to 00fffh. figure 2.1.1 shows the tmp88cu74 sfr and dbr. address read write address read write 00000h p0 port 00020h sbicr1 (sbi control register) 01 p1 port 21 sbidbr (sbi data buffer) 02 p2 port 22 i 2 car (i 2 c bus address) 03 p3 port 23 sbisr (sbi status) sbicr2 (sbi control register) 04 p4 port 24 reserved 05 p5 port 25 reserved 06 p6 port 26 reserved 07 p7 port 27 sio1sr (sio status) sio1cr1 (sio1 control 1) 08 p8 port 28 sio1cr2 (sio1 control 2) 09 p9 port 29 vftsr (vft status) vftcr1 (vft control 1) 0a p0cr (p0 port i/o output control) 2a vftcr2 (vft control 2) 0b p1cr (p1 port i/o output control) 2b p3cr (port i/o control) 0c p4cr (p4 port i/o output control) 2c reserved 0d p5cr (p5 port i/o output control) 2d reserved 0e adccr (ad converter control) 2e reserved 0f adcdr (ad conv.result) 2f reserved 10 treg1al 30 dvcr 11 treg1ah 31 reserved 12 treg1bl 32 reserved 13 treg1bh 33 reserved 14 tc1cr (tc1 control) 34 wdtcr1 15 tc2cr (tc2 control) 35 wdtcr2 16 treg2l 36 tbtcr (tbt/tg/dvo control) 17 treg2h 37 eintcr (external interrupt control) 18 treg3a (timer register 3a) 38 syscr1 19 treg3b (timer register 3b) 39 syscr2 1a tc3cr (tc3 control) 3a eirl 1b treg4 (timer register 4) 3b eirh 1c tc4cr (tc4 control) 3c ill 1d pd port 3d ilh 1e reserved 3e pswl 1f reserved 3f pswh (a) special function registers note 1: do not access reserved areas by the program. note 2: : cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). note 4: when defining address 0003fh with assembler symbols, use grbs. address 0003eh must be gpsw/gflag. figure 2.1.1 sfr and dbr (1/2) (timer register 1a) (timer register1b) watch-dog timer control (timer register 2) (system control) (interrupt enable register) (interrupt latch) (program status word) 2007-10-19
tmp88cu74 2003-02-17 88cu74-40 read write 00f80h vft display data buffer (80 bytes) 00fcf 00fd0 00ff7 00ff8 f9 fa fb fc fd fe ff (b) data buffer registers figure 2.1.2 sfr and dbr (2/2) 2.2 i/o ports the tmp88cu74 each have 11 parallel input/output ports (71 pins) each as follows: 1. port p0 8-bit i/o port serial port input/output 2. port p1 8-bit i/o port external interrupt input, timer/counter input, and divider output 3. port p2 3-bit i/o port low-frequency resonator connections, external interrupt input, and stop mode release signal input 4. port p3 3-bit i/o port serial bus interface input/output 5. port p4 8-bit i/o port anarog input 6. port p5 4-bit i/o port anarog input 7. port p6 8-bit i/o port vft output 8. port p7 8-bit i/o port vft output 9. port p8 8-bit i/o port vft output 10. port p9 8-bit i/o port vft output 11. port pd 5-bit i/o port vft output each output port contains a latch, which holds the output data. input ports excluding do not have latches, so the external input data should either be held ex ternally until re ad or reading should be performed several times before processing. figure 2.2.1 shows input/output timing examples. external data is read from an i/o port in the s1 state of the read cycle during execution of the read instruction. this timing can not be recognized from outside, so that transient input such as chattering must be processed by the program. output data changes in the s2 state of the write cycle during execution of the instruction which writes to an i/o port. note: do not access reserved areas by the program. reserved sio transmit data buffer (8 bytes) address 2007-10-19
tmp88cu74 2003-02-17 88cu74-41 figure 2.2.1 input/output timing (example) when reading an i/o port except programmable i/o ports p0 an d p1, whether the pin input data or the output latch contents are read depends on the instructions, as shown below: (a) instructions that read the output latch contents 1. xch r, (src) 2. clr/set/cpl (src).b 3. clr/set/cpl (pp).g 4. ld (src).b, cf 5. ld (pp).b, cf 6. xch cf, (src), b 7. add/addc/sub/subb/and/or/xor (src), n 8. (src) side of add/addc/sub/subb/and/or/xor (src), (hl) 9. mxor (src), m (b) instructions that read the pin input data 1. (hl) side of add/addc/sub/subb/and/or/xor (src), (hl) s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 fetch cycle fetch cycle read cycle ex.: ld a, (x) (a) input timing instruction execution cycle input strobe data ? input s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 fetch cycle fetch cycle write cycle ex.: ld (x) , a instruction execution cycle output latch pulse data output (b) output timing note: the positions of the read and write cycles may vary, depending on the instruction. old new 2007-10-19
tmp88cu74 2003-02-17 88cu74-42 2.2.1 port p0 (p07 to p00) port p0 is an 8-bit general-purpose input/output port which can be configured as either an input or an output in one-bit unit under software control. input/output mode is specified by the corresponding bit in the port p0 input/output control register (p0cr). port p0 is configured as an input if its corresponding p0cr bit is cleared to 0, and as an output if its corresponding p0cr bit is set to 1. port p0 is also used as serial interfase input/output. when used as a function pins should be set to the input mode. the pin should be set to the output mode and beforehand the output latch should be set to 1. note: input mode port reads the state of input pin. when input/output mode is used to mixed, the contents of output latch setting to the input mode may be overwritten by executing bit manipulation instructions. 7 6 5 4 3 2 1 0 p02 p01 p00 p0 (00000h) p07 p06 p05 p04 p03 so1 si1 sck1 (initial value: 0000 0000) 7 6 5 4 3 2 1 0 p0cr (0000ah) (initial value: 0000 0000) p0cr i/o control for port p0 (setting per bit) 0: input mode 1: output mode write only figure 2.2.2 port p0 and p0cr example: setting the upper 4 bits of port p0 as an input port and the lower 4 bits as an output port (initial output data are 1010b). ld (p0), 00001010b ; sets initial data to p0 output latches ld (p0cr), 00001111b ; sets the port p0 input/output mode d q p0cri data input data output control output control input output latch p00, p01 d q p0cri data input data output control output control input output latch p02 to p07 2007-10-19
tmp88cu74 2003-02-17 88cu74-43 2.2.2 port p1 (p17 to p10) port p1 is an 8-bit input/output port which ca n be configured as an input or an output in one-bit unit under software control. input/output mode is specified by the corresponding bit in the port p1 input/output control register (p1cr). port p1 is configured as an input if its corresponding p1cr bit is cleared to 0, and as an output if its corresponding p1cr bit is set to 1. during reset, p1cr is initialized to 0, which configures port p1 as an input . the p1 output latches are also initialized to 0. data is written into the output latch regardless of p1cr contents. therefore initial output data should be written into the output latch before setting p1cr. port p1 is also used as an external interrupt input, a timer/counter input, and a divider output. when used as a secondary function pin, the input pins should be set to the input mode, and the output pins should be set to the output mode and beforehand the output latch should be set to 1. it is recommended that pins p11 and p15 and p16 and p17 should be used as external interrupt inputs, timer/counter input, or input ports. the interrupt latch is set on the rising or falling edge of the output when used as output ports. pin p10 ( int0 ) can be configured as either an i/o port or an external interrupt input with int0en (bit 6 in eintcr). during reset, the pin p10 ( int0 ) is configured as an input port p10. 7 6 5 4 3 2 1 0 p17 p16 p15 p14 p13 p12 p11 p10 int4 int2 int3 pwm dvo ppg int1 int0 (initial value: 0000 0000) p1 (00001h) tc3 tc1 pd0 tc2 7 6 5 4 3 2 1 0 p1cr (0000bh) (initial value: 0000 0000) p1cr i/o control for port p1 (setting per bit) 0: input mode 1: output mode write only figure 2.2.3 port p1 and p1cr example: sets p17, p16 and p14 as output ports, p13 and p11 as input ports, and the others as function pins. internal output data is 1 for the p17 and p14 pins, and 0 for the p16 pin. ld (eintcr), 01000000b ; int0en 1 ld (p1), 10111111b ; p17 1, p14 1, p16 0 ld (p1cr), 11010000b note: input mode port reads the state of input pin. when input/output mode is used to mixed, the contents of output latch setting to the input mode may be overwritten by executing bit manipulation instructions. d q p1cri data inpu t data outpu t control outpu t control input output latch p1i note: i = 7 to 0 2007-10-19
tmp88cu74 2003-02-17 88cu74-44 2.2.3 port p2 (p22 to p20) port p2 is a 3-bit input/output port. it is also used as an external interrupt input, and low-frequency crystal connection pins when used as an input port, or the secondary function pin, the output latch should be set to 1. during reset, the output latches are initialized to 1. a low-frequency crystal (32.768 khz) is connected to pins p21 (xtin) and p22 (xtout) in the dual-clock mode. in the single-clock mode, pins p21 and p22 can be used as normal input/output ports. it is recommended that the p20 pin should be used as an external interrupt input, a stop mode release signal input, or an input port. if used as an output port, the interrupt latch is set on the falling edge of the output pulse. when a read instruction for port p2 is executed , bits 7 to 3 in p2 read in as undefined data. 7 6 5 4 3 2 1 0 p20 5 int p2 (00002h) p22 xtout p21 xtin stop (initial value: **** *111) figure 2.2.4 port p2 data inpu t data outpu t control input data inpu t data outpu t data inpu t data outpu t xten output latch set/clr/cpl /others cmp/m cmp/test/o thers d q p20 ( 5 int / stop ) p21 (xtin) d q d q p22 (xtout) osc. enable note 1: * : dont care note 2: xten is bit 6 in syscr2 fs 2007-10-19
tmp88cu74 2003-02-17 88cu74-45 2.2.4 port p3 (p32 to p30) port p3 is an 3-bit input/output port and serial interface (sio1) input/output. input/output mode is specified by the port p3 input/output control register (p3cr). during reset p3cr is initialized to 0 and port p3 is input mode. the port p3 output latches are initialized to 0. p3 is serial bus inte rface input/output. when used as function pins set to output mode by port p3 i/o control register, and i/o is controlling by output data. the output buffer can be change to the tri-state or shink-open drain by port p3 i/o control register (p3cr). when a read instruction for port p3 is execut ed, bits 7 to 3 in p3 read is an undefined data. note: input mode port reads the state of input pin. when input/output mode is used to mixed, the contents of output latch setting to the input mode may be overwritten by executing bit manipulation instructions ? 7 6 5 4 3 2 1 0 p30 0 sck p3 (00003h) p32 scl si0 p31 sda so0 (initial value: **** *000) 7 6 5 4 3 2 1 0 p3cr (0002bh) p3o dr2 p3o dr1 p3o dr0 p3cr (initial value: **00 0000) p3cr i/o control of port p3 (setting per bit) 0: input mode 1: output mode p3odr0 p30 tri-state/open-drain control p3odr1 p31 tri-state/open-drain control p3odr2 p32 tri-state/open-drain control 0: tri-state 1: open-drain write only figure 2.2.5 p3 and port p3 i/o control register d q p3cri data inpu t data outpu t output control input control output latch p3i p3odri note 1: * : dont care note 2: i = 2 to 0 2007-10-19
tmp88cu74 2003-02-17 88cu74-46 2.2.5 port p4 (p47 to p40) ports p4 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. input/output mode is specified by the corresponding bit in the port p4 input/output control register (p4cr). at reset, p4cr is set to 0 and ainds is cleared to 0. thus, p4 becomes an analog input port. at the same time, the output latch of port p4 is initialized to 0. p4cr is a write-only register. pins not used for analog input can be used as i/o ports. but do not execute the output instruction to keep the accuracy in ad conversion. executing an input instruction on port p4 when the ad converter is in use reads 0 at pins set for analog input: 1 or 0 at pins not set for analog input, depending on the pin input level. 7 6 5 4 3 2 1 0 p47 p46 p45 p44 p43 p42 p41 p40 p4 (00004h) ain7 ain6 ain5 ain4 ain3 ain2 ain1 ain0 (initial value: 0000 0000) 7 6 5 4 3 2 1 0 p4cr (0000ch) (initial value: 0000 0000) p4cr port p4 i/o control (setting per bit) 0: input mode 1: output mode write only note 1: set the terminal which is used as an analog input to input mode. note 2: i = 0 to 7 figure 2.2.6 p4 and port p4 control register analog input ainds sain p4cri read data input data output p4i d q 2007-10-19
tmp88cu74 2003-02-17 88cu74-47 2.2.6 port p5 (p53 to p50) ports p5 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. input/output mode is specified by the corresponding bit in the port p5 input/output control register (p5cr). at reset, p5cr is set to 0 and ainds is cleared to 0. thus, p5 becomes an analog input port . at the same time, the output latch of port p5 is initialized to 0. p5cr is a write-only register. pins not used for analog input can be used as i/o ports. but do not execute the output instruction to keep the accuracy in ad conversion. executing an input instruction on port p5 when the ad converter is in use reads 0 at pins set for analog input: 1 or 0 at pins not set for analog input, depending on the pin input level. 7 6 5 4 3 2 1 0 p53 p52 p51 p50 p5 (00005h) ain11 ain10 ain8 ain6 (initial value: **** 0000) 7 6 5 4 3 2 1 0 p5cr (0000dh) (initial value: **** 0000) p5cr port p5 i/o control (setting per bit) 0: input mode 1: output mode write only note 1: set the terminal which is used as an analog input to input mode. note 2: i = 0 to 3 note 3: * : dont care figure 2.2.7 p5 and port p5 i/o control register analog input ainds sain p5cri read data inpu t data outpu t p5i d q 2007-10-19
tmp88cu74 2003-02-17 88cu74-48 2.2.7 port 6 (p67 to p60) port 6 is an 8-bit high-bre akdown voltage input/output po rt, and also used as a vft driver output, which can directly drive vacuum fluorescent tube (vft). when used as an vft driver output, the output latch should be cleared to 0. pins not used for vft driver output can be used as i/o ports. when use an vft driver and normal input/output at the same time, vft driver output data buffer memory (dbf) need to cleared to 0. the output latches are initialized to 0 during reset. it recommends that port 6 shoud be used to drive directly drive vacuum fluorescent tube (vft), since this port has a pull down resistance. 7 6 5 4 3 2 1 0 p67 p66 p65 p64 p63 p62 p61 p60 p6 (00006h) v7 v6 v5 v4 v3 v2 v1 v0 (initial value: 0000 0000) figure 2.2.8 port p6 data input data output cmp/mcmp/test/others output latch d q set/clr/ cpl/others note: i = 7 to 0 vkk p6i 2007-10-19
tmp88cu74 2003-02-17 88cu74-49 2.2.8 port 7 (p77 to p70) port 7 is an 8-bit high-bre akdown voltage input/output po rt, and also used as a vft driver output, which can directly drive vacuum fluorescent tube (vft). when used as an vft driver output, the output latch should be cleared to 0. pins not used for vft driver output can be used as i/o ports. when use an vft driver and normal input/output at the same time, vft driver output data buffer memory (dbf) need to cleared to 0. the output latches are initialized to 0 during reset. it recommends that port 7 shoud be used to drive directly drive vacuum fluorescent tube (vft), since this port has a pull down resistance. 7 6 5 4 3 2 1 0 p77 p76 p75 p74 p73 p72 p71 p70 p7 (00007h) v15 v14 v13 v12 v11 v10 v9 v8 (initial value: 0000 0000) figure 2.2.9 port p7 data input data output vft driver output cmp/mcmp/test/others output latch d q set/clr/ cpl/others note: i = 7 to 0 vkk p7i 2007-10-19
tmp88cu74 2003-02-17 88cu74-50 2.2.9 port 8 (p87 to p80) port 8 is an 8-bit high-bre akdown voltage input/output po rt, and also used as a vft driver output, which can directly drive vacuum fluorescent tube (vft). when used as an vft driver output, the output latch should be cleared to 0. pins not used for vft driver output can be used as i/o ports. when use an vft driver and normal input/output at the same time, vft driver output data buffer memory (dbf) need to cleared to 0. the output latches are initialized to 0 during reset. it recommends that port 8 shoud be used to drive directly drive vacuum fluorescent tube (vft), since this port has a pull down resistance. 7 6 5 4 3 2 1 0 p87 p86 p85 p84 p83 p82 p81 p80 p8 (00008h) v23 v22 v21 v20 v19 v18 v17 v16 (initial value: 0000 0000) figure 2.2.10 port p8 data inpu t data outpu t vft driver outpu t cmp/mcmp/test/others output latch d q set/clr/ cpl/others note: i = 7 to 0 vkk p8i 2007-10-19
tmp88cu74 2003-02-17 88cu74-51 2.2.10 port 9 (p97 to p90) port 9 is an 8-bit high-bre akdown voltage input/output po rt, and also used as a vft driver output, which can directly drive vacuum fluorescent tube (vft). when used as an vft driver output, the output latch should be cleared to 0. pins not used for vft driver output can be used as i/o ports. when use an vft driver and normal input/output at the same time, vft driver output data buffer memory (dbf) need to cleared to 0. the output latches are initialized to 0 during reset. it recommends that port 9 shoud be used to drive directly drive vacuum fluorescent tube (vft), since this port has a pull down resistance. 7 6 5 4 3 2 1 0 p97 p96 p95 p94 p93 p92 p91 p90 p9 (00009h) v31 v30 v29 v28 v27 v26 v25 v24 (initial value: 0000 0000) figure 2.2.11 port p9 data input data output vft driver outpu t cmp/mcmp/test/others output latch d q set/clr/cpl/others vkk p9i note: i = 7 to 0 2007-10-19
tmp88cu74 2003-02-17 88cu74-52 2.2.11 pd (pd4 to pd0) port pd is high- breakdown voltage input/out put port, and also used as a vft driver output, which can directly dri ve vacuum fluorescent tube (vft). general-purpose or segment can be selected for each bit by vsel (bit 4 to 0) in vft driver control register 1 (vftcr1). the vsel is cleared to 0 during reset, which used as an input mode. when used as an input port or vft driver output, the output latch set to 0. the output latches are initialized to 0 during reset. when a read instruction for port pd is executed bit 7 to 5 in pd read in as undefined data. 7 6 5 4 3 2 1 0 pd4 pd3 pd2 pd1 pd0 pd (0001dh) v36 v35 v34 v33 v32 (initial value: *** 0 0000) figure 2.2.12 pd port data input data output vft driver output control cmp/mcmp/test/others output latch d q set/clr/ cpl/others vkk pdi note: i = 4 to 0 * : dont care vft driver output 2007-10-19
tmp88cu74 2003-02-17 88cu74-53 2.3 time base timer (tbt) the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). an inttbt is generated on the first rising edge of source clock (the divider output of the timing generator) after the time base timer has been enabled. the divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period (figure 2.3.1 (b)). the interrupt frequency (tbtck) must be selected with the time base timer disabled (the interrupt frequency must not be changed with the di sable from the enable state). both frequency selection and enabling can be performed simultaneously. figure 2.3.1 time base timer example: sets the time base timer frequency to fc/2 16 [hz] and enables an inttbt interrupt. ld (tbtcr), 00001010b set (eirl). 6 tbtcr tbtck 3 tbten time base timer control register (a) configuration source clock rising edge detector inttbt interrupt request fc/2 23 , fc/2 24 or fs/2 15 fc/2 21 , fc/2 22 or fs/2 13 fc/2 16 , fc/2 17 or fs/2 8 fc/2 14 , fc/2 15 or fs/2 6 fc/2 13 , fc/2 14 or fs/2 5 fc/2 12 , fc/2 13 or fs/2 4 fc/2 11 , fc/2 12 or fs/2 3 fc/2 9 , fc/2 10 or fs/2 source clock tbten inttbt enable tbt (b) time base timer interrupt interrupt period a b c d e f g h y s mpx 2007-10-19
tmp88cu74 2003-02-17 88cu74-54 7 6 5 4 3 2 1 0 tbtcr (00036h) (dvoen) (dvock) (dv7ck) tbten tbtck (initial value: 0 **0 0*** ) tbten time base timer enable/disable 0: disable 1: enable normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 slow, sleep mode 000 fc/2 23 fc/2 24 fs/2 15 fs/2 15 fs/2 15 001 fc/2 21 fc/2 22 fs/2 13 fs/2 13 fs/2 13 010 fc/2 16 fc/2 17 fs/2 8 fs/2 8 011 fc/2 14 fc/2 15 fs/2 6 fs/2 6 100 fc/2 13 fc/2 14 fs/2 5 fs/2 5 101 fc/2 12 fc/2 13 fs/2 4 fs/2 4 110 fc/2 11 fc/2 12 fs/2 3 fs/2 3 tbtck time base timer interrupt frequency select [hz] 111 fc/2 9 fc/2 10 fs/2 fs/2 r/w note: fc: high-frequency clock [hz], fs: low-frequency clock [hz], * : dont care figure 2.3.2 time base timer control register table 2.3.1 time base timer interrupt frequency (example: fc = 12.5 mhz, fs = 32.8 khz) time base timer interrupt frequency [hz] normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 tbtck dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 slow, sleep mode 000 001 010 011 100 101 110 111 1.49 5.96 190.73 762.94 1525.88 3051.76 6103.52 24414.06 0.75 2.98 95.37 381.47 762.94 1525.88 3051.76 12207.03 1 4 128 512 1024 2048 4096 16384 1 4 128 512 1024 2048 4096 16384 1 4 ? ? ? ? ? ? 2007-10-19
tmp88cu74 2003-02-17 88cu74-55 2.4 watchdog timer (wdt) the watchdog timer is a fail-safe system to rapidly detect the cpu malfunctions such as endless looping caused by noise or the like, or deadlock and resume the cpu to the normal state. the watchdog timer signal for detecting malfunction can be selected either a reset output or a pseudo non-maskable interrupt request. however, selection is possible only once after reset. at first the reset output is selected. when the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. 2.4.1 watchdog timer configuration figure 2.4.1 watchdog timer configuration q selector fc/2 23 , fc/2 24 or fs/2 15 fc/2 21 , fc/2 22 or fs/2 13 fc/2 19 , fc/2 20 or fs/2 11 fc/2 17 , fc/2 18 or fs/2 9 binary counters clock clear 1 2 overflow 2 wdt output reset release reset output internal reset wdtt wdten q s r interrupt request reset intwdt r s writing disable code writing clear code wdtout controller wdtcr1 00034h wdtcr2 00035h watchdog timer control registers 2007-10-19
tmp88cu74 2003-02-17 88cu74-56 2.4.2 watchdog timer control figure 2.4.2 shows the watchdog timer control registers (wdtcr1, wdtcr2). the watchdog timer is automatically enabled after reset. (1) malfunction detection methods using the watchdog timer the cpu malfunction is detected at follows. 1. setting the detection time, selecting ou tput, and clearing the binary counter. 2. repeatedly clearing the binary count er within the setting detection time if the cpu malfunctions such as endless looping or deadlock occur for any cause, the watchdog timer output will become active at the rising of an overflow from the binary counters unless the binary counters are cleared. at this time, when wdtout = 1 a reset is generated, which drives the reset pin low to reset the internal hardware and the external circuit. when wdtout = 0, a watchdog timer interrupt(intwdt) is generated. the watchdog timer temporarily stops counting in stop mode including warm-up or idle mode, and automatically restarts (continues counting) when the stop/idle mode is released. note: just right before disabling the watchdog timer, disable the acceptance of interrupts (di) and clear the watchdog timer. if the watchdog timer is disabled under conditions other than the above, the proper operation cannnot be guaranteed. example: di ; disable interrupt acceptance. ld (wdtcr2), 4eh ; clears the watchdog timer. ldw (wdtcr1), b100h ; disables the watchdog timer. ei ; enables interrupt acceptance. example: sets the watchdog timer detection time to 2 21 /fc [s] and resets the cpu malfunction. ld (wdtcr2), 4eh ; clears the binary counters ld (wdtcr1), 00001101b ; wdtt 10, wdtout 1 within wdt detection time ld (wdtcr2), 4eh ; clears the binary counters (always clear immediately after changing wdtt) ld (wdtcr2), 4eh ; clears the binary counters within wdt detection time ld (wdtcr2), 4eh ; clears the binary counters 2007-10-19
tmp88cu74 2003-02-17 88cu74-57 watchdog timer register 1 7 6 5 4 3 2 1 0 wdtcr1 (00034h) wdt en wdtt wdt out (initial value: ? **** 1001) wdten watchdog timer enable/disable 0: disable (it is necessary to write the disable code to wdtcr2) 1: enable norma1/2 mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 slow mode 00 2 25 /fc 2 26 /fc 2 17 /fs 2 17 /fs 2 17 /fs 01 2 23 /fc 2 24 /fc 2 15 /fs 2 15 /fs 2 15 /fs 10 2 21 /fc 2 22 /fc 2 13 /fs 2 13 /fs 2 13 /fs wdtt watchdog timer detection time [s] 11 2 19 /fc 2 20 /fc 2 11 /fs 2 11 /fs 2 11 /fs wdtout watchdog timer output select 0: interrupt request 1: reset output write only note 1: wdtout cannot be set to 1 by program after clearing wdtout to 0. note 2: fc: high-frequency clock [hz], fs: low-frequency clock [hz], * : dont care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. note 4: disable the watchdog timer or clear the counter just before switching to stop mode. when the counter is cleared just before switching to stop mode, clear the counter again subsequently to releasing stop mode. watchdog timer register 2 7 6 5 4 3 2 1 0 wdtcr2 (00035h) (initial value: **** **** ) wdtcr2 watchdog timer control code write register 4eh: watchdog timer binary counter clear (clear code) b1h: watchdog timer disable (disable code) others: invalid write only note 1: the disable code is invalid unless written when wdten = 0. note 2: * : dont care note 3: the binary counter of the watchdog timer must not be cleared by the interrupt task. figure 2.4.2 watchdog timer control registers (2) watchdog timer enable the watchdog timer is enabled by setting wdten (bit 3 in wdtcr1) to 1. wdten is initialized to 1 during reset, so the watchdog timer operates immediately after reset is released. example : enables watchdog timer (3) watchdog timer disable the watchdog timer is disabled by writing the disable code (b1h) to wdtcr2 after clearing wdten (bit 3 in wdtcr1) to 0. the watchdog timer is not disabled if this procedure is reversed and the disable code is written to wdtcr2 before wdten is cleared to 0. during disabling the watchdog timer, the binary counters are cleared to 0. example: disables watchdog timer ldw (wdtcr1), 0b101h ; wdten 0, wdtcr2 disable code 2007-10-19
tmp88cu74 2003-02-17 88cu74-58 table 2.4.1 watchdog timer detection time (example: fc = 12.5 mhz, fs = 32.8 khz) watchdog timer detection time [s] normal1/2 mode dv7ck = 0 dv7ck = 1 wdtt dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 slow mode 00 01 10 11 2.684 s 671.089 ms 167.772 ms 41.943 ms 5.369 s 1.342 s 335.544 ms 83.886 ms 4 s 1 s 250 ms 62.5 ms 4 s 1 s 250 ms 62.5 ms 4 s 1 s 250 ms 62.5 ms 2.4.3 watchdog timer interrupt (intwdt) this is a pseudo non-maskable interrupt which can be accepted regardless of the contents of the eir. if a watchdog timer interrupt or a software interrupt is already accepted, however, the new watchdog timer interrupt waits until the previous interrupt processing is completed (the end of the [retn] instruction execution). the stack pointer (sp) should be initialized be fore using the watchdog timer output as an interrupt source with wdtout. example: watchdog timer interrupt setting up ld sp, 0023fh ; sets the stack pointer ld (wdtcr1), 00001000b ; wdtout 0 2.4.4 watchdog timer reset if the watchdog timer output becomes active, a reset is generated, which drives the reset pin (sink open drain input/output with pu ll-up) low to reset th e internal hardware and external circuits. the reset output time is about 8/fc to 24/fc [s] (0.64 to 1.92 s at fc = 12.5 mhz, fcgck = fc). note: the high-frequency clock oscillator also turns on when a watchdog timer reset is generated in slow mode. the reset output time is 8/fc to 24/fc [s]. therefore, the reset time may include a certain amount of error if there is any fluctuation of the oscillation frequency at starting the high-frequency clock oscillation. thus, the reset time must be considered an approximated value. figure 2.4.3 watchdog timer interrupt/reset clock binary counter overflow intwdt interrupt wdt reset output 1 2 3 0 1 2 3 0 (wdtt = 11b) (l output) (high-z) writes 4eh to wdtcr2 2 17 /fc 2 19 /fc [s] 2007-10-19
tmp88cu74 2003-02-17 88cu74-59 2.5 divider output ( dvo ) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. divider output is from pin p13 ( dvo ). the p13 output latch should be set to 1 and then the p13 sh ould be configured as an output mode. 7 6 5 4 3 2 1 0 tbtcr (00036h) dvoen dvock (dv7ck) (tbten) (tbtck) (initial value: 0 **0 0*** ) dvoen divider output enable/disable 0: disable 1: enable normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 slow, sleep mode 00 fc/2 13 fc/2 14 fs/2 5 fs/2 5 fs/2 5 01 fc/2 12 fc/2 13 fs/2 4 fs/2 4 fs/2 4 10 fc/2 11 fc/2 12 fs/2 3 fs/2 3 fs/2 3 dvock divider output ( dvo ) frequency selection [hz] 11 fc/2 10 fc/2 11 fs/2 2 fs/2 2 fs/2 2 r/w note: fc: high-frequency clock [hz], fs: low-frequency clock [hz], * : dont care figure 2.5.1 divider output control register example: 1.5 khz pulse output (at fc = 12.5 mhz, dv1ck = 0) set (p1).3 ; p13 output latch 1 ld (p1cr), 00001000b ; configures p13 as an output mode ld (tbtcr), 10000000b ; dvoen 1, dvock 00 table 2.5.1 divider output frequency (example: at fc = 12.5 mhz, fs = 32.8 khz) divider output frequency [khz] normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 dvock dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 slow, sleep mode 00 01 10 11 1.526 k 3.502 6.104 12.207 0.763 k 1.526 3.502 6.104 1.024 k 2.048 4.096 8.192 1.024 k 2.048 4.096 8.192 1.024 k 2.048 4.096 8.192 figure 2.5.2 divider output data output output latch p13 ( dvo ) selector d q fc/2 13 , fc/2 14 or fs/2 5 fc/2 12 ,fc/2 13 or fs/2 4 fc/2 11 ,fc/2 12 or fs/2 3 fc/2 10 ,fc/2 11 or fs/2 2 a b c d s y 2 dvock dvoen dvock divider output control register (a) configuration of divider output circuit (b) divider output timing chart p13 output latch dvoen dvo pin outpu t output enable (p1cr 3 ) 2007-10-19
tmp88cu74 2003-02-17 88cu74-60 2.6 16-bit timer/counter 1 (tc1) 2.6.1 configuration figure 2.6.1 timer/counter 1 (tc1) external toggle q set clear mcap1 s a y b tc1 control register window mode source clock capture treg1b 16-bit timer register 1a, b fc/2 11 , fc/2 12 or fs/2 3 fc/2 7 or fc/2 8 fc/2 3 or fc/2 4 d a b y c s 2 tc1ck scap1 tc1cr command start rising edge detector mett1 int2es s tc1 pin pulse width measurement mode falling tc1s 2 decoder a y b b a s y treg1a inttc1 interrupt mppg1 tc1s clear ppg output mode set q clear start clear 16-bit up-counter clear set toggle pulse width measurement mode match cmp ppg output mode internal reset tc1cr write strobe write strobe tff1 match detection control enable treg1ah treg1bh treg1al treg1bl q ppg pin trigger start external trigger s a y b mpx mpx mpx mpx 2007-10-19
88cu74-61 tmp88cu74 2007-10-19 2.6.2 control the timer/counter 1 is controlled by a timer/counter 1 control register (tc1cr) and two 16-bit timer registers (treg1a and treg1b). reset does not affect treg1a and treg1b. note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2: writing to the lower byte of the timer registers (treg1al, treg1bl), the comparison is inhibited until the upper byte(treg1ah, treg1bh) is written. only the lower byte of the timer registers can not be changed. after writing to the upper byte, any match during 1 machine cycle (instruction execution cycle) is ignored. note 3: set the mode, source clock, edge (including int2es), ppg control and timer f/f control when tc1 stops (tc1s = 00). note 4: software capture can be used in only timer and event counter modes. scap1 is automatically cleared to 0 after capturing. note 5: values to be loaded to timer registers must satisfy the following condition. treg1a>treg1b>0(ppg output mode), treg1a>0 (others) note 6: always write 0 to tff1 except ppg output mode. note 7: tc1cr and treg1a are write-only registers and must not be used with any of the read-modify-write instructions such as set, clr, etc. note 8: writing to the treg1b is not possible unless tc1 is set to the ppg output mode. note 9: please use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. please read the capture value in a capture enabled condition. note 10:since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to 1. therefore, wait at least one cycle of the internal source clock before reading tc1drb for the first time. figure 2.6.2 timer registers and tc1 control register treg1a 1514131211109876543210 (00010, 00011h) treg1ah (00011h) treg1al (00010h) write only treg1b (00012, 00013h) treg1bh (00013h) treg1bl (00012h) read/write (writing is capable only when ppg output mode) 7 6 5 4 3 2 1 0 tc1cr (00014h) tff1 scap1 mcap1 mett1 mppg1 tc1s tc1ck tc1m (initial value: 0000 0000 ) tc1m tc1 operating mode select 00: timer/external trigger timer/event counter mode 01: window mode 10: pulse width measurement mode 11: ppg (programmable pulse generate) output mode tc1ck tc1 source clock select [hz] normal1/2, idle1/2 mode slow, sleep mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 00 fc/2 11 fc/2 12 fs/2 3 fs/2 3 fs/2 3 01 fc/2 7 fc/2 8 fc/2 7 fc/2 8 >+ 10 fc/2 3 fc/2 4 fc/2 3 fc/2 4 >+ 11 external clock (tc1 pin input) write only tc1s tc1 start control 00: stop and counter clear 01: command start 10: reserved 11: external trigger start scap1 software capture control 0: >+ 1: software capture trigger mcap1 pulse width measurement mode control 0: double edge capture 1: single edge capture mett1 external trigger timer mode control 0: trigger start 1: trigger start & stop mppg1 ppg output control 0: pulse 1: single tff1 time f/f1 control for ppg output mode 0: clear 1: set
tmp88cu74 2003-02-17 88cu74-62 2.6.3 function timer/counter 1 has six operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output mode. (1) timer mode in this mode, counting up is performed using the internal clock. the contents of treg1a are compared with the contents of up-counter. if a match is found, an inttc1 interrupt is generated, and the counter is cleared to 0. counting up resumes after the counter is cleared. the current contents of up-counter can be transferred to treg1b by setting scap1 (bit 6 in tc1cr) to 1(software capture function). scap1 is automatically cleared after capturing. table 2.6.1 source clock (internal clock) for timer/counter 1 (example: at fc = 12.5 mhz, fs = 32.8 khz) normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 tc1ck resolution [ s] maximum time setting resolution [ s] maximum time setting resolution [ s] maximum time setting resolution [ s] maximum time setting 00 01 10 163.84 s 10.24 s 0.64 s 10.8 s 0.64 s 41.92 ms 327.68 s 20.48 s 1.28 s 21.5 s 1.28 s 83.84 ms 244.14 s 8 s 0.5 s 16.0 s 0.5 s 32.75 ms 244.14 s 16 s 1 s 16.0 s 1.0 s 65.5 ms slow, sleep mode tc1ck resolution [ s] maximum time setting [s] 00 01 10 244.14 s ? ? 16.0 s ? ? example 1: sets the timer mode with source clock fs/2 3 [hz] and generates an interrupt 1 later (at fs = 32.8 khz). ldw (treg1a), 1000h ; sets the timer register (1 s 2 3 /fs = 1000h) set (eirl). ef4 ei ; enable inttc1 ld (tc1cr), 00010000b ; starts tc1 note: tc1cr is a write-only register and must not be used with [set(tc1cr).4] instruction. example 2: software capture ld (tc1cr), 01010000b ; scap1 1 (captures) ld wa, (treg1b) ; reads the capture value 2007-10-19
tmp88cu74 2003-02-17 88cu74-63 figure 2.6.3 timer mode timing chart (2) external trigger timer mode in this mode, counting up is started by an external tri gger. this trigger is the edge of the tc1 pin input. either the rising or fallin g edge can be selected with int2es in eintcr. edge selection is the same as for int3 pin. source clock is an internal clock selected with tc1ck. the contents of treg1a is compared with the contents of up-counter. if a match is found, an inttc1 interrupt is generated, and the counter is cleared to 0 and halted. the counter is restarted by the selected edge of the tc1 pin input. when mett1 (bit 6 in tc1cr) is 1, inputting the edge to the reverse direction of the trigger edge to start counting clears the counter, and the counter is stopped. inputting a constant pulse width can generate interrupts. when mett1 is 0, the reverse directive edge input is ignored. the tc1 pin input edge before a match detection is also ignored. the tc1 pin input has the same noise rejection as the int3 pin; therefore, pulses of 7/fc [s] or less are rejected as noise. a pulse width of 24/fc [s] or more is required for edge detection in normal1, 2 or idle1, 2 mode. the noise rejection circuit is turned off in slow and sleep modes. but, a pulse width of one machine cycle or more is required. example 1: detects rising edge in tc1 pin input and generates an interrupt 100 s later. (at fc = 12.5 mhz, dv1ck = 1) ld (eintcr), 00000000b ; int3es 0 (rising edge) ldw (treg1a), 004eh ; 100 s 2 4 /fc = 4eh set (eirl).ef4 ; inttc1 interrupt enable ei ld (tc1cr), 00111000b ; tc1 external trigger start, mett1 = 0 treg1b m ? 1 m m ? 2 ? up-counter scap1 capture m + 1 m + 2 (b) software capture treg1a inttc1 interrupt n ? 1 n n + 1 n m capture command start 1 source clock up-counter source clock 2 3 4 1 2 3 4 0 ? n n ? 1 n 0 5 6 7 match detect counter clear (a) timer mode 2007-10-19
tmp88cu74 2003-02-17 88cu74-64 example 2: generates an interrupt, inputting l level pulse (pulse width: 4 ms or more) to the tc1 pin. (at fc = 12.5 mhz, dv1ck = 1) ld (eintcr), 00000100b ; int2es 1 (l level) ldw (treg1a), 00c3h ; 4 ms 28/fc = c3h set (eirl).ef4 ; inttc1 interrupt enable ei ld (tc1cr), 01110100b ; tc1 external trigger start, mett1 = 1 figure 2.6.4 external trigger timer mode timing chart (3) event counter mode in this mode, events are counted at the edge of the tc1 pin input. either the rising or falling edge can be selected with int2es in eintcr. edge selection is the same as for int3 pin. the contents of treg1a are compared with the contents of up-counter. if a match is found, an inttc1 interrupt is generated, and the counter is cleared. this maximum applied frequency is shown in table 2.6.2. setting scap1 to 1 transfers the current contents of up-counter to treg1b (software capture function). scap1 is automatically cleared after capturing. inttc1 interrupt treg1a tc1 pin input n (b) trigger start and stop (mett1 = 1) internal clock 0 up-counter 1 treg1a 2 inttc1 interrupt 3 count start m trigger 0 0 2 1 0 n ? 2 1 n ? 1 2 n 3 0 match detect note: m tmp88cu74 2003-02-17 88cu74-65 figure 2.6.5 event counter mode timing chart table 2.6.2 timer/counter 1 external clock source maximum applied frequency [hz] normal1/2, idle1/2 mode slow, sleep mode fc/2 4 fs/2 4 (4) window mode counting up is performed on the rising edge of the pulse that is the logical and-ed product of the tc1 pin input (window pulse) and an internal clock. the contents of treg1a are compared with the contents of up-counter. if a match is found, an inttc1 interrupt is generated, and the counter is cleared. positive or negative logic for the tc1 pin input can be selected. edge selection is the same as for int3 pin. setting scap1 to 1 transfers the current contents of up-counter to treg1b. it is necessary that the maximum applied frequency be such that the counter value can be analyzed by the program. that is; the frequency must be considerably slower than the selecte d internal clock. figure 2.6.6 window mode timing chart (a) positive logic (at int3es = 0) tc1 pin input internal clock up-counter treg1a inttc1 interrupt ? 9 0 1 2 3 4 5 6 7 8 9 0 1 (b) negative logic (at int3es = 1) match detect counter clear command start tc1 pin input internal clock up-counter treg1a inttc1 interrupt command start ? 7 0 1 2 3 4 5 6 7 2 3 0 1 match detec t counter clear ? tc1 p in in p ut up-counter treg1a inttc1 interrupt command start n 0 1 2 n 1 n 0 1 2 match detec t counter clear int2es = 1 at the falling edge 2007-10-19
88cu74-66 tmp88cu74 2007-10-19 (5) pulse width measurement mode counting is started by the external trigger (set to external trigger start by tc1s). the trigger can be selected either the rising or falling edge of the tc1 pin input. the source clock is used an internal clock. on the next falling (rising) edge, the counter contents are transferred to treg1b and an inttc1 interrupt is generated. the counter is cleared when the single edge capture mode is set. when double edge capture is set, the counter continues and, at the next rising (falling) edge, the counter contents are again transferred to treg1b. if a falling (ri sing) edge capture va lue is required, it is necessary to read out treg1b contents until a rising (falling) edge is detected. falling or rising edge is selected with int3es, and single edge or double edge is selected with mcap1 (bit 6 in tc1cr). note: the first captured valu e after the timer starts may be read incorrectively, therefore, ignore the first captured value. example: duty measurement (resolution fc/2 7 [hz] dv1ck = 0) clr (inttc1sw). 0 ; inttc1 service switch initial setting ld (eintcr), 00000000b ; sets the rise edge at the int3 edge ld (tc1cr), 00000110b ; sets the tc1 mode and source clock set (eirl). ef4 ; enables inttc1 ei ld (tc1cr), 00110110b ; starts tc1 with an external trigger at mcap1=0 pinttc1: cpl (inttc1sw). 0 ; complements inttc1 service switch jrs f, sinttc1 ld (hpulse), (treg1bl) ; reads treg1b ( h level pulse width) ld (hpulse + 1), (treg1bh) reti sinttc1: ld (width), (treg1bl) ; reads treg1b (period) ld (width + 1), (treg1bh) ; duty calculation reti vinttc1: dw pinttc1 width hpulse tc1 pin inttc1sw
tmp88cu74 2003-02-17 88cu74-67 figure 2.6.7 pulse width measurement mode timing chart (6) programmable pulse generate (ppg) output mode counting is started by an ed ge of the tc1 pin input (either the rising or falling edge can be selected) or by a command. the source clock is used an internal clock. first, the contents of treg1b are compared with the contents of the up-counter. if a match is found, timer f/f1 output is toggled. when mppg1 = 0, an inttc1 interrupt is generated. next, timer f/f is again toggled and the counter is cleared by matching with treg1a. an inttc1 interrupt is generated at this time. timer f/f output is connected to the p12 ( ppg ) pin. in the case of ppg output, set the p12 output latch to 1 and configure as an output mode. timer f/f1 is cleared to 0 during reset. the timer f/f 1 value can also be set by tff1 (bit 7 in tc1cr) and either a positive or negative logic pulse output is available. also, writing to the treg1b is not possible unless the timer/counter 1 is set to the ppg output mode. example: pulse output h level 800 s, l level 200 s (at fc = 12.5 mhz, dv1ck = 0) set (p1).2 ; p12 output latch 1 ld (p1cr), 00000100b ; sets the p12 output mode ld (tc1cr), 10001011b ; sets the ppg output mode ldw (treg1a), 07d0h ; sets the period (1 ms 0.64 s = 061ah) ldw (treg1b), 0190h ; sets l level pulse width (200 s 0.64 s = 0138h) ld (tc1cr), 10011011b ; starts tc1 pin input count start internal clock up-counter treg1b inttc1 interrupt capture 0 1 2 4 n ? 1n 3 0 1 2 n [application] high or low pulse width measurement (a) single edge capture (mcap1 = 1) count start (int3es = 0) tc1 pin input count start internal clock up-counter treg1b inttc1 interrupt capture 0 1 2 4 n ? 1 n 3 n + 1 1 2 n (b) double edge capture (mcap1 = 0) count start (int3es = 0) n + 2 n + 3m ? 2m ? 1 m capture m [application] 1. period/frequency measurement 2. duty measurement trigger 2007-10-19
tmp88cu74 2003-02-17 88cu74-68 figure 2.6.8 ppg output figure 2.6.9 ppg output mode timing chart set clear q toggle timer f/f1 tc1s clear b y a s mppg1 data output p12 output latch d q r output enable tff1 tc1cr write strobe internal rese t match with treg1b match with treg1a inttc1 interrupt p12 ( ppg ) pin 0 count start external trigger start trigger tc1 pin input internal clock up-counter treg1b treg1a ppg pin output inttc1 interrupt 0 1 n n + 1 m0 n m (b) single [application] one shot pulse output internal clock up-counter treg1b treg1a ppg pin output inttc1 interrupt 0 1 n n + 1 m n m (a) pulse 2 1 n n + 1 2 m 0 1 2 command start 2007-10-19
tmp88cu74 2003-02-17 88cu74-69 2.7 16-bit timer/counter 2 (tc2) 2.7.1 configuration figure 2.7.1 timer/counter 2 (tc2) h a b c d e f g tc2s tc2m source clock timer/ event counter window fc/2 23 , fc/2 24 or fs/2 15 fc/2 13 , fc/2 14 or fs/2 5 fc/2 8 or fc/2 9 fc/2 3 or fc/2 4 fc fs fc/2 tc2 pin clear 16-bit timer register 2 tc2 control register tc2s tc2ck treg2l write strobe treg2h write strobe enable cmp match detect inttc2 interrupt b y a 16-bit up-counter s 3 s match detect control treg2 tc2cr y mpx mpx 2007-10-19
tmp88cu74 2003-02-17 88cu74-70 2.7.2 control the timer/counter 2 is controlled by a timer/counter 2 control register (tc2cr) and a 16-bit timer register 2 (treg2). reset does not affect treg2. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 treg2 (00016, 00017h) treg2h (00017h) treg2l (00016h) write only 7 6 5 4 3 2 1 0 tc2cr (00015h) 0 0 tc2s tc2ck tc2m (initial value: **00 00* 0) tc2m tc2 operating mode select 0: timer/event counter mode 1: window mode normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 slow mode sleep mode 000 001 010 011 100 101 110 fc/2 23 fc/2 13 fc/2 8 fc/2 3 ? fs ? fc/2 24 fc/2 14 fc/2 9 fc/2 4 ? fs ? fs/2 15 fs/2 5 fc/2 8 fc/2 3 ? fs ? fs/2 15 fs/2 5 fc/2 9 fc/2 4 ? fs ? fs/2 15 fs/2 5 ? ? fc ? fc/2 fs/2 15 fs/2 5 ? ? ? ? ? tc2ck tc2 source clock select [hz] 111 external clock (tc2 pin input) tc2s tc2 start control 0: stop and counter clear 1: start write only note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz], fcgck: gear clock [hz], * : dont care note 2: writing to the lower byte of timer register 2 (treg2l), the comparison is inhibited until the upper byte (treg2h) is written. after writing to the upper byte, any match during 1 machine cycle (instruction execution cycle) is ignored. note 3: set the mode and source clock when the tc2 stops (tc2s = 0). note 4: values to be loaded to the timer register must satisfy the following condition. treg2>0 (treg2 15 to 11 >0 at warm-up) note 5: fcgck can be selected as the source clock only in the timer mode during the slow mode. note 6: tc2cr and treg2 are write-only registers and must not be used with any of the read-modify-write instructions such as set, clr, etc. note 7: it recommends when used as an tc2ck = <100>, at fc 8 mhz, and used as an tc2ck = <110>, at fc = 12.5 mhz. figure 2.7.2 timer register 2 and tc2 control register 2007-10-19
tmp88cu74 2003-02-17 88cu74-71 2.7.3 function the timer/counter 2 has three operating modes: timer, event counter and window modes. also timer/counter 2 is used for warm-up when switching from slow mode to normal2 mode. (1) timer mode in this mode, the internal clock is used for counting up. the contents of treg2 are compared with the contents of up-counter. if a match is found, a timer/counter 2 interrupt (inttc2) is generated, and the counter is cleared. counting up is resumed after the counter is cleared. also, when fcgck is selected as the source clock during slow mode, the lower 11 bits of treg2 are ignored and an inttc2 interrupt is generated by matching the upper 5 bits. thus, in this case, only the treg2h setting is necessary. table 2.7.1 source clock (internal clock) for timer/counter 2 (at fc = 12.5 mhz, fs = 32.8 khz) normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 tc2ck resolution maximum time setting resolution maximum time setting resolution maximum time setting resolution maximum time setting 000 001 010 011 100 101 671 ms 655.36 s 20.48 s 0.64 s 30.5 s 12.2 h 43.0 s 1.34 s 41.92 ms 2 s 1.34 s 1.31 ms 40.96 s 1.28 s 30.5 s 24.4 h 1.4 min 2.7 s 83.8 ms 2 s 1 s 0.98 ms 16 s 0.5 s 30.5 s 18.2 h 1.07 min 1.05 s 32.75 ms 2 s 1 s 0.98 ms 32 s 1 s 30.5 s 18.2 h 1.07 min 2.1 s 65.5 ms 2 s slow mode sleep mode tc2ck resolution [s] maximum time setting resolution [s] maximum time setting 000 001 01* 100 110 101 1 s 0.98 ms 125 ns (note) 160 ns (note) 18.2 h 1.07 min 1 s 0.98 ms 18.2 h 1.07 min note: fc and fc/2 can be used only in the timer mode. it is used for warm-up when switching from slow mode to normal2 mode. (at fc = 8 mhz, tc2ck = <100>) example: sets the timer mode with source clock fc/2 4 [hz] and generates an interrupt every 25 ms (at fc = 12.5 mhz, dv1ck = 1). ldw (treg2), 4c46h ; sets treg2 (25 ms 2 4 /fc = 4c46h) set (eirh). ef14 ; enables inttc2 interrupt ei ld (tc2cr), 00101100b ; starts tc2 2007-10-19
tmp88cu74 2003-02-17 88cu74-72 (2) event counter mode in this mode, events are counted on the rising edge of the tc2 pin input. the contents of treg2 are compared with the contents of the up-counter. if a match is found, an inttc2 interrupt is generated, and the counter is cleared. the maximum frequency applied to the tc2 pin is shown in table 2.7.2. two or more machine cycles are required for both the h and l levels of the pulse width. example: sets the event counter mode and generates an inttc2 interrupt 640 counts later. ldw (treg2), 640 ; sets treg2 set (eirh). ef14 ; enables inttc2 interrupt ei ld (tc2cr), 00111100b ; starts tc2 table 2.7.2 timer/counter 2 external clock source maximum applied frequency [hz] normal1/2, idle1/2 mode slow, sleep mode fc/2 4 fs/2 4 (3) window mode in this mode, counting up is performed on the rising edge of an internal clock during tc2 external pin input(window pulse) is h level. the contents of treg2 are compared with the contents of up-counter. if a match is found, an inttc2 interrupt is generated, and the up-counter is cleared. the maximum applied frequency (tc2 input) must be considerably slower than the selected internal clock. example: generates an interrupt, inputting h level pulse width of 120 ms or more. (at fc = 12.5 mhz, dv1ck = 1) ldw (treg2), 0056h ; sets treg2 (120 ms 2 14 /fc = 0056h) set (eirh). ef14 ; enables inttc2 interrupt ei ld (tc2cr), 00100101b ; starts tc2 figure 2.7.3 window mode timing chart inttc2 interrupt treg2 n 0 1 2 n ? 3n ? 2 0 n ? 1 1 2 3 match detec t counter clear tc2 pin input internal clock up-counter n 2007-10-19
tmp88cu74 2003-02-17 88cu74-73 2.8 8-bit timer/counter 3 (tc3) 2.8.1 configuration figure 2.8.1 timer/counter 3 (tc3) s a b rising edge detector tc3in int4es tc3s falling inhibit capture control tc3m fc/2 12 , fc/2 13 or fs/2 4 fc/2 10 , fc/2 11 or fs/2 2 fc/2 7 , fc/2 8 h ay b c s y mpx tc3 pin capture 8-bit timer register 3a, b 2 tc3 control register source clock capture scap tc3ck tc3s clear treg3b treg3a comparator 8-bit up-counter overflow inttc3 interrupt cmp match tc3m tc3cr 2007-10-19
tmp88cu74 2003-02-17 88cu74-74 2.8.2 control the timer/counter 3 is controlled by a timer/counter 3 control register (tc3cr) and two 8-bit timer registers (treg3a and treg3b). 7 6 5 4 3 2 1 0 treg3a (00018h) read/write treg3b (00019h) read only 7 6 5 4 3 2 1 0 tc3cr (0001ah) 0 scap 0 tc3s tc3ck 0 tc3m (initial value: * 0 * 0 00* 0 ) tc3m tc3 operation mode set 0: timer/event counter 1: capture normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 slow, sleep mode 00 fc/2 12 fc/2 13 fs/2 4 fs/2 4 fs/2 4 01 fc/2 10 fc/2 11 fs/2 2 fs/2 2 ? 10 fc/2 7 fc/2 8 fs/2 7 fs/2 8 ? tc3ck tc3 source clock select [hz] 11 external clock (tc3 pin input) tc3s tc3 start select 0: stop and clear 1: start scap software capture control 0: ? 1: software capture trigger write only note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz], * : dont care note 2: set the mode, the source clock and the edge selection (int3es) when the tc3 stops (tc3s = 0). note 3: software capture can be used only in the timer and event counter mode. scap is automatically cleared to 0 after capturing. note 4: values to be loaded into timer register 3a must satisfy the following condition. treg3a>0 (in the timer and event counter mode) note 5: tc3cr is a write-only register and must not be used with any of read-modify-write instructions such as set, clr, etc. figure 2.8.2 timer register 3 and tc3 control register 2.8.3 function the timer/counter 3 has three operating modes: timer, event counter, and capture mode. when it is used in the capture mode, the noise rejection time of tc3 pin input can be set by remote control receive control register. (1) timer mode in this mode, the internal clock is used for counting up. the contents of treg3a are compared with the contents of up-counter. if a match is found, a timer/counter 3 interrupt (inttc3) is generated, and the up-counter is cleared. counting up resumes after the up-counter is cleared. the current contents of up-counter are loaded into treg3b by setting scap (bit 6 in tc3cr) to 1. scap is automatically cleared after capturing. 2007-10-19
tmp88cu74 2003-02-17 88cu74-75 table 2.8.1 source clock (internal clock) for timer/counter 3 (example: at fc = 12.5 mhz, fs = 32.8 khz) normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 tc3ck resolution [ s] maximum setting time [ms] resolution [ s] maximum setting time [ms] resolution [ s] maximum setting time [ms] resolution [ s] maximum setting time [ms] 00 01 10 327.68 81.92 10.24 83.6 20.9 2.6 655.36 163.84 10.48 167.8 41.7 5.2 488.28 122.07 8 124.5 31.1 2.0 488.28 122.07 16 124.5 31.1 4.1 slow, sleep mode tc3ck resolution [ s] maximum setting time [ms] 00 488.28 124.5 (2) event counter mode in this mode, the tc3 pin input pulses ar e used for counting up. either the rising or falling edge can be selected. edge selection is the same as for int3 pin. the contents of treg3a are compared with the contents of the up-counter. if a match is found, an inttc3 interrupt is generated and the counter is cleared. the maximum applied frequency is shown in table 2.8.2. two or more machine cycles are required for both the high and low levels of the pulse width. the current contents of up-counter are loaded into treg3b by setting scap (bit 6 in tc3cr) to 1. scap is automatically cleared to 0 after capturing. example: generates an interrupt every 0.5 s, inputting 50 hz pulses to the tc3 pin. ld (treg3a), 19h ; 0.5 s 1/50 = 25 = 19h ld (tc3cr), 00011110b ; starts tc3 table 2.8.2 source clock (external clock) for timer/counter maximum applied frequency [hz] normal1/2, idle1/2 mode slow, sleep mode fc/2 4 fs/2 4 2007-10-19
tmp88cu74 2003-02-17 88cu74-76 (3) capture mode the pulse width, period and duty of the tc3 pin input are measured in this mode, which can be used in decoding the remote control signals or distinguishing ac 50/60 hz, etc. the counter is free running by the internal clock. on the rising (falling) edge of the tc3 pin input, the current contents of counter is loaded into treg3a, then the up-counter is cleared to 0 and an intt c4 interrupt is generated. on the falling (rising) edge of the tc3 pin input, the current contents of the counter is loaded into treg3b. in this case, counting continues. on the next rising (falling) edge of the tc3 pin input, the current contents of counter are loaded into treg3a, then the counter is cleared again and an interrupt is generated. if the counter overflows before the edge is detected. ff h is set into treg3a, and the counter is cleared and an inttc3 interrupt is generated. during interrupt processing, it can be determined whether or not there is an overflow by checking whether or not the treg3a value is ff h . also, after an interrupt (capture to treg3a, or overflow detection) is generated, capture and overflow detection are halted until treg3a has been read out; however, the counter continues. as reading out treg3a resumes capture/overflow detection, treg3b must be before hand read out. figure 2.8.3 capture mode timing chart (at int4es = 0) m ? 1 source clock up-counter tc3 pin input treg3a k ? 2 n m m + 1 n? 1 0n 1 2 3 0 overflow ff (overflow) k ? 1 k 0 1 1 2 3 fe ff m k fe capture capture treg3b inttc3 interrupt reading treg3a 2007-10-19
tmp88cu74 2003-02-17 88cu74-77 2.9 8-bit timer/counter 4 (tc4) 2.9.1 configuration figure 2.9.1 timer/counter 4 (tc4) decoder comparator toggle set q clear overflow tc4ck 4 pwm / 4 pdo pin match fc/2 11 , fc/2 12 or fs/2 3 fc/2 7 or fc/2 8 fc/2 3 or fc/2 4 timer f/f4 source clock clear tc4s tff4 tc4s tc4m 8-bit timer register 4 tc4 control register 3 2 2 2 y s b a pwm output mode toggle set clear inttc4 interrupt tc4m 1 tff4 s y 8-bit up-counter treg4 tc4cr cmp c b a d mpx int4es s a b y tc4 pin 2007-10-19
tmp88cu74 2003-02-17 88cu74-78 2.9.2 control the timer/counter 4 is controlled by a timer/counter 4 control register (tc4cr) and an 8-bit timer register 4 (treg4). reset does not affect treg4. 7 6 5 4 3 2 1 0 treg4 (0001bh) write only 7 6 5 4 3 2 1 0 tc4cr (0001ch) tff4 0 tc4s tc4ck tc4m (initial value: 00 * 0 0000 ) tc4m tc4 operating mode select 00: timer 01: reserved 10: programmable divider output (pdo) mode 11: pulse width modulation (pwm) output mode normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 slow, sleep mode 00 fc/2 11 fc/2 12 fs/2 3 fs/2 3 fs/2 3 01 fc/2 7 fc/2 8 fc/2 7 fc/2 8 ? 10 fc/2 3 fc/2 4 fc/2 3 fc/2 4 ? tc4ck tc4 source clock select [hz] 11 reserved tc4s tc4 start control 0: stop and counter clear 1: start tff4 timer f/f4 control 00: clear 01: reserved 10: reserved 11: ? (note 3) write only note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz], * : dont care note 2: set the operating mode, the source clock selection, the edge selection (int4es) and timer f/f4 control when the tc4 stops (tc4s = 0) note 3: set tff4 to 11 in the timer and event counter mode and pwm mode. note 4: values to be loaded to the timer register must satisfy the following condition. 0 tmp88cu74 2003-02-17 88cu74-79 table 2.9.1 source clock (internal clock) for timer/counter 4 (example: at fc = 12.5 mhz, fs = 32.8 khz) normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 tc4ck resolution [ s] maximum setting time [s] resolution [ s] maximum setting time [s] resolution [ s] maximum setting time [s] resolution [ s] maximum setting time [s] 00 01 10 163.84 s 10.24 s 0.64 s 41.7 ms 2.6 ms 163.2 s 327.68 s 20.48 s 1.28 s 83.6 ms 5.2 ms 326 s 244.14 s 10.24 s 0.64 s 62.2 ms 2.6 ms 163.2 s 244.14 s 20.48 s 1.28 s 62.2 ms 5.2 ms 326 s slow, sleep mode tc4ck resolution [ s] maximum setting time [s] 00 01 10 244.14 s ? ? 62.2 ms ? ? (2) programmable di vider output (pdo) mode the internal clock is used for counting up. the contents of treg4 are compared with the contents of the up-counter. if a match is found, the timer f/f 4 output is toggled and the counter is cleared. timer f/f 4 output is inverted and output to the p14 ( ppo4 ) pin. when programmable divider output is executed, p14 output latch is set to 1. this mode can be used for approximate 50% duty pulse output. timer f/f 4 can be initialized by program, and it is initialized to 0 during reset. an inttc4 interrupt is generated each time the pdo output is toggled. example: output a 1024 hz pulse (at fc = 12.5 mhz) set (p1). 4 ; p14 output latch 1 ld (p1cr), 00010000b ; set output mode to p14 ld (treg4), 5fh ; 1/1024 2 7 /fc = 5fh ld (tc4cr), 00010010b ; starts tc4 figure 2.9.3 pdo mode timing chart 4 pdo pin output internal clock up-counter treg4 inttc4 interrupt n 0 n 0 1 2 n 0 1 timer f/f4 1 2 n 0 1 2 1 2 n 0 match detect 2007-10-19
tmp88cu74 2003-02-17 88cu74-80 (3) pulse width modulation (pwm) output mode pwm output with a resolution of 8 bits is possible. the internal clock is used for counting up. the contents of treg4 are compared with the contents of up-counter. if a match is found, the timer f/f 4 output is toggled. counting up resumes. and, when an overflow occurs, the timer is again toggled and the counter is cleared. timer f/f 4 output is inverted and output to the p14 ( pwm4 ) pin. when programmable divider output is executed, p14 output latch is set to 1. an inttc4 interrupt is generated when an overflow occurs. treg4 is configured a 2-stage shift register and, during output, will not switch until one output cycle is completed even if treg4 is overwritten; therefore, output can be altered continuously. also, the first time, treg4 is shifted by setting tc4s (bit 4 in tc4cr) to 1 after data are loaded to treg4. note: do not rewrite the contents of treg4 at only an inttc4 interrupt generation cycle. the contents of treg4 is rewritten by the inttc4 interrupt service routine. figure 2.9.4 pwm output mode timing chart table 2.9.2 pwm output mode (example: fc = 12.5 mhz) normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 tc4ck resolution [ s] repeat cycle [ms] resolution [ s] repeat cycle [ms] resolution [ s] repeat cycle [ms] resolution [ s] repeat cycle [ms] 00 01 10 163.84 s 10.24 s 0.64 s 41.7 ms 2.6 ms 163.2 s 327.68 s 20.48 s 1.28 s 83.6 ms 5.2 ms 326 s 244.14 s ? ? 62.5 ms ? ? 244.14 s ? ? 62.5 ms ? ? slow, sleep mode tc4ck resolution [ s] repeat cycle [ms] 00 01 10 244.14 s ? ? 62.5 ms ? ? 4 pwm pin output internal clock up-counter treg4 inttc4 interrupt n/n 0 n n + 1 ff 0 n 1 timer f/f4 1 0 1 n + 1 ff m ? 1 m match n/m m/m shift overwrite 1 cycle 2007-10-19
tmp88cu74 2003-02-17 88cu74-81 2.10 serial bus interface (sbi-ver.c) the tmp88cu74 has a 1-channel serial bus interface which employs a clocked-synchronous 8-bit serial bus interface and an i 2 c bus (a bus system by philips). the serial bus interface is connected to an external device through p31 (sda) and p30 (scl) in the i 2 c bus mode; and through p32 ( sck0 ), p32 (so0) and p30 (si0) in the clocked-synchronous 8-bit sio mode. the serial bus interface pins are also used for the p3 port. when used for serial bus interface pins, set the p3 output latches of these pins to 1, and control inputs and outputs of these pins by the i/o control register. when not used for serial bus interface pins, the pin is used as a normal i/o port. 2.10.1 configuration figure 2.10.1 serial bus interface (sbi-ver.c) intsbi interrupt sio clock control sio data control transfer control circuit i 2 c bus clock sync. + control shift register i 2 c bus data control scl sck input/ output control so0 fc/4 sbicr2/ sbisr sbidbr sbicr1 sbi control register 2/ sbi status register i 2 c bus address register sbi data buffer register sbi control register 1 si0 sda p32 p30 ( 0 sck ) (sda/so0) (scl/si0) p31 divider noise rejection circuit noise rejection circuit i2car 2007-10-19
tmp88cu74 2003-02-17 88cu74-82 2.10.2 control the following registers are used to control the serial bus interface and monitor the operation status. ? serial bus interface control register 1 (sbicr1) ? serial bus interface control register 2 (sbicr2) ? serial bus interface data buffer register (sbidbr) ? i 2 c bus address register (i 2 car) ? serial bus interface status register (sbisr) the above registers differ depending on an mode to be used. refe r to section 2.10.4 i 2 c bus mode control and 2.10.6 clocked-synchronous 8-bit sio mode control. 2.10.3 the data format in the i 2 c bus mode the data format in the i 2 c bus mode are shown in figure 2.10.2. s: start condition r/ w : direction bit ack: acknowledge bit p: stop condition figure 2.10.2 data format in i 2 c bus mode 1 1 or more 1 or more 1 or more 1 a c k a c k a c k a c k a c k data 1 1 slave address a c k a c k r / w r / w r / w p p p a c k a c k a c k s s s s (a) addressing format (b) addressing format (with restart) (c) free data format data 8 bits 1 to 8 bits 1 or more 1 data 1 to 8 bits slave address slave address data data data data 8 bits 8 bits 1 to 8 bits 1 to 8 bits 1 to 8 bits 8 bits 1 to 8 bits 1 1 1 1 1 1 1 1 2007-10-19
88cu74-83 tmp88cu74 2007-10-19 2.10.4 i 2 c bus mode control the following registers are used to control the serial bus interface (sbi-ver.c) and monitor the operation status in the i 2 c bus mode. note 1: fc: high-frequency clock [hz] note 2: set the bc to 000 before switching to 8-bit sio bus mode. note 3: sbicr1 is write-only registers, which cannot be used with any of read-modify-write instruction such as bit manipulation, etc. note 4: this i 2 c bus circuit does not support the fast mode. it supports the standard mode only. although the i 2 c bus circuit itself allows the setting of a baud rate over 100 kbps, the compliance with the i 2 c specification is not guaranteed in that case. note 1: for writing transmitted data, start from the msb (bit 7). note 2: cannot read the data which was written into sbidbr, since a write data buffer and a read data buffer are independent in sbidbr. therefore, sbidbr cannot be used with any of read-modify-write instructions such as bit manipulation, etc. note3: the data which was written into sbidbr is cleared to 0 when intsbi is generated. note: i 2 car is write-only register, which cannot be used with any of read-modify-write instruction such as bit manipulation, etc. figure 2.10.3 serial bus interface contr ol register 1, serial bus inte rface data buffer register and i 2 c bus address register in the i 2 c bus mode serial bus interface control register 1 sbicr176543210 (0020h) bc ack swrst sck (initial value: 0000 0000) bc number of transferred bits ack = 0 ack = 1 write only bc number of clock bits number of clock bits 000 8 8 9 8 001 1 1 2 1 010 2 2 3 2 011 3 3 4 3 100 4 4 5 4 101 5 5 6 5 110 6 6 7 6 111 7 7 8 7 ack acknowledge mode specification 0: acknowledge not returned to transmitter. 1: acknowledge returned to transmitter. read/ write swrst initiate a internal of sbi 0: - 1: initialized (clearing "0" after initialized) read/ write sck serial clock selection 000:reserved (note4) 001:reserved (note4) 010: 91.9 khz 011: 47.3 khz 100: 24.0 khz 101: 12.1 khz 110: 6.08 khz 111: reserved at fc = 12.5 mhz (output on scl pin) write only serial bus interface data buffer register sbidbr 76543210 (0021h) r/w i 2 c bus address register i 2 car 7 6 5 4 3 2 1 0 slave address als (initial value: 0000 0000) (0022h) sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa tmp88cu74 slave address selection write only als address recognition mode specification 0: slave address recognition 1: non slave address recognition
tmp88cu74 2003-02-17 88cu74-84 serial bus interface control register 2 7 6 5 4 3 2 1 0 sbicr2 (0023h) mst trx bb pin sbim 0 0 (initial value: 0001 00 **) mst master/slave selection 0: slave 1: master trx transmitter/receiver selection 0: receiver 1: transmitter bb start/stop generation 0: stop condition 1: start condition pin cancel interrupt service request 0: ? (cannot be cleared to 0) 1: cancel interrupt service request sbim serial bus interface operating mode selection 00: port mode (serial bus interface output disable) 01: clocked-synchronous 8-bit sio mode 10: i 2 c bus mode 11: reserved write only note 1: * : dont care note 2: switch a mode to port after confirming that the bus is free. note 3: switch a mode to i2c bus mode after confiming that input signals via port are high level. note 4: sbicr2 has write-only register bits, which can not be used with any of read-modify-write instructions such as bit manipulation, etc. note 5: clear bits 1 and 0 in sbicr2 to 0. 7 6 5 4 3 2 1 0 sbisr (0023h) mst trx bb pin al aas ad0 lrb (initial value: 0001 0000) mst master/slave selection status monitor 0: slave 1: master trx transmitter/receiver selection status monitor 0: receiver 1: transmitter bb bus status monitor 0: bus free 1: bus busy pin interrupt service request status monitor 0: intsbi occurs 1: intsbi not occurs al arbitration loss detection monitor 0: arbitration loss undetected 1: arbitration loss detected aas slave address match detection monitor 0: slave address unmatch or general call undetected 1: slave address match or general call detected ad0 general call detection monitor 0: general call undetected 1: general call detected lrb last received bit monitor 0: last received bit 0 1: last received bit 1 read only figure 2.10.4 serial bus interface control register 2 and serial bus interface status register in the i 2 c bus mode 2007-10-19
88cu74-85 tmp88cu74 2007-10-19 (1) acknowledge mode specification set the ack (bit 4 in sbicr1) to 1 for operation in the acknowledge mode. the tmp88cu74 generates an additional clock pulse for an acknowledge signal when operating in the master mode. in the transmitter mo de during the clock pulse cycle, the sda pin is released in order to receive the acknowledge signal from the receiver. in the receiver mode during the clock pulse cycle, the sda pin is set to the low level in order to generate the acknowledge signal. reset the ack for operation in the non-acknowledge mode. the tmp88cu74 does not generate a clock pulse for the acknowledge signal when operating in the master mode. in the acknowledge mode, the tmp88cu74 counts a clock pulse for the acknowledge signal when operating in the slave mode. during the clock pulse, when the received slave address is the same as the value set at the i2car or when a general call is received, the sda pin is set to the low level in order to generate the acknowledge signal. in the transmitter mode during the clock pulse cycle after matching the slave addresses or receiving a general call, the sda pin is released in order to receive the acknowledge signal from the receiver. in the receiver mode during the clock pulse cycle, the sda pin is set to the low level in order to generate the ackn owledge signal. in non-acknowledge mode, the tmp88cu74 does not count a clock pulse for the acknowledge signal when operating in the slave mode. (2) number of transfer bits the bc (bits 7 to 5 in sbicr1) is used to select a number of bits for transmitting and receiving data. since the bc is cleared to 000 as a start condition, a slave address and direction bit transmissions are always executed in 8 bits. other than these, the bc retains a specified value. (3) serial clock a. clock source the sck (bits 2 to 0 in sbicr1) is used to select a maximum transfer frequency output from the scl pin in the master mode. set a communication baud rate that meets the i 2 c bus specification, such as the shortest pulse width of tlow, based on the equations shown below. in both master mode and slave mode, a pulse width of at least 4 machine cycles is required for both high and low levels. figure 2.10.5 clock source 1/fscl t low t high t low = 2 /fc t high = 2 /fc + 8/fc fscl = 1/( t low + t high) n n fc: +ljkiuhtxhqf\forfn 6&. (bits 2 to 0 in the sbicr1) 000 001 010 011 100 101 110 4 5 6 7 8 9 10 n
tmp88cu74 2003-02-17 88cu74-86 b. clock synchronization in the i 2 c bus mode, in order to drive a bus with a wired and, a master device which pulls down a clock pulse to low will, in the first place, invalidate a clock pulse of another master device which generates a high-level clock pulse. the master device with a high-level clock pulse needs to detect the situation and implement the following procedure. the tmp88cu74 has a clock synchronization function for normal data transfer even when more than one master exists on a bus. the example explains clock sy nchronization procedures when two masters simultaneously exist on a bus. figure 2.10.6 clock synchronization as master 1 pulls down the scl pin to the low level at point a, the scl line of the bus becomes the low level. after detecting this situation, master 2 resets counting a clock pulse in the high level and sets the scl pin to the low level. master 1 finishes counting a clock pulse in the low level at point b and sets the scl pin to the high level. since master 2 holds the scl line of the bus at the low level, master 1 waits for counting a clock pulse in the high level. after master 2 sets a clock pulse to the high level at point c and detects the scl line of the bus at the high level, master 1 starts counting a clock pulse in the high level. the clock pulse on the bus is deteminded by the master device with the shortest high-level period and the master device with the longest low-level period from among those master devices connected to the bus. (4) slave address and address recognition mode specification when the serial bus interface circuit is used with an addressing format to recognize the slave address, clear the als (bit 0 in i 2 car) to 0, and set the sa (bits 7 to 1 in i 2 car) to the slave address. when the serial bus interface circuit is used with a free data format not to recognize the slave address, set the als to 1. with a free data format, the slave address and the direction bit are not recognized, and they are processed as data from immediately after start condition. (5) master/slave selection set the mst (bit 7 in sbicr2) to 1 for operating the tmp88cu74 as a master device. reset the mst for operation as a slave device. the mst is cleared to 0 by the hardware after a stop condition on the bus is detected or arbitration is lost. scl pin (master 1) scl pin (master 2) scl (bus) count reset wait count start count reset a b c 2007-10-19
tmp88cu74 2003-02-17 88cu74-87 (6) transmitter/receiver selection set the trx (bit 6 in sbicr2) to 1 for operating the tmp88cu74 as a transmitter. reset the trx for operation as a receiver. when data with an addressing format is transferred in the slave mode, the trx is set to 1 if the direction bit (r/ w ) sent from the master device is 1, and is cleared to 0 if the bit is 0. in the master mode, after an acknowledge signal is returned from the slave device with the hardware, the trx is set to 0 if a transmitted direction bit is 1, and set to 1 if it is 0. when an acknowledge signal is not returned, the current condition is maintained. the trx is cleared to 0 by the hardware after a stop condition on the bus is detected or arbitration is lost. the following table shows trx changing co nditions and trx value after changing. mode direction bit conditions trx after changing 0 0 slave mode 1 when the received slave address is the same as i 2 car 1 0 1 master mode 1 when the ack signal is returned 0 when the serial bus interface circuit is used with a free data format, the trx is not changed by hardware since the slave address and the direction bit are not recognized, and they are processed as data from immediately after start condition. (7) start/stop condition generation a start condition and 8-bit data are output on the bus by writing 1 to the mst, trx and bb when the bb (bit 5 in sbicr2) is 0. it is necessary to set the transmitting data to the data buffer register and 1 to ack beforehand. figure 2.10.7 start condition generation and slave address generation when the bb is 1, sequence of generating a stop condition is started by writing 1 to the mst, trx, and pin, and 0 to the bb. do not modify the contents of mst, trx, bb and pin until a stop condition is generated on a bus. figure 2.10.8 stop condition generation scl pin sda pin start condition slave address and the direction bit acknowledge signal 1 2 3 4 5 6 7 8 9 a6 a5 a4 a3 a2 a1 a0 r/w sda pin scl pin stop condition 2007-10-19
tmp88cu74 2003-02-17 88cu74-88 the bus condition can be indicated by reading the contetns of the bb (bit 5 in sbisr). the bb is set to 1 when a start condition on a bus is detected and is cleared to 0 when a stop condition is detected. (8) interrupt service request cancel in the master mode, a serial bus interface interrupt request (intsbi) occurs after the number of clocks which is specified by the bc and ack has been transmitted. in the slave mode, when the received slave address is the same as the value set at the i 2 car, after outputting the acknowle dge signal when a general call is received, or when data transfer is complete after matching the slave addresses or receiving a general call, an intsbi interrupt request occurs. when a serial bus interface interrupt request occurs, the pin (bit 4 in sbisr) is cleared to 0. during the time that the pin is 0, the scl pin is pulled down to the low level. either writing/reading data to/from the sbidbr sets the pin to 1. the time from the pin being set to 1 until the scl pin is released takes t low . although the pin (bit 4 in sbicr2) can be set to 1 by the program, the pin is not set to 0 when 0 is written. (9) serial bus interface operating mode the sbim (bits 3, 2 in sbicr2) is used to specify the serial bus interface operation mode. set the sbim to 10 after confirming that the serial bus interface pin is set to high level when used in the i 2 c bus mode. switch a mode to port after making sure that a bus is free. (10) arbitration lost detection monitor since more than one master device can exist simultaneously on a bus in the i 2 c bus mode, a bus arbitration procedure is implemented in order to guarantee the contents of transferred data. data on the sda line is used for bus arbitration of the i 2 c bus. the following shows an example of a bus arbitration procedure when two master devices exist simultaneously on the bus. master 1 and master 2 output the same data until point a. after master 1 outputs 1 and master 2, 0, the sda line of the bus is wired and and the sda line is pulled down to the low level by master 2. when the scl line of the bus is pulled up at point b, the slave device reads data on the sda line, that is, data in master 2. data transmitted from master 1 becomes invalid. the state in master 1 is called arbitration lost. a master device which loses arbitration releases the sda pin and the scl pin in order not to effect data transmitted from other masters with arbitration. when more than one master sends the same data at the first word, arbitration occurs continuously after the second word. 2007-10-19
tmp88cu74 2003-02-17 88cu74-89 figure 2.10.9 arbitration lost the tmp88cu74 compares levels of the sda line of the bus with those of the tmp88cu74 sda pin at the rising edge of the scl line. if the levels are unmatched, arbitration is lost and the al (bit 3 in sbisr) is set to 1. when the al is set to 1, the mst and trx are reset to 0 and the mode is switched to a slave receiver mode. the al is reset to 0 by writing/reading da ta to/from the sbidbr or writing data to the sbicr2. figure 2.10.10 example of when tmp88cu74 is a master b sda (bus) sda pin becomes 1 after losing arbitration. a b scl (bus) sda pin (master 2) sda pin (master 1) ~~~ fix sda, scl pin to high level as losing arbitration. 1 2 3 4 5 6 7 8 9 1 2 3 4 d7a d6a d5a d4a d3a d2a d1a d0a d7a d6a d5a d4a d7b d6b scl pin sda pin scl pin sda pin al mst trx accessed to sbidbr or sbicr2 master a master b 1 2 ~~~ 2007-10-19
tmp88cu74 2003-02-17 88cu74-90 (11) slave address match detection monitor the aas (bit 2 in sbisr) is set to 1 in the slave mode, in the address recognition mode (als = 0), or when receiving a slave address with the same value that sets a general call or i 2 car. when the als is 1, the aas is set to 1 after receiving the first 1-word of data. the aas is cleared to 0 by after writing/reading data to/from a data buffer register. (12) general call detection monitor the ad0 (bit 1 in sbisr) is set to 1 in the slave mode, when all 8-bit data received immediately after a start condition are 0. the ad0 is cleared to 0 when a start or stop condition is detected on the bus. (13) last received bit monitor the sda value stored at the rising edge of the scl line is set to the lrb (bit 0 in sbisr). when the contents of the lrb are read immediately after an intsbi interrupt request is generated in the acknowledge mode, and ack signal is read. (14) software reset function software reset function is used to initialize sbi, when sbi is rocked by external noise, etc. swrst (bit 0 in sbicr) is set to 1, internal reset signal pulse is generated and inputted into sbi circuit. all command registers and status registers are initialized to an initial value. swrst is automatically cleared to 0 after initializing sbi circuit. 2007-10-19
tmp88cu74 2003-02-17 88cu74-91 2.10.5 data transfer in i 2 c bus mode (1) device initialization first, set the ack in the sbicr1 to 1, the bc to 000, and the data length to 8-bit to count a clock pulse for the acknowledge signal. in addition, set the transmit frequency to the sck. next, set the slave address to the sa in the i 2 car. clear the als to 0 to set the addressing format. after confirming that the serial bus interface pin is high level, for specifying the default setting to a slave receiver mode, clear 0 to the mst, trx, and bb in the sbicr2; 1 to the pin; 10 to the sbim; and 0 to bits 1 and 0. note: to initialize the serial bus interface circuit, a constant period that the start conditions are not generated for any device is required after all devices which are connected to the bus are initialized. then, the initialization must be completed during the period. if not, other devices may start transmitting data before the serial bus interface circuit has been initialized. thus, data can not be normally received. (2) start condition and slave address generation confirm a bus free status (when bb = 0). set the ack to 1 and specify a slave address and a direction bit to be transmitted to the sbidbr. when the bb is 0, the start condition are generated and the slave address and the direction bit which are set to the sbidbr are output on a bus by writing 1 to the mst, trx, bb, and pin. an intsbi interrupt request occurs at the 9th falling edge of the scl clock cycle, and the pin is cleared to 0. the scl pin is pulled down to the low level while the pin is 0. when an interrupt request occurs, the trx changes by the hardware according to the direction bit only when an acknowledge signal is returned from the slave device. note 1: the slave address to be output to the sbidbr must be set after the bus free is detected by software. if setting of the slave address is executed before detection bus free, the current output data may be corrupted. note 2: the bus free must be confirmed by software within 98.0 s (the shortest transmitting time according to the i 2 c bus standard) after setting of the slave address to be output. only when the bus free is confirmed, set 1 to the mst, trx, bb, and pin to generate the start conditions. if the start conditions are generated without writing 1 to them, transferring may be executed by other masters between the time when the slave address to be output to the sbidbr is written and the time when 1 is written to the mst, trx, bb, and pin in the sbicr2. thus, the slave address may be corrupted. figure 2.10.11 start condition generation and slave address transfer scl pin sda pin start condition slave address + direction bit acknowledge signal from a slave device 1 2 3 4 5 6 7 8 9 a6 a5 a4 a3 a2 a1 a0 r/ w pin intsbi interrupt request 2007-10-19
tmp88cu74 2003-02-17 88cu74-92 (3) 1-word data transfer check the mst by the intsbi interrupt pr ocess after a 1-word data transfer is completed, and determine whether the mode is a master or slave. a. when the mst is 1 (master mode) check the trx and determine whether the mode is a transmitter or receiver. 1. when the trx is 1 (transmitter mode) check the lrb. when the lrb is 1, a receiver does not request data. implement the process to generate a stop condition and terminate data transfer. when the lrb is 0, the receiver requests new data. when the next transmitted data is other than 8 bits, set the bc and write the transmitted data to the sbidbr after setting ack to 1. after writing the data, the pin becomes 1, a serial clock pulse is generated for transferring a new 1-word of data from the scl pin, and then the 1-word data is transmitted. after the data is transmitted, an intsbi interrupt request occurs. the pin becomes 0 and the scl pin is pulled down to the low level. if the data to be transferred is more than one word in length, repeat the procedure from the lrb checking above. figure 2.10.12 example when bc = 000, ack = 1 2. when the trx is 0 (receiver mode) when the next transmitted data is other than 8 bits, set the bc again. set the ack to 1 and read the received da ta from the sbidbr (data which is read immediately after a slave address is sent is undefined). after the data is read, the pin becomes 1. the tmp88cu74 outputs a serial clock pulse to the scl to transfer new 1-word of data and sets the sda pin to 0 at the acknowledge signal timing. an intsbi interrupt request occurs and the pin becomes 0. the tmp88cu74 outputs a clock pulse for 1-word of data transfer and the acknowledge signal each time that received data is read from the sbidbr. figure 2.10.13 example when bc = 000, ack = 1 scl pin sda pin acknowledge signal to a transmitter 1 2 3 4 5 6 7 8 9 d7 d6 d5 d4 d3 d2 d1 pin intsbi interrupt request d0 read sbidbr new d7 scl pin sda pin acknowledge signal from a receiver 1 2 3 4 5 6 7 8 9 d7 d6 d5 d4 d3 d2 d1 pin intsbi interrupt request d0 write to sbidbr 2007-10-19
tmp88cu74 2003-02-17 88cu74-93 in order to terminate tran smitting data to a transmitter, clear the ack to 0 before reading data which is 1 word before the last data to be received. the last data does not generate a clock pulse for the acknowledge signal. after the data is transmitted and an interrupt request has o ccurred, set the bc to 001 and read the data. the tmp88cu74 generates a clock pulse for a 1-bit data transfer. since the master device is a receiver, the sda line of the bus keeps the high level. the transmitter receives the high-level signal as an ack signal. the receiver indicates to the transmitter that data transfer is complete. after 1-bit data is received and an interrupt request has occurred, the tmp88cu74 generates a stop condition and terminates data transfer. figure 2.10.14 termination of data transfer in master receiver mode b. when the mst is 0 (slave mode) in the slave mode, the tmp88cu74 operates either in normal slave mode or in slave mode after losing arbitration. in the slave mode, an intsbi interrupt request occurs when the tmp88cu74 receives a slave address or a general call from the master device, or when a general call is received and data trans fer is comple te after matching a received slave address. in the master mode, the tmp88cu74 operates in a slave mode if it is losing arbitration. an intsbi interrupt request occurs when word data transfer terminates after losing arbitration. when an intsbi interrupt request occurs, the pin (bit 4 in the sbicr2) is reset, and the scl pin is pulled down to the low level. either reading/ writing from/to the sbidbr or setting the pin to 1 releases the scl pin after taking t low time. check the al (bit 3 in the sbisr), the trx (bit 6 in the sbisr), the aas (bit 2 in the sbisr), and the ad0 (bit 1 in the sbisr) and implements processes according to conditions listed in the next table. scl pin sda pin acknowledge signal sent to a transmitter 1 2 3 4 5 6 7 8 1 d7 d6 d5 d4 d3 d2 d1 pin intsbi interrupt request d0 0 ack, read sbidbr 001 bc, read sbidbr 2007-10-19
tmp88cu74 2003-02-17 88cu74-94 table 2.10.1 operation in the slave mode trx al aas ad0 conditions process 1 1 0 the tmp88cu74 loses arbitration when transmitting a slave address and receives a slave address of which the value of the direction bit sent from another master is 1. 1 0 in the slave receiver mode, the tmp88cu74 receives a slave address of which the value of the direction bit sent from the master is 1. set the number of bits in 1 word to the bc and write transmitted data to the sbidbr. 1 0 0 0 in the slave transmitter mode, 1-word data is transmitted. check the lrb. if the lrb is set to 1, set the pin to 1 since the receiver does not request next data. then, clear the trx to 0 release the bus. if the lrb is cleared to 0, set the number of bits in a word to the bc and write transmitted data to the sbidbr since the receiver requests next data. 0 1/0 the tmp88cu74 loses arbitration when transmitting a slave address and receives a slave address or general call of which the value of the direction bit sent from another master is 0. 1 0 0 the tmp88cu74 loses arbitration when transmitting a slave address or data and terminates transferring word data. 1 1/0 in the slave receiver mode, the tmp88cu74 receives a slave address or general call of which the value of the direction bit sent from the master is 0. read the sbidbr for setting the pin to 1 (reading dummy data) or write 1 to the pin. 0 0 0 1/0 in the slave receiver mode, the tmp88cu74 terminates receiving of 1-word data. set the number of bits in a word to the bc and read received data from the sbidbr. (4) stop condition generation when the bb is 1, a sequence of generating a stop condition is started by writing 1 to the mst, trx, and pin, and 0 to the bb. do not modify the contents of the mst, trx, bb, pin until a stop condition is generated on a bus. figure 2.10.15 stop condition generation 1 mst 1 trx 0 bb 1 pin scl pin stop condition sda pin bb (read) pin 2007-10-19
tmp88cu74 2003-02-17 88cu74-95 (5) restart restart is used to change the direction of data transfer between a master device and a slave device during transferring data. the following explains how to restart when the tmp88cu74 is in the master mode. specify 0 to the mst, trx, and bb and 1 to the pin and release the bus. the sda pin retains the high level and the scl pin is released. since a stop condition is not generated on a bus, a bus is assumed to be in a busy state from other devices. check the bb until it becomes 0 to check that the scl pin of thetmp88cu74 is released. check the lrb until it becomes 1 to check that the scl line of a bus is not pulled down to the low level by other devices. af ter confirming that a bus stays in a free state, generate a start condition with procedure (2). in order to meet setup time when restarting, take at least 4.7 [ s] of waiting time by software from the time of restarting to confirm that the bus is free until the time to generate the start condition. figure 2.10.16 timing diagram when restarting thetmp88cu74 start condition sda (pin) scl pin 0 mst 0 trx 0 bb 1 pin scl (bus) lrb bb pin 1 mst 1 trx 1 bb 1 pin 4.7 [ s] (min) 2007-10-19
tmp88cu74 2003-02-17 88cu74-96 2.10.6 clocked-synchronous 8-bit sio mode control the following registers are used to control the serial bus interface (sbi-ver.c) and monitor the operation status in the clocked-synchronous 8-bit sio mode. serial bus interface control register 1 7 6 5 4 3 2 1 0 sbicr1 (00020h) sios sio inh siom 0 sck (initial value: 0000 * 000) sios indicate transfer start/stop 0: stop 1: start sioinh continue/abort transfer 0: continue transfer 1: abort transfer (automatically cleared after abort) siom transfer mode select 00: 8-bit transmit mode 01: reserved 10: 8-bit transmit/receive mode 11: 8-bit receive mode sck serial clock select 000: fc/2 5 (390 khz) 001: fc/2 6 (195 khz) 010: fc/2 7 (97.6 khz) 011: fc/2 8 (48.8 khz) 100: fc/2 9 (24.4 khz) 101: fc/2 10 (12.2 khz) 110: fc/2 11 (6.1 khz) 111: external clock (input from sck pin) write only note 1: * : dont care note 2: set the sios to 0 when setting the transfer mode or serial clock. note 3: sbicr1 is write-only register, which cannot be used with any of read-modify-write instruction such as bit manipulation, etc. serial bus interface data buffer register 7 6 5 4 3 2 1 0 sbidbr (00021h) r/w note: cannot read the data which was written into sbidbr, since a write data buffer and a read buffer are independent in sbidbr. therefore, sbidbr cannot be used with any in read-modify-write instruction such as bit manipulation, etc. serial bus interface control register 2 7 6 5 4 3 2 1 0 sbicr2 (00023h) 0 0 0 1 sbim 0 0 (initial value: **** 00 **) sbim serial bus interface operation mode selection 00: port mode (serial bus interface output disable) 01: clocked-synchronous 8-bit sio mode 10: i 2 c bus mode 11: reserved write only note 1: * : dont care note 2: switch a mode to port after data transfer is complete. note 3: switch a mode to i2c bus mode or clocked-synchronous 8-bit sio mode after confirming that input signal via port is high level. note 4: sbicr2 is write-only register, which cannot be used with any of read-modify-write instruction such as bit manipulation, etc. note 5: clear bits 7 to 5 and bits 1 to 0 in sbicr2 to 0, and set bit 4 to 1. serial bus interface status register 7 6 5 4 3 2 1 0 sbisr (00023h) 1 1 1 1 siof sef 1 1 siof serial transfer operating status monitor 0 : transfer terminated 1 : transfer in process sef shift operating status monitor 0 : shift operation terminated 1 : shift operation in process read only figure 2.10.17 control register/data buffer register/status register in sio mode at fc = 12.5 mhz (output on sck pin) 2007-10-19
tmp88cu74 2003-02-17 88cu74-97 (1) serial clock a. clock source the sck(bits 2 to 0 in sbicr1) is used to select the following functions. 1. internal clock in an internal clock mode, any of seven frequencies can be selected. the serial clock is output to the outside on the sck0 pin. the sck0 pin becomes a high level when data transfer starts. when writing (in the transmit mode) or reading (in the receive mode) data cannot follow the serial clock rate, an automatic-wait function is executed to stop th e serial clock automatic ally and hold the next shift operation until reading or writing is complete. figure 2.10.18 automatic wait function 2. external clock (sck = 111) an external clock supplied to the sck0 pin is used as the serial clock. in order to ensure shift operation, a pulse width of at least 4 machine cycles is required for both high and low levels in the ser ial clock. the maximum da ta transfer frequency is 390 khz (fc = 12.5 mhz). figure 2.10.19 the maximum data transfer frequency in the external clock input b. shift edge the leading edge is used to transmit data, and the trailing edge is used to receive data. 1. leading edge data is shifted on the leading edge of the serial clock (at a falling edge of the sck0 pin input/output). 2. trailing edge data is shifted on the trailing edge of the serial clock (at a rising edge of the sck0 pin input/output). a 0 ? automatic-wait function 0 sck pin output so0 pin output write transmitted data a b a 1 a 2 a 7 b 0 c 0 c 1 c 2 c 1 2 6 7 8 1 2 3 1 2 3 7 8 a 6 b 7 b 6 b 5 b 1 b 4 a 5 0 sck pin t sckl t sckh t sckl , t sckh > 4 tcyc note: tcyc = 4/fc (in normal mode, idle mode) 2007-10-19
tmp88cu74 2003-02-17 88cu74-98 figure 2.10.20 shift edge (2) transfer mode the siom (bits 5 and 4 in sio1cr) is used to select a transmit, receive, or transmit/receive mode. a. 8-bit transmit mode set a control register to a transmit mode and write data to the sbidbr. after the data is written, set the sios to 1 to start data transfer. the transmitted data is transferred from the sbidbr to the shift register and output to the so0 pin in synchronous with the serial clock, starting from the least significant bit (lsb). when the data is transferred to the shift register, the sbidbr becomes empty. the intsbi (buffer empty) interrupt request is generated to request new data. when the internal clock is used, the serial clock will stop and automatic-wait function will be initiated if new data is not loaded to the data buffer register after the specified 8-bit data is transmitted. when new data is written, automatic-wait function is canceled. when the external clock is used, data should be written to the sbidbr before new data is shifted. the transfer speed is determined by the maximum delay time between the time when an interrupt request is generated and the time when data is written to the sbidbr by the interrupt service program. when the transmit is started, the same value as the final bit of the last data is output until the falling edge of the sck after the siof goes 1. transmitting data is ended by cleaning the sios to 0 by the buffer empty interrupt service program or setting the sioinh to 1. when the sios is cleared, the transmitted mode ends when all data is output. in order to confirm if data is surely transmitted by the program, set the siof (bit 3 in the sbisr) to be sensed. the siof is cleared to 0 when transmitting is complete. when the sioinh is set, transmitting data stops. the siof turns 0. when the external clock is used, it is also necessary to clear the sios to 0 before new data is shifted; otherwise, dummy data is transmitted and operation ends. 0 sck pin so0 pin shift register 0 sck pin si0 pin shift register bit 0 bit 1 (a) leading edge (b) trailing edge ******** 76543210 *7654321 **765432 ***76543 ****7654 *****765 ******76 *******7 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 ******* 10****** 210***** 3210**** 43210*** 543210** 6543210* 76543210 * : dont care bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 2007-10-19
tmp88cu74 2003-02-17 88cu74-99 figure 2.10.21 transfer mode example: sio0 transfer end command (external clock) stest1: test (sbisr). sef ; if sef = 1 then loop jrs f, stest1 stest2: test (p3). 6 ; if sck = 0 then loop jrs t, stest2 ld (sbicr1), 00000111b ; sios 0 clear sios siof 0 sck pin (output) so0 pin intsio interrupt request (a) interral clock sios sef sbidbr write transmitted data a b siof 0 sck pin (input) so0 pin intsbi interrupt request (b) external clock sios sef sbidbr write transmitted data a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 4 a 5 a 6 a 7 * a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 4 a 5 a 6 a 7 * a b clear sios 2007-10-19
tmp88cu74 2003-02-17 88cu74-100 figure 2.10.22 transmitted data hold time at end of transmit b. 8-bit receive mode set a control register to a receive mode and the sios to 1 for switching to a receive mode. data is received from the si0 pin to the shift register in synchronous with the serial clock, starting from the least significant bit (lsb). when the 8-bit data is received, the data is transferred from the shift register to the sbidbr. the intsbi (buffer full) interrupt request is generated to request of reading the received data. the data is then read from the sbidbr by the interrupt service program. when the internal clock is used, the serial clock will stop and automatic-wait function will be initiated until the received data is read from the sbidbr. when the external clock is used, since shift operation is synchronized with the clock pulse provided externally, the received data should be read before new data is transferred to the sbidbr. if the received data is not read, further data to be received is canceled. the maximum transfer speed when the external clock is used is determined by the delay time between th e time when an interrupt request is generated and the time when received data is read. receiving data is ended by clearing the sios to 0 by the buffer full interrupt service program or setting the sioinh to 1. when the sios is cleared, received data is transferred to the sbidbr in co mplete blocks. the received mode ends when the transfer is complete. in order to confirm if data is surely received by the program, set the siof (bit 3 in sbidbr) to be sensed. the siof is cleared to 0 when receiving is complete. after confirming that receiving has ended, the last data is read. when the sioinh is set, receiving data stops. the siof turns 0 (the received data becomes invalid, therefore no need to read it). note: when the transfer mode is switched, the sbidbr contents are lost. in case that the mode needs to be switched, conclude receiving data by clearing the sios to 0, read the last data, and then switch the mode. 0 sck pin bit6 bit7 t sodh = 3.5/fc [s] (min) (in normal mode, idle mode) siof so0 pin 2007-10-19
tmp88cu74 2003-02-17 88cu74-101 figure 2.10.23 receive mode (example: internal clock) c. 8-bit transmit/receive mode set a control register to a transmit/receive mode and write data to the sbidbr. after the data is written, set the sios to 1 to start transmitting/receiving. when transmitting, the data is output from the so0 pin on the leading edges in synchronous with the serial clock, starting from the least significant bit (lsb). when receiving, the data is input to the si0 pin on the trailing edges of the serial clock. 8-bit data is transferred from the shift register to the sbidbr, and the intsbi interrupt request occurs. the interrupt service program reads the received data from the d ata buffer registe r and writes data to be transmitted. the sbidbr is used for both transmitting and receiving. transmitted data should always be written after received data is read. when the internal clock is used, automatic-wait function is initiated until received data is read and next data is written. when the external clock is used, since the shift operation is synchronized with the serial clock provided externally, received data is read and transmitted data is written before new shift operation is executed. the maximum transfer speed when the external clock is used is determined by the delay time between the time when an interrupt request is generated and the time when received data is read and transmitted data is written. when the transmit is started, the same value as the final bit of the last data is output until the falling edge of the sck after the siof goes 1. transmitting/receiving data is ended by cleaning the sios to 0 by the intsbi interrupt service program or setting the sioinh to 1. when the sios is cleared, received data is transferred to the sbidbr in complete blocks. the transmit/receive mode ends when the transfer is complete. in order to confirm if data is surely transmitted/received by th e program, set the siof (bit 3 in sbisr) to be sensed. the siof becomes 0 after transmitting/receiving is complete. when the sioinh is set, transmitting/receiving data stops. the siof turns 0. note: when the transfer mode is switched, the sbidbr contents are lost. in case that the mode needs to be switched, conclude transmitting/receiving data by clearing the sios to 0, read the last data, and then switch the transfer mode. siof 0 sck pin (output) si0 pin intsbi interrupt request sios sef sbidbr read received data a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 4 a 5 a 6 a 7 read received data a b clear sios 2007-10-19
tmp88cu74 2003-02-17 88cu74-102 figure 2.10.24 transmit/receive mode (example: internal clock) figure 2.10.25 transmitted data hold time at end of transmit/receive 0 sck pin bit 6 t sodh = min 4/fc [s] (in normal mode, idle mode) siof so0 pin bit 7 in last transmitted word siof so0 pin intsbi interrupt request sios sef sbidbr write transmitted data (b) c 0 c 1 c 2 c 3 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 c 4 c 5 c 6 c 7 read received data (d) b d clear sios a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 4 a 5 a 6 a 7 a c * read received data (c) write transmitted data (a) si0 pin 0 sck pin 2007-10-19
tmp88cu74 2003-02-17 88cu74-103 2.11 serial interface (sio1) the tmp88cu74 has clocked-synchronous 8-bit serial interfaces (sio1). the serial interface has an 8-byte transmit and receive data bu ffer that can automatically and continuously transfer up to 64 bits of data. the serial interface is connected to external devices via pins p02 (so1), p01 (si1), p00 ( sck1 ) for sio1. the serial interface pins are also used as port p0. when used as serial interface pins, the output latches of these pins should be set to 1 and set to input mode by p0cr. in the transmit mode, pins p01 can be used as normal i/o ports, and in the receive mode, the pins p02 can be used as normal i/o ports. 2.11.1 configuration figure 2.11.1 serial interface 2.11.2 control the serial interface is controlled by sio1 control registers (sio1cr1/sio1cr2). the serial interface status can be determined by reading sio1 status register (sio1sr). the transmit and receive data buffer is controlled by the buf (bits 2 to 0 in sio1cr2). the data buffer is assigned to addresses 0ff8h to 0fffh fo r sio1 in the dbr area, and can continuously transfer up to 8 words (bytes or nibbles) at one time. when the specified number of words has been transferred, a buffer empty (in the transmit mode) or a buffer full (in the receive mode or transmit/recei ve mode) interrupt (intsio1) is generated. when the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a fixed interval wait can be applied to the serial clock for each word transferred. four different wait times can be selected with wait (bits 4 and 3 in sio1cr2). sio control/status registers control circuit buffer control circuit transmit and receive data buffer 8 byte in dbr sio1cr1/sio1sr sio1cr2 cpu interrupt request 7 intsio1 shift clock 8-bit transfer 6 5 4 shift register 3 2 1 0 4-bit transfer serial clock so1 serial data output si1 serial data input 1 sck serial clock input/output 2007-10-19
tmp88cu74 2003-02-17 88cu74-104 sio interface 1 control register 1 7 6 5 4 3 2 1 0 sio1cr1 (00027h) sios sio inh siom sck (initial value: 0000 0000) sios indicate transfer start/stop 0: stop 1: start sioinh continue/abort transfer 0: continue transfer 1: abort transfer (automatically cleared after abort) siom transfer mode select 000: 8-bit transmit mode 010: 4-bit transmit mode 100: 8-bit transmit/receive mode 101: 8-bit receive mode 110: 4-bit receive mode normal1/2, idle1/2 mode dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 slow, sleep mode 000 fc/2 13 fc/2 14 fs/2 5 fs/2 5 fs/2 5 001 fc/2 8 fc/2 9 fc/2 8 fc/2 9 010 fc/2 6 fc/2 7 fc/2 6 fc/2 7 011 fc/2 5 fc/2 6 fc/2 5 fc/2 6 sck 111 external clock (input from sck pin) write only note 1: set sios to 0 and sioinh to 1 when setting the transfer mode or serial clock. note 2: sio1cr1 is write-only registers, which cannot access any of in read-modify-write instruction such as bit operate, etc. sio interface 1 control register 2 7 6 5 4 3 2 1 0 sio1cr2 (00028h) wait buf (initial value: ***0 0000) wait wait control always 0 (except 8 bit transmit/receive modes) 00: t f = t d (non-wait) 01: t f = 2t d 10: t f = 4t d (wait) 11: t f = 8t d buf number of transfer words buffer address used sio1 000: 1 word transfer 00ff8h 001: 2 words transfer 00ff8 - 00ff9h 010: 3 words transfer 00ff8 - 00ffah 011: 4 words transfer 00ff8 - 00ffbh 100: 5 words transfer 00ff8 - 00ffch 101: 6 words transfer 00ff8 - 00ffdh 110: 7 words transfer 00ff8 - 00ffeh 111: 8 words transfer 00ff8 - 00fffh write only figure 2.11.2 sio interface 1 control registers (1/2) output on sck 1 pin serial clock select 2007-10-19
tmp88cu74 2003-02-17 88cu74-105 note 1: t f : frame time, t d : data transfer time note 2: the lower 4 bits of each buffer are used during 4-bit transfers. zeros (0) are stored to the upper 4 bits when receiving. note 3: transmitting starts at the lowest address. received data are also stored starting from the lowest address to the highest address. for example, in the case of si o, the first buffer address transmitted is 00ff8h. note 4: the value to be loaded to buf is held after transfer is completed. note 5: set the sios to 0 when setting the transfer mode or serial clock. note 6: * : dont care note 7: sio1cr2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. figure 2.11.3 sio interface 1 control registers (2/2) 7 6 5 4 3 2 1 0 sio1sr (00027h) siof sef 1 1 1 1 1 1 siof serial transfer operating status monitor 0: transfer terminated 1: transfer in process sef shift operating status monitor 0: shift operation terminated 1: shift operation in process read only figure 2.11.4 sio interface 1 status register (1) serial clock a. clock source sck (bits 2 to 0 in sio1cr1) is able to select the following: 1. internal clock any of four frequencies can be selected. the se rial clock is output to the outside on the sck1 pin. the sck1 pin goes high when transfer starts. when data writing (in the transmit mode) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial cl ock rate, there is a wait function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. table 2.11.1 serial clock rate serial clock maximum transfer rate dv7ck = 0 dv7ck = 1 dv1ck = 0 dv1ck = 1 dv1ck = 0 dv1ck = 1 slow, sleep mode fc = 12.5 mhz fs = 32.768 khz fc/2 13 [hz] fc/2 8 fc/2 6 fc/2 5 fc/2 14 [hz] fc/2 9 fc/2 7 fc/2 6 fs/2 5 [hz] fc/2 8 fc/2 6 fc/2 5 fs/2 5 [hz] fc/2 9 fc/2 7 fc/2 6 fs/2 5 [hz] ? ? ? 1.50 kbit/s 48.8 185 390 1 kbit/s ? ? ? note: 1 kbit = 1024 bits 1 sck pin t d t f 2007-10-19
tmp88cu74 2003-02-17 88cu74-106 figure 2.11.5 clock source (internal clock) 2. external clock an external clock connected to the sck1 pin is used as the serial clock. in this case, the p00 ( sck1 ) output latch must be set to 1. to ensure shifting, a pulse width of at least 4 machine cycles is required. thus, the maximum transfer speed is 390 kbit/s. (at fc = 12.5 mhz). b. shift edge the leading edge is used to transmit, and the trailing edge is used to receive. 1. leading edge transmitted data are shifted on the leadin g edge of the serial clock (falling edge of the sck1 pin input/output). 2. trailing edge received data are shifted on the trailing edge of the serial clock (rising edge of the sck1 pin input/output). 1 sck pin input t sckh note: tcyc = 4/fc (in noraml1/2, idle1/2 modes) 4/fs (in slow, sleep modes) t sckl t sckl , t sckh > 4tcyc a 0 automatically wait function 1 sck pin output so1 pin output written transmit data to the dbr a b a 1 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2007-10-19
tmp88cu74 2003-02-17 88cu74-107 figure 2.11.6 shift edge (2) number of bits to transfer either 4-bit or 8-bit serial transfer can be selected. when 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer register are used. the upper 4 bits are cleared to 0 when receiving. the data is transferred in sequence starting at the least significant bit (lsb). (3) number of words to transfer up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be transferred continuously. the number of words to be transferred is loaded to buf in siobcr. an intsio interrupt is generated when the specified number of words has been transferred. if the number of words is to be changed during transfer, the serial interface must be stopped before making the change. 1 sck pin so1 pin shift register bit 0 bit 1 bit 2 bit 3 3210 * 321 **32 ***3 (a) leading edge 1 sck pin si1 pin shift register 0 *** 10** 3210 (b) trailing edge **** 210* * : dont care bit 1 bit 2 bit 3 bit 0 2007-10-19
tmp88cu74 2003-02-17 88cu74-108 figure 2.11.7 number of bits to transfer (example: 4-bit serial transfer) (4) transfer mode siom (bits 5 to 3 in sio1cr) is used to select the transmit, receive, or transmit/receive mode. a. 4-bit and 8-bit transmit modes in these modes, the sio1cr1 is set to the transmit mode and then the data to be transmitted first are written to the data buffer registers (dbr). after the data are written, the transmission is started by setting sios to 1. the data are then output sequentially to the so1 pin in synchronous with the serial clock, starting with the least significant bit (lsb). as soon as the lsb has been output, the data are transferred from the data buffer register to the shift register. when the final data bit has been transferred and the data buffer register is empty, an intsio (buffer empty) interrupt is generated to request the next transmitted data. when the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next transmitted data are not loaded to the data buffer register by the time the number of data words specified with the buf has been transmitted. writing even one word of data cancels the automatic-wait; therefore, when transmitting two or more words, always write the next word before transmission of the previous word is completed. note: waits are also canceled by writing to a dbr not being used as a transmit data buffer register; therefore, during sio do not use such dbr for other applications. when an extern al clock is used, the data must be written to the data buffer register before shifting next data. thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. 1 sck pin so1 pin intsio interrupt 1 sck pin so1 pin intsio interrupt 1 sck pin si1 pin intsio interrupt a 0 a 1 a 2 a 3 (a) 1 word transmit a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 (b) 3 words transmit a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 (c) 3 words receive 2007-10-19
tmp88cu74 2003-02-17 88cu74-109 the transmission is ended by clearing sios to 0 at the time that the final bit of the data being shifted out has been transferred. that the transmission has ended can be determined from the status of siof (bit 7 in sio1sr) because siof is cleared to 0 when a transfer is completed. when an external clock is used, it is also necessary to clear sios to 0 before shifting the next data; otherwise, dummy data will be transmitted and the operation will end. figure 2.11.8 transfer mode (example: 8-bit, 1 word transfer) siof 1 sck pin (output) so1 pin intsio interrupt sios sef dbr clear sios a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 (a) internal clock a 4 a 5 a 6 a 7 a b clear sios write (a) a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 4 a 5 a 6 a 7 a b (b) external clock siof 1 sck pin (output) so1 pin intsio interrupt sios sef dbr write (b) write (a) write (b) 2007-10-19
tmp88cu74 2003-02-17 88cu74-110 figure 2.11.9 transmitted data hold time at end of transmit b. 4-bit and 8-bit receive modes after setting the control registers to the receive mode, set sios to 1 to enable receiving. the data are then transferred to the shift register via the si pin in synchronous with the serial clock. when one word of data has been received, it is transferred from the shift register to the data buffer register (dbr). when the number of words specified with the buf has been received, an intsio (buffer full) interrupt is generated to request th at these data be read out. the data are then read from the data buffer registers by the interrupt service program. when the internal clock is used, and the previous data are not read from the data buffer register before the next data are received, the serial clock will stop and an automatic-wait will be initiated until the data are read. a wait will not be initiated if even one data word has been read. note: waits are also canceled by reading a dbr not being used as a received data buffer register is read; therefore, during sio do not use such dbr for other applications. when an external clock is used, the shift operation is synchronized with the external clock; therefore, the previous data are read before the next data are transferred to the data buffer register. if the previous data have not been read, the next data will not be transferred to the data buffer register and the receiving of any more data will be canceled. when an external clock is used, the maximum transfer speed is determined by the delay between the time when the interrupt request is generated and when the data received have been read. clear sios to 0 to end receiving. when sios is cleared, the current data are transferred to the buffer in 4-bit or 8-bit blocks. the receiving mode ends when the transfer is completed. siof is cleared to 0 when receiving is ended and thus can be sensed by program to co nfirm that receiving has ended. note: the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by clearing sios to 0, read the last data and then switch the transfer mode ? 1 sck pin t sodh = 3.5/fc [s] (min) (in the normal1/2, idle1/2 modes) = 3.5/fs [ s ] ( min ) ( in the slow , sleep modes ) siof so1 pin bit7 2007-10-19
tmp88cu74 2003-02-17 88cu74-111 figure 2.11.10 receive mode (example: 8-bit, 1 word, internal clock) c. 8-bit transmit/receive mode after setting the control registers to the 8-bit transmit/receive mode, write the data to be transmitted first to the data buffer registers (dbr). after that, enable transceiving by setting sios to 1. when transmitting, the data are output from the so1 pin at leading edges of the serial clock. when receiving, the data are input to the si1 pin at the trailing edges of the serial clock. 8-bit data are transferred from the shift register to the data buffer register. an intsio interrupt is generated when the number of data words specified with the buf has been transferred. the interrupt service program reads the received data from the data buffer registe r and then writes th e data to be transmitte d. the data buffer register is used for both transmitting and receiving; therefore, always write the data to be transmitted after reading the received data. when the internal clock is used, a wait is initiated until the received data are read and the next data are written. note: waits are also canceled by reading a dbr not being used as a received data buffer register is read; therefore, during sio do not use such dbr for other applications. when an external clock is used, the shift operation is synchronized with the external clock; therefore, it is necessary to read the received data and write the data to be transmitted next before starting the next shift operation. when an external clock is used, the transfer speed is determined by the maximum delay between generation of an interrupt request and the received data are read and the data to be transmitted next are written. clear sios to 0 to enable the transmit mode. when sios is cleared, the current data are transferred to the data buffer register in 8-bit blocks. the transmit mode ends when the transfer is completed. siof is cleared to 0 when receiving is ended and thus can be sensed by program to confirm that receiving has ended. note: the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by clearing sios to 0, read the last data and then switch the transfer mode. siof si1 pin input intsio interrupt sios sef dbr read out a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 4 a 5 a 6 a 7 read out a b clear sios 1 sck pin (output) 2007-10-19
tmp88cu74 2003-02-17 88cu74-112 figure 2.11.11 transmit/receive mode (example: 8-bit, 1 word, internal clock) figure 2.11.12 transmitted data hold time at end of transmit/receive siof so1 pin intsio interrupt sios sef dbr write (b) c 0 c 1 c 2 c 3 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 c 4 c 5 c 6 c 7 read out (d) b d clear sios a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 4 a 5 a 6 a 7 a c read out (c) write (a) si1 pin 1 sck pin output 1 sck pin bit6 siof so1 pin bit7 t sodh = 4/fc [s] (min) (in the normal1/2, idle1/2 modes) = 4/fs [s] (min) (in the slow, sleepmodes) t sodh 2007-10-19
tmp88cu74 2003-02-17 88cu74-113 2.12 8-bit ad converter (adc) the tmp88cu74 each have an 8-channel mu ltiplexed-input 12-bit successive approximate type ad converter with sample and hold. 2.12.1 configuration figure 2.12.1 ad converter 2.12.2 control the ad converter is controlled by the ad converter control register (adccr). the operating state of the ad converter is confirmed by reading eocf in adccr. the ad conversion value is confirmed by reading the contents of ad conversion value registers. ad conversion result register 7 6 5 4 3 2 1 0 adcdr (0000fh) read only figure 2.12.2 ad conversion result register p4cr, p5cr tap decoder successive approximate circuit control circuit adccr adcdr ladder resistors r/2 r r r/2 vass varef stop ainds analog input multiplexer ain0 ain1 ain10 ain11 a b k l y en s sample and hold sain ainds sampling clock ads eocf shift clock 12 8 8 analog comparator reference voltage p4, p5 input/output control register ad converter control register ad conversion result register 4 to to to en 2007-10-19
tmp88cu74 2003-02-17 88cu74-114 ad converter control register 7 6 5 4 3 2 1 0 adccr (0000eh) eocf ads ack ainds sain (initial value: 0000 0000) sain analog input selection 0000: ain0 select 1000: ain8 select 0001: ain1 select 1001: ain9 select 0010: ain2 select 1010: ain10 select 0011: ain3 select 1011: ain11 select 0100: ain4 select 1100: reserved 0101: ain5 select 1101: reserved 0110: ain6 select 1110: reserved 0111: ain7 select 1111: reserved ainds analog input control 0: enable 1: disable ack conversion time selection 0: 184/fc [s]: 23 s (fc = 8 mhz) 1: 736/fc [s]: 59 s (fc = 12.5 mhz) ads ad conversion start 0: ? 1: ad conversion start r/w eocf end of ad conversion flag 0: under conversion or before conversion 1: end of conversion read only note 1: select analog input when ad converter stops. note 2: the ads is automatically cleared to 0 after starting conversion. note 3: the eocf is cleared to 0 when reading the adcdr. note 4: the eocf is read-only. note 5: (ack = 0 at fc 8 mhz) note 6: when stop or slow mode is activated, the ad control registers are initialized. after normal mode is resumed, set both the ad control registers again if necessary. figure 2.12.3 ad converter control register and ad conversion result register 2.12.3 operation analog reference voltage on high si de is applied to the varef pin ; on the low side, to the vass pin. the reference voltage between varef and vass is divided a ladder resistor and compared with the analog voltage input for ad conversion. (1) start of ad conversion first, set the corressponding p4cr and p5cr bi t to 0 for analog input. clear the ainds (bit 4 in adccr) to 0 and select one of twelve analog input ain11-ain0 with the sain (bits 3 to 0 in adccr). note: the pin that is not used as an analog input can be used as regular input/output pins. during conversion, do not perform output instruction to maintain a precision for all of the pins. ad conversion is started by setting the ads (bit 6 in adccr) to 1. conversion is accomplished in 59 machine cycles (184/fc [s]). the eocf (bit 7 in adccr) is set to 1 at end of conversion. when setting the ads to 1 under ad conversion, the ad converte r circuit is initialized and the ad conversion try again from start. the sampling of the analog input voltage is excuted at 4 machine cycles after setting the ads to 1. note: the circuit of sample and hold is included in a capacitor of (12 pf (typ.)) through a register (5 k (typ.)). therefore, until 4 machine cycles is over, this capacitor must be charged. 2007-10-19
tmp88cu74 2003-02-17 88cu74-115 (2) reading of ad conversion result after the end of conversion, read the conversion result from the adcdr. the eocf is automatically cleared to 0 when reading the adcdr. (3) ad conversion in stop mode when the mcu places in the stop mode during the ad conversion, the conversion is terminated and the adcdr contents become indefinite. however, if the stop mode is started after the end of conversion (eocf = 1), the adcdr contents are held. figure 2.12.4 ad conversion timing chart (ack = 1) example: ; ain select ld (adccr), 00100100b ; selects ain4, ack = 1 ; ad convert start set (adccr). 6 ; ads = 1 sloop: test (adccr). 7 ; eocf = 1 ? jrs t, sloop ; result data read ld (9eh), (adcdr) result result invalid invalid conversion time conversion time 736/fc [s] 736/fc [s] ads adcdr eocf read star t invalid read star t star t 2007-10-19
tmp88cu74 2003-02-17 88cu74-116 figure 2.12.5 analog input voltage vs ad conversion result (typ.) 0 1 2 3 253 254 255 256 01h 02h 03h fdh feh ffh varef ? vass 256 analog input voltage conversion result 2007-10-19
tmp88cu74 2003-02-17 88cu74-117 2.13 vacuum fluorescent tube (vft) driver circuit the tmp88cu74 features built-in high-breakdown voltage output buffers for directly driving fluorescent tubes, and a display control circuit used to automatically transfer display data to the output port. the segment and the digit, as it is the vft drive circuit which included in the usual products, are not allocated. the segment and the digit can be freely allocated in the timing (t0 to t15) which is specified according to the display tube types and the layout. 2.13.1 functions (1) 37 high-breakdown voltage output buffers built-in. ? large current output pin (typ. 20 ma) 37 (v0 to v36) there is also the vkk pin used for the vft drive power supply. (2) the dynamic lighting system makes it possible to select 1 to 16 digits (t0 to t15) by program. (3) pins not used for vft driver can be used as general-purpose ports. ? pins can be selected using the vsel (bits 4 to 0) in vft control register1 bit by bit. (4) display data (112 bytes in dbr) are automatically transferred to the vft output pin. (5) brightness level can be adjusted in 8 steps using the dimmer function. (6) table 2.13.1 shown in setting of display time. table 2.13.1 setting of display time dv1ck = 0 [s] dv1ck = 1 [s] 2 10 /fc 2 11 /fc 2 12 /fc 2 13 /fc 2 10 /fc 2 11 /fc 2 12 /fc 2 13 /fc 2007-10-19
tmp88cu74 2003-02-17 88cu74-118 2.13.2 configuration figure 2.13.1 vacuum fluorescent tube (vft) driver circuit t0 to t15 v0 v1 v2 v3 v4 v5 v34 v35 v36 fc internal data bus display data memory (112 bytes in dbr) vft timing generator output data latch high-breakdown voltage output display control register 2 display control register 1 2007-10-19
tmp88cu74 2003-02-17 88cu74-119 2.13.3 control the vft driver circuit is controlled by the vft control registers (vftcr1, vftcr2). reading vftsr determines the vft operating status. switching the mode from normal1/2 to slow or stop puts the vft driver circuit into blanking state, and sets segment outputs and digit outputs are cleared to 0. thus, ports p6 to p9, and pd function as general-purpose output ports with pull-down. vft control register 1 7 6 5 4 3 2 1 0 vftcr1 (00029h) blk sdt vsel (initial value: 0000 0000) blk vft display control 0: display enable 1: disable dv1ck = 0 [s] dv1ck = 1 [s] 00 2 10 /fc 2 10 /fc 01 2 11 /fc 2 11 /fc 10 2 12 /fc 2 12 /fc sdt display time select (tdisp) (display time of 1 digit) 11 2 13 /fc 2 13 /fc vsel automatic display select (when using vft driver (automatic display), v31 to v0 are only used to output vft.) pins which are not selected by the output pins other than the above-mentioned pins can be used as general-purpose input/output pins. (when using as a general-purpose input/output pin, the display data which corresponds to the pin must be set to 0) 00000: 32 (v31 to v0) 00001: 33 (v32 to v0) 00010: 34 (v33 to v0) 00011: 35 (v34 to v0) 00100: 36 (v35 to v0) 00101: 37 (v36 to v0) write only note 1: fc: high frequency clock note 2: vftcr1 is write-only register, which cannot use any of in read-modify-write instruction such as bit operate, etc. figure 2.13.2 vft control register 1 2007-10-19
tmp88cu74 2003-02-17 88cu74-120 vft control register 2 7 6 5 4 3 2 1 0 vftcr2 (0002ah) dim sta (initial value: 000 * 0000) dim dimmer time select 000: (15/16) tdisp (s) 001: (14/16) tdisp (s) 010: (12/16) tdisp (s) 011: (10/16) tdisp (s) 100: (8/16) tdisp (s) 101: (6/16) tdisp (s) 110: (4/16) tdisp (s) 111: (2/16) tdisp (s) sta number of state (display) 0000: 1 display mode (t0) 0001: 2 display mode (t1 to t0) 0010: 3 display mode (t2 to t0) 0011: 4 display mode (t3 to t0) 0100: 5 display mode (t4 to t0) 0101: 6 display mode (t5 to t0) 0110: 7 display mode (t6 to t0) 0111: 8 display mode (t7 to t0) 1000: 9 display mode (t8 to t0) 1001: 10 display mode (t9 to t0) 1010: 11 display mode (t10 to t0) 1011: 12 display mode (t11 to t0) 1100: 13 display mode (t12 to t0) 1101: 14 display mode (t13 to t0) 1110: 15 display mode (t14 to t0) 1111: 16 display mode (t15 to t0) write only note 1: vftcr2 is write-only register, which cannot use any of in read-modify-write instruction such as bit operate, etc. note 2: even if a number of the display digit is set a pin which is equal to the digit dose not output. it is necessary to write data to the data buffer which corresponds to the digit according to the display timing (t0 to t15). note 3: * : dont care 7 6 5 4 3 2 1 0 vftsr (00029h) wait wait vft operational status monitor 0: vft display in operation 1: vft display operation disabled read only figure 2.13.3 vft control register 2, vft status register (1) setting of display mode vft display mode is set by vft control register 1 (vftcr1) and vft control register 2 (vftcr2). vft control register 1 (vftcr1) sets 1 display time (tdisp) and the number of display lines (vsel), and vft control register 2 (vftcr2) sets dimmer timer (dim) and state (sta). (blk of vftcr1 must be set to 1.) the segments and the digits are not fixed, so that they can be freely allocated. however the number of states must be specified according to the number of digits of vft which you use. (see display operation in section 2.13.4 for display timing and data setting procedures.) 2007-10-19
tmp88cu74 2003-02-17 88cu74-121 (2) display data setting data are converted into vft display data by instructions. the converted data stored in the display data buffer (addresses 00f80 to 00fcf in dbr) are automatically transferred to the vft driver circuit, then transferred to the high-breakdown voltage output buffer. thus, to change the display p attern, just chan ge the data in the display data buffer. bits in the vft segment (dot) and display data area correspond one to one. when data are set to 1, the segments corresponding to the bits light. the display data buffer is assigned to the dbr area shown in figure 2.13.4. (the display data buffer can not be used as data memory) bit 0 to 7 0 to 7 0 to 7 0 to 7 0 to 4 timing 00f80h 00f90h 00fa0h 00fb0h 00fc0h t0 00f81h 00f91h 00fa1h 00fb1h 00fc1h t1 00f82h 00f92h 00fa2h 00fb2h 00fc2h t2 00f83h 00f93h 00fa3h 00fb3h 00fc3h t3 00f84h 00f94h 00fa4h 00fb4h 00fc4h t4 00f85h 00f95h 00fa5h 00fb5h 00fc5h t5 00f86h 00f96h 00fa6h 00fb6h 00fc6h t6 00f87h 00f97h 00fa7h 00fb7h 00fc7h t7 00f88h 00f98h 00fa8h 00fb8h 00fc8h t8 00f89h 00f99h 00fa9h 00fb9h 00fc9h t9 00f8ah 00f9ah 00faah 00fbah 00fcah t10 00f8bh 00f9bh 00fabh 00fbbh 00fcbh t11 00f8ch 00f9ch 00fach 00fbch 00fcch t12 00f8dh 00f9dh 00fadh 00fbdh 00fcdh t13 00f8eh 00f9eh 00faeh 00fbeh 00fceh t14 00f8fh 00f9fh 00fafh 00fbfh 00fcfh t15 segment v0 to v7 v8 to v15 v16 to v23 v24 to v31 v32 to v36 note: writing 0 in 7 to 5 bit of address 00fc0h to 00fcfh in dbr. figure 2.13.4 vft display data buffer memory (dbr) 2.13.4 display operation as the above-mentioned, the segment and the digit are not allocated. after setting of the display timing for the number of digits according to the using vft and storing the segment and digit data according to the respective timi ngs, clearing blk in vftcr1 to 0 starts vft display. figure 2.13.5 shows the vft drive pulse and figure 2.13.6, figure 2.13.7 show the display operation. 2007-10-19
tmp88cu74 2003-02-17 88cu74-122 figure 2.13.5 vft drive waveform and display timing 2.13.5 example of display operation (1) for conventional type vft when using the conventional type vft, the output timing of the digits is specified to output 1 digit for 1 timing. data must be set to output the pins which are specified to the digit in sequence. the following figure shows a data allocation of the display data buffer (dbr) and the output timing when vft of 10 digits is used and v0 to v9 pins are allocated as the digit outputs. (when data is first written by the data buffer which corresponds to the digit pin, it is unnecessary to rewrite the data later.) t 9 8 7 6 5 4 3 2 1 0 address 0 f 9 9 0 f 9 8 0 f 8 7 0 f 8 6 0 f 8 5 0 f 8 4 0 f 8 3 0 f 8 2 0 f 8 1 0 f 8 0 v0 v1 v2 v3 v4 v5 v6 v7 lsb msb 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 v8 v9 lsb 0 1 1 0 seg seg seg seg seg seg msb * * * * * * * * * * * * figure 2.13.6 example of conventional type vft driver pulse one display time (tdisp) dimmer time (dim) t15 t14 t13 t0 seg/deg g1 g0 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 seg (write change by display data) g2 g3 g4 g5 g6 g7 g8 g9 2007-10-19
tmp88cu74 2003-02-17 88cu74-123 (2) for grid scan type vft when using the grid scan type vft, two or more grids must be simultaneously selected to turn the display pattern which contains two or more grids on. additionally, the timing and the data must be determined to set the grid scan mode as follows. ? when the display pattern which is fully set in the respective grids is turned on, only the grids which correspond as ever must be scanned in sequence to turn on the display pattern. (timing of t8 to t3 in the following figure) ? when the display pattern which contains two or more grids is turned on, two or more corresponding grids are simultaneously selected to turn on the display pattern. (timing of t2 to t0 in the following figure) t 8 7 6 5 4 3 2 1 0 address 0 f 8 8 0 f 8 7 0 f 8 6 0 f 8 5 0 f 8 4 0 f 8 3 0 f 8 2 0 f 8 1 0 f 8 0 v0 v1 v2 v3 v4 v5 lsb msb 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 figure 2.13.7 grid scan type display vacuum fluorescent tube ware 2.13.6 port function (1) high-breakdown voltage buffer to drive fluorescent display tube, clears the port output latch to 0. the port output latch is initialized to 0 at reset. it is recommended that ports p5, p6, p7, p8 and p9 should be used as vft driver output. precaution for using as general-purpose i/o pins are follows. note: when not using a pin which is pulled down to pin v kk (rk = typ. 80 k ), it must be set to open. it is necessary to clear the port output latch and the data buffer memory (dbr) to 0. 1. ports p6 to p9 when a part of p6 to p9 is used as the input/output pin (vft driver in operation), the data buffer memory (dbr) of the segment which is also used as the input/output pin must be cleared to 0. t8 t7 t6 t5 t4 t3 t2 t1 t0 seg (a to g (dig 1 to 6)) s1 s2 s3 s4 g0 g1 g2 g5 g3 g4 2007-10-19
tmp88cu74 2003-02-17 88cu74-124 2. port pd vft output and usual input/output are controlled by vsel of vft control register in bits. when a pin which is pulled down to pin v kk is used as usual output or input, the following cautions are required. (a) when outputting when level l is output, a port which is pulled down to pin v kk is pin v kk voltage. such processes as clamping with the diode as shown in figure 2.13.8. (a) are necessary to prevent pin v kk voltage applying to the external circuit. (b) when inputting when the external data is input, th e port output latch is cleared to 0. the input threshold is the same as that of the other usual input/output port. however it is necessary to drive r k (typ. 80 k ) sufficiently because of pulled down to pin v kk . figure 2.13.8 external circuit interface r k r vdd v kk r1 (a) at output r k r vdd v kk r1 (b) at input 2007-10-19
tmp88cu74 2003-02-17 88cu74-125 input/output circuitry (1) control pins the input/output circuitries of the tmp88cu74 control pins are shown below. control pin i/o circuitry remarks xin xout input output resonator connecting pins (high-frequency) r f = 1.2 m (typ.) xtin xtout input output resonator connecting pins (low-frequency) r f = 6 m (typ.) r o = 220 k (typ.) reset i/o hysteresis input r in = 220 k (typ.) r = 1 k (typ.) stop / 5 int input hysteresis input r = 1 k (typ.) test input pull-down resistor r in = 70 k (typ.) r = 1 k (typ.) note: the test pin of the tmp88pu74 does not have a pull-down resistor. fix the test pin at low-level. r o osc. enable vdd vdd r f xin xout fc ? r o osc. enable vdd vdd r f xtin xtout fs ? address-trap-reset watchdog-timer-reset system-clock-reset r vdd r in r vdd r in r p20 stop / 5 int 2007-10-19
tmp88cu74 2003-02-17 88cu74-126 (2) C 1. input/output ports port i/o input/output circuitry remarks p00 p01 p1 i/o tri-state i/o hysteresis input r = 1 k (typ.) p02 to p07 i/o tri-state i/o r = 1 k (typ.) p2 i/o sink open drain output hysteresis input r = 1 k p3 i/o tri-state i/o hysteresis input programmable k open-drain r = 1 k (typ.) p4 p5 i/o tri-state i/o r = 1 k (typ.) p6 p7 p8 p9 i/o source open drain i/o high-breakdown voltage r k = 80 k (typ.) r = 1 k (typ.) r1 = 200 k (typ.) initial high-z r vdd disable initial high-z disable r vdd initial high-z r initial high-z disable r vdd r initial high-z vdd disable open-drain r1 r k r vdd vkk initial high-z 2007-10-19
tmp88cu74 2003-02-17 88cu74-127 (2) C 2. input/output ports port i/o input/output circuitry remarks pd i/o source open drain i/o high-breakdown voltage r k = 80 k (typ.) r = 1 k (typ.) r1 = 200 k (typ.) r k r vdd r1 vkk initial high-z 2007-10-19
tmp88cu74 2003-02-17 88cu74-128 electrical characteristics absolute maximum ratings (v ss = 0 v) parameter symbol pins ratings unit supply voltage v dd ? 0.3 to 6.5 input voltage v in ? 0.3 to v dd + 0.3 v out1 p2, p3 (at open-drain) ? 0.3 to v dd + 0.3 output voltage v out2 p6, p7, p8, p9, pd v dd ? 40 to v dd + 0.3 v i out1 p0, p1, p2, p3, p4, p5 ports 3.2 output current (per 1 pin) i out2 p6, p7, p8, p9, pd ports ? 25 i out1 p0, p1, p3, p4, p5 ports ? 40 i out2 p0, p1, p2, p3, p4, p5 ports 120 output current (total) i out3 p6, p7, p8, p9, pd ports ? 160 ma power dissipation [topr = 25 c] pd (note 2) 1200 mw soldering temperature (time) tsld 260 (10 s) storage temperature tstg ? 55 to + 125 operating temperature topr ? 30 to + 70 c note 1: the absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. note 2: power dissipation (pd); for pd, it is necessary to decrease 14.3 mw/ c. recommended operating conditions (v ss = 0 v, topr = ? 30 to 70 c) parameter symbol pins conditions min max unit normal1, 2 modes fc = 12.5 mhz idle1, 2 modes 4.5 fs = 32.768 khz slow modes sleep modes 2.7 supply voltage v dd stop modes 2.0 5.5 v ih1 except hysteresis input v dd 0.70 v ih2 hysteresis input v dd 4.5 v v dd 0.75 input high voltage v ih3 v dd < 4.5 v v dd 0.90 v dd v il1 except hysteresis input v dd 0.30 v il2 hysteresis input v dd 4.5 v v dd 0.25 input low voltage v il3 v dd < 4.5 v 0 v dd 0.10 v xin, xout v dd = 4.5 to 5.5 v (note 2) 8 12.5 mhz clock frequency fc xtin, xtout v dd = 2.7 to 5.5 v 30.0 34.0 khz note 1: the recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified ac/dc values etc.), malfunction may occur. thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. note 2: clock frequency fc: supply voltage range is specified in normal 1/2 mode and idle 1/2 mode. 2007-10-19
tmp88cu74 2003-02-17 88cu74-129 how to calculate power consumption. with the tmp88cu74, a pull-down resistor (r k = 80 k typ.) can be built into a vft driver using mask option (port by port). the share of vft driver loss (vft driver output loss + pull-down resistor (r k ) loss) in power consumption pmax is high. when using a fluorescent display tube with a large number of segments, the maximum power consumption p d must not be exceeded. power consumption pmax = operating power consumption + normal output port loss + vft driver loss where, 1. operating power consumption: v dd i dd 2. normal power consumption: i out2 0.4 3. vft driver loss: vft driver output loss + pull-down resistor (r k ) loss example: when ta = 10 to 50 c and a fluorescent display tube with segment output = 3 ma, digit output = 15 ma, vxx =? 25 v is used. operating conditions: v dd = 5 v 10%, fc = 12.5 mhz, vft dimmer time (dim) = (14/16) tseg: power consumption pmax = (1) + (2) + (3) where, segments pin = x grid pin = y, y = 2 1. operating power consumption: v dd i dd = 5.5 v 20 ma = 110 mw 2. normal output port loss: iout2 0.4 v = 120 ma 0.4 v = 48 mw 3. vft driver loss: segment pin = 3 ma 2 v number of segmentsx = 6 mw x number of gridsy digit pin = 15 ma 2 v 14/16 (dim) = 52.5 mw r k loss = (5.5 + 25 v) 2 /50 k ? (number of segments x + number of digits y) = 18.605 mw (x + 2) therefore, pmax = 110 mw + 48 mw + 6 mw x + 52.5 mw + 18.605 mw (x + 2) = 253.71 mw + 24.605 x maximum power consumption p d when ta = 50 c is determined by the following equation: p d > pmax 842.5 mw > 253.71 + 24.605 x 23.9 > x thus, a fluorescent display tube with less than 23 segments can be used. if a fluorescent display tube with 23 segments or more is used, either a pull-down resistor must be attached externally , or the number of segments to be lit must be kept to less than 23 by software. 2007-10-19
tmp88cu74 2003-02-17 88cu74-130 dc characteristics (v ss = 0 v, topr = ? 30 to 70c) parameter symbol pins conditions min typ. max unit hysteresis voltage v hs hysteresis input 0.9 ? v i in1 test i in2 open drain ports, tri-state ports input current i in3 reset , stop v dd = 5.5 v v in = 5.5 v/0 v ? ? 2 a input resistance r in3 reset 100 220 450 pull-down resistance r k source open drain ports v dd = 5.5 v, v kk = ? 30 v 50 80 110 k i lo1 sink open drain ports v dd = 5.5 v, v out = 5.5 v ? ? 2 i lo2 source open drain ports v dd = 5.5 v, v out = ? 32 v ? ? ? 2 output leakage current i lo3 tri-state ports v dd = 5.5 v, v out = 5.5 v/0 v ? ? 2 a output high voltage v oh2 tri-state ports v dd = 4.5 v , i oh = ? 0.7 ma 4.1 ? ? output low voltage v ol except xout v dd = 4.5 v, i ol = 1.6 ma ? ? 0.4 v output high current i oh p6, p7, p8, p9, pd port v dd = 4.5 v, v oh = 2.4 v ? ? 20 ? supply current in normal 1, 2 modes ? 18 26 supply current in idle 1, 2 modes v dd = 5.5 v v in = 5.3 v/0.2 v fc = 12.5 mhz fs = 32.768 khz ? 5.5 8.5 ma supply current in slow mode ? 30 60 supply current in sleep mode v dd = 3.0 v v in = 2.8 v/0.2 v fs = 32.768 khz ? 15 30 supply current in stop mode i dd v dd = 5.5 v v in = 5.3 v/0.2 v ? 0.5 10 a note 1: typical values show those at topr = 25c, vdd = 5 v. note 2: input current iin1,iin3; the current through resistor is not included, when the input resistor (pull-up/pull-down) is contained. ad conversion characteristics (v ss = 0 v, v dd = 4.5 to 5.5 v, topr = ? 30 to 70c) parameter symbol conditions min typ. max unit v aref 4.5 ? v dd analog reference voltage v ass v ss analog input voltage v ain v ass ? v aref v analog supply current i ref v aref = 5.5 v, v ass = 0.0 v ? 0.5 1.0 ma nonlinearity error ? ? 1 zero point error ? ? 1 full scale error ? ? 1 total error v dd = 5.0 v, v ss = 0.0 v v aref = 5.000 v v ass = 0.000 v ? ? 2 lsb note: total errors includes all errors, except quantization error. 2007-10-19
tmp88cu74 2003-02-17 88cu74-131 ac characteristics (v ss = 0 v, v dd = 4.5 to 5.5 v, topr = ? 30 to 70c) parameter symbol conditions min typ. max unit in normal1, 2 modes in idle 1, 2 modes 0.32 ? 10 in slow mode machine cycle time tcy in sleep mode 117.6 ? 133.3 s high level clock pulse width t wch low level clock pulse width t wcl for external clock operation (xin input), fc = 12.5 mhz 33.75 ? ? ns high level clock pulse width t wsh low level clock pulse width t wsl for external clock operation (xtin input), fs = 32.768 khz 14.7 ? ? s recommended oscillating ? conditions (v ss = 0 v, v dd = 4.5 to 5.5 v, topr = ? 30 to 70c) recommended constant parameter oscillator oscillation frequency recommended oscillator c 1 c 2 12.5 mhz murata csa12.5mtz 30 pf 30 pf ceramic resonator 8 mhz murata csa8.00mtz 30 pf 30 pf high-frequency oscillation crystal oscillator 12.5 mhz ndk at -51 10 pf 10 pf low-frequency oscillation crystal oscillator 32.768 khz ndk mx-38t 15 pf 15 pf note 1: an electrical shield by metal shield plate on the surface of ic package should be recommendable in order to prevent the device from the high electric fieldstress applied from crt (cathode ray tube) for continuous reliable operation. note 2: the product numbers and specifications of the resonators by murata manufacturing co., ltd. are subject to change. for up-to-date information, please refer to the following url; http://www.murata.co.jp/search/index.html c 1 (1) high-frequency oscillation c 2 xin xout (2) low-frequency oscillation xtin xtout c 1 c 2 2007-10-19
tmp88cu74 2003-02-17 88cu74-132 2007-10-19

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