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lt3640 3640f typical a pplica t ion descrip t ion dual monolithic buck regulator with power-on reset and watchdog timer the lt ? 3640 is a dual channel, current mode monolithic buck switching regulator with a power-on reset and a watchdog timer. both regulators are synchronized to a single oscillator with an adjustable frequency (350khz to 2.5mhz). at light loads, both regulators operate in low ripple burst mode ? to maintain high effciency and low output ripple. the high voltage channel is a nonsynchronous buck with an internal 2.4a top switch that operates from an input of 4v to 35v; a 36.5v ovlo protects the device to 55v. the low voltage channel operates from an input of 2.5v to 5.5v. internal synchronous power switches provide high effciency without the need of external schottky diode. both channels have cycle-by-cycle current limit, providing protection against shorted outputs. the power-on reset and watchdog timeout periods are both adjustable using external capacitors. the window mode watchdog timer fags when the p pulses group too close together or too far apart. the lt3640 is available in a 28-pin 4mm 5mm qfn package and 28-pin tssop package. both packages have an exposed pad for low thermal resistance. 2mhz 3.3v/0.8a and 1.8v/0.8a step down regulators fea t ures a pplica t ions n high voltage buck regulator: 4v to 35v operating range 1.3a output current n ovlo protects input to 55v n low voltage synchronous buck regulator: 2.5v to 5.5v input voltage range 1.1a output current n synchronizable, adjustable 350khz to 2.5mhz switching frequency n programmable power-on reset timer n programmable window mode watchdog timer n typical quiescent current: 290a n short-circuit robust n programmable soft-start n low shutdown current: i q < 1a n available in thermally enhanced 28-lead (4mm 5mm) qfn and 28-lead tssop packages n industrial power supplies n automotive electronic control units 3640 ta01a sync pgood wde 1nf 1nf 1.5nf 1.5nf 32.4k v out2 1.8v/0.8a v out1 3.3v/0.8a 22f 10f 100k rst2 en2 wdo wdi fb2 cwdt cpor rt gnd ss2 ss1 rst1 sw2 sw1 en/uvlo v in v in 5v to 35v sw lt3640 bst v in2 fb1 1h 100k v out1 p 100k 49.9k 80.6k 49.9k 3.3h 0.22f da 22f hv channel effciency, 2mhz, v out1 = 3.3v l , lt, ltc, ltm, linear technology, burst mode and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. lv channel effciency, 2mhz, v out2 = 1.8v v out1 current (a) 0 70 efficiency (%) 80 0.2 0.4 0.80.6 1.0 90 75 85 1.2 3640 ta01b v in = 12v v out2 current (a) 0 70 efficiency (%) 80 0.2 0.4 0.8 0.6 1 90 75 85 3640 ta01c v in2 = 3.3v
lt3640 3640f a bsolu t e maxi m u m r a t ings v in , en/uvlo voltage (note 7) .................................55v wde voltage .............................................................30v bst above sw, sw1 voltage ....................... C0.3v to 6v sw1 above sw voltage ............................... C0.3v to 6v v in2 , sync, en2, pgood, wdi, wdo, rst1, rst2 , voltages ....................... C0.3v to 6v ss1, ss2, fb1, fb2, rt, cwdt, cpor voltages... ........................... C0.3v to 2.5v (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view fe package 28-lead plastic tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 fb2 pgood en/uvlo sync ss1 fb1 rt rst2 rst1 wdo cwdt cpor wde wdi ss2 en2 gnd sw2 v in2 gnd v in bst sw sw1 da nc gnd gnd 29 gnd ja = 30c/w, jc = 8c/w exposed pad (pin 29) is gnd, must be soldered to pcb 9 10 top view ufd package 28-lead (4mm s 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 sync ss1 fb1 rt rst2 rst1 wdo cwdt sw2 v in2 gnd v in bst sw sw1 da en/uvlo pgood fb2 ss2 en2 gnd cpor wde wdi gnd gnd nc 7 17 18 19 20 21 22 16 8 15 29 gnd ja = 34c/w, jc = 2.7c/w exposed pad (pin 29) is gnd, must be soldered to pcb p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt3640efe#pbf lt3640efe#trpbf lt3640fe 28-lead plastic tssop C40c to 125c lt3640ife#pbf lt3640ife#trpbf lt3640fe 28-lead plastic tssop C40c to 125c lt3640eufd#pbf lt3640eufd#trpbf 3640 28-lead (4mm 5mm) plastic qfn C40c to 125c lt3640iufd#pbf lt3640iufd#trpbf 3640 28-lead (4mm 5mm) plastic qfn C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ sw2 voltage ................................ C0.3v to (v in2 + 0.3v) operating junction temperature range (note 2) lt3640e ................................................. C40c to 125c lt3640i .................................................. C40c to 125c storage temperature range ................... C65c to 150c lead temperature, fe only (soldering, 10 sec) .... 300c
lt3640 3640f the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 12v, v in2 = 3.3v, en/uvlo = 12v, en2 = 3.3v, unless otherwise noted. e lec t rical c harac t eris t ics parameter conditions min typ max units v in undervoltage lockout threshold l 3.6 4 v v in undervoltage release threshold l 3.8 4.2 v v in overvoltage lockout threshold l 35 36.5 38 v v in overvoltage release threshold l 34 35.5 37 v quiescent current from v in en/uvlo = 0.3v not switching 0.1 275 1 375 a a en/uvlo threshold voltage 1.2 1.26 1.3 v en/uvlo high bias current en/uvlo = threshold + 60mv 2 a en/uvlo low bias current en/uvlo = threshold C 60mv 0.1 a sync input frequency 0.35 2.5 mhz sync threshold voltage 0.4 0.8 1 v switching frequency rt = 32.4k rt = 182k l l 1.75 450 2 500 2.35 550 mhz khz fb1 voltage l 1.24 1.265 1.29 v fb1 bias current fb1 = 1.265v 30 100 na fb1 line regulation 5v < v in < 30v 0.001 %/v sw1 minimum off-time 70 100 ns sw1 v cesat i sw1 = 800ma 400 mv sw1 leakage current 0.1 1 a sw1 current limit fb1 = 1v (note 3) fb1 = 0.1v l 2.2 2.8 1.8 3.4 a a da current limit fb1 = 1v (note 4) fb1 = 0.1v l 1.35 1.7 1 2.2 a a bst pin current i sw1 = 800ma 30 50 ma minimum bst-sw voltage 2 2.7 v fb1 to start lv channel 80 100 130 mv fb1 hysteresis to stop lv channel 30 50 90 mv v in2 minimum operating voltage l 2.3 2.5 v v in2 maximum operating voltage l 5.5 v en2 threshold voltage 0.3 1 1.5 v fb2 voltage l 588 600 612 mv fb2 bias current fb2 = 0.6v 0 100 na fb2 line regulation 2.5v < v in2 < 5.5v 0.01 %/v sw2 minimum off-time 70 100 ns sw2 pmos current limit (note 5) l 1.5 1.9 2.2 a sw2 nmos current limit (note 5) l 1.2 1.6 2 a sw2 pmos r ds(on) i sw2 = 0.5a (note 6) 275 m sw2 nmos r ds(on) i sw2 = 0.5a (note 6) 200 m fb2 to enable pgood 20 40 80 mv fb2 hysteresis to disable pgood 20 40 80 mv pgood voltage fb2 = 0.6v, i pgood = 1ma 200 320 mv
lt3640 3640f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3640e is guaranteed to meet performance specifcations from 0c to 125c junction temperature. specifcations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3640i is guaranteed and tested over the full C40c to 125c operating junction temperature range. parameter conditions min typ max units ss1, ss2 charge current ss1 = 0.5v, ss2 = 0.5v 1.4 1.9 2.5 a ss1 to fb1 offset voltage ss1 = 0.6v 5 30 mv ss2 to fb2 offset voltage ss2 = 0.3v 5 30 mv rst1 threshold as percentage of v fb l 90 92 94 % rst2 threshold as percentage of v fb l 89 92 94 % undervoltage to rst assert time 20 s rst1, rst2, wdo pull-up current rst1, rst2, wdo = 0v 5 15 30 a rst1, rst2, wdo output voltage i rst1 , i rst2 , i wdo = 2ma 150 250 mv rst1, rst2 timeout period (t rst ) cpor = 220pf l 8 9.5 11 ms watchdog start delay time (t dly ) cwdt = 820pf 14 16 18 ms watchdog upper boundary (t wdu ) cwdt = 820pf l 27 32 35 ms watchdog lower boundary (t wdl ) cwdt = 820pf l 1.68 2 2.2 ms wdi pull-up current wdi = 1.2v 2 a wdi voltage threshold 0.55 0.85 1.15 v wdi low minimum pulse width 300 ns wdi high minimum pulse width 300 ns wde pull-down current wde = 2v 1 a wde threshold l 0.5 0.7 0.9 v the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 12v, v in2 = 3.3v, en/uvlo = 12v, en2 = 3.3v, unless otherwise noted. note 3: sw1, sw2 current limit is guaranteed by design and/or correlation to static test. slope compensation reduces current limit at higher duty cycle. note 4: the oscillator cycle is extended when da current exceeds its limit. da current limit is fat over duty cycle. note 5: if the sw2 nmos current exceeds its limit at the start of an oscillator cycle, the pmos will not be turned on in the cycle. note 6: the qfn switch r ds(on) is guaranteed by correlation to wafer level measurement. note 7: absolute maximum voltage at v in and run/ss pin is 55v for nonrepetitive one second transients, and 36v for continuous operation. e lec t rical c harac t eris t ics
lt3640 3640f typical p er f or m ance c harac t eris t ics lv channel effciency (2mhz, v out2 = 1.8v) quiescent current vs v in quiescent current vs temperature hv channel effciency (2mhz, v out1 = 3.3v) hv channel effciency (2mhz, v out1 = 5v) lv channel effciency (2mhz, v out2 = 1.2v) t a = 25c, unless otherwise noted. fb1 voltage vs temperature fb1 voltage vs ss1 fb2 voltage vs temperature v out1 current (a) 0 70 efficiency (%) 80 0.2 0.4 0.80.6 1.0 90 75 85 1.2 3640 g01 v in = 12v v in = 24v v in = 16v v out1 current (a) 0 70 efficiency (%) 80 0.2 0.4 0.80.6 1.0 90 75 85 1.2 3640 g02 v in = 12v v in = 24v v in = 16v v out2 current (a) 0 70 efficiency (%) 80 0.2 0.4 0.8 0.6 1.0 90 75 85 3640 g04 v in2 = 3.3v v in2 = 5v v in voltage (v) 0 v in quiescent current (ma) 0.20 0.25 0.30 0.15 0.10 20 10 30 40 0.05 0.00 0.35 3640 g05 temperature (c) ?50 v in quiescent current (a) 200 250 300 150 100 50 0 100 150 50 0 350 3640 g06 temperature (c) ?50 fb1 voltage (v) 50 0 100 150 3640 g07 1.00 1.10 1.20 1.30 1.40 1.05 1.15 1.25 1.35 regulation rst1 threshold ss1 voltage (v) fb1 voltage (v) 1.0 0 0.5 1.5 2.0 3640 g08 0.0 0.4 0.8 1.2 1.4 0.2 0.6 1.0 temperature (c) ?50 fb2 voltage (v) 50 0 100 150 3640 g09 0.45 0.55 0.65 0.70 0.50 0.60 regulation rst2 threshold v out2 current (a) 0 70 efficiency (%) 80 0.2 0.4 0.8 0.6 1.0 90 75 85 3640 g03 v in2 = 3.3v v in2 = 5v
lt3640 3640f typical p er f or m ance c harac t eris t ics fb2 voltage vs ss2 switching frequency vs temperature hv channel current limit vs duty cycle v out1 minimum load to run at full frequency (v out1 = 3.3v) hv channel switching frequency (v out1 = 3.3v) lv channel switching frequency (v out2 = 1.8v) lv channel peak current limit vs duty cycle lv channel switch voltage drop vs current (v in2 = 3.3v) t a = 25c, unless otherwise noted. ss2 voltage (mv) fb2 voltage (mv) 3640 g10 0 200 400 600 700 100 300 500 0 200 400 6000 800 1000 temperature (c) ?50 switching frequency (mhz) 50 0 100 150 3640 g11 0.48 0.50 0.52 0.49 0.51 r t = 182k duty cycle (%) sw1 peak current limit (a) 3640 g12 0 20 40 60 80 100 0.0 1.0 2.0 2.5 0.5 1.5 duty cycle (%) sw2 peak current limit (a) 3640 g13 0 20 40 60 80 100 0.0 1.0 2.0 0.5 1.5 sw2 current (a) 0 sw2 voltage drop (mv) 300 350 400 250 200 0.5 1 1.5 50 0 150 450 100 3640 g14 pmos nmos v in voltage (v) 0 v out1 current (a) 0.30 0.35 0.40 0.25 0.20 5 1510 20 25 30 0.05 0 0.15 0.45 0.10 3640 g15 2mhz 2.5mhz v out1 current (a) switching frequency (mhz) 3640 g16 0 1.0 2.0 2.5 0.5 1.5 0 0.2 0.4 0.6 0.8 1.0 1.2 v in = 12v v in = 24v v in = 16v r t = 32.4k v out2 current (a) switching frequency (mhz) 3640 g17 0 1.0 2.0 2.5 0.5 1.5 0 0.2 0.4 0.6 0.8 1.0 v in2 = 3.3v v in2 = 5v
lt3640 3640f typical p er f or m ance c harac t eris t ics full frequency waveforms light load operation waveforms t a = 25c, unless otherwise noted. watchdog upper boundary period vs c wdt watchdog upper boundary period vs temperature rst/wdo pull-up current 200ns/div sw1 10v/div i l1 0.5a/div sw2 5v/div i l2 0.5a/div 3640 g18 v in1 = 12v v out1 = 3.3v/0.5a v in2 = v out1 v out2 = 1.8v/0.5a 500ns/div sw1 10v/div i l1 0.5a/div sw2 5v/div i l2 0.5a/div 3640 g19 v in1 = 12v v out1 = 3.3v/25ma v in2 = v out1 v out2 = 1.8v/30ma c wdt capacitance (pf) 0 watchdog upper boundary period (ms) 120 140 160 100 80 2000 1000 3000 4000 5000 20 0 60 180 40 3640 g20 temperature (c) ?50 watchdog upper boundary period (ms) 20 25 30 15 10 50 0 100 150 5 0 35 3640 g21 rst/ wdo voltage (v) 0 rst/ wdo pull-up current (a) 1 0.5 1.5 2 3640 g22 0 10 20 5 15
lt3640 3640f p in func t ions fb2 (pin 1/pin 26): the low voltage converter regulates the fb2 pin to 600mv. connect the feedback resistor divider tap to this pin to set output voltage. pgood (pin 2/pin 27): open-drain logic output that starts to sink current when fb2 is in regulation. en/uvlo (pin 3/pin 28): pull this pin below 0.3v to shut down the lt3640. the 1.26v threshold can function as an accurate undervoltage lockout, preventing the lt3640 from operating until v in voltage has reached the programmed level. sync (pin 4/pin 1): driving the sync pin with an external clock signal synchronizes both converters to the applied frequency. the lowest external clock frequency should be 20% higher than the internal oscillator frequency. ss1 (pin 5/pin 2): the ss1 pin sets the fb1 voltage ex- ternally between 0v and 1.265v, providing soft-start and tracking. tie this pin 1.5v or higher to use the internal 1.265v reference. a capacitor to ground at this pin sets the ramp time to regulated output voltage for the high voltage converter. use a resistor divider to track another supply. fb1 (pin 6/pin 3): the high voltage converter regulates the fb1 pin to 1.265v. connect the feedback resistor divider tap to this pin to set output voltage. rt (pin 7/pin 4): oscillator resistor input. connecting a resistor to ground from this pin sets the internal oscillator frequency. rst2 (pin 8/pin 5): open-drain logic output that remains asserted for the period set by the cpor pin capacitor after fb2 goes above 550mv. rst1 (pin 9/pin 6): open-drain logic output that remains asserted for the period set by the cpor pin capacitor after fb1 goes above 1.165v. wdo (pin 10/pin 7): open-drain logic output that remains asserted for the period set by the cpor pin capacitor if wde is enabled and wdi pin is not driven by an appropri- ate signal. cwdt (pin 11/pin 8): connect a capacitor to ground at this pin to set watchdog timer. cpor (pin 12/pin 9): connect a capacitor to ground at this pin to set the power-on reset timer and wdo output timer. wde (pin 13/pin 10): watchdog enable pin. wdi (pin 14/pin 11): the wdi pin receives watchdog signals from a microprocessor. gnd (pins 15, 16, 23, 26, exposed pad pin 29/pins 12, 13, 20, 23, exposed pad pin 29): ground. these pins must be soldered to pcb ground. nc (pin 17/pin 14): not connected. this pin can be con- nected to ground. da (pin 18/pin 15): the da pin is used to sense the catch diode current for current limit and protection. connect this pin to catch diode anode. sw1 (pin 19/pin 16): output of the high voltage internal power switch. connect this pin to the inductor and catch diode cathode. sw (pin 20/pin 17): the sw pin is used to charge the boost capacitor. connect this pin to the boost capacitor. bst (pin 21/pin 18): the bst pin is used to provide a drive voltage, higher than v in pin voltage, to the high voltage channel internal power switch. connect an external boost diode to this pin. v in (pin 22/pin 19): the v in pin supplies current to the lt3640s internal circuitry and to the high voltage channel internal power switch. this pin must be locally bypassed. v in2 (pin 24/pin 21): the v in2 pin supplies current to the internal power mosfet of the low voltage converter and to the lt3640s internal circuitry when v in2 is above 3v. sw2 (pin 25/pin 22): switch node of the low voltage converter. connect this pin to an inductor. en2 (pin 27/pin 24): low voltage converter enable pin. pull this pin below 0.3v to shut down the low voltage converter. pull this pin above 1.5v to enable the low volt- age converter. ss2 (pin 28/pin 25): the ss2 pin sets the fb2 voltage externally between 0v and 0.6v, providing soft-start and tracking. tie this pin 0.8v or higher to use the internal 0.6v reference. a capacitor to ground at this pin sets the ramp time to regulated output voltage for the low voltage converter. use a resistor divider to track another supply. (fe/qfn)
lt3640 3640f b lock diagra m 3640 bd + + ? g m2 v ref 600mv v out2 v out1 vc2 vc1 100k 5.5v 2a r2 fb1 ss1 en/ uvlo enable bst sw sw1 driver l1 l2 da rt sync sw2 r1 + ? 2a 2a + + ? g m1 2a + ? 2a + ? a4 a8 + ? a3 + ? a2 + ? a1 + ? a7 a9 r4 fb2 50mv pgood r3 ss2 cpor 3 3 v ref 1.265v ramp generator por timer watchdog timer oscillator s logic circuit r q s r q + ? a6 + ? a5 v in c in v out1 v out2 v in2 c in2 c bst c out1 c out2 d bst q1 d1 en2 cwdt rst1 rst2 wde wdi wdo + ? + ?
lt3640 0 3640f ti m ing diagra m s the lt3640 is a dual channel, constant-frequency, current mode monolithic buck switching regulator with power-on reset and watchdog timer. both channels are synchronized to a single oscillator with frequency set by rt. operation can be best understood by referring to the block diagram. buck regulators the high voltage channel is a nonsynchronous buck regulator that operates from the v in pin. the start of each oscillator cycle sets an sr latch and turns on the internal npn power switch. an amplifer and comparator monitor the current fowing between the v in and sw1 pins, turning the switch off when this current reaches a level determined by the voltage at vc1 node. an error amplifer measures the output voltage through an external resistor divider tied to the fb1 pin and servos the vc1 node. the reference of the error amplifer is determined by the lower of the internal reference and the voltage at the ss1 pin. if the error amplifers output increases, more current is delivered to the output; if it decreases, less current is delivered. o pera t ion an active clamp (not shown) on the vc1 node provides peak current limit. a da pin current comparator extends the oscillator cycle until the catch diode current is below the valley current limit. both the peak and valley current limits help to control the inductor current in fault condi- tions such as shorted output with high v in . both current limits are reduced when the voltage at the fb1 pin is below 0.2v. this current foldback helps to control the inductor current during start-up and overload. the npn power switch driver operates from either the v in pin or the bst pin. an external capacitor and diode are used to generate a voltage between the bst and sw pins. during the power-up of the lt3640, an internal 5ma current source charges the external bst capacitor. the regulator starts switching when the (bst-sw) voltage reaches the 2v threshold. the internal npn power switch can be fully saturated for effcient operation when the (bst-sw) volt- age is between 2.3v and 5.5v. the low voltage channel is a synchronous buck regulator that operates from the v in2 pin. it starts switching only fb rst wdi wdo 3640 td t rst t uv t < t wdl t rst t dly t < t wdu t wdl < t < t wdu t wdu t rst power-on reset timing watchdog timing
lt3640 3640f when the v in2 pin voltage is above 2.3v, the en2 pin is pulled high and the fb1 pin voltage is above 1.165v. the internal top power mosfet is turned on each cycle at the beginning of each oscillator cycle, and turned off when the current fowing through the top mosfet reaches a level determined by the voltage at the vc2 node. an error amplifer measures the output voltage through an external resistor divider tied to the fb2 pin and servos the vc2 node. the reference of the error amplifer is determined by the lower of the internal 600mv reference and the voltage at the ss2 pin. while the top mosfet is off, the bottom mosfet is turned on in an oscillator cycle until the inductor current starts to reverse. if the inductor current is higher than the valley current limit at the beginning of an oscillator cycle, the top mosfet will not turn on in this cycle, limiting inductor current in shorted output fault. an internal regulator provides power to the control circuitry. the regulator draws most power from the v in2 pin and a small portion of power from the v in pin when the v in2 pin voltage is higher than 3v. if the voltage at v in2 pin is lower than 3v, the regulator draws all power from the v in pin. the en/uvlo pin is used to put the lt3640 in shutdown, reducing the input current to less than 1a. the accurate 1.26v threshold of the en/uvlo pin provides a program- mable v in undervoltage lockout through an external resistor divider tied to the en/uvlo pin. a 2a hysteresis current on the en/uvlo pin prevents switching noise from shut- ting down the lt3640. the lt3640 has an overvoltage protection feature which disables switching action in both channels when the v in pin voltage goes above 36v. when switching is disabled, the lt3640 can sustain v in voltages up to 55v for one second. internal 2a current sources charge the ss1 pin and the ss2 pin up to about 2v. soft-start or output voltage tracking of the two channels can be independently imple- mented with capacitors from the ss1 pin and the ss2 pin to ground. any overvoltage or undervoltage condition on the v in pin triggers an internal latch that discharges the ss1 pin to below 100mv before it is released. if the en2 pin goes low, the v in2 voltage falls below 2.2v or the fb1 pin goes below 1.165v, the ss2 pin will be discharged to below 100mv before it is released. to optimize effciency, the lt3640 switches to low ripple burst mode operation in light load situations. between switching pulses, control-circuitry current is minimized. a power good comparator with 40mv of hysteresis trips when the low voltage channel is enabled and the fb2 pin is above 550mv. the pgood pin is an open-drain output that is pulled low when both the outputs are in regulation. power-on reset and watchdog timer the lt3640 includes one power-on reset timer for each buck regulator and one common watchdog timer. power- on reset and watchdog timers are both adjustable using external capacitors. operation can be best understood by referring to the timing diagram. the rst1, rst2 and wdo pins are all open-drain outputs with weak internal pull-ups to about 2v. the rst1 and rst2 pins are pulled low when the lt3640 is enabled and v in is above 3.6v. once the fb1 pin rises above 1.165v, the high voltage channel reset timer is started and rst1 is released after the reset timeout period. the low voltage channel reset timer is started once the fb2 pin rises above 550mv, and releases rst2 after the reset timeout period. the watchdog circuit monitors a ps activity. as soon as both rst1 and rst2 are released, a delay timer is started. the watchdog timer is started after the delay timer times out. the lt3640 implements windowed watchdog function for higher system reliability. the watchdog timer detects falling edges on the wdi pin. if the falling edges are grouped too close together or too far apart, the wdo pin is pulled down and the reset timer is started. when the reset timer times out, wdo is released and the watchdog timer is again started after the delay period. o pera t ion
lt3640 3640f setting the output voltages the internal reference voltage is 1.265v for the high volt- age channel, and 600mv for the low voltage channel. the output voltages are set by resistor dividers according to the following formulas: r r v v r r v v out out 2 1 1 265 1 4 3 0 6 1 1 2 = ? ? ? ? ? ? ? = ? ? ? . ? . ?? ? ? ? ? use 1% resistors in the resistor dividers. to avoid noise problems, r1 should be 100k or less, and r3 should be 50k or less. reference designators refer to the block diagram. switching frequency the lt3640 uses a constant-frequency pwm architecture that can be programmed to switch from 350khz to 2.2mhz by using a resistor tied from the rt pin to ground. table 1 shows the necessary r t value for a desired switching frequency. table 1. switching frequency vs r t value switching frequency (mhz) r t (k) 0.35 267 0.5 182 1 82.5 2 32.4 2.2 27.4 selection of the operating frequency is mainly a trade-off between effciency and component size. the advantage of high frequency operation is that smaller inductor and capacitor values may be used. the disadvantage is lower effciency. the high switching frequency also decreases the duty cycle range. the reason is that the lt3640 switches have fnite minimum on- and off-times independent of the switching frequency. the top switch in the high voltage channel can turn on for a minimum of ~60ns and turn off for a minimum of ~70ns. the top switch in the low voltage channel can turn on for a minimum of ~110ns and turn a pplica t ions i n f or m a t ion off for a minimum of ~70ns. the minimum and maximum duty cycles are: dc min = f s ? t on(min) dc max = 1 C f s ? t off(min) where f s is the switching frequency, t on(min) is the mini- mum switch on-time, and t off(min) is the minimum switch off-time. these equations illustrate how duty cycle range increases when switching frequency decreases. the internal oscillator of the lt3640 can be synchronized to an external 350khz to 2.5mhz positive clock signal on the sync pin. the r t value should be chosen such that the internal oscillators frequency is 20% lower than the lowest sync clock frequency (refer to table 1). to avoid erratic operation, the lt3640 ignores the sync signal until the fb1 pin voltage is above 1.165v. when applying a sync signal, the rising edges reset the lt3640s internal clock and initiate a switch cycle. the amplitude of the sync signal must be at least 2v. the sync pulse width must be at least 40ns. v in voltage range the lt3640s minimum operating voltage is 3.6v typical. a higher minimum operating voltage can be accurately programmed with a resistor divider between the v in pin and the en/uvlo pin. the en/uvlo threshold is 1.26v. when the lt3640 is enabled, a 2a current fows out of the en/uvlo pin generating hysteresis to prevent the switch- ing action from falsely disabling the lt3640. choose the divider resistances for appropriate hysteresis voltage. the high voltage nonsynchronous channel operates from the v in pin. the minimum v in voltage to regulate output voltage is: v v v dc v v in min out d max d ce ( ) = + ? ? ? ? ? ? ? + 1 where v d is the forward voltage drop of the catch diode, v ce is the voltage drop of the internal npn power switch, and dc max is the maximum duty cycle (refer to the switching frequency section). if v in is below the calculated minimum voltage, output will lose regulation.
lt3640 3640f figure 1. lower switching frequency occurs in high voltage channel when required on-time is below 50ns the maximum v in should not exceed the absolute maxi- mum rating. for fxed frequency operation, the maximum v in is: v v v dc v v in max out d min d ce ( ) = + ? ? ? ? ? ? ? + 1 note that the high voltage buck will still regulate at an input voltage that exceeds v in(max) (up to 35v). however, the switching frequency will be lowered to satisfy the equa- tion (figure 1). once the input voltage reaches 36.5v, an internal overvoltage lockout (ovlo) circuit is triggered to disable switching ac- tion (figure 2). without switching, the lt3640 can sustain v in voltage transients up to 55v for one second. v in2 voltage range the low voltage synchronous channel operates from the v in2 pin. the v in2 pin can be connected to either an independent voltage supply or the high voltage channel output for a two-stage power regulator. in either confguration, if the high voltage channel is over- loaded and pulled out of regulation, the low voltage channel will be disabled. the ss2 pin will be discharged as well. the minimum v in2 voltage to regulate output voltage is: v v dc in min out max 2 2 ( ) where dc max is the maximum duty cycle (refer to the switching frequency section). if v in2 is below the calculated minimum voltage, the output will fall out of regulation. the maximum v in2 for fxed frequency operation is: v v dc in max out min 2 2 ( ) where dc min is the minimum duty cycle (refer to the switch- ing frequency section). for voltage that exceeds v in2(max) (up to 5.5v), the low voltage channel exhi-bits pulse-skip- ping behavior, and the output ripple will increase. inductor selection inductor selection involves inductance, saturation current, series resistance (dcr) and magnetic loss. the inductance for the high voltage channel is: l v v f out d s 1 1 7 1 = + . ? where v out1 is high voltage channel output voltage, v d is the forward voltage drop of the catch diode, and f s is the switching frequency. for example, 3.3h is a reason- able inductance for a 3.3v output with 2mhz switching frequency. once the inductance is selected, the inductor current ripple and peak current can be calculated: ? i v v i f v v v l out d l s out d in 1 1 1 1 1 = + + ? ? ? ? ? ? ( ) ? ? ? i i i l peak out max l ( ) ( ) = + ? 2 figure 2. v in overvoltage lockout a pplica t ions i n f or m a t ion 200ns/div sw1 10v/div i l1 0.5a/div 3640 f01 v in = 30v v out1 = 3.3v/0.2a r t set = 2mhz 10s/div v in 20v/div 55v pk , 40v, 15v i l1 2a/div 3640 f02
lt3640 3640f a pplica t ions i n f or m a t ion to guarantee suffcient output current, peak inductor cur- rent must be lower than the switch current limit (i lim ). the largest inductor current ripple occurs at the highest v in . to guarantee current capacity, use v in(max) in the above formula. the inductance for the low voltage channel is: l v f out s 2 1 5 2 = . for a selected inductance, the inductor current ripple can be calculated: ? i v l f v v l out s out in 2 2 2 2 2 1 = ? ? ? ? ? ? ? ? ? for robust operation in fault conditions, the inductor saturation current should be higher than the upper limit of the corresponding top switch current limit. to keep the effciency high, the inductor series resistance (dcr) should be as small as possible (must be < 0.1), and the core material should be intended for the chosen operation frequency. high effciency converters generally cannot afford the core loss found in low cost powdered iron cores; instead use ferrite, molypermalloy or kool m cores. table 2 lists several vendors and suitable inductor series. table 2. inductor vendors part series vendor lqh55d murata www.murata.com slf7045 slf10145 tdk www.componenttdk.com d62cb, d63cb d75c, d75f toko www.toko.com cr54, cdrh74 cdrh6d38, cr75 sumida www.sumida.com of course, such a simple design guide will not always result in the optimum inductors for the applications. a larger value inductor provides a slightly higher maximum load current and will reduce the output voltage ripple. a larger value inductor also results in higher effciency in the condition of same dcr and same magnetic loss. however, for a same series of inductors, a larger value inductor has higher dcr. the trade-off between inductance and dcr is not always obvious. use experiments to fnd optimum inductors. low inductance may result in discontinuous mode opera- tion, which is okay, but reduces maximum load current. for details of maximum output current and discontinuous mode operation, see the linear technology application note 44. for duty cycles greater than 50%, there is a minimum inductance required to avoid subharmonic oscillations. see the linear technology application note 19. input capacitor bypass the v in pin of the lt3640 with a ceramic capacitor of x7r (C55c to 125c) or x5r (C55c to 85c) type. buck converters draw pulse current from the input sup- ply. the input capacitor is required to reduce the resulting voltage ripple. use a ceramic capacitor with: c f f in s 10 where f s in the switching frequency in mhz. a second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the lt3640. a ceramic input capacitor combined with trace or cable inductance forms a under damped tank circuit. if the lt3640 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the lt3640s voltage rating. this situation can be easily avoided (see the linear technology application note 80).
lt3640 3640f output capacitors and output ripple the output capacitor has two essential functions. in steady state, it determines the output voltage ripple. in transient, it stores energy in order to satisfy transient loads and stabilize the control loop. ceramic capacitors have low equivalent series resistance (esr) and provide the best ripple performance. a good starting value is: c v f out out s 1 150 = ? where f s is in mhz, and c out is the recommended output capacitance in f. use x5r or x7r types. this choice will provide low output ripple and good transient response. a good starting value for the low voltage channel output capacitor is: c v f out out s 2 2 100 = ? in the case where v in2 is connected to the high voltage channel output, the high voltage channel output capacitor can be used as the low voltage channel input capacitor. the required v in2 input capacitor value is usually smaller than the high voltage output capacitor. low esr ceramic capacitors for v in2 input and high volt- age channel output could form resonant tank and cause jitter in certain operating area. avoid v in2 input capacitor if possible. when choosing a capacitor, look carefully through the data sheet to fnd out what the actual capacitance is under operating conditions (applied voltage and temperature). a physically larger capacitor or one with a higher voltage rating may be required. high performance tantalum or electrolytic capacitors can be used for the output capacitor. low esr is important, so choose one that is intended for use in switching regulators. table 3 lists several capacitor vendors. table 3. capacitor vendors part series vendor ceramic, polymer, tantalum panasonic www.panasonic.com ceramic, tantalum kemet www.kemet.com ceramic, polymer, tantalum sanyo www.sanyovideo.com ceramic murata www.murata.com ceramic, tantalum avx www.avxcorp.com ceramic taiyo yuden www.taiyo-yuden.com catch diode the high voltage channel requires an external catch diode to conduct current during switch off-time. average forward current in normal operation can be calculated from: i i v v v d avg out in out in ( ) ( ) = ? where i out is the output load current. use a 1a or 2a rated schottky diode. peak reverse voltage is equal to the regulator input voltage. use a diode with a reverse voltage rating greater than the input voltage. table 4 lists several schottky diodes and their manufacturers. table 4. diode vendors part number v r (v) i ave (a) v f at 1a (mv) v f at 2a (mv) on semiconductor mbrm120e mbrm140 20 40 1 1 530 595 diodes inc. b120 b130 b220 b230 dfls240l 20 30 20 30 40 1 1 2 2 2 500 500 500 500 500 international rectifer 10bq030 20bq030 30 30 1 2 420 470 470 a pplica t ions i n f or m a t ion
lt3640 3640f bst and sw pin considerations the high voltage channel requires an external capacitor between the bst and sw pins and an external boost diode from a voltage source to the bst pin. in most cases, a 0.22f capacitor will work well. the (bst-sw) voltage cannot exceed 5.5v, and must be more than 2.3v for best effciency. connect the boost diode to any voltage between 2.7v and 5.5v. the v in2 pin is the best choice if the low voltage channel is used. the high voltage channel will not start until the (bst-sw) voltage is 2v or above. when the lt3640 is enabled, an internal ~5ma current source from v in fows out of the bst pin. the sw pin is disconnected from the sw1 pin, and is pulled down by an internal current source to ground. the external boost capacitor can be charged up regardless of the output. when the (bst-sw) voltage reaches 2v, the sw pin is connected to the sw1 pin, and the high voltage chan- nel starts switching. however, the internal bipolar power switch cannot be fully saturated until the (bst-sw) voltage is further charged to above 2.3v. to start up a traditional nonsynchronous buck regulator with very light load, the input voltage needs to be a couple of volts higher than the minimum running input voltage if the input voltage is ramping up slowly. the lt3640s unique boost capacitor charging scheme solves this start-up issue. figure 3 shows that the minimum input voltage to start the high voltage channel nonsynchronous buck regulator of the lt3640 is very close to the minimum input voltage to regulate the output voltage for most of the load range. soft-start the lt3640 has a soft-start pin for each channel. the feedback pin voltage is regulated to the lower of the cor- responding ss pin and the internal references, which is 1.265v for the high voltage channel, and 600mv for the low voltage channel. a capacitor from the ss pin to ground is charged by an internal 2a current source resulting in an output ramping linearly from 0v to the regulated voltage. the duration of the ramp is: t c v a t c mv a ss ss ss ss 1 1 2 2 1 265 2 600 2 = = ? . ? where t ss1 is the ramping time for the ss1 pin, t ss2 is the ramping time for the ss2 pin, c ss1 is the capacitance from the ss1 pin to ground, and c ss2 is the capacitance from the ss2 pin to ground. at power-up, a latch is set to discharge the ss1 pin. after the ss1 pin is discharged to below 100mv, the latch is reset. the internal 2a current source starts to charge the ss1 pin when the (bst-sw) voltage is charged to above 2v. figure 3. high voltage channel minimum input voltage for v out1 = 3.3v a pplica t ions i n f or m a t ion (3a) f s = 2mhz (3b) f s = 500khz v out current (a) 0.001 4 v in voltage (v) 0.01 0.1 1 3 2 1 0 5 3640 f03a start run v out current (a) 0.001 4 v in voltage (v) 0.01 0.1 1 3 2 1 0 5 3640 f03b start run
lt3640 3640f in the event of v in undervoltage lockout, v in overvoltage lockout or the en/uvlo pin being driven below 1.26v, the soft-start latch is set, triggering a start-up sequence. a latch is set to discharge the ss2 pin at power-up. after the fb1 pin reaches 1.165v, the v in2 voltage is above 2.3v, the en2 pin is enabled, and the ss2 pin is below 100mv, the latch is reset. the internal 2a current source starts to charge the ss2 pin. in the event of v fb1 out of regulation, the v in2 pin falling below 2.2v, or the en pin going low, the ss2 discharging latch is set, triggering a start-up sequence. the ss pins can also be pulled up by external current sources or resistors for output tracking. the external pull- up current should not exceed 100a for either ss pin. figure 4 shows the soft-start for a 3.3v and 1.8v application. shorted-output protection if an inductor is chosen that will not saturate excessively, the lt3640 will tolerate a shorted output. for the high voltage channel, the da current comparator extends the internal oscillator period until the catch diode current is below its limit. both the top switch and the da comparator have current foldback to help limit load current when the output is shorted to ground. the da current limit is 1.7a when the fb1 voltage is above 0.2v, and is 1a when the fb1 voltage is below 0.2v. figure 5 shows the high voltage channel operation under shorted output. because of the low v in2 voltage, the low voltage channel does not have current foldback. the low voltage channel does not extend the internal oscillator in shorted output condition allowing the high voltage channel to operate in constant frequency. if the bottom mosfet current exceeds the nmos current limit at the start of a clock cycle, the top mosfet is kept off in this cycle (similar to pulse-skipping operation). the inductor valley current is kept below the nmos current limit to ensure robustness in shorted output condition (figure 6). figure 4. soft-start of lt3640 figure 5. the high voltage channel reduces frequency to protect against shorted output with 30v input figure 6. the low voltage channel operates in pulse-skipping mode to protect against shorted output a pplica t ions i n f or m a t ion 500s/div v out2 1v/div pgood 2v/div v out1 2v/div en 2v/div 3640 f04 v in = 12v r t set = 2mhz 1s/div sw1 10v/div i l1 0.5a/div 3640 f05 v in = 30v v out1 = short 1s/div sw2 2v/div i l2 1a/div 3640 f06 v in2 = 5v v out2 = short
lt3640 3640f the threshold of power-on comparator is 1.15v for the high voltage channel, and 550mv for the low voltage channel. both rst1 and rst2 are open-drain outputs with weak internal pull-ups (100k to ~2v). the dc characteristics of the rst1 and rst2 pull-down strength are shown in the typical performance characteristics section. the weak reverse protection in battery charging applications or in battery back-up systems, the output will be held high when the input to the lt3640 is absent. if the v in pin is foated and the lt3640 is enabled, the lt3640s internal circuitry will pull its quiescent current through the sw1 pin or the sw2 pin. this is fne if the system can tolerate a few ma in this state. if the lt3640 is disabled, the sw1 pin and the sw2 pin current will drop to essentially zero. however, if the v in pin is grounded while the high voltage channel output is held high, an external diode is required at the v in pin to prevent current being pulled out of the v in pin. if the v in2 pin is grounded while the low voltage channel output is held high, an external diode is required at the v in2 pin to prevent current being pulled out of the v in2 pin (figure 7). figure 8. pfm operation pfm operation to improve effciency at light loads, the lt3640 auto- matically switches to pulse frequency modulation (pfm) operation which minimizes the switching loss and keeps the output voltage ripples small. because the two channels of the lt3640 may have differ- ent loads, the two channels can have different switching frequency (figure 8). power-on reset timer each channel of the lt3640 has a power-on comparator. both comparators are enabled when the lt3640 is powered up and starts monitoring their corresponding feedback voltages. figure 7. diodes prevent shorted inputs from discharging a battery tied to the outputs a pplica t ions i n f or m a t ion 3640 f07 out2 out1 gnd fb2 sw2 sw1 en/uvlo v in in sw lt3640 bst v in2 fb1 da + ? + ? in2 500ns/div i l1 0.5a/div sw1 10v/div i l2 0.5a/div sw2 5v/div 3640 f08a v in = 12v v out1 = 3.3v/25ma v in2 = v out1 v out2 = 1.8v/30ma 2s/div i l1 0.5a/div sw1 10v/div i l2 0.5a/div sw2 5v/div 3640 f08b v in = 12v v out1 = 3.3v/25ma v in2 = v out1 v out2 = 1.8v/20ma 2s/div i l1 0.5a/div sw1 10v/div i l2 0.5a/div sw2 5v/div 3640 f08c v in = 12v v out1 = 3.3v/0ma v in2 = v out1 v out2 = 1.8v/30ma (8a) (8b) (8c)
lt3640 3640f pull-ups eliminate the need for external pull-ups when the rise time of these pins is not critical. the open-drain confguration allows wired-or connections. the two power-on reset timers share one oscillator. the power-on reset timeout period, t rst (64 cycles on the cpor pin), which is the same for the two channels, can be programmed by connecting a capacitor, c por , between the cpor pin and ground: t c s f rst por = ? ? ? ? ? ? ? ?37 10 6 for example, using a capacitor value of 8.2nf gives a 303ms reset timeout period. the accuracy of t rst will be limited by the accuracy and temperature coeffcient of the capacitor cpor. extra parasitic capacitance on the cpor pin, such as probe capacitance, can affect t rst . watchdog the wde pin is the enable pin for the watchdog. as soon as both rst1 and rst2 are released, the watchdog starts a delay period, t dly , during which the input signal at the wdi pin is ignored for higher reliability. after the delay period, the watchdog starts detecting falling edges on the wdi pin. if the time between any two wdi falling edges is shorter than the watchdog lower boundary, t wdl , or longer than the watchdog upper boundary, t wdu , the wdo pin is pulled down for a period of t rst , which is the same as the power-on reset timeout period. when the wdo pin is released, the watchdog again starts the delay period. the wdo is open-drain output with weak internal pull-up, similar to the rst pins. the delay period corresponding to 33 cycles on cwdt, the watchdog lower boundary (4 cycles on cwdt), and the watchdog upper boundary (64 cycles on cwdt) are all related and set by a capacitor, c wdt , between the cwdt pin and ground: t t t t t c dly wdu wdl wdu wdu wdt = ? ? ? ? ? ? = = ? ? 33 64 16 37 ?? 10 6 s f ? ? ? ? ? ? the accuracy of the watchdog timer will be limited by the accuracy and temperature coeffcient of the capacitor c wdt . extra parasitic capacitance on the cwdt pin, such as probe capacitance, can affect the watchdog timer. figure 9. power-on reset and watchdog timing a pplica t ions i n f or m a t ion (9a) (9b) (9c) 20ms/div cpor cwdt fb1 fb2 rst2 rst1 3640 f09a 64 cycles 64 cycles wd starts 1ms/div cpor cwdt wdi wdo 3640 f09b 50ms/div cpor cwdt wdi wdo 3640 f09c
lt3640 0 3640f 3640 f10 l2 l1 c in2 c in c bst c out1 c out2 figure 9a shows the power-on reset timing. having fb1 or fb2 high starts the cpor oscillator. after t rst , the cor- responding rst is released. when both rst1 and rst2 are released, the cwdt oscillator starts. figure 9b shows the watchdog waveform with the wdi period between t wdl and t wdu . the wdi falling edge resets the cwdt oscillator. the cpor oscillator is disabled and wdo remains high. figure 9c shows the watchdog waveform with the wdi period longer than t wdu . wdo is asserted for a period of t rst when the watchdog upper boundary, t wdu , expires. pcb layout for proper operation and minimum emi, care must be taken during the printed circuit board (pcb) layout. figure 10 shows the recommended component placement with trace, ground plane and via locations. the input loop of the high voltage channel, which is formed by the v in and sw1 pins, the external catch diode (d1), the input capacitor (c in ) and the ground, should be as small as possible. these external components should be placed on the same side of the circuit board as the lt3640, and their connections should be made on that layer. place a local, unbroken ground plane below these components. the bst and sw nodes should be as small as possible. the boost capacitor (c bst ) should be as close to the bst and sw pins as possible. the input loop of the low voltage channel is formed by the v in2 pin, the input capacitor (c in2 ) and the ground. place c in2 close to the v in2 and the gnd pin to minimize this loop. place a local, unbroken ground plane below this input loop. keep the fb1 and fb2 nodes small so that the ground traces will shield them from the switching nodes. the exposed pad on the bottom of the package must be sol- dered to the ground so that the pad acts as a heat sink. to keep thermal resistance low, extend the ground plane as much as possible, and add thermal vias under and near the lt3640 to additional ground planes within the circuit board and on the bottom side. figure 10. recommended pcb layout, fe28 package a pplica t ions i n f or m a t ion
lt3640 3640f 3640 ta03 sync d1 wdi wdi wde pgood 1nf 1nf 1.5nf 1.5nf 32.4k v out2 1.2v/1a v out1 5v/0.8a 22f 4.7f rst1 rst2 en2 wdo fb2 cwdt cpor rt gnd ss2 ss1 sw2 sw1 en/uvlo v in v in 7v to 35v sw lt3640 bst v in2 fb1 l2 0.47h 453k 100k 100k out1 49.9k 49.9k 301k 100k l1 4.7h 0.22f d2 da 22f 100k 100k 100k l1: vishay ihlp-2020 l2: vishay ihlp-1616 d1: diodes b240a d2: central semi cmdsh-4e typical a pplica t ions 2mhz 3.3v/1.3a and 1.8v/1a buck regulators 2mhz 5v/0.8a and 1.2v/1a buck regulators 3640 ta02 sync d1 wde pgood 1nf 1nf 1.5nf 1.5nf 32.4k v out2 1.8v/1.1a v out1 3.3v/1.3a v in2 2.5v to 5.5v 22f 4.7f rst1 rst2 en2 wdo wdi l1: vishay ihlp-2020 l2: vishay ihlp-1616 d1: diodes b240a d2: central semi cmdsh-4e fb2 cwdt cpor rt gnd ss2 ss1 sw2 sw1 en/uvlo v in v in 5v to 35v sw lt3640 bst v in2 fb1 l2 1h 301k 100k 49.9k 100k 80.6k 49.9k l1 3.3h d2 0.22f da 4.7f 22f 3640 ta04 sync wde pgood 1nf 1nf 1.5nf 1.5nf 22f 4.7f rst1 rst2 wdo wdi fb2 cwdt cpor rt gnd ss2 ss1 sw2 sw1 en/uvlo v in sw lt3640 bst v in2 fb1 68.1k 49.9k 0.22f da 22f en2 d1 32.4k v out2 0.6v/1a v out1 3v/0.8a v in 4v to 30v l2 0.47h l1 3.3h d2 l1: vishay ihlp-2020 l2: vishay ihlp-1616 d1: on semi mbrs230 d2: central semi cmdsh2-3 2mhz 2.5v/0.8a and 0.6v/1a buck regulators
lt3640 3640f p ackage descrip t ion fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation eb fe28 (eb) tssop 0204 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 13 14 192022 21 151618 17 9.60 ? 9.80* (.378 ? .386) 4.75 (.187) 2.74 (.108) 28 2726 25 24 23 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.75 (.187) 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
lt3640 3640f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) p ackage descrip t ion
lt3640 3640f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0510 ? printed in usa r ela t e d p ar t s typical a pplica t ion 2mhz 3.3v/0.8a and 0.8v/1.2a buck regulators 3640 ta05 sync wde pgood 1nf 1nf 1.5nf 1.5nf 32.4k v out2 0.8v/1.2a v out1 3.3v/0.8a 22f rst1 rst2 wdo wdi fb2 cwdt cpor rt gnd ss2 ss1 sw2 sw1 en/uvlo v in sw lt3640 bst v in2 fb1 0.47h 49.9k 16.5k 80.6k 49.9k 3.3h 0.22f da 22f 4.7f v in 4v to 35v en2 part number description comments lt3689 36v, 60v transient protection, 800ma, 2.2mhz high effciency micropower step-down dc/dc converter with por reset and watchdog timer v in : 3.6v to 36v, transient to 60v, v out(min) = 0.8v, i q = 75a, i sd < 1a, 3mm 3mm qfn-16 package lt3686 37v, 55v max , 1.2a, 2.5mhz high effciency step-down dc/dc converter v in : 3.6v to 37v, transient to 55v, v out(min) = 1.21v, i q = 1.1ma, i sd < 1a, 3mm 3mm dfn-10 package lt3682 36v, 60v max , 1a, 2.2mhz high effciency micropower step-down dc/dc converter v in : 3.6v to 36v, v out(min) = 0.8v, i q = 75a, i sd < 1a, 3mm 3mm dfn-12 package lt3971 38v, 1.2a (i out ), 2mhz, high effciency step-down dc/dc converter with only 2.8a of quiescent current v in : 4.2v to 38v, v out(min) = 1.2v, i q = 2.8a, i sd < 1a, 3mm 3mm dfn-10, msop-10e packages lt3991 55v, 1.2a (i out ), 2mhz, high effciency step-down dc/dc converter with only 2.8a of quiescent current v in : 4.2v to 55v, v out(min) = 1.2v, i q = 2.8a, i sd < 1a, 3mm 3mm dfn-10, msop-10e packages

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