-top view- c-mos ecc and rll1-7 encode (gate array) * * * * * il16 CXD8941BQ(1/3) 1 10 20 30 40 41 50 60 70 121 130 140 150 81 90 100 110 120 80 160 v ss v dd = +5v
v ss = gnd v dd 13 v ss 23 v ss v dd 13 v ss 23 v ss v dd 13 v ss v dd 13 v ss 23 v ss v ss v dd 13 v ss v ss v ss 23 v ss v ss v ss v dd 13 v ss 23 v ss v ss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 94 95 96 97 98 99 100 93 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 pin no. signal i/o pin no. signal i/o pin no. signal i/o pin no. signal i/o v dd vss v dd vss vss v dd vss vss (fix) vss (fix) vss vss v dd (fix) vss vss vss (fix) v dd vss vss (fix) vss v dd dpbuf cs dp cs ck32m sodn socn sodt soct ck46m ptc cs bufc cs pi oe1 po we1 pi oe2 po we2 spc cs0 spc cs1 sps rst v dd v dd (fix) vss vss cpu rst tgntsel ram1 a0 ram1 a1 ram1 a2 ram1 a3 ram1 a4 ram1 a5 ram1 a6 ram1 a7 ram1 a8 ram1 a9 ram1 a10 ram1 a11 ram1 a13 ram1 a12 ram1 i/o 0 ram1 i/o 1 ram1 i/o 2 ram1 i/o 3 ram1 i/o 4 ram1 i/o 5 ram1 i/o 6 ram1 i/o 7 ram1 we weext weint bp 0 bp 1 sidn 0 sicn sidn 1 renn rsmn wrstn wrstt rent rsmt bp 2 bp 3 sm en chsel sidt 0 sidt 1 sict ram2 i/o 0 ram2 i/o 1 ram2 i/o 2 ram2 i/o 3 ram2 i/o 4 ram2 i/o 5 ram2 i/o 6 ram2 i/o 7 ram2 we ram2 a0 ram2 a1 ram2 a2 ram2 a3 ram2 a4 ram2 a5 ram2 a6 ram2 a7 ram2 a8 ram2 a9 ram2 a10 ram2 a11 ram2 a12 ram2 a13 vss vss mclk bp 4 bp 5 bp 6 bp 7 dir crcert data i/o 7 ck25m buf en crcern derrt derrn ecctest data i/o 6 data i/o 5 CXD8941BQ(2/3) data i/o 3 data i/o 2 data i/o 1 data i/o 0 cs3 cs4 cs6 spc r/w uds lds cpu ck wrh wrl wait cpu d0 cpu d1 cpu d2 cpu d3 cpu d4 cpu d5 cpu d6 cpu d7 rd cpu a1 cpu a2 cpu a3 cpu a4 cpu a5 cpu a6 cpu a7 ca11 cpu a0 i o o o o o o i i i o o o o o o o o o o o o o o o o o o o o o o o i/o i/o i/o i/o i/o i i i i o o o i/o i/o i/o i/o i/o i/o i/o i/o o i o o o i i i i i i i i i i/o i/o i/o o o o o o o o o o o o o o o o o o o o o o o o o o i i i i/o i/o i/o i i i i i i i i i i i/o i/o i/o i/o i/o i/o i/o i/o o i i i o o o i i/o i/o i/o i/o i/o i i data i/o 4
CXD8941BQ(3/3) cpu d 0-7
dataio 0-7
ram1 io 0-7
ram2 io 0-7 cpu data
data i/o
memory1 data
memory2 data ;
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; input/output ca11
chsel
ck25m
ck32m
ck46m
cpu a 0-7
cpu ck
cpu rst
cs3, 4, 6
ecctest
mclk
rd
renn
rent
rsmn
rsmt
sicn
sict
sidn 0, 1
sidt 0, 1
tgntsel
weext
wrh
wrl
wrstn
wrstt cpu address 11
channel select (l : ch1/h : ch2)
memory controller clock 2.5 mhz
channel clock (inside) 32 mhz
channel clock (outside) 46 mhz
cpu address
cpu clock (20 mhz)
reset
chip select
h : ecc test mode
ecc master clock (10 mhz)
cpu read
read enable (inside)
read enable (outside)
reset sector mark (inside)
reset sector mark (outside)
serial in clock (inside)
serial in clock (outside)
serial in data (inside)
serial in data (outside)
ref. timing select (l : inside, h : outside)
external we in
cpu write (high)
cpu write (low)
write reset (inside)
write reset (outside) ;
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; input bit port
buffer enable
buffer controller chip select [ocycend]
crc error (inside)
crc error (outside)
data error (inside)
data error (outside)
direction l : encode/h : decode
dual port ram chip select [ocdend]
dual port buffer chip select [ostart]
spc lower data select
port1 read
port2 read [usgerr]
port1 write
port2 write
pulse train controller chip select
memory1 address
memory1 write enable
memory2 address
memory2 write enable
sector mark enable
serial out clock (inside)
serial out clock (outside)
serial out data (inside)
serial out data (outside) [ocodeerr]
scsi protocol controller chip select
spc read/write (h : read/l : write)
scsi protocol controller reset
spc upper data select
cpu wait
internal we out bp 0-7
buf en
bufc cs
crcern
crcert
derrn
derrt
dir
dp cs
dpbuf cs
lds
pi oe1
pi oe2
po we1
po we2
ptc cs
ram1 a 0-13
ram1 we
ram2 a 0-13
ram2 we
sm en
socn
soct
sodn
sodt
spc cs 0, 1
spc r w
spc rst
uds
wait
weint ;
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; output
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