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| LRS1B12 64m (x16) flash + 64m (x16) flash date mar . 5. 2003 32m (x16) scram + 8m (x16) sram .com .com .com .com 4 .com u datasheet
LRS1B12 ? ? ? ? ? ? ? ? ? ? .com .com .com .com .com 4 .com u datasheet LRS1B12 1 contents 1. description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5. recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6. flash memory 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1.1 bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1.2 simultaneous operation modes allowed with four planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 command definitions for flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2.1 command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2.2 identifier codes for read operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2.3 functions of block lock and block lock-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2.4 block locking state transitions upon command write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2.5 block locking state transitions upon wp transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.4 memory map for flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 dc electrical characteristics for flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.6 ac electrical characteristics for flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6.1 ac test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6.2 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6.3 write cycle (f-we / f 1 -ce controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.6.4 block erase, full chip erase, (page buffer) program performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6.5 flash memory ac characteristics timing chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.6.6 reset operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7. flash memory 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1.1 bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1.2 simultaneous operation modes allowed with four planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 command definitions for flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.2.1 command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.2.2 identifier codes for read operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2.3 functions of block lock and block lock-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2.4 block locking state transitions upon command write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2.5 block locking state transitions upon wp transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.4 memory map for flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.5 dc electrical characteristics for flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.6 ac electrical characteristics for flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.6.1 ac test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.6.2 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.6.3 write cycle (f-we / f 2 -ce controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.6.4 block erase, full chip erase, (page buffer) program performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.6.5 flash memory ac characteristics timing chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.6.6 reset operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 .com .com .com .com .com 4 .com u datasheet LRS1B12 2 8. smartcombo ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.1 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.1.1 bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.2 dc electrical characteristics for smartcombo ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.3 ac electrical characteristics for smartcombo ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.3.1 ac test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.3.2 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.3.3 write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.3.4 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.3.5 sleep mode entry / exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.4 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.5 page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.5.1 features of page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.6 mode register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.6.1 mode register setting method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.6.2 cautions for setting mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.7 smartcombo ram ac characteristics timing chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9. sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.1 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.1.1 bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.2 dc electrical characteristics for sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.3 ac electrical characteristics for sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.3.1 ac test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.3.2 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.3.3 write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.4 sram ac characteristics timing chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.5 data retention characteristics for sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10. notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11. flash memory data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12. design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13. related document information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 14. package and packing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 .com .com .com .com .com 4 .com u datasheet LRS1B12 3 1. description the LRS1B12 is a combination memory organized as 4,194,304 x16 bit flash memory, 4,194,304 x16 bit flash memory, 2,097,152 x16 bit smartcombo ram and 524,288 x16 bit static ram in one package. features -power supply ? ? ? ? 2.7v to 3.1v -operating temperature ? ? ? ? -25c to +85c -not designed or rated as radiation hardened -72 pin csp(lcsp072-p-0811) plastic package -flash memory has p-type bulk silicon, and smartcombo ram has p-type bulk silicon, and sram has p-type bulk silicon -flash memory and smartcombo ram share one power supply pin (f/sc-v cc ) -for specifications of flash memory, smartcombo ram and sram, refer to specification of each chip standby current of flash memory and smartcombo ram -power supply current ? ? ? ? 150 a (max.) flash memory 1 (f 1 : 64m (x16) bit flash memory) -access time (address) ? ? ? ? 65 ns (max.) -power supply current (the current for f/sc-v cc pin and v pp pin) read ? ? ? ? 25 ma (max. t cycle = 200ns, cmos input) word write ? ? ? ? 60 ma (max.) block erase ? ? ? ? 30 ma (max.) flash memory 2 (f 2 : 64m (x16) bit flash memory) -access time (address) ? ? ? ? 65 ns (max.) -power supply current (the current for f/sc-v cc pin and v pp pin) read ? ? ? ? 25 ma (max. t cycle = 200ns, cmos input) word write ? ? ? ? 60 ma (max.) block erase ? ? ? ? 30 ma (max.) smartcombo ram (32m (x16) bit smartcombo ram) -access time (address) ? ? ? ? 65 ns (max.) -cycle time ? ? ? ? 65 ns (min.) -power supply current operating current ? ? ? ? 50 ma (max. t rc , t wc = min.) sram (8m (x16) bit sram) -access time (address) ? ? ? ? 65 ns (max.) -power supply current operating current ? ? ? ? 45 ma (max. t rc , t wc = min.) standby current ? ? ? ? 15 a (max.) .com .com .com .com .com 4 .com u datasheet LRS1B12 4 2. pin configuration nc nc gnd a 16 a 11 a 8 a 10 a 15 a 14 a 9 dq 15 a 13 a 12 1 234 5 6 7 8 s-we f-we rst t 1 f-a 21 ry/by s-a 17 t 2 dq 12 dq 13 dq 6 ce 2 wp lb v pp ub s-oe a 19 dq 11 t 3 dq 9 f/sc -v cc dq 10 dq 8 a b c d e f g a 18 f-a 17 a 7 a 6 a 3 a 2 gnd 9 dq 14 dq 4 s-v cc dq 2 dq 0 a 1 nc 10 dq 7 dq 5 f/sc -v cc dq 3 dq 1 sc-ce 1 nc 11 nc 12 nc h nc a 5 a 4 a 0 gnd f-oe s-ce 1 nc nc f 1 -ce index (top view) a 20 f 2 -ce note) from t 1 to t 3 pins are needed to be open. two nc pins at the corner are connected. do not float any gnd pins. .com .com .com .com .com 4 .com u datasheet LRS1B12 5 pin description type a 0 to a 16 , a 18 address inputs (common) input a 19 to a 20 address inputs (flash, smartcombo ram) input f-a 17, f-a 21 address inputs (flash) input s-a 17 address input (sram, smartcombo ram) input f 1 -ce chip enable input (flash - f 1 selected) input f 2 -ce chip enable input (flash - f 2 selected) input sc-ce 1 chip enable input (smartcombo ram) input s-ce 1 chip enable input (sram) input ce 2 chip enable input (sram), sleep state input (smartcombo ram) input f-we write enable input (flash) input s-we write enable input (sram, smartcombo ram) input f-oe output enable input (flash) input s-oe output enable input (sram, smartcombo ram) input lb sram, smartcombo ram byte enable input (dq 0 to dq 7 ) input ub sram, smartcombo ram byte enable input (dq 8 to dq 15 ) input rst reset power down input (flash) block erase and write : v ih read : v ih reset power down : v il input wp write protect input (flash) when wp is v il , locked-down blocks cannot be unlocked. erase or program operation can be executed to the blocks which are not locked and locked-down. when wp is v ih , lock-down is disabled. input ry/by ready/busy output (flash) during an erase or write operation : v ol block erase and write suspend : high-z (high impedance) open drain output dq 0 to dq 15 data inputs and outputs (common) input / output f/sc-v cc power supply (flash, smartcombo ram) power s-v cc power supply (sram) power v pp monitoring power supply voltage (flash) block erase and write : v pp = v pph all blocks locked : v pp < v pplk input gnd gnd (common) power nc non connection - t 1 to t 3 test pins (should be all open) - * see chapter b-1 .com .com .com .com .com 4 .com u datasheet LRS1B12 6 3. block diagram f 1 : 64m (x16) bit flash memory f 2 : 64m (x16) bit flash memory v pp s-v cc gnd f/sc-v cc dq 0 to dq 15 ry/by f-a 17 f-a 21 a 0 to a 16 a 18 f-oe, f-we, wp, rst f 1 -ce f 2 -ce 32m (x16) bit smartcombo ram 8m (x16) bit sram s-a 17 a 19 to a 20 sc-ce 1 s-ce 1 ce 2 , s-oe, s-we, lb, ub note: only one among f 1 -ce, f 2 -ce, sc-ce 1 and s-ce 1 can be ?low?. two or more should not be ?low?. .com .com .com .com .com 4 .com u datasheet LRS1B12 7 4. absolute maximum ratings notes: 1. the maximum applicable voltage on any pins with respect to gnd. 2. -1.0v undershoot is allowed when the pulse width is less than 5 nsec. 3. v in should not be over v cc +0.3v. 5. recommended dc operating conditions (t a = -25c to +85c) notes: 1. v cc is the lower of f/sc-v cc or s-v cc . 2. v cc is the higher of f/sc-v cc or s-v cc . 3. v cc includes both f/sc-v cc and s-v cc . symbol parameter notes ratings unit v cc supply voltage 1 -0.2 to +3.9 v v in input voltage 1,2,3 -0.5 to v cc +0.3 v t a operating temperature -25 to +85 c t stg storage temperature -55 to +125 c v pp v pp voltage 1,2 -0.2 to +3.6 v symbol parameter notes min. typ. max. unit v cc supply voltage 3 2.7 3.1 v v pp v pp voltage (write operation) 1.65 3.1 v v pp voltage (read operation) 03.1v v ih input voltage v cc -0.4 (2) v cc +0.3 (1) v v il input voltage -0.3 0.4 v .com .com .com .com .com 4 .com u datasheet LRS1B12 8 6. flash memory 1 6.1 truth table 6.1.1 bus operation (1) notes: 1. l = v il , h = v ih , x = h or l, high-z = high impedance. refer to the dc characteristics. 2. command writes involving block erase, full chip erase, (page buffer) program are reliably executed when v pp = v pph and v cc = 2.7v to 3.1 v . block erase, full chip erase, (page buffer) program with v pp < v pph (min.) produce spurious results and should not be attempted. 3. never hold f-oe low and f-we low at the same timing. 4. refer to section 6.2 command definitions for flash memory valid d in during a write operation. 5. wp set to v il or v ih . 6. electricity consumption of flash memory is lowest when rst = gnd 0.2v. 7. flash read mode flash notes f 1 -ce rst f-oe f-we dq 0 to dq 15 read 3,5 lh l h (7) output disable 5 h high - z write 2,3,4,5 l d in standby 5 h h xxhigh - z reset power down 5,6 x l mode address dq 0 to dq 15 read array x d out read identifier codes see 6.2.2 see 6.2.2 read query refer to the appendix refer to the appendix .com .com .com .com .com 4 .com u datasheet LRS1B12 9 6.1.2 simultaneous operation modes allowed with four planes (1,2) notes: 1. ?x? denotes the operation available. 2. configurative partition dual work restrictions: status register reflects partition state, not wsm (write state machine) state - this allows a status register for each partitio n. only one partition can be erased or programmed at a time - no command queuing. commands must be written to an address within the block targeted by that command. if one partition is: then the modes allowed in the other partition is: read array read id read status read query word program page buffer program block erase full chip erase program suspend block erase suspend read arrayxxxxxxx xx read idxxx xxxx xx read statusxxx xxxxxxx read query x x x x x x x x x word program x x x x x page buffer program xxx x x block erase x x x x full chip erase x program suspend xxx x x block erase suspend xxx xxx x .com .com .com .com .com 4 .com u datasheet LRS1B12 10 6.2 command definitions for flash memory (11) 6.2.1 command definitions notes: 1. bus operations are defined in 6.1.1 bus operation. 2. all addresses which are written at the first bus cycle should be the same as the addresses which are written at the second bus cycle. x=any valid address within the device. pa=address within the selected partition. ia=identifier codes address (see 6.2.2 identifier codes for read operation). qa=query codes address. refer to the lh28f320bf, lh28f640bf, lh28f128bf series appendix for details. ba=address within the block being erased, set/cleared block lock bit or set block lock-down bit. wa=address of memory location for the program command or the first address for the page buffer program command. pcrc=partition configuration register code presented on the address a 0 -a 15 . 3. id=data read from identifier codes (see 6.2.2 identifier codes for read operation). qd=data read from query database. refer to the lh28f320bf, lh28f640bf, lh28f128bf series appendix for details. srd=data read from status register. see 6.3 register definition for a description of the status register bits. wd= data to be programmed at location wa. data is latched on the rising edge of f-we or f 1 -ce (whichever goes high first) during command write cycles. n-1=n is the number of the words to be loaded into a page buffer. 4. following the read identifier codes command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code (see 6.2.2 identifier codes for read operation). the read query command is available for reading cfi (common flash interface) information. 5. block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. unlocked block can be erased or programmed when rst is v ih . 6. either 40h or 10h are recognized by the cui (command user interface) as the program setup. 7. following the third bus cycle, input the program sequential address and write data of ?n? times. finally, input the any valid address within the target block to be programmed and the confirm command (d0h). refer to the lh28f320bf, lh28f640bf, lh28f128bf series appendix for details. command bus cycles req?d notes first bus cycle second bus cycle oper (1) address (2) data oper (1) address (2) data (3) read array 1 write pa ffh read identifier codes ? ? .com .com .com .com .com 4 .com u datasheet LRS1B12 11 8. if the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. full chip erase operation can not be suspended. 10. following the clear block lock bit command, block which is not locked-down is unlocked when wp is v il . when wp is v ih , lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. commands other than those shown above are reserved by sharp for future device implementations and should not be used. .com .com .com .com .com 4 .com u datasheet LRS1B12 12 6.2.2 identifier codes for read operation notes: 1. bottom parameter device has its parameter blocks in the plane 0 (the lowest address). 2. block address = the beginning location of a block address within the partition to which the read identifier codes command (90h) has been written. dq 15 -dq 2 is reserved for future implementation. 3. pcrc = partition configuration register code. 4. the address a 21 -a 16 are shown in below table for reading the manufacturer, device, device configuration code. the address to read the identifier codes is dependent on the partition which is selected when writing the read identifier codes command (90h). see section 6.3 partition configuration register definition (p.17) for the partition configuration register. identifier codes for read operation on partition configuration (64m (x16)-bit device) code address [a 15 -a 0 ] data [dq 15 -dq 0 ] notes manufacturer code manufacturer code 0000h 00b0h 4 device code 64m (x16) bottom parameter device code 0001h 00b1h 1, 4 block lock configuration code block is unlocked block address + 2 dq 0 = 0 2 block is locked dq 0 = 1 2 block is not locked-down dq 1 = 0 2 block is locked-down dq 1 = 1 2 device configuration code partition configuration register 0006h pcrc 3, 4 partition configuration register address (64m (x16)-bit device) pcr.10 pcr.9 pcr.8 [a 21 -a 16 ] 00000h 0 0 1 00h or 10h 0 1 0 00h or 20h 1 0 0 00h or 30h 0 1 1 00h or 10h or 20h 1 1 0 00h or 20h or 30h 1 0 1 00h or 10h or 30h 1 1 1 00h or 10h or 20h or 30h .com .com .com .com .com 4 .com u datasheet LRS1B12 13 6.2.3 functions of block lock and block lock-down notes: 1. dq 0 = 1: a block is locked; dq 0 = 0: a block is unlocked. dq 1 = 1: a block is locked-down; dq 1 = 0: a block is not locked-down. 2. erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 3. at power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (wp = 0) or [101] (wp = 1), regardless of the states before power-off or reset operation. 4. when wp is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 6.2.4 block locking state transitions upon command write (4) notes: 1. ?set lock? means set block lock bit command, ?clear lock? means clear block lock bit command and ?set lock- down? means set block lock-down bit command. 2. when the set block lock-down bit command is written to the unlocked block (dq 0 = 0), the corresponding block is locked-down and automatically locked at the same time. 3. ?no change? means that the state remains unchanged after the command written. 4. in this state transitions table, assumes that wp is not changed and fixed v il or v ih . current state erase/program allowed (2) state wp dq 1 (1) dq 0 (1) state name [000] 0 0 0 unlocked yes [001] (3) 0 0 1 locked no [011] 0 1 1 locked-down no [100] 1 0 0 unlocked yes [101] (3) 1 0 1 locked no [110] (4) 1 1 0 lock-down disable yes [111] 1 1 1 lock-down disable no current state result after lock command written (next state) state wp dq 1 dq 0 set lock (1) clear lock (1) set lock-down (1) [000] 0 0 0 [001] no change [011] (2) [001] 0 0 1 no change (3) [000] [011] [011] 0 1 1 no change no change no change [100] 1 0 0 [101] no change [111] (2) [101] 1 0 1 no change [100] [111] [110] 1 1 0 [111] no change [111] (2) [111] 1 1 1 no change [110] no change .com .com .com .com .com 4 .com u datasheet LRS1B12 14 6.2.5 block locking state transitions upon wp transition (4) notes: 1. ?wp = 0 ? ? ? ? ? ? .com .com .com .com .com 4 .com u datasheet LRS1B12 15 6.3 register definition status register definition rrrrrrrr 15 14 13 12 11 10 9 8 wsms bess befces pbps vpps pbpss dps r 76543210 sr.15 - sr.8 = reserved for future enhancements (r) sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = block erase suspend status (bess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = block erase and full chip erase status (befces) 1 = error in block erase or full chip erase 0 = successful block erase or full chip erase sr.4 = (page buffer) program status (pbps) 1 = error in (page buffer) program 0 = successful (page buffer) program sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok sr.2 = (page buffer) program suspend status (pbpss) 1 = (page buffer) program suspended 0 = (page buffer) program in progress/completed sr.1 = device protect status (dps) 1 = erase or program attempted on a locked block, operation abort 0 = unlocked sr.0 =reserved for future enhancements (r) notes: status register indicates the status of the partition, not wsm (write state machine). even if the sr.7 is ?1?, the wsm may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. check sr.7 or ry/by to determine block erase, full chip erase, (page buffer) program completion. sr.6 - sr.1 are invalid while sr.7= ?0?. if both sr.5 and sr.4 are ?1?s after a block erase, full chip erase, (page buffer) program, set/clear block lock bit, set block lock-down bit or set partition configuration register attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after block erase, full chip erase, (page buffer) program com- mand sequences. sr.3 is not guaranteed to report accurate feedback when v pp ? .com .com .com .com .com 4 .com u datasheet LRS1B12 16 extended status register definition rrrrrrrr 15 14 13 12 11 10 9 8 smsrrrrrrr 76543210 xsr.15-8 = reserved for future enhancements (r) xsr.7 = state machine status (sms) 1 = page buffer program available 0 = page buffer program not available xsr.6-0 = reserved for future enhancements (r) notes: after issue a page buffer program command (e8h), xsr.7= ? 1 ? indicates that the entered command is accepted. if xsr.7 is ? 0 ? , the command is not accepted and a next page buffer program command (e8h) should be issued again to check if page buffer is available or not. xsr.15-8 and xsr.6-0 are reserved for future use and should be masked out when polling the extended status register. .com .com .com .com .com 4 .com u datasheet LRS1B12 17 partition configuration register definition partition configuration rrrrrpc2pc1pc0 15 14 13 12 11 10 9 8 rrrrrrrr 76543210 pcr.15-11 = reserved for future enhancements (r) pcr.10-8 = partition configuration (pc2-0) 000 = no partitioning. dual work is not allowed. 001 = plane1-3 are merged into one partition. (default in a bottom parameter device) 010 = plane 0-1 and plane 2-3 are merged into one partition respectively. 100 = plane 0-2 are merged into one partition. (default in a top parameter device) 011 = plane 2-3 are merged into one partition. there are three partitions in this configuration. dual work oper- ation is available between any two partitions. 110 = plane 0-1 are merged into one partition. there are three partitions in this configuration. dual work oper- ation is available between any two partitions. 101 = plane 1-2 are merged into one partition. there are three partitions in this configuration. dual work oper- ation is available between any two partitions. 111 = there are four partitions in this configuration. each plane corresponds to each partition respectively. dual work operation is available between any two partitions. pcr.7-0 = reserved for future enhancements (r) notes: after power-up or device reset, pcr 10-8 (pc2-0) is set to ?001? in a bottom parameter device and ?100? in a top parameter device. see the table below for more details. pcr.15-11 and pcr.7-0 are reserved for future use and should be masked out when checking the partition configuration register. plane1 plane0 plane2 plane3 partition1 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 partition1 partition1 partition0 plane1 plane0 plane2 plane3 partition1 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 partition1 partition1 partition0 partition2 partition3 partition2 partition2 partition1 partition2 000 001 010 100 011 110 101 111 pc2 pc1pc0 partitioning for dual work partitioning for dual work pc2 pc1pc0 .com .com .com .com .com 4 .com u datasheet LRS1B12 18 6.4 memory map for flash memory 6 5 4 3 2 1 0 7 4k-word 007000h - 007fffh 4k-word 006000h - 006fffh 4k-word 005000h - 005fffh 4k-word 004000h - 004fffh 4k-word 003000h - 003fffh 4k-word 002000h - 002fffh 4k-word 001000h - 001fffh 4k-word 000000h - 000fffh plane2 (uniform plane) 92 93 94 95 64 65 72 73 74 75 32k-word 278000h - 27ffffh 32k-word 270000h - 277fffh 32k-word 268000h - 26ffffh 32k-word 260000h - 267fffh 32k-word 258000h - 25ffffh 32k-word 250000h - 257fffh 32k-word 248000h - 24ffffh 32k-word 240000h - 247fffh 32k-word 238000h - 23ffffh 32k-word 230000h - 237fffh 32k-word 228000h - 22ffffh 32k-word 220000h - 227fffh 32k-word 218000h - 21ffffh 32k-word 210000h - 217fffh 32k-word 208000h - 20ffffh 32k-word 200000h - 207fffh 2f8000h - 2fffffh 2f0000h - 2f7fffh 2e8000h - 2effffh 2e0000h - 2e7fffh 2d8000h - 2dffffh 2d0000h - 2d7fffh 2c8000h - 2cffffh 2c0000h - 2c7fffh 2b8000h - 2bffffh 2b0000h - 2b7fffh 2a8000h - 2affffh 2a0000h - 2a7fffh 298000h - 29ffffh 290000h - 297fffh 288000h - 28ffffh 280000h - 287fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 76 78 79 80 81 82 83 77 84 85 66 68 69 70 71 67 86 88 89 90 91 87 plane1 (uniform plane) block number address range 62 63 32 33 34 35 42 43 44 45 32k-word 178000h - 17ffffh 32k-word 170000h - 177fffh 32k-word 168000h - 16ffffh 32k-word 160000h - 167fffh 32k-word 158000h - 15ffffh 32k-word 150000h - 157fffh 32k-word 148000h - 14ffffh 32k-word 140000h - 147fffh 32k-word 138000h - 13ffffh 32k-word 130000h - 137fffh 32k-word 128000h - 12ffffh 32k-word 120000h - 127fffh 32k-word 118000h - 11ffffh 32k-word 110000h - 117fffh 32k-word 108000h - 10ffffh 32k-word 100000h - 107fffh 1f8000h - 1fffffh 1f0000h - 1f7fffh 1e8000h - 1effffh 1e0000h - 1e7fffh 1d8000h - 1dffffh 1d0000h - 1d7fffh 1c8000h - 1cffffh 1c0000h - 1c7fffh 1b8000h - 1bffffh 1b0000h - 1b7fffh 1a8000h - 1affffh 1a0000h - 1a7fffh 198000h - 19ffffh 190000h - 197fffh 188000h - 18ffffh 180000h - 187fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 46 48 49 50 51 52 53 47 54 55 36 38 39 40 41 37 56 58 59 60 61 57 12 13 14 15 32k-word 078000h - 07ffffh 32k-word 070000h - 077fffh 32k-word 068000h - 06ffffh 32k-word 060000h - 067fffh 32k-word 058000h - 05ffffh 32k-word 050000h - 057fffh 32k-word plane0 (parameter plane) 048000h - 04ffffh 32k-word 040000h - 047fffh 32k-word 038000h - 03ffffh 32k-word 030000h - 037fffh 32k-word 028000h - 02ffffh 32k-word 020000h - 027fffh 32k-word 018000h - 01ffffh 32k-word 010000h - 017fffh 32k-word 008000h - 00ffffh 0f8000h - 0fffffh 0f0000h - 0f7fffh 0e8000h - 0effffh 0e0000h - 0e7fffh 0d8000h - 0dffffh 0d0000h - 0d7fffh 0c8000h - 0cffffh 0c0000h - 0c7fffh 0b8000h - 0bffffh 0b0000h - 0b7fffh 0a8000h - 0affffh 0a0000h - 0a7fffh 098000h - 09ffffh 090000h - 097fffh 088000h - 08ffffh 080000h - 087fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 16 18 19 20 21 22 23 17 24 25 8 9 10 11 26 28 29 30 31 27 127 128 129 130 131 132 133 32k-word plane3 (uniform plane) 3f8000h - 3fffffh 122 123 124 102 103 104 105 32k-word 378000h - 37ffffh 32k-word 370000h - 377fffh 32k-word 368000h - 36ffffh 32k-word 360000h - 367fffh 32k-word 358000h - 35ffffh 32k-word 350000h - 357fffh 32k-word 348000h - 34ffffh 32k-word 340000h - 347fffh 32k-word 338000h - 33ffffh 32k-word 330000h - 337fffh 32k-word 328000h - 32ffffh 32k-word 320000h - 327fffh 32k-word 318000h - 31ffffh 32k-word 310000h - 317fffh 32k-word 308000h - 30ffffh 32k-word 300000h - 307fffh 3f0000h - 3f7fffh 3e8000h - 3effffh 3e0000h - 3e7fffh 3d8000h - 3dffffh 3d0000h - 3d7fffh 3c8000h - 3cffffh 3c0000h - 3c7fffh 3b8000h - 3bffffh 3b0000h - 3b7fffh 3a8000h - 3affffh 3a0000h - 3a7fffh 398000h - 39ffffh 390000h - 397fffh 388000h - 38ffffh 380000h - 387fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 106 108 109 110 111 112 113 107 114 115 96 98 99 100 101 97 116 118 119 120 121 117 125 126 134 block number address range bottom parameter .com .com .com .com .com 4 .com u datasheet LRS1B12 19 6.5 dc electrical characteristics for flash memory dc electrical characteristics (t a = -25c to +85c, v cc = 2.7v to 3.1v) symbol parameter notes min. typ. max. unit test conditions c in input capacitance 5 7 pf v in = 0v, f = 1mhz, t a = 25c c io i/o capacitance 5 10 pf v i/o = 0v, f = 1mhz, t a = 25c i li input leakage current 1 ? ? ? ? ? .com .com .com .com .com 4 .com u datasheet LRS1B12 20 dc electrical characteristics (continue) (t a = -25c to +85c, v cc = 2.7v to 3.1v) notes: 1. all currents are in rms unless otherwise noted. typical values are the reference values at v cc = 3.0v and t a = +25 ? ? ? ? ? ? ? ? .com .com .com .com .com 4 .com u datasheet LRS1B12 21 6.6 ac electrical characteristics for flash memory 6.6.1 ac test conditions 6.6.2 read cycle (t a = -25c to +85c, v cc = 2.7v to 3.1v) notes: 1. sampled, not 100% tested. 2. f-oe may be delayed up to t elqv ? ? ? ? ? ? .com .com .com .com .com 4 .com u datasheet LRS1B12 22 6.6.3 write cycle (f-we / f 1 -ce controlled) (1,2) (t a = -25c to +85c, v cc = 2.7v to 3.1v) notes: 1. the timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program operations are the same as during read-only operations. see the ac characteristics for read cycle. 2. a write operation can be initiated and terminated with either f 1 -ce or f-we . 3. sampled, not 100% tested. 4. write pulse width (t wp ) is defined from the falling edge of f 1 -ce or f-we (whichever goes low last) to the rising edge of f 1 -ce or f-we (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . 5. write pulse width high (t wph ) is defined from the rising edge of f 1 -ce or f-we (whichever goes high first) to the falling edge of f 1 -ce or f-we (whichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 6. v pp should be held at v pp =v pph until determination of block erase, full chip erase, (page buffer) program success (sr.1/ 3/4/5=0). 7. t whr0 (t ehr0 ) after the read query or read identifier codes command=t avqv +100ns. 8. see 6.2.1 command definitions for valid address and data for block erase, full chip erase, (page buffer) program or lock bit configuration. symbol parameter notes min. max. unit t avav write cycle time 65 ns t phwl (t phel ) rst high recovery to f-we ( f 1 -ce ) going low 3 150 ns t elwl (t wlel )f 1 -ce ( f-we ) setup to f-we (f 1 -ce ) going low 0ns t wlwh (t eleh ) f-we (f 1 -ce ) pulse width 450 ns t dvwh (t dveh ) data setup to f-we (f 1 -ce ) going high 840 ns t av w h (t av e h ) address setup to f-we (f 1 -ce ) going high 850 ns t wheh (t ehwh )f 1 -ce ( f-we ) hold from f-we (f 1 -ce ) high 0ns t whdx (t ehdx ) data hold from f-we (f 1 -ce ) high 0ns t whax (t ehax ) address hold from f-we (f 1 -ce ) high 0ns t whwl (t ehel ) f-we (f 1 -ce ) pulse width high 515 ns t shwh (t sheh )wp high setup to f-we (f 1 -ce ) going high 30 ns t vvwh (t vveh )v pp setup to f-we (f 1 -ce ) going high 3 200 ns t whgl (t ehgl ) write recovery before read 30 ns t qvsl wp high hold from valid srd, ry/by high-z 3, 6 0 ns t qvvl v pp hold from valid srd, ry/by high-z 3, 6 0 ns t whr0 (t ehr0 ) f-we (f 1 -ce ) high to sr.7 going ?0? 3, 7 t avqv +50 ns t whrl (t ehrl ) f-we (f 1 -ce ) high to ry/by going low 3 100 ns .com .com .com .com .com 4 .com u datasheet LRS1B12 23 6.6.4 block erase, full chip erase, (page buffer) program performance (3) (t a = -25c to +85c, v cc = 2.7v to 3.1v) notes: 1. typical values measured at v cc =3.0v, v pp =3.0v, and t a =+25 ? ? ? ? .com .com .com .com .com 4 .com u datasheet LRS1B12 24 6.6.5 flash memory ac characteristics timing chart ac waveform for single asynchronous read operations from status register, identifier codes or query code t avqv t ehqz t ghqz t elqv t phqv t glqv t oh v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il (d/q) (a) a 21-0 dq 15-0 high-z t elqx valid output valid address t avav t glqx t ghgl t ehel t avel t avgl t glax t elax t oh (e) f 1 -ce (g) f-oe (w) f-we (p) rst .com .com .com .com .com 4 .com u datasheet LRS1B12 25 ac waveform for asynchronous 4-word page mode read operations from main blocks or parameter blocks t avqv valid address valid address valid address valid address valid address t avav t elqv t ehqz t ghqz t oh t apa t glqv t phqv high-z v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il (p) (d/q) (w) (g) (e) (a) a 21-3 v ih v il (a) a 2-0 dq 15-0 f 1 -ce f-oe f-we rst t glqx t elqx valid output valid output valid output valid output .com .com .com .com .com 4 .com u datasheet LRS1B12 26 ac waveform for asynchronous 8-word page mode read operations from main blocks or parameter blocks valid output valid output valid output valid output valid output valid output valid output valid output t avqv t elqv t ehqz t ghqz t oh t apa t glqv t phqv t glqx t elqx valid address t avav valid address valid address valid address valid address valid address valid address valid address valid address high-z v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il (p) (d/q) (w) (g) (e) (a) a 21-3 v ih v il (a) a 2-0 dq 15-0 f 1 -ce f-oe f-we rst .com .com .com .com .com 4 .com u datasheet LRS1B12 27 ac waveform for write operations (f- we / f 1 - ce controlled) t avav t avwh (t aveh ) t whax (t ehax ) t elwl (t wlel ) t phwl (t phel ) t wlwh t whwl (t ehel ) t whdx (t ehdx ) t dvwh (t dveh ) t shwh (t sheh ) t vvwh (t vveh ) t whqv1,2,3 (t ehqv1,2,3 ) t qvsl t qvvl t wheh (t ehwh )t whgl (t ehgl ) v ih v il v ih v il v ih v il v ih v il v ih v il notes 5, 6 notes 5, 6 v ih v pph v pplk v il v il v ih v il (t eleh ) note 1 note 2 note 3 note 4 note 5 valid address valid address valid address data in data in valid srd notes: 1. v cc power-up and standby. 2. write each first cycle command. 3. write each second cycle command or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. for read operation, f-oe and f 1 -ce must be driven active, and f-we de-asserted. ( ? 1 ? ) ( ? 0 ? ) t whr0 (t ehr0 ) high-z v ol t whrl (t ehrl ) (d/q) (w) (g) (e) (a) a 21-0 dq 15-0 (v) v pp (p) rst f 1 -ce f-oe f-we (s) wp ry/by(r) (sr.7) .com .com .com .com .com 4 .com u datasheet LRS1B12 28 6.6.6 reset operations (t a = -25c to +85c, v cc = 2.7v to 3.1v) notes: 1. a reset time, t phqv , is required from the later of sr.7 (ry/by ) going ?1? (high-z) or rst going high until outputs are valid. see the ac characteristics - read cycle for t phqv . 2. t plph is <100ns the device may still reset but this is not guaranteed. 3. sampled, not 100% tested. 4. if rst asserted while a block erase, full chip erase or (page buffer) program operation is not executing, the reset will complete within 100ns. 5. when the device power-up, holding rst low minimum 100ns is required after v cc has been in predefined range and also has been in stable there. ac waveform for reset operation symbol parameter notes min. max. unit t plph rst low to reset during read (rst should be low during power-up.) 1, 2, 3 100 ns t plrh rst low to reset during erase or program 1, 3, 4 22 abort complete t plph t plph t vph t plrh t phqv t phqv (a) reset during read array mode (b) reset during erase or program mode (c) rst rising timing rst rst v il v ih v il v ih v cc gnd 2.7v rst v il v ih sr.7= ?1? v oh v ol (d/q) dq 15-0 valid output high-z (p) (p) (p) v oh v ol (d/q) dq 15-0 valid output high-z v oh v ol (d/q) dq 15-0 valid output high-z t phqv t vhqv .com .com .com .com .com 4 .com u datasheet LRS1B12 29 7. flash memory 2 7.1 truth table 7.1.1 bus operation (1) notes: 1. l = v il , h = v ih , x = h or l, high-z = high impedance. refer to the dc characteristics. 2. command writes involving block erase, full chip erase, (page buffer) program are reliably executed when v pp = v pph and v cc = 2.7v to 3.1 v . block erase, full chip erase, (page buffer) program with v pp < v pph (min.) produce spurious results and should not be attempted. 3. never hold f-oe low and f-we low at the same timing. 4. refer to section 7.2 command definitions for flash memory valid d in during a write operation. 5. wp set to v il or v ih . 6. electricity consumption of flash memory is lowest when rst = gnd 0.2v. 7. flash read mode flash notes f 2 -ce rst f-oe f-we dq 0 to dq 15 read 3,5 lh l h (7) output disable 5 h high - z write 2,3,4,5 l d in standby 5 h h xxhigh - z reset power down 5,6 x l mode address dq 0 to dq 15 read array x d out read identifier codes see 7.2.2 see 7.2.2 read query refer to the appendix refer to the appendix .com .com .com .com .com 4 .com u datasheet LRS1B12 30 7.1.2 simultaneous operation modes allowed with four planes (1,2) notes: 1. ?x? denotes the operation available. 2. configurative partition dual work restrictions: status register reflects partition state, not wsm (write state machine) state - this allows a status register for each partitio n. only one partition can be erased or programmed at a time - no command queuing. commands must be written to an address within the block targeted by that command. if one partition is: then the modes allowed in the other partition is: read array read id read status read query word program page buffer program block erase full chip erase program suspend block erase suspend read arrayxxxxxxx xx read idxxx xxxx xx read statusxxx xxxxxxx read query x x x x x x x x x word program x x x x x page buffer program xxx x x block erase x x x x full chip erase x program suspend xxx x x block erase suspend xxx xxx x .com .com .com .com .com 4 .com u datasheet LRS1B12 31 7.2 command definitions for flash memory (11) 7.2.1 command definitions notes: 1. bus operations are defined in 7.1.1 bus operation. 2. all addresses which are written at the first bus cycle should be the same as the addresses which are written at the second bus cycle. x=any valid address within the device. pa=address within the selected partition. ia=identifier codes address (see 7.2.2 identifier codes for read operation). qa=query codes address. refer to the lh28f320bf, lh28f640bf, lh28f128bf series appendix for details. ba=address within the block being erased, set/cleared block lock bit or set block lock-down bit. wa=address of memory location for the program command or the first address for the page buffer program command. pcrc=partition configuration register code presented on the address a 0 -a 15 . 3. id=data read from identifier codes (see 7.2.2 identifier codes for read operation). qd=data read from query database. refer to the lh28f320bf, lh28f640bf, lh28f128bf series appendix for details. srd=data read from status register. see 7.3 register definition for a description of the status register bits. wd= data to be programmed at location wa. data is latched on the rising edge of f-we or f 2 - ce (whichever goes high first) during command write cycles. n-1=n is the number of the words to be loaded into a page buffer. 4. following the read identifier codes command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code (see 7.2.2 identifier codes for read operation). the read query command is available for reading cfi (common flash interface) information. 5. block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. unlocked block can be erased or programmed when rst is v ih . 6. either 40h or 10h are recognized by the cui (command user interface) as the program setup. 7. following the third bus cycle, input the program sequential address and write data of ?n? times. finally, input the any valid address within the target block to be programmed and the confirm command (d0h). refer to the lh28f320bf, lh28f640bf, lh28f128bf series appendix for details. command bus cycles req?d notes first bus cycle second bus cycle oper (1) address (2) data oper (1) address (2) data (3) read array 1 write pa ffh read identifier codes ? ? .com .com .com .com .com 4 .com u datasheet LRS1B12 32 8. if the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. full chip erase operation can not be suspended. 10. following the clear block lock bit command, block which is not locked-down is unlocked when wp is v il . when wp is v ih , lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. commands other than those shown above are reserved by sharp for future device implementations and should not be used. .com .com .com .com .com 4 .com u datasheet LRS1B12 33 7.2.2 identifier codes for read operation notes: 1. bottom parameter device has its parameter blocks in the plane 0 (the lowest address). 2. block address = the beginning location of a block address within the partition to which the read identifier codes command (90h) has been written. dq 15 -dq 2 is reserved for future implementation. 3. pcrc = partition configuration register code. 4. the address a 21 -a 16 are shown in below table for reading the manufacturer, device, device configuration code. the address to read the identifier codes is dependent on the partition which is selected when writing the read identifier codes command (90h). see section 7.3 partition configuration register definition (p.38) for the partition configuration register. identifier codes for read operation on partition configuration (64m (x16)-bit device) code address [a 15 -a 0 ] data [dq 15 -dq 0 ] notes manufacturer code manufacturer code 0000h 00b0h 4 device code 64m (x16) bottom parameter device code 0001h 00b1h 1, 4 block lock configuration code block is unlocked block address + 2 dq 0 = 0 2 block is locked dq 0 = 1 2 block is not locked-down dq 1 = 0 2 block is locked-down dq 1 = 1 2 device configuration code partition configuration register 0006h pcrc 3, 4 partition configuration register address (64m (x16)-bit device) pcr.10 pcr.9 pcr.8 [a 21 -a 16 ] 00000h 0 0 1 00h or 10h 0 1 0 00h or 20h 1 0 0 00h or 30h 0 1 1 00h or 10h or 20h 1 1 0 00h or 20h or 30h 1 0 1 00h or 10h or 30h 1 1 1 00h or 10h or 20h or 30h .com .com .com .com .com 4 .com u datasheet LRS1B12 34 7.2.3 functions of block lock and block lock-down notes: 1. dq 0 = 1: a block is locked; dq 0 = 0: a block is unlocked. dq 1 = 1: a block is locked-down; dq 1 = 0: a block is not locked-down. 2. erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 3. at power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (wp = 0) or [101] (wp = 1), regardless of the states before power-off or reset operation. 4. when wp is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 7.2.4 block locking state transitions upon command write (4) notes: 1. ?set lock? means set block lock bit command, ?clear lock? means clear block lock bit command and ?set lock- down? means set block lock-down bit command. 2. when the set block lock-down bit command is written to the unlocked block (dq 0 = 0), the corresponding block is locked-down and automatically locked at the same time. 3. ?no change? means that the state remains unchanged after the command written. 4. in this state transitions table, assumes that wp is not changed and fixed v il or v ih . current state erase/program allowed (2) state wp dq 1 (1) dq 0 (1) state name [000] 0 0 0 unlocked yes [001] (3) 0 0 1 locked no [011] 0 1 1 locked-down no [100] 1 0 0 unlocked yes [101] (3) 1 0 1 locked no [110] (4) 1 1 0 lock-down disable yes [111] 1 1 1 lock-down disable no current state result after lock command written (next state) state wp dq 1 dq 0 set lock (1) clear lock (1) set lock-down (1) [000] 0 0 0 [001] no change [011] (2) [001] 0 0 1 no change (3) [000] [011] [011] 0 1 1 no change no change no change [100] 1 0 0 [101] no change [111] (2) [101] 1 0 1 no change [100] [111] [110] 1 1 0 [111] no change [111] (2) [111] 1 1 1 no change [110] no change .com .com .com .com .com 4 .com u datasheet LRS1B12 35 7.2.5 block locking state transitions upon wp transition (4) notes: 1. ?wp = 0 ? ? ? ? ? ? .com .com .com .com .com 4 .com u datasheet LRS1B12 36 7.3 register definition status register definition rrrrrrrr 15 14 13 12 11 10 9 8 wsms bess befces pbps vpps pbpss dps r 76543210 sr.15 - sr.8 = reserved for future enhancements (r) sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = block erase suspend status (bess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = block erase and full chip erase status (befces) 1 = error in block erase or full chip erase 0 = successful block erase or full chip erase sr.4 = (page buffer) program status (pbps) 1 = error in (page buffer) program 0 = successful (page buffer) program sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok sr.2 = (page buffer) program suspend status (pbpss) 1 = (page buffer) program suspended 0 = (page buffer) program in progress/completed sr.1 = device protect status (dps) 1 = erase or program attempted on a locked block, operation abort 0 = unlocked sr.0 =reserved for future enhancements (r) notes: status register indicates the status of the partition, not wsm (write state machine). even if the sr.7 is ?1?, the wsm may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. check sr.7 or ry/by to determine block erase, full chip erase, (page buffer) program completion. sr.6 - sr.1 are invalid while sr.7= ?0?. if both sr.5 and sr.4 are ?1?s after a block erase, full chip erase, (page buffer) program, set/clear block lock bit, set block lock-down bit or set partition configuration register attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after block erase, full chip erase, (page buffer) program com- mand sequences. sr.3 is not guaranteed to report accurate feedback when v pp ? .com .com .com .com .com 4 .com u datasheet LRS1B12 37 extended status register definition rrrrrrrr 15 14 13 12 11 10 9 8 smsrrrrrrr 76543210 xsr.15-8 = reserved for future enhancements (r) xsr.7 = state machine status (sms) 1 = page buffer program available 0 = page buffer program not available xsr.6-0 = reserved for future enhancements (r) notes: after issue a page buffer program command (e8h), xsr.7= ? 1 ? indicates that the entered command is accepted. if xsr.7 is ? 0 ? , the command is not accepted and a next page buffer program command (e8h) should be issued again to check if page buffer is available or not. xsr.15-8 and xsr.6-0 are reserved for future use and should be masked out when polling the extended status register. .com .com .com .com .com 4 .com u datasheet LRS1B12 38 partition configuration register definition partition configuration rrrrrpc2pc1pc0 15 14 13 12 11 10 9 8 rrrrrrrr 76543210 pcr.15-11 = reserved for future enhancements (r) pcr.10-8 = partition configuration (pc2-0) 000 = no partitioning. dual work is not allowed. 001 = plane1-3 are merged into one partition. (default in a bottom parameter device) 010 = plane 0-1 and plane 2-3 are merged into one partition respectively. 100 = plane 0-2 are merged into one partition. (default in a top parameter device) 011 = plane 2-3 are merged into one partition. there are three partitions in this configuration. dual work oper- ation is available between any two partitions. 110 = plane 0-1 are merged into one partition. there are three partitions in this configuration. dual work oper- ation is available between any two partitions. 101 = plane 1-2 are merged into one partition. there are three partitions in this configuration. dual work oper- ation is available between any two partitions. 111 = there are four partitions in this configuration. each plane corresponds to each partition respectively. dual work operation is available between any two partitions. pcr.7-0 = reserved for future enhancements (r) notes: after power-up or device reset, pcr 10-8 (pc2-0) is set to ?001? in a bottom parameter device and ?100? in a top parameter device. see the table below for more details. pcr.15-11 and pcr.7-0 are reserved for future use and should be masked out when checking the partition configuration register. plane1 plane0 plane2 plane3 partition1 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 partition1 partition1 partition0 plane1 plane0 plane2 plane3 partition1 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 partition1 partition1 partition0 partition2 partition3 partition2 partition2 partition1 partition2 000 001 010 100 011 110 101 111 pc2 pc1pc0 partitioning for dual work partitioning for dual work pc2 pc1pc0 .com .com .com .com .com 4 .com u datasheet LRS1B12 39 7.4 memory map for flash memory 6 5 4 3 2 1 0 7 4k-word 007000h - 007fffh 4k-word 006000h - 006fffh 4k-word 005000h - 005fffh 4k-word 004000h - 004fffh 4k-word 003000h - 003fffh 4k-word 002000h - 002fffh 4k-word 001000h - 001fffh 4k-word 000000h - 000fffh plane2 (uniform plane) 92 93 94 95 64 65 72 73 74 75 32k-word 278000h - 27ffffh 32k-word 270000h - 277fffh 32k-word 268000h - 26ffffh 32k-word 260000h - 267fffh 32k-word 258000h - 25ffffh 32k-word 250000h - 257fffh 32k-word 248000h - 24ffffh 32k-word 240000h - 247fffh 32k-word 238000h - 23ffffh 32k-word 230000h - 237fffh 32k-word 228000h - 22ffffh 32k-word 220000h - 227fffh 32k-word 218000h - 21ffffh 32k-word 210000h - 217fffh 32k-word 208000h - 20ffffh 32k-word 200000h - 207fffh 2f8000h - 2fffffh 2f0000h - 2f7fffh 2e8000h - 2effffh 2e0000h - 2e7fffh 2d8000h - 2dffffh 2d0000h - 2d7fffh 2c8000h - 2cffffh 2c0000h - 2c7fffh 2b8000h - 2bffffh 2b0000h - 2b7fffh 2a8000h - 2affffh 2a0000h - 2a7fffh 298000h - 29ffffh 290000h - 297fffh 288000h - 28ffffh 280000h - 287fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 76 78 79 80 81 82 83 77 84 85 66 68 69 70 71 67 86 88 89 90 91 87 plane1 (uniform plane) block number address range 62 63 32 33 34 35 42 43 44 45 32k-word 178000h - 17ffffh 32k-word 170000h - 177fffh 32k-word 168000h - 16ffffh 32k-word 160000h - 167fffh 32k-word 158000h - 15ffffh 32k-word 150000h - 157fffh 32k-word 148000h - 14ffffh 32k-word 140000h - 147fffh 32k-word 138000h - 13ffffh 32k-word 130000h - 137fffh 32k-word 128000h - 12ffffh 32k-word 120000h - 127fffh 32k-word 118000h - 11ffffh 32k-word 110000h - 117fffh 32k-word 108000h - 10ffffh 32k-word 100000h - 107fffh 1f8000h - 1fffffh 1f0000h - 1f7fffh 1e8000h - 1effffh 1e0000h - 1e7fffh 1d8000h - 1dffffh 1d0000h - 1d7fffh 1c8000h - 1cffffh 1c0000h - 1c7fffh 1b8000h - 1bffffh 1b0000h - 1b7fffh 1a8000h - 1affffh 1a0000h - 1a7fffh 198000h - 19ffffh 190000h - 197fffh 188000h - 18ffffh 180000h - 187fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 46 48 49 50 51 52 53 47 54 55 36 38 39 40 41 37 56 58 59 60 61 57 12 13 14 15 32k-word 078000h - 07ffffh 32k-word 070000h - 077fffh 32k-word 068000h - 06ffffh 32k-word 060000h - 067fffh 32k-word 058000h - 05ffffh 32k-word 050000h - 057fffh 32k-word plane0 (parameter plane) 048000h - 04ffffh 32k-word 040000h - 047fffh 32k-word 038000h - 03ffffh 32k-word 030000h - 037fffh 32k-word 028000h - 02ffffh 32k-word 020000h - 027fffh 32k-word 018000h - 01ffffh 32k-word 010000h - 017fffh 32k-word 008000h - 00ffffh 0f8000h - 0fffffh 0f0000h - 0f7fffh 0e8000h - 0effffh 0e0000h - 0e7fffh 0d8000h - 0dffffh 0d0000h - 0d7fffh 0c8000h - 0cffffh 0c0000h - 0c7fffh 0b8000h - 0bffffh 0b0000h - 0b7fffh 0a8000h - 0affffh 0a0000h - 0a7fffh 098000h - 09ffffh 090000h - 097fffh 088000h - 08ffffh 080000h - 087fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 16 18 19 20 21 22 23 17 24 25 8 9 10 11 26 28 29 30 31 27 127 128 129 130 131 132 133 32k-word plane3 (uniform plane) 3f8000h - 3fffffh 122 123 124 102 103 104 105 32k-word 378000h - 37ffffh 32k-word 370000h - 377fffh 32k-word 368000h - 36ffffh 32k-word 360000h - 367fffh 32k-word 358000h - 35ffffh 32k-word 350000h - 357fffh 32k-word 348000h - 34ffffh 32k-word 340000h - 347fffh 32k-word 338000h - 33ffffh 32k-word 330000h - 337fffh 32k-word 328000h - 32ffffh 32k-word 320000h - 327fffh 32k-word 318000h - 31ffffh 32k-word 310000h - 317fffh 32k-word 308000h - 30ffffh 32k-word 300000h - 307fffh 3f0000h - 3f7fffh 3e8000h - 3effffh 3e0000h - 3e7fffh 3d8000h - 3dffffh 3d0000h - 3d7fffh 3c8000h - 3cffffh 3c0000h - 3c7fffh 3b8000h - 3bffffh 3b0000h - 3b7fffh 3a8000h - 3affffh 3a0000h - 3a7fffh 398000h - 39ffffh 390000h - 397fffh 388000h - 38ffffh 380000h - 387fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 106 108 109 110 111 112 113 107 114 115 96 98 99 100 101 97 116 118 119 120 121 117 125 126 134 block number address range bottom parameter .com .com .com .com .com 4 .com u datasheet LRS1B12 40 7.5 dc electrical characteristics for flash memory dc electrical characteristics (t a = -25c to +85c, v cc = 2.7v to 3.1v) symbol parameter notes min. typ. max. unit test conditions c in input capacitance 5 7 pf v in = 0v, f = 1mhz, t a = 25c c io i/o capacitance 5 10 pf v i/o = 0v, f = 1mhz, t a = 25c i li input leakage current 1 ? ? ? ? ? .com .com .com .com .com 4 .com u datasheet LRS1B12 41 dc electrical characteristics (continue) (t a = -25c to +85c, v cc = 2.7v to 3.1v) notes: 1. all currents are in rms unless otherwise noted. typical values are the reference values at v cc = 3.0v and t a = +25 ? ? ? ? ? ? ? ? .com .com .com .com .com 4 .com u datasheet LRS1B12 42 7.6 ac electrical characteristics for flash memory 7.6.1 ac test conditions 7.6.2 read cycle (t a = -25c to +85c, v cc = 2.7v to 3.1v) notes: 1. sampled, not 100% tested. 2. f-oe may be delayed up to t elqv ? ? ? ? ? ? .com .com .com .com .com 4 .com u datasheet LRS1B12 43 7.6.3 write cycle (f-we / f 2 -ce controlled) (1,2) (t a = -25c to +85c, v cc = 2.7v to 3.1v) notes: 1. the timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program operations are the same as during read-only operations. see the ac characteristics for read cycle. 2. a write operation can be initiated and terminated with either f 2 -ce or f-we . 3. sampled, not 100% tested. 4. write pulse width (t wp ) is defined from the falling edge of f 2 -ce or f-we (whichever goes low last) to the rising edge of f 2 -ce or f-we (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . 5. write pulse width high (t wph ) is defined from the rising edge of f 2 -ce or f-we (whichever goes high first) to the falling edge of f 2 -ce or f-we (whichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 6. v pp should be held at v pp =v pph until determination of block erase, full chip erase, (page buffer) program success (sr.1/ 3/4/5=0). 7. t whr0 (t ehr0 ) after the read query or read identifier codes command=t avqv +100ns. 8. see 7.2.1 command definitions for valid address and data for block erase, full chip erase, (page buffer) program or lock bit configuration. symbol parameter notes min. max. unit t avav write cycle time 65 ns t phwl (t phel ) rst high recovery to f-we ( f 2 -ce ) going low 3 150 ns t elwl (t wlel )f 2 -ce ( f-we ) setup to f-we (f 2 -ce ) going low 0ns t wlwh (t eleh ) f-we (f 2 -ce ) pulse width 450 ns t dvwh (t dveh ) data setup to f-we (f 2 -ce ) going high 840 ns t av w h (t av e h ) address setup to f-we (f 2 -ce ) going high 850 ns t wheh (t ehwh )f 2 -ce ( f-we ) hold from f-we (f 2 -ce ) high 0ns t whdx (t ehdx ) data hold from f-we (f 2 -ce ) high 0ns t whax (t ehax ) address hold from f-we (f 2 -ce ) high 0ns t whwl (t ehel ) f-we (f 2 -ce ) pulse width high 515 ns t shwh (t sheh )wp high setup to f-we (f 2 -ce ) going high 30 ns t vvwh (t vveh )v pp setup to f-we (f 2 -ce ) going high 3 200 ns t whgl (t ehgl ) write recovery before read 30 ns t qvsl wp high hold from valid srd, ry/by high-z 3, 6 0 ns t qvvl v pp hold from valid srd, ry/by high-z 3, 6 0 ns t whr0 (t ehr0 ) f-we (f 2 -ce ) high to sr.7 going ?0? 3, 7 t avqv +50 ns t whrl (t ehrl ) f-we (f 2 -ce ) high to ry/by going low 3 100 ns .com .com .com .com .com 4 .com u datasheet LRS1B12 44 7.6.4 block erase, full chip erase, (page buffer) program performance (3) (t a = -25c to +85c, v cc = 2.7v to 3.1v) notes: 1. typical values measured at v cc =3.0v, v pp =3.0v, and t a =+25 ? ? ? ? .com .com .com .com .com 4 .com u datasheet LRS1B12 45 7.6.5 flash memory ac characteristics timing chart ac waveform for single asynchronous read operations from status register, identifier codes or query code t avqv t ehqz t ghqz t elqv t phqv t glqv t oh v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il (d/q) (a) a 21-0 dq 15-0 high-z t elqx valid output valid address t avav t glqx t ghgl t ehel t avel t avgl t glax t elax t oh (e) f 2 -ce (g) f-oe (w) f-we (p) rst .com .com .com .com .com 4 .com u datasheet LRS1B12 46 ac waveform for asynchronous 4-word page mode read operations from main blocks or parameter blocks t avqv valid address valid address valid address valid address valid address t avav t elqv t ehqz t ghqz t oh t apa t glqv t phqv high-z v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il (p) (d/q) (w) (g) (e) (a) a 21-3 v ih v il (a) a 2-0 dq 15-0 f 2 -ce f-oe f-we rst t glqx t elqx valid output valid output valid output valid output .com .com .com .com .com 4 .com u datasheet LRS1B12 47 ac waveform for asynchronous 8-word page mode read operations from main blocks or parameter blocks valid output valid output valid output valid output valid output valid output valid output valid output t avqv t elqv t ehqz t ghqz t oh t apa t glqv t phqv t glqx t elqx valid address t avav valid address valid address valid address valid address valid address valid address valid address valid address high z v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il (p) (d/q) (w) (g) (e) (a) a 21-3 v ih v il (a) a 2-0 dq 15-0 f 2 -ce f-oe f-we rst .com .com .com .com .com 4 .com u datasheet LRS1B12 48 ac waveform for write operations (f- we / f 2 - ce controlled) t avav t avwh (t aveh ) t whax (t ehax ) t elwl (t wlel ) t phwl (t phel ) t wlwh t whwl (t ehel ) t whdx (t ehdx ) t dvwh (t dveh ) t shwh (t sheh ) t vvwh (t vveh ) t whqv1,2,3 (t ehqv1,2,3 ) t qvsl t qvvl t wheh (t ehwh )t whgl (t ehgl ) v ih v il v ih v il v ih v il v ih v il v ih v il notes 5, 6 notes 5, 6 v ih v pph v pplk v il v il v ih v il (t eleh ) note 1 note 2 note 3 note 4 note 5 valid address valid address valid address data in data in valid srd notes: 1. v cc power-up and standby. 2. write each first cycle command. 3. write each second cycle command or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. for read operation, f-oe and f 2 -ce must be driven active, and f-we de-asserted. ( ? 1 ? ) ( ? 0 ? ) t whr0 (t ehr0 ) high-z v ol t whrl (t ehrl ) (d/q) (w) (g) (e) (a) a 21-0 dq 15-0 (v) v pp (p) rst f 2 -ce f-oe f-we (s) wp ry/by(r) (sr.7) .com .com .com .com .com 4 .com u datasheet LRS1B12 49 7.6.6 reset operations (t a = -25c to +85c, v cc = 2.7v to 3.1v) notes: 1. a reset time, t phqv , is required from the later of sr.7 (ry/by ) going ?1? (high-z) or rst going high until outputs are valid. see the ac characteristics - read cycle for t phqv . 2. t plph is <100ns the device may still reset but this is not guaranteed. 3. sampled, not 100% tested. 4. if rst asserted while a block erase, full chip erase or (page buffer) program operation is not executing, the reset will complete within 100ns. 5. when the device power-up, holding rst low minimum 100ns is required after v cc has been in predefined range and also has been in stable there. ac waveform for reset operation symbol parameter notes min. max. unit t plph rst low to reset during read (rst should be low during power-up.) 1, 2, 3 100 ns t plrh rst low to reset during erase or program 1, 3, 4 22 abort complete t plph t plph t vph t plrh t phqv t phqv (a) reset during read array mode (b) reset during erase or program mode (c) rst rising timing rst rst v il v ih v il v ih v cc gnd 2.7v rst v il v ih sr.7= ?1? v oh v ol (d/q) dq 15-0 valid output high-z (p) (p) (p) v oh v ol (d/q) dq 15-0 valid output high-z v oh v ol (d/q) dq 15-0 valid output high-z t phqv t vhqv .com .com .com .com .com 4 .com u datasheet LRS1B12 50 8. smartcombo ram 8.1 truth table 8.1.1 bus operation (1) notes: 1. l = v il , h = v ih , x = h or l, high-z = high impedance. refer to the dc characteristics. 2. ce 2 pin must be fixed to high level except sleep mode. 3. lb , ub control mode smartcombo ram notes sc-ce 1 ce 2 s-oe s-we lb ub dq 0 to q 15 read l h lh (3) (3) output disable hhxx high - z write h l (3) (3) standby h xx xx high - z xhh sleep 2 x l x x lb ub dq 0 to dq 7 dq 8 to dq 15 ll d out /d in d out /d in lh d out /d in high - z hl high - z d out /d in .com .com .com .com .com 4 .com u datasheet LRS1B12 51 8.2 dc electrical characteristics for smartcombo ram dc electrical characteristics (t a = -25c to +85c, v cc = 2.7v to 3.1v) notes: 1. sampled, not 100% tested. 2. memory cell data is held. (ce 2 = ?v ih ?) 3. memory cell data is not held. (ce 2 = ?v il ?) symbol parameter notes min. typ. max. unit test conditions c in input capacitance 1 8 pf v in = 0v c io i/o capacitance 1 10 pf v i/o = 0v i li input leakage current 1 a v in = v cc or gnd i lo output leakage current 1 a v out = v cc or gnd i sb v cc standby current 2100a sc-ce 1 .com .com .com .com .com 4 .com u datasheet LRS1B12 52 8.3 ac electrical characteristics for smartcombo ram 8.3.1 ac test conditions notes: 1. including scope and socket capacitance. 2. ac characteristics directed with the note should be measured with the output load shown in below. input pulse level 0.2v cc to 0.8v cc input rise and fall time 5 ns input and output timing ref. level 1/2 v cc output load 1ttl +c l (30pf) (1, 2) dq (output) zo=50 ? 1/2 v cc c l 50 ? .com .com .com .com .com 4 .com u datasheet LRS1B12 53 8.3.2 read cycle (t a = -25c to +85c, v cc = 2.7v to 3.1v) notes: 1. t clol and t op (max.) are applied while sc-ce 1 is being hold at low level. 2. t bhah is specified after both lb and ub are high. symbol parameter notes min. max. unit t rc read cycle time 65 ns t aa address access time 65 ns t ace chip enable access time 65 ns t oe output enable to output valid 45 ns t be byte enable access time 65 ns t paa page access time 20 ns t oh output hold from address change 5 ns t prc page read cycle time 20 ns t clz sc-ce 1 low to output active 10 ns t olz s-oe low to output active 5 ns t blz ub or lb low to output active 5 ns t chz sc-ce 1 high to output in high-z 25 ns t ohz s-oe high to output in high-z 25 ns t bhz ub or lb high to output in high-z 25 ns t aso address setup to s-oe low 0 ns t ohah s-oe high level to address hold -5 ns t chah sc-ce 1 high level to address hold 0ns t bhah lb , ub high level to address hold 20 ns t clol sc-ce 1 low level to s-oe low level 1 0 10,000 ns t olch s-oe low level to sc-ce 1 high level 45 ns t cp sc-ce 1 high level pulse width 10 ns t bp lb , ub high level pulse width 10 ns t op s-oe high level pulse width 1 2 10,000 ns .com .com .com .com .com 4 .com u datasheet LRS1B12 54 8.3.3 write cycle (t a = -25c to +85c, v cc = 2.7v to 3.1v) notes: 1. t oes and t oeh (max.) are applied while sc-ce 1 is being hold at low level. 2. t bhah is specified after both lb and ub are high. symbol parameter notes min. max. unit t wc write cycle time 65 ns t cw chip enable to end of write 55 ns t aw address valid to end of write 55 ns t bw byte select time 55 ns t wp write pulse width 50 ns t wr write recovery time 0 ns t cp sc-ce 1 high level pulse width 10 ns t bp lb , ub high level pulse width 10 ns t whp s-we high pulse width 10 ns t whz s-we low to output in high-z 25 ns t ow s-we high to output active 15 ns t as address setup time 0 ns t dw input data setup time 30 ns t dh input data hold time 0 ns t ohah s-oe high level to address hold -5 ns t chah sc-ce 1 high level to address hold 0ns t bhah lb , ub high level to address hold 20 ns t oes s-oe high level to s-we set 1 0 10,000 ns t oeh s-we high level to s-oe set 1 10 10,000 ns .com .com .com .com .com 4 .com u datasheet LRS1B12 55 8.3.4 initialization (t a = -25c to +85c, v cc = 2.7v to 3.1v) 8.3.5 sleep mode entry / exit (t a = -25c to +85c, v cc = 2.7v to 3.1v) symbol parameter notes min. max. unit t vhmh power application to ce 2 low level hold 50 s t chmh sc-ce 1 high level to ce 2 high level 10 ns t mhcl following power application ce 2 high level hold to sc-ce 1 low level 300 s symbol parameter notes min. max. unit t chml sleep mode entry sc-ce 1 high level to ce 2 low level 0ns t mhcl sleep mode exit to normal operation ce 2 high level to sc-ce 1 low level 300 s .com .com .com .com .com 4 .com u datasheet LRS1B12 56 8.4 initialization initialize the power application using the following sequence to stabilize internal circuits. (1) following power application, make ce 2 high level after fixing ce 2 to low level for the period of t vhmh . make sc-ce 1 high level before making ce 2 high level. (2) sc-ce 1 and ce 2 are fixed to high level for the period of t mhcl . normal operation is possible after the completion of initialization. initialization normal operation t chmh t vhmh t mhcl v cc (min.) v ih v il v il v ih ce 2 sc-ce 1 v cc notes: 1. make ce 2 low level when starting the power supply. 2. t vhmh is specified from when the power supply voltage reaches the prescribed minimum value (v cc min.). .com .com .com .com .com 4 .com u datasheet LRS1B12 57 standby mode state machine power on initial state active standby mode sc-ce 1 = v il , ce 2 = v ih sc-ce 1 = v il sc-ce 1 = v ih , ce 2 = v ih a sc-ce 1 = v ih or v il , ce 2 = v il sc-ce 1 = v ih or v il , ce 2 = v il ce 2 = v ih .com .com .com .com .com 4 .com u datasheet LRS1B12 58 8.5 page read operation 8.5.1 features of page read operation (2) notes: 1. an interrupt is output when sc-ce 1 = high or in case a 3 or a higher address changes. 2. page length: 8 words is supported as the page lengths. page-corresponding addresses: the page read-enabled addresses are a 2 , a 1 , and a 0 . fix addresses other than a 2 , a 1 , and a 0 during page read operation. page start address: since random page read is supported, any address (a 2 , a 1 , a 0 ) can be used as the page read start address. page direction: since random page read is possible, there is not restriction on the page direction. interrupt during page read operation: when generating an interrupt during page read, either make sc-ce 1 high level or change a 3 and higher addresses. when page read is not used: since random page read is supported, even when not using page read, random access is possible as usual. features notes 8 words mode page length 8 words page read-corresponding addresses a 2 , a 1 , a 0 page read start address don?t care page direction don?t care interrupt during page read operation 1 enabled .com .com .com .com .com 4 .com u datasheet LRS1B12 59 8.6 mode register settings the sleep mode can be set using the mode register. since the initial value of the mode register at power application is undefined, be sure to set the mode register after initialization at power application. however, since sleep mode is not entered unless ce 2 = low when sleep mode is not used, it is not necessary to set the mode register. moreover, when using page read without using sleep mode, it is not necessary to set the mode register. 8.6.1 mode register setting method the mode register setting mode can be entered by successively writing two specific data after two continuous reads of the highest address (1fffffh). the mode register setting is a continuous four-cycle operation (two read cycles and two write cycles). commands are written to the command register. the command register is used to latch the addresses and data required for executing commands, and it does not have an exclusive memory area. for the timing chart and flow chart, refer to mode register setting timing chart (p.73), mode register setting flow chart (p.74). following table shows the commands and command sequences. command sequence 4th bus cycle (write cycle) command sequence 1st bus cycle (read cycle) 2nd bus cycle (read cycle) 3rd bus cycle (write cycle) 4th bus cycle (write cycle) address data address data address data address data sleep mode 1fffffh - 1fffffh - 1fffffh 00h 1fffffh 07h dq 1514131211109876543210 mode register setting 0000000000000pl11 page length 1 8 words (p.72) (p.73) .com .com .com .com .com 4 .com u datasheet LRS1B12 60 8.6.2 cautions for setting mode register since, for the mode register setting, the internal counter status is judged by toggling sc-ce 1 and s-oe , toggle sc-ce 1 at every cycle during entry (read cycle twice, write cycle twice), and toggle s-oe like sc-ce 1 at the first and second read cycles. if incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the mode register are not performed correctly. when the highest address (1fffffh) is read consecutively three or more times, the mode register setting entries are cancelled. once the sleep mode has been set in the mode register, these settings are retained until they are set again, while applying the power supply. however, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. for the timing chart and flow chart, refer to mode register setting timing chart (p.73), mode register setting flow chart (p.74). (p.72) (p.73) .com .com .com .com .com 4 .com u datasheet LRS1B12 61 8.7 smartcombo ram ac characteristics timing chart read cycle timing chart 1 (sc- ce 1 controlled) v ih v il address v ih v il sc-ce 1 v ih v il v ih v il v oh v ol s-oe t rc ub lb t ace t ace t clz t chz t chah t chah t clz t chz t cp t cp t rc d out high - z high - z address stable address stable note: 1. in read cycle, ce 2 and s-we should be fixed to high level. valid output valid output .com .com .com .com .com 4 .com u datasheet LRS1B12 62 read cycle timing chart 2 (s- oe controlled) v ih v il address v ih v il sc-ce 1 v ih v il v ih v il v oh v ol s-oe t rc ub lb t rc t aa t aa t oe t aso t aso t oe t aso t olz t ohz t ohah t ohah t bhah t bhah t olz t ohz t op t op d out high - z high - z valid output valid output address stable address stable note: 1. in read cycle, ce 2 and s-we should be fixed to high level. .com .com .com .com .com 4 .com u datasheet LRS1B12 63 read cycle timing chart 3 (sc- ce 1 / s- oe controlled) v ih v il address v ih v il sc-ce 1 v ih v il v ih v il v oh v ol s-oe t rc ub lb t rc t ace t clz t chz t ohah t oe t clol t oe t aso t olz t olz t ohz t ohah t bhah t aa t chah t bhah d out valid output valid output high - z high - z address stable address stable t ohz note: 1. in read cycle, ce 2 and s-we should be fixed to high level. t olch .com .com .com .com .com 4 .com u datasheet LRS1B12 64 read cycle timing chart 4 (address controlled) v ih v il address v ih v il sc-ce 1 v ih v il v ih v il v oh v ol s-oe t rc ub lb t rc t aa t aa t oh t oh t oh d out valid output valid output address stable address stable notes: 1. in read cycle, ce 2 and s-we should be fixed to high level. 2. when read cycle time is less than t rc (min.), the address access time (t aa ) is not guaranteed. .com .com .com .com .com 4 .com u datasheet LRS1B12 65 read cycle timing chart 5 ( lb / ub controlled) v ih v il address v ih v il sc-ce 1 v ih v il v ih v il v oh v ol s-oe t rc ub lb t blz t be t bhz t bhah t bp d out valid output valid output t rc t blz t be t bhz t bhah t bp high - z address stable address stable note: 1. in read cycle, ce 2 and s-we should be fixed to high level. .com .com .com .com .com 4 .com u datasheet LRS1B12 66 8 word page read cycle timing chart v ih v il v ih v il v ih v il v ih v il v oh v ol sc-ce 1 t rc t prc t prc t prc t oh t chz t oe t clol t aa t aso t olz t ohz t chah t ohah t paa t ace t clz t oh t paa t oh t paa t oh d out address stable (a n ) t prc t paa t oh t prc t paa t oh t prc t paa t oh t prc t paa t oh s-oe address ( a 3 to a 16 , s-a 17 , a 18 to a 20 ) page address (a 0 to a 2 ) address stable (a n+1 ) address stable (a n+2 ) address stable (a n+3 ) address stable (a n+4 ) address stable (a n+5 ) address stable (a n+6 ) address stable (a n+7 ) valid output (q n ) valid output (q n+1 ) valid output (q n+2 ) valid output (q n+3 ) valid output (q n+4 ) valid output (q n+5 ) valid output (q n+6 ) valid output (q n+7 ) notes: 1. in read cycle, ce 2 and s-we should be fixed to high level. 2. lb and ub are low level. .com .com .com .com .com 4 .com u datasheet LRS1B12 67 write cycle timing chart 1 (sc- ce 1 controlled)) address sc-ce 1 s-we ub lb t ohah t aso t oes t oeh v ih v il v ih v il v ih v il v ih v il v ih v il t wc v ih v il s-oe t cw t wr t as t wc t cw t wr t as t as t dw t dh t dw t dh t cp t cp d in address stable address stable valid input valid input high - z high - z notes: 1. during address transition, at least one of sc-ce 1 , s-we or lb, ub pins should be inactivated. 2. do not input data to the dq pins while they are in the output state. 3. in write cycle, ce 2 and s-oe should be fixed to high level. 4. write operation is done during the overlap time of a low level sc-ce 1 , s-we, lb and/or ub. .com .com .com .com .com 4 .com u datasheet LRS1B12 68 write cycle timing chart 2 (s- we controlled)) v ih v il address v ih v il sc-ce 1 v ih v il v ih v il s-we t wc ub lb v ih v il s-oe t cw t oes t oeh t cw t chah t bhah t ohah t aso t bhah t wp t as t wc t wp t as t cp t cp t whp address stable address stable t chah t wr t wr notes: 1. during address transition, at least one of sc-ce 1 , s-we or lb, ub pins should be inactivated. 2. do not input data to the dq pins while they are in the output state. 3. in write cycle, ce 2 and s-oe should be fixed to high level. 4. write operation is done during the overlap time of a low level sc-ce 1 , s-we, lb and/or ub. v ih v il t dw t dh t dw t dh d in high - z high - z valid input valid input v oh v ol t whz t ow d out high - z .com .com .com .com .com 4 .com u datasheet LRS1B12 69 write cycle timing chart 3 (s- we controlled)) v ih v il address v ih v il sc-ce 1 v ih v il v ih v il s-we t wc ub lb t aw t aw t wp t wr t as t wc t wp t wr t as t whp d in address stable address stable v ih v il s-oe t oes t oeh t ohah t aso t bhah t bhah notes: 1. during address transition, at least one of sc-ce 1 , s-we or lb, ub pins should be inactivated. 2. do not input data to the dq pins while they are in the output state. 3. in write cycle, ce 2 and s-oe should be fixed to high level. 4. write operation is done during the overlap time of a low level sc-ce 1 , s-we, lb and/or ub. v ih v il t dw t dh t dw t dh high - z high - z valid input valid input v oh v ol t whz t ow d out high - z .com .com .com .com .com 4 .com u datasheet LRS1B12 70 write cycle timing chart 4 ( lb / ub controlled)) v ih v il address v ih v il sc-ce 1 v ih v il v ih v il v ih v il s-we t wc ub lb t bw t wr t as t wc t bw t wr t as t dw t dh t dw t dh t bp t bp d in address stable address stable valid input valid input high - z high - z v ih v il s-oe t oes t oeh t ohah t aso notes: 1. during address transition, at least one of sc-ce 1 , s-we or lb, ub pins should be inactivated. 2. do not input data to the dq pins while they are in the output state. 3. in write cycle, ce 2 and s-oe should be fixed to high level. 4. write operation is done during the overlap time of a low level sc-ce 1 , s-we, lb and/or ub. .com .com .com .com .com 4 .com u datasheet LRS1B12 71 write cycle timing chart 5 ( lb / ub independent controlled)) v ih v il address v ih v il sc-ce 1 v ih v il v ih v il v ih v il ub t wc v ih v il v ih v il lb s-we t bw t wr t as t wc t bw t wr t as t bp t dw t dh t dw t dh d in (dq 0 to dq 7 ) d in (dq 8 to dq 15 ) address stable address stable valid input valid input high - z high - z v ih v il s-oe t oes t oeh t ohah t aso notes: 1. during address transition, at least one of sc-ce 1 , s-we or lb, ub pins should be inactivated. 2. do not input data to the dq pins while they are in the output state. 3. in write cycle, ce 2 and s-oe should be fixed to high level. 4. write operation is done during the overlap time of a low level sc-ce 1 , s-we, lb and/or ub. .com .com .com .com .com 4 .com u datasheet LRS1B12 72 mode register setting timing chart v ih v il address v ih v il sc-ce 1 v ih v il v ih v il v ih v il v ih v il s-oe t rc ub lb s-we mode register setting t rc t wc t wc t wp t wr t wp t wr t dw t dh d in 1fffffh 1fffffh xxxxh xxxxh 1fffffh 1fffffh t dw t dh .com .com .com .com .com 4 .com u datasheet LRS1B12 73 mode register setting flow chart start no no no no no no address = 1fffffh read with toggled the sc-ce 1 , s-oe address = 1fffffh read with toggled the sc-ce 1 , s-oe address = 1fffffh write data = 00h? fail data = 07h? address = 1fffffh write mode register setting exit end .com .com .com .com .com 4 .com u datasheet LRS1B12 74 sleep mode entry / exit timing chart v ih v il sc-ce 1 v ih v il ce 2 t chml t mhcl sleep mode standby mode .com .com .com .com .com 4 .com u datasheet LRS1B12 75 9. sram 9.1 truth table 9.1.1 bus operation (1) notes: 1. l = v il , h = v ih , x = h or l, high-z = high impedance. refer to the dc characteristics. 2. lb , ub control mode sram notes s-ce 1 ce 2 s-oe s-we lb ub dq 0 to dq 15 read lh lh (2) (2) output disable hhxx high - z write x l (2) (2) standby hx xx xx high - z xl xx xx hh lb ub dq 0 to dq 7 dq 8 to dq 15 ll d out /d in d out /d in lh d out /d in high - z hl high - z d out /d in .com .com .com .com .com 4 .com u datasheet LRS1B12 76 9.2 dc electrical characteristics for sram dc electrical characteristics (t a = -25c to +85c, v cc = 2.7v to 3.1v) note: 1. sampled, not 100% tested. symbol parameter notes min. typ. max. unit test conditions c in input capacitance 1 8 pf v in = 0v , f = 1mhz, t a =25 c c io i/o capacitance 1 10 pf v i/o = 0v , f = 1mhz, t a =25 c i li input leakage current 1 a v in = v cc or gnd i lo output leakage current 1 a v out = v cc or gnd i sb v cc standby current 25 a s-ce 1 , ce 2 .com .com .com .com .com 4 .com u datasheet LRS1B12 77 9.3 ac electrical characteristics for sram 9.3.1 ac test conditions note: 1. including scope and socket capacitance. 9.3.2 read cycle (t a = -25c to +85c, v cc = 2.7v to 3.1v) notes: 1. active output to high-z and high-z to output active tests specified for a 200mv transition from steady state levels into the test load. 2. the period from s-ce 1 rise, ub rise, lb rise s-oe rise (ce 2 : falling) to output buffer off is logically 10ns. input pulse level 0.4 v to 2.2 v input rise and fall time 5 ns input and output timing ref. level 1.5 v output load 1ttl + c l (30pf) (1) symbol parameter notes min. max. unit t rc read cycle time 65 ns t aa address access time 65 ns t ace1 chip enable access time (s-ce 1 ) 65 ns t ace2 chip enable access time (ce 2 ) 65 ns t be byte enable access time 65 ns t oe output enable to output valid 40 ns t oh output hold from address change 10 ns t lz1 s-ce 1 low to output active 110 ns t lz2 ce 2 high to output active 110 ns t olz s-oe low to output active 1 5 ns t blz ub or lb low to output active 1 10 ns t hz1 s-ce 1 high to output in high-z 1, 2 0 25 ns t hz2 ce 2 low to output in high-z 1, 2 0 25 ns t ohz s-oe high to output in high-z 1, 2 0 25 ns t bhz ub or lb high to output in high-z 1, 2 0 25 ns .com .com .com .com .com 4 .com u datasheet LRS1B12 78 9.3.3 write cycle (t a = -25c to +85c, v cc = 2.7v to 3.1v) note: 1. active output to high-z and high-z to output active tests specified for a 200mv transition from steady state levels into the test load. symbol parameter notes min. max. unit t wc write cycle time 65 ns t cw chip enable to end of write 60 ns t aw address valid to end of write 60 ns t bw byte select time 60 ns t as address setup time 0 ns t wp write pulse width 50 ns t wr write recovery time 0 ns t dw input data setup time 30 ns t dh input data hold time 0 ns t ow s-we high to output active 1 5 ns t wz s-we low to output in high-z 1 0 25 ns .com .com .com .com .com 4 .com u datasheet LRS1B12 79 9.4 sram ac characteristics timing chart read cycle timing chart v ih v il address v ih v il s-ce 1 v ih v il ce 2 v ih v il ub lb v ih v il s-oe v ih v il s-we v oh v ol dq out t aa high - z high - z t rc t hz1,2 t bhz t ohz t ace1,2 t lz1,2 t blz t olz t be t oe t oh address stable data valid data valid standby device address selection .com .com .com .com .com 4 .com u datasheet LRS1B12 80 write cycle timing chart (s- we controlled) v ih v il address v ih v il s-ce 1 v ih v il ce 2 v ih v il ub lb v ih v il s-oe v ih v il s-we v oh t wz t ow t dh t dw t aw high - z high - z t wc (5) t wr (2) t cw (3) t bw (1) t wp (4) t as address stable data valid valid input data undefined standby device address selection v ol (7,8) dq out v ih v il (6) dq in notes: 1. a write occurs during the overlap of a low s-ce 1 , a high ce 2 and a low s-we. a write begins at the latest transition among s-ce 1 going low, ce 2 going high and s-we going low. a write ends at the earliest transition among s-ce 1 going high, ce 2 going low and s-we going high. t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the later of s-ce 1 going low or ce 2 going high to the end of write. 3. t bw is measured from the time of going low ub or low lb to the end of write. 4. t as is measured from the address valid to beginning of write. 5. t wr is measured from the end of write to the address change. t wr applies in case a write ends at s-ce 1 going high, ce 2 going low or s-we going high. 6. during this period dq pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 7. if s-ce 1 goes low or ce 2 goes high simultaneously with s-we going low or after s-we going low, the outputs remain in high impedance state. 8. if s-ce 1 goes high or ce 2 goes low simultaneously with s-we going high or before s-we going high, the outputs remain in high impedance state. .com .com .com .com .com 4 .com u datasheet LRS1B12 81 write cycle timing chart (s- ce 1 controlled) t aw (1) t wp v ih v il address v ih v il s-ce 1 v ih v il ce 2 v ih v il ub lb v ih v il s-oe v ih v il s-we v oh t dh t dw high - z t wc (5) t wr (2) t cw (3) t bw (4) t as address stable data valid valid input standby device address selection v ol dq out v ih v il dq in notes: 1. a write occurs during the overlap of a low s-ce 1 , a high ce 2 and a low s-we. a write begins at the latest transition among s-ce 1 going low, ce 2 going high and s-we going low. a write ends at the earliest transition among s-ce 1 going high, ce 2 going low and s-we going high. t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the later of s-ce 1 going low or ce 2 going high to the end of write. 3. t bw is measured from the time of going low ub or low lb to the end of write. 4. t as is measured from the address valid to beginning of write. 5. t wr is measured from the end of write to the address change. t wr applies in case a write ends at s-ce 1 going high, ce 2 going low or s-we going high. .com .com .com .com .com 4 .com u datasheet LRS1B12 82 write cycle timing chart ( ub / lb controlled) v ih v il address v ih v il s-ce 1 v ih v il ce 2 v ih v il ub lb v ih v il s-oe v ih v il s-we v oh t dh t dw t aw high - z t wc (5,6) t wr (2) t cw (3) t bw (1) t wp (4,6) t as address stable data valid valid input standby device address selection v ol dq out v ih v il dq in notes: 1. a write occurs during the overlap of a low s-ce 1 , a high ce 2 and a low s-we. a write begins at the latest transition among s-ce 1 going low, ce 2 going high and s-we going low. a write ends at the earliest transition among s-ce 1 going high, ce 2 going low and s-we going high. t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the later of s-ce 1 going low or ce 2 going high to the end of write. 3. t bw is measured from the time of going low ub or low lb to the end of write. 4. t as is measured from the address valid to beginning of write. 5. t wr is measured from the end of write to the address change. t wr applies in case a write ends at s-ce 1 going high, ce 2 going low or s-we going high. 6. ub and lb need to make the time of start of a cycle, and an end ?high? level for reservation of t as and t wr . .com .com .com .com .com 4 .com u datasheet LRS1B12 83 9.5 data retention characteristics for sram (t a = -25c to +85c) notes: 1. reference value at t a = 25c, v cc = 3.0v. 2. s-ce 1 ? ? ? ? ? ? v cc 2.7v v cc -0.4v v ccdr s-ce 1 0v data retention mode s-ce 1 v cc -0.2v t cdr t r n ote: 1. to control the data retention mode at s-ce 1 , fix the input level of ce 2 between ?v ccdr and v ccdr -0.2v? or ?0v and 0.2v? during the data retention mode. v cc 2.7v ce 2 v ccdr 0.4v 0v data retention mode ce 2 0.2v t cdr t r .com .com .com .com .com 4 .com u datasheet LRS1B12 84 10. notes this product is a stacked csp package that a 64m (x16) bit flash memory, a 64m (x16) bit flash memory, a 32m (x16) bit smartcombo ram and a 8m (x16) bit sram are assembled into. -supply power maximum difference (between f/sc-v cc and s-v cc ) of the voltage is less than 0.3v. -power supply and chip enable of flash memory, smartcombo ram and sram two or more chips among flash memory (f 1 , f 2 ), smartcombo ram and sram should not be active simultaneously. if the two memories are active together, possibly they may not operate normally by interference noises or data collision on dq bus. both f/sc-v cc and s-v cc are needed to be applied by the recommended supply voltage at the same time except smartcombo ram sleep mode and/or sram data retention mode. -power up sequence when turning on flash memory power supply, keep rst low. after f/sc-v cc reaches over 2.7v, keep rst low for more than 100 nsec. -device decoupling this is a 4 chips stacked csp package. when one of the chips is active, others are in standby mode. therefor, these power supplies should be designed very carefully. exclusive power supply pins for each memory and gnd pin need careful decoupling of devices. especially, note flash memory, smartcombo ram and sram peak current caused by transition of control signals. when one of the flash memory is in busy mode, (page buffer) program, block erase and full chip erase command should not be inputted to the other (f 1 -ce , f 2 -ce , sc-ce 1 , s-ce 1 , ce 2 ). .com .com .com .com .com 4 .com u datasheet LRS1B12 85 11. flash memory data protection noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions o n some systems. such noises, when induced onto f-we signal or power supply, may be interpreted as false commands and causes undesired memory updating. to protect the data stored in the flash memory against unwanted writing, systems operating with the flash memory should have the following write protect designs, as appropriate: the below describes data protection method. 1. protection of data in each block ? ? ? ? protection against noises on f-we signal to prevent the recognition of false commands as write commands, system designer should consider the method for reducing noises on f-we signal. .com .com .com .com .com 4 .com u datasheet LRS1B12 86 12. design considerations 1. power supply decoupling to avoid a bad effect to the system by flash memory, smartcombo ram and sram power switching characteristics, each device should have a 0.1f ceramic capacitor connected between f/sc-v cc and gnd, between v pp and gnd and between s-v cc and gnd. low inductance capacitors should be placed as close as possible to package leads. 2. v pp trace on printed circuit boards updating the memory contents of flash memories that reside in the target system requires that the printed circuit board designer pay attention to the v pp power supply trace. use similar trace widths and layout considerations given to the f/sc-v cc power bus. 3. the inhibition of overwrite operation please do not execute reprograming ?0? for the bit which has already been programed ?0?. overwrite operation may generate unerasable bit. in case of reprograming ?0? to the data which has been programed ?1?. ?program ?0? for the bit in which you want to change data from ?1? to ?0?. ?program ?1? for the bit which has already been programed ?0?. for example, changing data from ?1011110110111101? to ?1010110110 111100? requires ?1110111111111110? programing. 4. power supply block erase, full chip erase, (page buffer) program with an invalid v pp (see chapter 6.5, 7.5 dc electrical characteristics for flash memory ) produce spurious results and should not be attempted. device operations at invalid f/sc-v cc voltage (see chapter 6.5, 7.5 dc electrical characteristics for flash memory , 8.2 dc electrical characteristics for smartcombo ram ) produce spurious results and should not be attempted. .com .com .com .com .com 4 .com u datasheet LRS1B12 87 13. related document information (1) note: 1. international customers should contact their local sharp or distribution sales offices. document no. document name fum00701 lh28f320bf, lh28f640bf, lh28f128bf series appendix .com .com .com .com .com 4 .com u datasheet .com .com .com .com .com 4 .com u datasheet rev. 1.10 i a-1 recommended operating conditions a-1.1 at device power-up ac timing illustrated in figure a-1 is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a-1. ac timing at device power-up for the ac specifications t vr , t r , t f in the figure, refer to the next page. see the ?ac electrical characteristics for flash memory? described in specifications for the supply voltage range, the operating temperature and the ac specifications not shown in the next page. t vph gnd v cc (min) v il v ih t phqv gnd v ccwh1/2 v il v ih v il v ih v il v ih v il v ih v oh v ol high-z valid output t vr t f t elqv t f t glqv valid t r or t f address v il v ih t avqv t r or t f t r t r *1 to prevent the unwanted writes, system designers should consider the design, which applies v pp to 0v during read operations and v ccwh1/2 (v pph1/2 ) during write or erase operations. see the application note ap-007-sw-e for details. (v pph1/2 ) v cc (p) v pp *1 (v) f-ce (e) f-we (w) f-oe (g) wp (s) (d/q) data (a) address rst (f-be) .com .com .com .com .com 4 .com u datasheet rev. 1.10 ii a-1.1.1 rise and fall time notes: 1. sampled, not 100% tested. 2. this specification is applied for not only the device power-up but also the normal operations. symbol parameter notes min. max. unit t vr v cc rise time 1 0.5 30000 .com .com .com .com .com 4 .com u datasheet rev. 1.10 iii a-1.2 glitch noises do not input the glitch noises which are below v ih (min.) or above v il (max.) on address, data, reset, and control signals, as shown in figure a-2 (b). the acceptable glitch noises are illustrated in figure a-2 (a). figure a-2. waveform for glitch noises see the ?dc electrical characteristics? described in specifications for v ih (min.) and v il (max.). (a) acceptable glitch noises input signal v ih (min.) input signal v ih (min.) input signal v il (max.) input signal v il (max.) (b) not acceptable glitch noises .com .com .com .com .com 4 .com u datasheet rev. 1.10 iv a-2 related document information (1) note: 1. international customers should contact their local sharp or distribution sales office. document no. document name ap-001-sd-e flash memory family software drivers ap-006-pt-e data protection method of sharp flash memory ap-007-sw-e rp#, v pp electric potential switching circuit .com .com .com .com .com 4 .com u datasheet v a-3 status register read operations if ac timing for reading the status register described in specifications is not satisfied, a system processor can check the status register bit sr.15 instead of sr.7 to determine when the erase or program operation has been completed. figure a-3-1. example of checking the status register (in this example, the device contains four partitions.) table a-3-1. status register definition (sr.15 and sr.7) sr.15 = write state machine status: (dq 15 ) 1 = ready in all partitions 0 = busy in any partition sr.7 = write state machine status for each partition: (dq 7 ) 1 = ready in the addressed partition 0 = busy in the addressed partition notes: sr.15 indicates the status of wsm (write state machine). if sr.15="0", erase or program operation is in progress in any partition. sr.7 indicates the status of the partition. if sr.7="0", erase or program operation is in progress in the addressed partition. even if the sr.7 is "1", the wsm may be occupied by the other partition. v ih v il v ih v il v ih v il v ih v il (d/q) (a) address dq 15-0 valid address within partition 0 valid command "1" "0" (r) sr.15 ( partition 0 ) "1" "0" (r) sr.7 ( partition 0 ) "1" "0" (r) sr.15 ( partition 1 ) "1" "0" (r) sr.7 ( partition 1 ) "1" "0" (r) sr.15 ( partition 2 ) "1" "0" (r) sr.7 ( partition 2 ) "1" "0" (r) sr.15 ( partition 3 ) "1" "0" (r) sr.7 ( partition 3 ) plane1 plane0 plane2 plane3 partition0 partition1 partition2 partition3 operation to partition 0 t whr0 (t ehr0 ) valid address within partition 2 valid command operation to partition 2 t whr0 (t ehr0 ) check sr.15 instead of sr.7 in partition 0 check sr.15 instead of sr.7 in partition 2 (w) (e) f-ce f-we .com .com .com .com .com 4 .com u datasheet i b-1 power up sequence of smartcombo ram when turning on smartcombo ram power supply, the following sequence is needed. b-1.1 sequence of smartcombo ram power supply (1) supply power. (2) keep s-ce 2 low longer than or equal to 50s. (see notes *1) (3) keep s-ce 1 and s-ce 2 high longer than or equal to 300s. (see notes *2 ) (4) end of initialization. by executing above (1) to (4), the initialization of chip inside and the power occurred inside become stable. |
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