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1 advanced double-ended pwm controller isl6742b the isl6742b is a high-performance double-ended pwm controller with advanced synchronous rectifier control and current limit features. it is su itable for both current- and voltage-mode control methods. the isl6742b includes complemented pwm outputs for synchronous rectifier (sr) control. the complemented outputs may be dynamically advanced or delayed relative to the main outputs using an external control voltage. its advanced current sensing circuitry employs sample and hold methods to provide a precise average current signal. suitable for average current limiting, a technique which virtually eliminates the current tail-out common to peak current limiting methods, it is also applicable to current sharing circuits and average current mode control. this advanced bicmos design fe atures an adjustable oscillator frequency up to 2mhz, internal over-temperature protection, precision deadtime control, and short propagation delays. additionally, multi-pulse suppressi on ensures alternating output pulses at low duty cycles wh ere pulse skipping may occur. features ? synchronous rectifier control outputs with adjustable delay/advance ? adjustable average current signal ? 3% tolerance cycle-by-cycle peak current limit ? fast current sense to output delay ? adjustable oscillator frequency up to 2mhz ? adjustable deadtime control ? voltage- or current-mode operation ? separate ramp and cs inputs for voltage feed-forward or current-mode applications ? tight tolerance error amplifier reference over line, load, and temperature ? 175a start-up current ? supply uvlo ?adjustable soft-start ? 70ns leading edge blanking ? multi-pulse suppression ? internal over-temperature protection ? pb-free (rohs compliant) applications ? half-bridge, full-bridge, interleaved forward, and push-pull converters ? telecom and datacom power ? wireless base station power ? file server power ? industrial power systems related literature ? see an1890 , ?isl6742beval3z power converter 36v to 75v input, 12v output up to 10a? ordering information part # (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL6742BAAZA isl6742 baaz -40 to +105 16 ld qsop m16.15a notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic pack aged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anne al (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb -free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl6742b . for more information on msl, please see tech brief tb363 . january 31, 2014 fn8565.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl6742b 2 fn8565.0 january 31, 2014 table of contents pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 typical application - telecom primary side control half-bridge co nverter with synchronous rectification . . . . . . . . . . . . . . 6 typical application - high voltage input secondary side control full-bridge converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 soft-start operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 gate drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 overcurrent operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 voltage feed-forward operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 implementing synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 synchronous rectifier outputs and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 parallel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 average current mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 fault conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ground plane requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
isl6742b 3 fn8565.0 january 31, 2014 pin configuration isl6742b (16 ld qsop) top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 vref verr rtd ct fb ramp iout cs ss vdd outa outb outan outbn gnd vadj pin descriptions pin # symbol description 1 vref the 5v reference voltage output having 3% tolerance over lin e, load and operating temperatur e. bypass to gnd with a 0.1f to 2.2f low esr capacitor. 2 verr the verr pin is the output of the error amplifier and cont rols the inverting input of the pwm comparator. feedback compens ation components connect between verr and fb. there is a nominal 1m a pull-up current source connected to verr. soft-start is implemented as a voltage clamp on the verr signal. the outputs, outa and outb, reduce to 0% duty cycle when ve rr is pulled below 0.6v. outan and outbn, the complements of outa and outb, respectively, go to 100% duty cycle when this occurs. 3 rtd this is the oscillator timing capaci tor discharge current control pin. the current flowing in a resistor connected between this pin and gnd determines the magnitude of the current that discharges ct. the ct discharge current is nomi nally 20x the resistor current. the pwm deadtime is determined by the timing capacitor discha rge duration. the voltage at rtd is nominally 2v. the minimum recommended value of rtd is 2.00k ? . 4 ct the oscillator timing capaci tor is connected between this pi n and gnd. it is charged through an internal 200a current sourc e and discharged with a user adjustable current source controlled by rtd. 5 fb fb is the inverting input to the error amplifier (ea). the am plifier may be used as the error amplifier for voltage feedback or used as the average current limit amplifier (iea). if th e amplifier is not used, fb should be grounded. 6 ramp this is the input for the sawtooth waveform for the pwm comp arator. the ramp pin is shorted to gnd at the termination of t he pwm signal. a sawtooth voltage waveform is required at this inpu t. for current-mode control this pin is connected directly to c s and the current loop feedback signal is applied to both inputs. for voltage-mode control, the oscillator sawtooth waveform may be buffered and used to generate an appropriate signal, or ramp may be connected to the input voltage through an rc network for voltage feed forward control, or ramp may be connected to vref through an rc network to produce the desired sawtooth waveform. 7 cs this is the input to the overcurrent comparator and the averag e current sample and hold circuit. the overcurrent comparator threshold is set at 1v nominal. the cs pin is shorted to gnd at the termination of either pwm output. depending on the current sensing source impedance, a series inpu t resistor may be required due to the delay between the interna l clock and the external power switch. this delay may result in cs being discharged prior to the power switching device being tur ned off. 8 iout output of the 4x buffer amplifier of the sample and hold circuitry that captures and averages the cs signal. 9 gnd signal and power ground connections for this device. due to high peak currents an d high frequency operation, a low impedanc e layout is necessary. ground planes an d short traces are highly recommended. 11, 10 outan and outbn these outputs are the complements of outa and outb, respecti vely. these outputs are suitable for control of synchronous rectifiers. the phase relationship between each output and it s complement is set by a control voltage applied to vadj. 13, 12 outa and outb these paired outputs are the pulse width modulated outputs for controlling the switching fets in alternate sequence.
isl6742b 4 fn8565.0 january 31, 2014 14 vdd vdd is the power connection for the ic. to optimize noise immunity, bypass vdd to gnd with a 0.1f or larger high frequenc y ceramic capacitor as close to th e vdd and gnd pins as possible. vdd is monitored for supply voltage undervoltage lock-out (uvlo) . the start and stop thresholds track each other resulting in relatively constant hysteresis. 15 vadj a 0v to 5v control voltage applied to this input sets th e relative delay or advance between outa/outb and outan/outbn. voltages below 2.425v result in outan/outbn being advanced relative to outa/outb. voltages above 2.575v result in outan/outbn being delayed relative to outa/outb. a voltage of 2.50v 75mv results in zero phase difference. a weak internal 50% divider from vref results in no phas e delay if this input is left floating. the range of phase delay/advance is either zero or 40ns to 300ns with the phase differential increasing as the voltage deviatio n from 2.5v increases. the relationship between the control voltage and phase differential is non-linear. the gain ( t/ v) is low for control voltages near 2.5v and rapidly increases as the voltage approaches the extremes of the control range. this behavior provides the designer increased accuracy when selecting a shorter delay/advance duration. when the pwm outputs are delayed relative to the sr outputs (vadj < 2.425v), the delay time should not exceed 90% of the deadtime as determined by rtd and ct. 16 ss connect the soft-start timing capacitor between this pin and gnd to control the duration of soft-start. the value of the ca pacitor determines the rate of increase of the duty cycle during start- up. although no minimum value of capacitance is required, it is recommended that a value of at least 100pf be used for noise immunity. ss may also be used to inhibit the outputs by grounding throug h a small transistor in an open collector/drain configuration. pin descriptions (continued) pin # symbol description
isl6742b 5 fn8565.0 january 31, 2014 functional block diagram outan outbn outa outb vdd pwm steering logic iout uvlo over- temperature protection vref oscillator ct rtd vdd gnd vref + - + - 0.6v 0.33 80mv vref soft-start control vref verr fb 1ma ss cs pwm comparator + - 1.00v overcurrent comparator +70ns leading edge blanking delay/ advance timing control vadj sample and hold 4x ramp
isl6742b 6 fn8565.0 january 31, 2014 typical application - telecom primary si de control half-bridge converter with synchronous rectification vin+ vin- +vout rtn hip2100 vdd hb ho hs lo li hi vss cr2 r7 r12 c10 c12 c13 c8 c23 c6 r3 r1 r2 q7 c4 c5 q2 q1 c2 c3 c1 r8 36v to 75v u1 u2 isl6742b cr1 l1 t1 t2 r4 vr1 q3 q4 c15 r13 c14 r9 c22 q6 q5 r17 r16 c17 c16 cr 3 c7 r23 r24 r21 c20 c21 u3 u4 tl431 +vout r19 r20 r22 c19 + vr 2 r18 ct cs outb outa rtd vdd fb vadj ss vref iout gnd 1 2 4 3 5 6 7 89 10 11 12 13 14 15 16 verr outbn outan ramp u5 t3 c18 r15 r14 cr4 el7212 el7212 u6 c9 c11 r5 r6 r10 r11 r25 c24
isl6742b 7 fn8565.0 january 31, 2014 typical application - high voltage input se condary side control full-bridge converter vin+ vin- return t2 r6 c20 c2 400 vdc u1 l1 t1 r2 r8 + v out c21 c1 q2 q3 r14 r13 r16 r17 c5 c3 c19 c18 t3 cr3 cr4 + + secondary bias supply r19 r18 c16 c17 u3 r20 q1 q4 r3 c4 r7 r9 r5 q16 q15 c6 q12a q12b q11a q11b r11 cr5 r12 cr6 q13a q13b q14a q14b q7a q7b c8 q8a q8b c7 c14 q5a q5b c9 q6a q6b c10 c11 c12 c13 c15 r4 r10 r15 ct cs outb outa rtd vdd fb vadj ss vref iout gnd 1 2 4 3 5 6 7 8 9 10 11 12 13 14 15 16 verr outbn outan ramp isl6742b q15 r21 cr1 cr2 + - vref vref cr7 r22 r23 c22
isl6742b 8 fn8565.0 january 31, 2014 absolute maximum ratings (note 4) thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +20.0v outxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v dd signal pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v ref + 0.3v vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .gnd - 0.3v to 6.0v peak gate current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1a esd classification human body model (per mil-std-883 method 3015.7) . . . . . . . . 2000v charged device model (per eos/es d ds5.3, 4/14/93). . . . . . . . 1000v machine model (per eia/jesd22-a115-a) . . . . . . . . . . . . . . . . . . . . . 75v operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +105c supply voltage range (typical). . . . . . . . . . . . . . . . . . . . . . . 9vdc to 16vdc thermal resistance (typical) ja (c/w) jc (c/w) 16 lead qsop (notes 5, 6) . . . . . . . . . . . . . 90 48 maximum junction temperature . . . . . . . . . . . . . . . . . . . -55c to +150c maximum storage temperature range . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. all voltages are with respect to gnd. 5. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 6. for jc , the ?case temp? location is taken at the package top center. electrical specifications recommended operating conditions unless otherwise note d. refer to ?functional block diagram? on page 5, ?typical application - telecom primary side control half-bridge converter with synchronous rectification? on page 6 and ?typical application - high voltage input secondary side control full-bridge co nverter? on page 7. 9v < vdd < 16v, rtd = 10.0k ? , ct = 470pf, t a = -40c to +105c, typical values are at t a = +25c. boldface limits apply across the oper ating temperature range, -40c to +105c parameter test conditions min (note 7) typ max (note 7) units supply voltage supply voltage -- 20 v start-up current, i dd vdd = 5.0v - 175 400 a operating current, i dd r load , c out = 0 - 7.5 12.0 ma uvlo start threshold 8.00 8.75 9.00 v uvlo stop threshold 6.50 7.00 7.50 v hysteresis -1.75- v reference voltage overall accuracy i vref = 0ma to 10ma 4.850 5.000 5.150 v long term stability t a = +125c, 1000 hours (note 8) - 3 - mv operational current (source) -10 --ma operational current (sink) 5 --ma current limit vref = 4.00v -15 - -100 ma current sense current limit threshold verr = vref 0.97 1.00 1.03 v cs to out delay excl. leb (note 8) - 35 50 ns leading edge blanking (leb) duration (note 8) 50 70 100 ns cs to out delay + leb t a = +25c - - 130 ns cs sink current device impedance v cs = 0.7v - - 20 ? input bias current v cs = 0.3v -1.0 - 1.0 a iout sample and hold buffer amplifier gain t a = +25c 4.00 4.09 4.15 v/v iout sample and hold voh v cs = 1.00v, i load = -300a 3.9 --v iout sample and hold vol v cs = 0.00v, i load = 10a - - 0.3 v
isl6742b 9 fn8565.0 january 31, 2014 ramp ramp sink current device impedance v ramp = 0.2v - - 20 ? ramp to pwm comparator offset t a = +25c 65 80 95 mv bias current v ramp = 0.3v -5.0 - -2.0 a clamp voltage (note 8) 6.5 - 8.0 v soft-start charging current ss = 3v -60 -70 -80 a ss clamp voltage 4.410 4.500 4.590 v ss discharge current ss = 2v 10 --ma reset threshold voltage t a = +25c 0.23 0.27 0.33 v error amplifier input common mode (cm) range (note 8) 0 - vref v gbwp (note 8) 5 --mhz verr vol i load = 2ma - - 0.4 v verr voh i load = 0ma 4.20 --v verr pull-up current source verr = 2.50v 0.8 1.0 1.3 ma ea reference t a = +25c 0.594 0.600 0.606 v ea reference + ea input offset voltage 0.590 0.600 0.612 v pulse width modulator minimum duty cycle verr < 0.6v - - 0 % maximum duty cycle (per half-cycle) verr = 4.20v, v ramp = 0v, v cs = 0v (note 9) -94- % rtd = 2.00k ? , ct = 220pf - 97 - % rtd = 2.00k ? , ct = 470pf - 99 - % zero duty cycle verr voltage 0.85 - 1.20 v verr to pwm comparator input offset t a = +25c 0.7 0.8 0.9 v verr to pwm comparator input gain 0.31 0.33 0.35 v/v common mode (cm) input range (note 8) 0 - 4.45 v oscillator frequency accuracy, overall (note 8) 165 183 201 khz -10 - +10 % frequency variation with vdd t a = +25c, (f 20v - - f 10v )/f 10v -0.31.7% temperature stability vdd = 10v, |f -40c - f 0c |/f 0c (note 8) -4.5- % |f 0c - f 105c |/f 25c (note 8) -1.5- % charge current t a = +25c, v cs = 1.8v -189 -200 -211 a discharge current gain 19 21 23 a/a ct valley voltage static threshold 0.75 0.80 0.88 v ct peak voltage static threshold 2.75 2.80 2.88 v ct pk-pk voltage static value 1.92 2.00 2.05 v rtd voltage 1.97 2.00 2.03 v electrical specifications recommended operating conditions unless otherwise note d. refer to ?functional block diagram? on page 5, ?typical application - telecom primary side control half-bridge converter with synchronous rectification? on page 6 and ?typical application - high voltage input secondary side control full-bridge co nverter? on page 7. 9v < vdd < 16v, rtd = 10.0k ? , ct = 470pf, t a = -40c to +105c, typical values are at t a = +25c. boldface limits apply across the operating te mperature range, -40c to +105c (continued) parameter test conditions min (note 7) typ max (note 7) units
isl6742b 10 fn8565.0 january 31, 2014 output high level output voltage (voh) i out = -10ma, vdd - voh - 0.5 1.0 v low level output voltage (vol) i out = 10ma, vol - gnd - 0.5 1.0 v rise time c out = 220pf, vdd = 15v (note 8) - 110 200 ns fall time c out = 220pf, vdd = 15v (note 8) - 90 150 ns uvlo output voltage clamp (note 8) vdd = 7v, i load = 1ma (note 10) - - 1.25 v output delay/advance range outan/outbn relative to outa/outb v adj = 2.50v (note 8) - - 3 ns v adj < 2.425v -40 - -300 ns v adj > 2.575v 40 - 300 ns delay control voltage range outan/outbn relative to outa/outb outxn delayed 2.575 - 5.000 v outx delayed 0 - 2.425 v vadj delay time t a = +25c (outx delayed) (note 11) vadj = 0 280 300 320 ns vadj = 0.5v 92 105 118 ns vadj = 1.0v 61 70 80 ns vadj = 1.5v 48 55 65 ns vadj = 2.0v 41 50 58 ns t a = +25c (outxn delayed) vadj = vref 280 300 320 ns vadj = vref - 0.5v 86 100 114 ns vadj = vref - 1.0v 59 68 77 ns vadj = vref - 1.5v 47 55 62 ns vadj = vref - 2.0v 41 48 55 ns thermal protection thermal shutdown (note 8) 130 140 150 c thermal shutdown clear (note 8) 115 125 135 c hysteresis, internal protection (note 8) - 15 - c notes: 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 8. limits established by characteriza tion and are not production tested. 9. this is the maximum duty cycle achievable using the specified va lues of rtd and ct. larger or smaller maximum duty cycles may be obtained using other values for these componen ts. see equations 1 through 3. 10. adjust vdd below the uvlo stop threshold prior to setting at 7v. 11. when outx is delayed relative to outlxn (vadj < 2.425v), the de lay duration as set by vadj should not exceed 90% of the ct d ischarge time (deadtime) as determined by ct and rtd. electrical specifications recommended operating conditions unless otherwise note d. refer to ?functional block diagram? on page 5, ?typical application - telecom primary side control half-bridge converter with synchronous rectification? on page 6 and ?typical application - high voltage input secondary side control full-bridge co nverter? on page 7. 9v < vdd < 16v, rtd = 10.0k ? , ct = 470pf, t a = -40c to +105c, typical values are at t a = +25c. boldface limits apply across the operating te mperature range, -40c to +105c (continued) parameter test conditions min (note 7) typ max (note 7) units
isl6742b 11 fn8565.0 january 31, 2014 functional description features the isl6742b pwm is an excellent choice for low cost bridge and push-pull topologies in applicatio ns requiring accurate duty cycle and deadtime control. with its many protection and control features, a highly flexible design with minimal external components is possible. among its many features are current- or voltage-mode control, adjustable soft-start, peak and average overcurrent protection, thermal protection, synchronous rectifier outputs with variable delay/ad vance timing, and adjustable oscillator frequency. oscillator the isl6742b oscillator, with a programmable frequency range to 2mhz, is set with only an external resistor and capacitor. the switching period is the sum of the timing capacitor charge and discharge durations. the charge duration is determined by ct and a fixed 200a internal current source. the discharge duration is determined by rtd and ct. where t c and t d are the charge and discha rge times, respectively, t sw is the oscillator period, and f sw is the oscillator frequency. since the isl6742b is a double-ended controller, one output switching cycle requires two oscillator cycles. the actual charge and discharge times will be slightly longer than calculated due to internal propagation delays of approximately 10ns/transition. this delay adds directly to the sw itching duration, but also causes slight overshoot of the timing capacitor peak and valley voltage thresholds, effectively increasing the peak-to-peak voltage on the timing capacitor. additionally, if very low discharge currents are used, there will be increased error due to the input impedance at the ct pin. typical performance curves figure 1. reference voltage vs temperature figur e 2. ct discharge curren t gain vs rtd current figure 3. deadtime (dt) vs capacita nce figure 4. capacitance vs frequency -40 -25 -10 5 20 35 50 65 80 95 110 0.98 0.99 1.00 1.01 1.02 temperature (c) normalized v ref 0 200 400 600 800 1000 18 19 20 21 22 23 24 25 rtd current (a) ct discharge current gain 0 102030405060708090100 10 100 1?10 4 rtd (k ? ) deadtime (ns) 1?10 3 ct = 1000pf 680pf 470pf 330pf 220pf 100pf 0.1 1 10 10 100 1?10 3 ct (nf) frequency (khz) rtd = 10k ? 50k ? 100k ? t c 11.5 10 ? 3 ct ? s (eq. 1) t d 0.06 rtd ct ?? () 50 10 9 ? ? + s (eq. 2) t sw t c t d + 1 f sw ------------ == s (eq. 3)
isl6742b 12 fn8565.0 january 31, 2014 the maximum duty cycle, d, and percent deadtime, dt, can be calculated from: soft-start operation the isl6742b features a soft-start using an external capacitor in conjunction with an internal current source. soft-start reduces component stresses and surge currents during start-up. upon start-up, the soft-start circ uitry limits the error voltage input (verr) to a value equal to the soft -start voltage. the output pulse width increases as the soft-start ca pacitor voltage increases. this has the effect of increasing the duty cycle from zero to the regulation pulse width during the soft-start period. when the soft-start voltage exceeds the error vo ltage, soft-start is completed. soft-start occurs during start-up and after recovery from a fault condition. the soft-start charging period may be calculated using equation 6: where t is the charging period in ms and c is the value of the soft-start capacitor in f. the soft-start duration experienced by the power supply will be less than or equal to this value, depending on when the feedback loop takes control. the soft-start voltage is clam ped to 4.50v with an overall tolerance of 2%. it is suitable for use as a ?soft-started? reference provided the current draw is kept well below the 70a charging current. the outputs may be inhibited by using the ss pin as a disable input. pulling ss below 0.25v forces all outputs low. an open collector/drain configuration may be used to couple the disable signal to the ss pin. gate drive the isl6742b outputs are capable of sourcing and sinking 10ma (at rated voh, vol) and are intend ed to be used in conjunction with integrated fet drivers or discrete bipolar totem pole drivers. the typical on-resistance of the outputs is 50 ? . overcurrent operation two overcurrent protection mechanisms are available to the power supply designer. the first method is cycle-by-cycle peak overcurrent protection, which provides fast response. the second method is a slower, averaging me thod, which produces constant or ?brick-wall? current limit behavior. if voltage-mode control is used, the average overcurrent protection also maintains flux balance in the transformer by maintaining duty cycle symmetry between half-cycles. the current sense signal applied to the cs pin connects to the peak current comparator and a sample and hold averaging circuit. after a 70ns leading edge blanking (leb) delay, the current sense signal is actively sampled during the on-time, the average current for the cycle is determined, and the result is amplified by 4x and output on the iout pin. if an rc f ilter is placed on the cs input, its time constant should not exceed ~50ns or significant error may be introduced on iout. figure 5 shows the relationship between the cs signal and iout under steady state conditions. iout is 4x the average of cs. figure 6 shows the dynamic behavior of the current averaging circuitry when cs is modulated by an external sine wave. notice iout is updated by the sample and hold circuitry at the termination of the active output pulse. the average current signal on iout remains accurate provided that the output inductor current is co ntinuous (ccm operation). once the inductor current becomes disc ontinuous (dcm operation), iout represents 1/2 the peak inductor current rather than the average current. this occurs because the samp le and hold circuitry is active only during the on-time of the switch ing cycle. it is unable to detect when the inductor current reac hes zero during the off-time. if average overcurrent limit is desired, iout may be used with the available error amplifier of the isl6742b. typically, iout is divided down and filtered as required to achieve the desired amplitude. the resulting signal is input to the current error d t c t sw ---------- = (eq. 4) dt 1 d ? = (eq. 5) t 64.3 c ? = ms (eq. 6) figure 5. cs input vs iout channel 1 (yellow): outa channel 3 (blue): cs channel 2 (red): outb channel 4 (green): iout figure 6. dynamic behavior of cs vs iout channel 1 (yellow): outa channel 3 (blue): cs channel 2 (red): outb channel 4 (green): iout
isl6742b 13 fn8565.0 january 31, 2014 amplifier (iea). the iea is similar to the voltage ea found in most pwm controllers, except it cannot source current. instead, verr has a separate internal 1ma pull-up current source. configure the iea as an integrating (type i) amplifier using the internal 0.6v reference. the volt age applied at fb is integrated against the 0.6v reference. the re sulting signal, verr, is applied to the pwm comparator where it is compared to the sawtooth voltage on ramp. if fb is less than 0.6v, the iea will be open loop (can?t source current), verr will be at a level determined by the voltage loop, and the duty cycle is unaffected. as the output load increases, iout will increase, and the voltage applied to fb will increase until it reaches 0.6v. at this point the iea will reduce verr as required to maintain the output current at the level that corresponds to the 0.6v reference. when the output current again drops below the average cu rrent limit threshold, the iea returns to an open loop conditio n, and the duty cycle is again controlled by the voltage loop. the average current control loop behaves much the same as the voltage control loop found in typical power supplies except it regulates current rather than voltage. the ea available on the isl6742b may also be used as the voltage ea for the voltage feedback control loop rather than the current ea as described previously. an external op amp may be used as either the current or voltage ea providing the circuit is not allowed to source current into verr. the external ea must only sink current, which may be accomplished by adding a diode in series with its output. the 4x gain of the sample and hold buffer allows a range of 150mv to 1000mv peak on the cs signal, depending on the resistor divider placed on iout. the overall bandwidth of the average current loop is determined by the integrating current ea compensation and the divider on iout. the current ea crossover frequency, assuming r6 >> (r4||r5), is expressed in equation 7: where f co is the crossover frequency. a capacitor in parallel with r4 may be used to provide a double-pole roll-off. the average current loop bandwidth is normally set to be much less than the switching frequency, typically less than 5khz and often as slow as a few hundred hertz or less. this is especially useful if the application experi ences large surges. the average current loop can be set to the st eady state overcurrent threshold and have a time response that is longer than the required transient. the peak current limit can be set higher than the expected transient so that it does not interfere with the transient, but still protects for short-term larg er faults. in essence, a 2-stage overcurrent response is possible. the peak overcurrent behavior is similar to most other pwm controllers. if the peak current exceeds 1v, the active output pulse is terminated immediately. if voltage-mode control is used in a bridge topology, it should be noted that peak current limit results in inherently unstable operation. dc blocking capacitors used in voltage-mode bridge topologies become unbalanced, as does the flux in the transformer core. the average over current circuitry prevents this behavior by maintaining symmetric duty cycles for each half- cycle. if the average current limit circuitry is not used, a latching overcurrent shutdown method using external components is recommended. the cs to output propagation delay is increased by the leading edge blanking (leb) interval. the effective delay is the sum of the two delays and is 130ns maximum. voltage feed-forward operation voltage feed-forward is a technique used to regulate the output voltage for changes in input volt age without the intervention of the control loop. voltage feed-forward is often implemented in voltage-mode control loops, but is redundant and unnecessary in peak current-mode control loops. voltage feed-forward operates by modulating the sawtooth ramp in direct proportion to the inpu t voltage. figure 8 demonstrates the concept. input voltage feed-forward may be implemented using the ramp input. an rc network connected between the input voltage and ground, as shown in figure 9, generates a voltage ramp proportional to the amplitude of the source voltage. at the termination of the active output pulse, ramp is discharged to ground so that a repetitive sawtooth waveform is created. the figure 7. average overcurrent implementation 150mv to 1000mv + - 0.6v s&h 4x r6 r5 r4 c10 cs fb iout 1 2 4 3 5 6 7 89 1 0 1 1 1 2 1 3 1 4 1 5 1 6 verr isl6742b f co 1 2 r6 c10 ?? ----------------------------------- = hz (eq. 7) figure 8. voltage feed forward behavior vin error voltage ramp ct outa, outb
isl6742b 14 fn8565.0 january 31, 2014 ramp waveform is compared to the verr voltage to determine duty cycle. the selection of the rc components depends upon the desired input voltage operating range and the frequency of the oscillator. in typical applic ations, the rc components are selected so that the ramp am plitude reaches 1v at minimum input voltage within the du ration of one half-cycle. referring to figure 9, the charging time of the ramp capacitor is expressed in equation 8: for optimum performance, the maximum value of the capacitor should be limited to 10nf. the dc current throug h the resistor should be limited to 3ma. for example, if the oscillator frequency is 400khz, the minimum input volt age is 300v and a 4.7nf ramp capacitor is selected. the value of the resistor can be determined by rearranging equation 8. where t is equal to the oscillator period minus the deadtime. if the deadtime is short relative to the oscillator period, it can be ignored for this calculation. when implemented, the voltage feed-forward feature also provides a volt-second clamp on the transformer. the maximum duty cycle is determined by the lesser of the oscillator period or the ramp charge time. as the input voltage increases, the ramp charge time decreases, limiting the duty cycle proportionately. if feed-forward operation is not desired, the rc network may be connected to vref or a buffered ct signal rather than the input voltage. regardless, a sawtooth waveform must be generated on ramp as it is required for proper pwm operation. implementing synchronization synchronization to an external cl ock signal may be accomplished in the same manner as many pwm controllers that do not have a separate synchronization input. by injecting a short pulse across a small resistor in series with the timing capacitor, the oscillator sawtooth waveform may be terminated prematurely. the injected pulse width should be narrower than the sawtooth discharge duration. synchronous rectifier outputs and control the isl6742b provides double-ended pwm outputs, outa and outb, and synchronous rectifier (sr) outputs, outan and outbn. the sr outputs are the complements of the pwm outputs. it should be noted that complemented outputs are used in conjunction with the opposite pwm output, i.e., outa and outbn are paired together and outb and outan are paired together. referring to figure 11, the srs alternate between being both on during the free-wheeling portion of the cycle (outa/outb off), and one or the other being off when outa or outb is on. if outa is on, its corresponding sr must also be on, indicating that outbn is the correct sr control sign al. likewise, if outb is on, its corresponding sr must also be on , indicating that outan is the correct sr control signal. a useful feature of the isl6742b is the ability to vary the phase relationship between the pwm outputs (outa, outb) and their complements (outan, outbn) by 300ns. this feature allows the designer to compensate for differences in the signal figure 9. voltage feed-forward control vin r3 c7 gnd 1 2 4 3 5 6 7 89 10 11 12 13 14 15 16 ramp isl6742b tr3c71 v ramp peak () v in min () --------------------------------------- - ? ?? ?? ?? ln ?? ? = s (eq. 8) r3 t ? c7 1 v ramp peak () v in min ) () --------------------------------------- - ? ?? ?? ?? ln ? ------------------------------------------------------------------------- 2.5 ? 10 6 ? ? 4.7 10 9 ? 1 1 300 --------- - ? ?? ?? ln ?? ------------------------------------------------------------ == 159k = (eq. 9) figure 10. synchronization to an external clock ct rs ct gnd 1 2 4 3 5 6 7 89 10 11 12 13 14 15 16 isl6742b figure 11. basic waveform timing ct outa outb outan (sr1) outbn (sr2)
isl6742b 15 fn8565.0 january 31, 2014 propagation delays between th e pwm fets and the sr fets. a voltage applied to vadj cont rols the phase relationship. figures 12 and 13 demonstrate the delay relationships. setting vadj to vref/2 results in no delay on any output. the no delay voltage has a 75mv tolerance window. control voltages below the vref/2 zero delay th reshold cause the pwm outputs, outa/outb, to be delayed. cont rol voltages greater than the vref/2 zero delay threshold cause the sr outputs, outan/outbn, to be delayed. it should be noted that when the pwm outputs, outa/outb, are delayed, the cs to output propagation delay is increased by the amount of the added delay. the delay feature is provided to compensate for mismatched propagation delays between th e pwm and sr outputs as may be experienced when one set of signals crosses the primary- secondary isolation boundary. if required, individual output pulses may be stretched or compressed as required using external resistors, capacitors, and diodes. slope compensation peak current-mode control requ ires slope compensation to improve noise immunity, particular ly at lighter loads, and to prevent current loop instability, part icularly for duty cycles greater than 50%. slope compensation may be accomplished by summing an external ramp with th e current feedback signal or by subtracting the external ramp fr om the voltage feedback error signal. adding the external ramp to the current feedback signal is the more popular method. from the small signal current-mode model [1] it can be shown that the naturally-sampled modulator gain, f m , without slope compensation, is expressed in equation 10: where s n is the slope of the sawtooth signal and t sw is the duration of the half-cycle. when an external ramp is added, the modulator gain becomes equation 11: where s e is slope of the external ramp and: the criteria for determining the correct amount of external ramp can be determined by appropriately setting the damping factor of the double-pole located at half the oscillator frequency. the double-pole will be critically damped if the q-factor is set to 1, over-damped for q > 1, and under-damped for q < 1. an under-damped condition may result in current loop instability. where d is the percent of on-time during a half cycle (half period duty cycle). setting q = 1 and solving for s e yields equation 14: since s n and s e are the on-time slopes of the current ramp and the external ramp, respectively, they can be multiplied by t on to obtain the voltage change that occurs during t on . where v n is the change in the current feedback signal during the on time and v e is the voltage that must be added by the external ramp. v n can be solved for in terms of input voltage, current transducer components, and output induct ance yielding equation 16: where r cs is the current sense burden resistor, n ct is the current transformer turns ratio, l o is the output inductance, v o is the output voltage, and n s and n p are the secondary and primary turns, respectively. figure 12. waveform timing with pwm outputs delayed, 0v < vadj < 2.425v ct outa outb outan (sr1) outbn (sr2) ct outa outb outan (sr1) outbn (sr2) figure 13. waveform timing with sr outputs delayed, 2.575v < vadj < 5.00v f m 1 s n s n -------------- = (eq. 10) f m 1 s n s e + () t sw ------------------------------------ 1 m c s n t sw -------------------------- == (eq. 11) m c 1 s e s n ------ - + = (eq. 12) q 1 m c 1d ? () 0.5 ? () ------------------------------------------------- = (eq. 13) s e s n 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = (eq. 14) v e v n 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = (eq. 15) v e t sw v ? o r cs ? n ct l o ? --------------------------------------- - n s n p ------- - ? 1 -- - d0.5 ? + ?? ?? = v (eq. 16)
isl6742b 16 fn8565.0 january 31, 2014 the current sense signal, which represents the inductor current after it has been reflected th rough the isolation and current sense transformers, and passe d through the current sense burden resistor, is expressed in equation 17: where v cs is the voltage across the current sense resistor and i o is the output current at current limit. since the peak current limit thre shold is 1v, the total current feedback signal plus the external ramp voltage must sum to this value when the output load is at the current limit threshold. substituting equations 16 and 17 into equation 18 and solving for r cs yields equation 19: for simplicity, idealized components have been used for this discussion, but the effect of magnetizing inductance must be considered when determining the amount of external ramp to add. magnetizing inductance provides a degree of slope compensation and reduces the amount of external ramp required. the magnetizing inductance adds primary current in excess of what is reflected from the inductor current in the secondary. where v in is the input voltage that corresponds to the duty cycle d and lm is the primary magnetizing inductance. the effect of the magnetizing current at the current sense resistor, r cs , is expressed in equation 21: if v cs is greater than or equal to ve, then no additional slope compensation is needed and r cs becomes equation 22: if v cs is less than v e , then equation 19 is still valid for the value of r cs , but the amount of slope compensation added by the external ramp must be reduced by v cs . adding slope compensation is accomplished in the isl6742b using an external buffer and the ct signal. a typical application sums the buffered ct signal with the current sense feedback and applies the result to the cs pin as shown in figure 14. assuming the designer has selected values for the rc filter (r6 and c4) placed on the cs pin, the value of r9 required to add the appropriate external ramp can be found by superposition. rearranging to solve for r9 yields: the value of r cs determined in equation 19 must be rescaled so that the current sense signal presented at the cs pin is that predicted by equation 17. the divider created by r6 and r9 makes this necessary. example: v in = 280v v o = 12v l o = 2.0h n p /n s = 20 lm = 2mh i o = 55a oscillator frequency, f sw = 400khz duty cycle, d = 85.7% n ct = 50 r6 = 499 ? solve for the current sense resistor, r cs , using equation 19. r cs = 15.1 ? . determine the amount of voltage, v e , that must be added to the current feedback signal using equation 16. v e = 153mv v cs n s r cs ? n p n ct ? ------------------------ i o dt ? sw 2l o ------------------- v in n s n p ------- - ? v o ? ?? ?? ?? + ?? ?? ?? = v (eq. 17) v e v cs + 1 = (eq. 18) r cs n p n ct ? n s ------------------------ 1 i o v o l o ------- - t sw 1 -- - d 2 --- - + ?? ?? + ---------------------------------------------------- ? = (eq. 19) i p v in dt sw ? l m ----------------------------- = a (eq. 20) v cs i p r cs ? n ct ------------------------- - = v (eq. 21) r cs n ct n s n p ------- - i o dt sw 2l o --------------- v in n s n p ------- - ? v o ? ?? ?? ?? ? + ?? ?? ?? ? v in dt sw ? l m ----------------------------- + ------------------------------------------------------------------------------------------------------------------------------- -- - = (eq. 22) figure 14. adding slope compensation r6 c4 r9 r cs ct ct cs 1 2 4 3 5 6 7 89 10 11 12 13 14 15 16 isl6742b vref v e v cs ? 2d r6 ? r6 r9 + ---------------------- = v (eq. 23) r9 2d v e v cs + ? () r6 ? v e v cs ? ------------------------------------------------------------ - = (eq. 24) r cs r6 r9 + r9 ---------------------- r cs ? = (eq. 25)
isl6742b 17 fn8565.0 january 31, 2014 next, determine the effect of the magnetizing current from equation 21. v cs = 91mv using equation 24, solve for the summing resistor, r9, from ct to cs. r9 = 13.2k ? determine the new value of r cs , r? cs , using equation 25. r? cs = 15.7 ? additional slope compensation may be considered for design margin. this discussion determines the minimum external ramp that is required. the buffer transistor used to create the external ramp from ct should have a sufficiently high gain (>200) so as to minimize the required base current. whatever base current is required reduces the charging current into ct and will reduce the oscillator frequency. parallel operation parallel operation of converters using the isl6742b may be accomplished using the average current signal, iout. iout provides a very accurate representation of the output current and may be used for active current sharing with many sharing techniques commonly used including master-slave and average current sharing methods. since iout represents the av erage inductor current (ccm operation), sharing errors introduced by techniques using peak inductor current are reduced. in particular, the current sharing error introduced by mismatched switching frequencies is eliminated. figure 15 illustrates a master-slave current sharing method. in parallel and redundant applicat ions, the ishare signals from each power supply are connected together. each power supply produces a voltage proportional to its average output current on iout, and through limiting resistor r3, on ishare. the unit with the highest ishare signal (and highest output current) sources current onto the ishare bus, and is identified as the master unit. the units with lower ishare sign als do not source current onto ishare, and are identified as slave units. each slave unit compares the master?s ishare signal with its own, and if there is sufficient difference, turns q1 on, which pulls down on the feedback voltage. reducing the feedback voltage causes the output voltage to appear low; th e feedback loop compensates by increasing the output voltage, and the output current increases. each slave unit will increase its output voltage until its output current is nearly equal to that of the master. the difference between the master?s output current and that of a slave unit is set by r1 and r2. some difference is required to prevent undesirable switching of master and slave roles. this difference also prevents operation of the current sharing circuitry when a power supply is operating stand alone. the maximum output voltage that a slave can induce in its output is controlled by r6 and the ou tput voltage feedback divider. typically, the maximum allowed output voltage increase is limited to a few percent, but must be greater than the tolerance of the feedback and reference components and any distribution drops between units. if remote sensin g is used, the adjustment range must also include the difference in distribution drops between the power supply outputs and the remote sensing location. the current limit circuit must limit the voltage change to less than the output overvoltage threshold or an over voltage condition can be induced. amplifier u2a sets the scaling factor from iout to ishare and increases the current sourcing capa bility of ishare. u2b is a low bandwidth amplifier that sets the frequency response and gain of the current share circuitry. the current share bandwidth must be much lower than the voltage feedback loop bandwidth to ensure overall stability. the gain is set by r1 and r5, and the bandwidth by r5 and c1. the disconnect in series with ishare may be omitted for power systems that do not require fault isolation. the disconnect switch is normally implemented with mosfet or jfet devices. figure 15. master-slave curr ent sharing using average current cs 1 2 4 3 5 6 7 89 10 11 12 13 14 15 16 isl6742b iout s&h 4x + - + - ishare vout output voltage feedback divider voltage error amplifier inverting (-) input disconnect if p/s fails or is turned off r1 r2 (>>r1) r3 r4 (>>r3) r5 (>>r1) r6 c1 vdd bias u1 u2a u2b q1 r7
isl6742b 18 fn8565.0 january 31, 2014 average current mode control the average current signal produced on iout may also be used for average current mode control rather than peak current mode control. there are many advantages to average current mode control, most notably, improved noise immunity and greater design flexibility of the current feedback loop compensation. figure 16 portrays the concept. instead of being compared to a peak current sense signal as it would be in a peak current mode control configuration, the voltage amplifier output is integr ated against the average output current. the voltage loop compensation and the current loop compensation may be adjusted independently. the voltage error amplifier programs the average output current of the supply, and its maximum output level determines the maximum output current. either io ut or the voltage ea output must be scaled appropriately to achieve the desired current limit setpoint. the offset voltage shown in figure 16 must be provided to compensate for input offset voltage of the current amplifier to ensure that zero duty cycle operation is achievable. depending on the performance requ irements of the control loop, compensation networks other than shown may be required. fault conditions a fault condition occurs if vref or vdd fall below their undervoltage lockout (uvlo) thresholds or if the thermal protection is triggered. when a fault is detected, the soft-start capacitor is quickly discharged, and the outputs are disabled low. when the fault condition clears an d the soft-start voltage is below the reset threshold, a soft-start cycle begins. an overcurrent condition is not considered a fault and does not result in a shutdown. thermal protection internal die over temperature protection is provided. an integrated temperature sensor protects the device should the junction temperature exceed +140c. there is approximately +15c of hysteresis. ground plane requirements careful layout is essential for satisfactory operation of the device. a good ground plane must be employed. vdd and vref should be bypassed directly to gnd with good high frequency capacitance. references [1] ridley, r., ?a new continuous-time model for current mode control?, ieee transact ions on power electronics, vol. 6, no. 2, april 1991. figure 16. average current mode control ref + - r1 rb r2 c1 + - iout vout verr c2 offset voltage error amplifier current error amplifier r3 r4 u1 u2
isl6742b 19 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8565.0 january 31, 2014 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change january 31, 2014 fn8565.0 initial release.
isl6742b 20 fn8565.0 january 31, 2014 package outline drawing m16.15a 16 lead shrink small outlin e plastic package (qsop/ssop) 0.150? wide body rev 3, 8/12 notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. package length does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. package width does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. terminal numbers are shown for reference only. 7. lead width does not include dambar protrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum material condition. 8. controlling dimension: millimeter. index area 16 1 -b- 0.17(0.007) ca m bs -a- m -c- seating plane 0.10(0.004) x 45 0.25 0.010 gauge plane 3.99 3.81 6.20 5.84 4 0.25(0.010) b m m 0.89 0.41 0.41 0.25 5 8 0 1.55 1.40 0.249 0.191 4.98 4.80 3 1.73 1.55 0.249 0.102 0.31 0.20 7 0.635 bsc 5.59 4.06 7.11 0.38 0.635 detail ?x? side view 1 typical recommended land pattern top view side view 2

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